1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2017-2018, Linaro Limited 4 5 #include <linux/module.h> 6 #include <linux/init.h> 7 #include <linux/platform_device.h> 8 #include <linux/device.h> 9 #include <linux/wait.h> 10 #include <linux/bitops.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/kernel.h> 15 #include <linux/slimbus.h> 16 #include <sound/soc.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc-dapm.h> 19 #include <linux/of_gpio.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <sound/tlv.h> 23 #include <sound/info.h> 24 #include "wcd9335.h" 25 #include "wcd-clsh-v2.h" 26 27 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 28 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 29 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 30 /* Fractional Rates */ 31 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100) 32 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \ 33 SNDRV_PCM_FMTBIT_S24_LE) 34 35 /* slave port water mark level 36 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes) 37 */ 38 #define SLAVE_PORT_WATER_MARK_6BYTES 0 39 #define SLAVE_PORT_WATER_MARK_9BYTES 1 40 #define SLAVE_PORT_WATER_MARK_12BYTES 2 41 #define SLAVE_PORT_WATER_MARK_15BYTES 3 42 #define SLAVE_PORT_WATER_MARK_SHIFT 1 43 #define SLAVE_PORT_ENABLE 1 44 #define SLAVE_PORT_DISABLE 0 45 #define WCD9335_SLIM_WATER_MARK_VAL \ 46 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \ 47 (SLAVE_PORT_ENABLE)) 48 49 #define WCD9335_SLIM_NUM_PORT_REG 3 50 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2) 51 52 #define WCD9335_MCLK_CLK_12P288MHZ 12288000 53 #define WCD9335_MCLK_CLK_9P6MHZ 9600000 54 55 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000 56 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0) 57 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1) 58 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2) 59 60 #define WCD9335_NUM_INTERPOLATORS 9 61 #define WCD9335_RX_START 16 62 #define WCD9335_SLIM_CH_START 128 63 #define WCD9335_MAX_MICBIAS 4 64 #define WCD9335_MAX_VALID_ADC_MUX 13 65 #define WCD9335_INVALID_ADC_MUX 9 66 67 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 68 #define CF_MIN_3DB_4HZ 0x0 69 #define CF_MIN_3DB_75HZ 0x1 70 #define CF_MIN_3DB_150HZ 0x2 71 #define WCD9335_DMIC_CLK_DIV_2 0x0 72 #define WCD9335_DMIC_CLK_DIV_3 0x1 73 #define WCD9335_DMIC_CLK_DIV_4 0x2 74 #define WCD9335_DMIC_CLK_DIV_6 0x3 75 #define WCD9335_DMIC_CLK_DIV_8 0x4 76 #define WCD9335_DMIC_CLK_DIV_16 0x5 77 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02 78 #define WCD9335_AMIC_PWR_LEVEL_LP 0 79 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1 80 #define WCD9335_AMIC_PWR_LEVEL_HP 2 81 #define WCD9335_AMIC_PWR_LVL_MASK 0x60 82 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5 83 84 #define WCD9335_DEC_PWR_LVL_MASK 0x06 85 #define WCD9335_DEC_PWR_LVL_LP 0x02 86 #define WCD9335_DEC_PWR_LVL_HP 0x04 87 #define WCD9335_DEC_PWR_LVL_DF 0x00 88 89 #define WCD9335_SLIM_RX_CH(p) \ 90 {.port = p + WCD9335_RX_START, .shift = p,} 91 92 #define WCD9335_SLIM_TX_CH(p) \ 93 {.port = p, .shift = p,} 94 95 /* vout step value */ 96 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25) 97 98 #define WCD9335_INTERPOLATOR_PATH(id) \ 99 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \ 100 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \ 101 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \ 102 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \ 103 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \ 104 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \ 105 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \ 106 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \ 107 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \ 108 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \ 109 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \ 110 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \ 111 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \ 112 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \ 113 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \ 114 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \ 115 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \ 116 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \ 117 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \ 118 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \ 119 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \ 120 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \ 121 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \ 122 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \ 123 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \ 124 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \ 125 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \ 126 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \ 127 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \ 128 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \ 129 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \ 130 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \ 131 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \ 132 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \ 133 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \ 134 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \ 135 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \ 136 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \ 137 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"} 138 139 #define WCD9335_ADC_MUX_PATH(id) \ 140 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 141 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 142 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \ 143 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \ 144 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \ 145 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \ 146 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \ 147 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \ 148 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \ 149 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \ 150 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \ 151 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \ 152 {"AMIC MUX" #id, "ADC1", "ADC1"}, \ 153 {"AMIC MUX" #id, "ADC2", "ADC2"}, \ 154 {"AMIC MUX" #id, "ADC3", "ADC3"}, \ 155 {"AMIC MUX" #id, "ADC4", "ADC4"}, \ 156 {"AMIC MUX" #id, "ADC5", "ADC5"}, \ 157 {"AMIC MUX" #id, "ADC6", "ADC6"} 158 159 enum { 160 WCD9335_RX0 = 0, 161 WCD9335_RX1, 162 WCD9335_RX2, 163 WCD9335_RX3, 164 WCD9335_RX4, 165 WCD9335_RX5, 166 WCD9335_RX6, 167 WCD9335_RX7, 168 WCD9335_RX8, 169 WCD9335_RX9, 170 WCD9335_RX10, 171 WCD9335_RX11, 172 WCD9335_RX12, 173 WCD9335_RX_MAX, 174 }; 175 176 enum { 177 WCD9335_TX0 = 0, 178 WCD9335_TX1, 179 WCD9335_TX2, 180 WCD9335_TX3, 181 WCD9335_TX4, 182 WCD9335_TX5, 183 WCD9335_TX6, 184 WCD9335_TX7, 185 WCD9335_TX8, 186 WCD9335_TX9, 187 WCD9335_TX10, 188 WCD9335_TX11, 189 WCD9335_TX12, 190 WCD9335_TX13, 191 WCD9335_TX14, 192 WCD9335_TX15, 193 WCD9335_TX_MAX, 194 }; 195 196 enum { 197 SIDO_SOURCE_INTERNAL = 0, 198 SIDO_SOURCE_RCO_BG, 199 }; 200 201 enum wcd9335_sido_voltage { 202 SIDO_VOLTAGE_SVS_MV = 950, 203 SIDO_VOLTAGE_NOMINAL_MV = 1100, 204 }; 205 206 enum { 207 AIF1_PB = 0, 208 AIF1_CAP, 209 AIF2_PB, 210 AIF2_CAP, 211 AIF3_PB, 212 AIF3_CAP, 213 AIF4_PB, 214 NUM_CODEC_DAIS, 215 }; 216 217 enum { 218 COMPANDER_1, /* HPH_L */ 219 COMPANDER_2, /* HPH_R */ 220 COMPANDER_3, /* LO1_DIFF */ 221 COMPANDER_4, /* LO2_DIFF */ 222 COMPANDER_5, /* LO3_SE */ 223 COMPANDER_6, /* LO4_SE */ 224 COMPANDER_7, /* SWR SPK CH1 */ 225 COMPANDER_8, /* SWR SPK CH2 */ 226 COMPANDER_MAX, 227 }; 228 229 enum { 230 INTn_2_INP_SEL_ZERO = 0, 231 INTn_2_INP_SEL_RX0, 232 INTn_2_INP_SEL_RX1, 233 INTn_2_INP_SEL_RX2, 234 INTn_2_INP_SEL_RX3, 235 INTn_2_INP_SEL_RX4, 236 INTn_2_INP_SEL_RX5, 237 INTn_2_INP_SEL_RX6, 238 INTn_2_INP_SEL_RX7, 239 INTn_2_INP_SEL_PROXIMITY, 240 }; 241 242 enum { 243 INTn_1_MIX_INP_SEL_ZERO = 0, 244 INTn_1_MIX_INP_SEL_DEC0, 245 INTn_1_MIX_INP_SEL_DEC1, 246 INTn_1_MIX_INP_SEL_IIR0, 247 INTn_1_MIX_INP_SEL_IIR1, 248 INTn_1_MIX_INP_SEL_RX0, 249 INTn_1_MIX_INP_SEL_RX1, 250 INTn_1_MIX_INP_SEL_RX2, 251 INTn_1_MIX_INP_SEL_RX3, 252 INTn_1_MIX_INP_SEL_RX4, 253 INTn_1_MIX_INP_SEL_RX5, 254 INTn_1_MIX_INP_SEL_RX6, 255 INTn_1_MIX_INP_SEL_RX7, 256 257 }; 258 259 enum { 260 INTERP_EAR = 0, 261 INTERP_HPHL, 262 INTERP_HPHR, 263 INTERP_LO1, 264 INTERP_LO2, 265 INTERP_LO3, 266 INTERP_LO4, 267 INTERP_SPKR1, 268 INTERP_SPKR2, 269 }; 270 271 enum wcd_clock_type { 272 WCD_CLK_OFF, 273 WCD_CLK_RCO, 274 WCD_CLK_MCLK, 275 }; 276 277 enum { 278 MIC_BIAS_1 = 1, 279 MIC_BIAS_2, 280 MIC_BIAS_3, 281 MIC_BIAS_4 282 }; 283 284 enum { 285 MICB_PULLUP_ENABLE, 286 MICB_PULLUP_DISABLE, 287 MICB_ENABLE, 288 MICB_DISABLE, 289 }; 290 291 struct wcd9335_slim_ch { 292 u32 ch_num; 293 u16 port; 294 u16 shift; 295 struct list_head list; 296 }; 297 298 struct wcd_slim_codec_dai_data { 299 struct list_head slim_ch_list; 300 struct slim_stream_config sconfig; 301 struct slim_stream_runtime *sruntime; 302 }; 303 304 struct wcd9335_codec { 305 struct device *dev; 306 struct clk *mclk; 307 struct clk *native_clk; 308 u32 mclk_rate; 309 u8 version; 310 311 struct slim_device *slim; 312 struct slim_device *slim_ifc_dev; 313 struct regmap *regmap; 314 struct regmap *if_regmap; 315 struct regmap_irq_chip_data *irq_data; 316 317 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX]; 318 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX]; 319 u32 num_rx_port; 320 u32 num_tx_port; 321 322 int sido_input_src; 323 enum wcd9335_sido_voltage sido_voltage; 324 325 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS]; 326 struct snd_soc_component *component; 327 328 int master_bias_users; 329 int clk_mclk_users; 330 int clk_rco_users; 331 int sido_ccl_cnt; 332 enum wcd_clock_type clk_type; 333 334 struct wcd_clsh_ctrl *clsh_ctrl; 335 u32 hph_mode; 336 int prim_int_users[WCD9335_NUM_INTERPOLATORS]; 337 338 int comp_enabled[COMPANDER_MAX]; 339 340 int intr1; 341 int reset_gpio; 342 struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY]; 343 344 unsigned int rx_port_value; 345 unsigned int tx_port_value; 346 int hph_l_gain; 347 int hph_r_gain; 348 u32 rx_bias_count; 349 350 /*TX*/ 351 int micb_ref[WCD9335_MAX_MICBIAS]; 352 int pullup_ref[WCD9335_MAX_MICBIAS]; 353 354 int dmic_0_1_clk_cnt; 355 int dmic_2_3_clk_cnt; 356 int dmic_4_5_clk_cnt; 357 int dmic_sample_rate; 358 int mad_dmic_sample_rate; 359 360 int native_clk_users; 361 }; 362 363 struct wcd9335_irq { 364 int irq; 365 irqreturn_t (*handler)(int irq, void *data); 366 char *name; 367 }; 368 369 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = { 370 WCD9335_SLIM_TX_CH(0), 371 WCD9335_SLIM_TX_CH(1), 372 WCD9335_SLIM_TX_CH(2), 373 WCD9335_SLIM_TX_CH(3), 374 WCD9335_SLIM_TX_CH(4), 375 WCD9335_SLIM_TX_CH(5), 376 WCD9335_SLIM_TX_CH(6), 377 WCD9335_SLIM_TX_CH(7), 378 WCD9335_SLIM_TX_CH(8), 379 WCD9335_SLIM_TX_CH(9), 380 WCD9335_SLIM_TX_CH(10), 381 WCD9335_SLIM_TX_CH(11), 382 WCD9335_SLIM_TX_CH(12), 383 WCD9335_SLIM_TX_CH(13), 384 WCD9335_SLIM_TX_CH(14), 385 WCD9335_SLIM_TX_CH(15), 386 }; 387 388 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = { 389 WCD9335_SLIM_RX_CH(0), /* 16 */ 390 WCD9335_SLIM_RX_CH(1), /* 17 */ 391 WCD9335_SLIM_RX_CH(2), 392 WCD9335_SLIM_RX_CH(3), 393 WCD9335_SLIM_RX_CH(4), 394 WCD9335_SLIM_RX_CH(5), 395 WCD9335_SLIM_RX_CH(6), 396 WCD9335_SLIM_RX_CH(7), 397 WCD9335_SLIM_RX_CH(8), 398 WCD9335_SLIM_RX_CH(9), 399 WCD9335_SLIM_RX_CH(10), 400 WCD9335_SLIM_RX_CH(11), 401 WCD9335_SLIM_RX_CH(12), 402 }; 403 404 struct interp_sample_rate { 405 int rate; 406 int rate_val; 407 }; 408 409 static struct interp_sample_rate int_mix_rate_val[] = { 410 {48000, 0x4}, /* 48K */ 411 {96000, 0x5}, /* 96K */ 412 {192000, 0x6}, /* 192K */ 413 }; 414 415 static struct interp_sample_rate int_prim_rate_val[] = { 416 {8000, 0x0}, /* 8K */ 417 {16000, 0x1}, /* 16K */ 418 {24000, -EINVAL},/* 24K */ 419 {32000, 0x3}, /* 32K */ 420 {48000, 0x4}, /* 48K */ 421 {96000, 0x5}, /* 96K */ 422 {192000, 0x6}, /* 192K */ 423 {384000, 0x7}, /* 384K */ 424 {44100, 0x8}, /* 44.1K */ 425 }; 426 427 struct wcd9335_reg_mask_val { 428 u16 reg; 429 u8 mask; 430 u8 val; 431 }; 432 433 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = { 434 /* Rbuckfly/R_EAR(32) */ 435 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00}, 436 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60}, 437 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00}, 438 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50}, 439 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50}, 440 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08}, 441 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08}, 442 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C}, 443 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00}, 444 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40}, 445 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03}, 446 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02}, 447 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01}, 448 {WCD9335_EAR_CMBUFF, 0x08, 0x00}, 449 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 450 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 451 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 452 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, 453 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80}, 454 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80}, 455 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01}, 456 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01}, 457 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01}, 458 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01}, 459 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01}, 460 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01}, 461 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01}, 462 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01}, 463 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01}, 464 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01}, 465 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01}, 466 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01}, 467 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01}, 468 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01}, 469 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01}, 470 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01}, 471 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01}, 472 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01}, 473 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01}, 474 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01}, 475 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08}, 476 {WCD9335_RCO_CTRL_2, 0x0F, 0x08}, 477 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10}, 478 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20}, 479 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A}, 480 {WCD9335_HPH_L_TEST, 0x01, 0x01}, 481 {WCD9335_HPH_R_TEST, 0x01, 0x01}, 482 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12}, 483 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08}, 484 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18}, 485 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12}, 486 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08}, 487 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18}, 488 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45}, 489 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4}, 490 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08}, 491 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02}, 492 }; 493 494 /* Cutoff frequency for high pass filter */ 495 static const char * const cf_text[] = { 496 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ" 497 }; 498 499 static const char * const rx_cf_text[] = { 500 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ", 501 "CF_NEG_3DB_0P48HZ" 502 }; 503 504 static const char * const rx_int0_7_mix_mux_text[] = { 505 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 506 "RX6", "RX7", "PROXIMITY" 507 }; 508 509 static const char * const rx_int_mix_mux_text[] = { 510 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", 511 "RX6", "RX7" 512 }; 513 514 static const char * const rx_prim_mix_text[] = { 515 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 516 "RX3", "RX4", "RX5", "RX6", "RX7" 517 }; 518 519 static const char * const rx_int_dem_inp_mux_text[] = { 520 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 521 }; 522 523 static const char * const rx_int0_interp_mux_text[] = { 524 "ZERO", "RX INT0 MIX2", 525 }; 526 527 static const char * const rx_int1_interp_mux_text[] = { 528 "ZERO", "RX INT1 MIX2", 529 }; 530 531 static const char * const rx_int2_interp_mux_text[] = { 532 "ZERO", "RX INT2 MIX2", 533 }; 534 535 static const char * const rx_int3_interp_mux_text[] = { 536 "ZERO", "RX INT3 MIX2", 537 }; 538 539 static const char * const rx_int4_interp_mux_text[] = { 540 "ZERO", "RX INT4 MIX2", 541 }; 542 543 static const char * const rx_int5_interp_mux_text[] = { 544 "ZERO", "RX INT5 MIX2", 545 }; 546 547 static const char * const rx_int6_interp_mux_text[] = { 548 "ZERO", "RX INT6 MIX2", 549 }; 550 551 static const char * const rx_int7_interp_mux_text[] = { 552 "ZERO", "RX INT7 MIX2", 553 }; 554 555 static const char * const rx_int8_interp_mux_text[] = { 556 "ZERO", "RX INT8 SEC MIX" 557 }; 558 559 static const char * const rx_hph_mode_mux_text[] = { 560 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB", 561 "Class-H Hi-Fi Low Power" 562 }; 563 564 static const char *const slim_rx_mux_text[] = { 565 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB", 566 }; 567 568 static const char * const adc_mux_text[] = { 569 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2" 570 }; 571 572 static const char * const dmic_mux_text[] = { 573 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 574 "SMIC0", "SMIC1", "SMIC2", "SMIC3" 575 }; 576 577 static const char * const dmic_mux_alt_text[] = { 578 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5", 579 }; 580 581 static const char * const amic_mux_text[] = { 582 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6" 583 }; 584 585 static const char * const sb_tx0_mux_text[] = { 586 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192" 587 }; 588 589 static const char * const sb_tx1_mux_text[] = { 590 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192" 591 }; 592 593 static const char * const sb_tx2_mux_text[] = { 594 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192" 595 }; 596 597 static const char * const sb_tx3_mux_text[] = { 598 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192" 599 }; 600 601 static const char * const sb_tx4_mux_text[] = { 602 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192" 603 }; 604 605 static const char * const sb_tx5_mux_text[] = { 606 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192" 607 }; 608 609 static const char * const sb_tx6_mux_text[] = { 610 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192" 611 }; 612 613 static const char * const sb_tx7_mux_text[] = { 614 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192" 615 }; 616 617 static const char * const sb_tx8_mux_text[] = { 618 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192" 619 }; 620 621 static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0); 622 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); 623 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1); 624 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0); 625 626 static const struct soc_enum cf_dec0_enum = 627 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text); 628 629 static const struct soc_enum cf_dec1_enum = 630 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text); 631 632 static const struct soc_enum cf_dec2_enum = 633 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text); 634 635 static const struct soc_enum cf_dec3_enum = 636 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text); 637 638 static const struct soc_enum cf_dec4_enum = 639 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text); 640 641 static const struct soc_enum cf_dec5_enum = 642 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text); 643 644 static const struct soc_enum cf_dec6_enum = 645 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text); 646 647 static const struct soc_enum cf_dec7_enum = 648 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text); 649 650 static const struct soc_enum cf_dec8_enum = 651 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text); 652 653 static const struct soc_enum cf_int0_1_enum = 654 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text); 655 656 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2, 657 rx_cf_text); 658 659 static const struct soc_enum cf_int1_1_enum = 660 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text); 661 662 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2, 663 rx_cf_text); 664 665 static const struct soc_enum cf_int2_1_enum = 666 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text); 667 668 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2, 669 rx_cf_text); 670 671 static const struct soc_enum cf_int3_1_enum = 672 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text); 673 674 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2, 675 rx_cf_text); 676 677 static const struct soc_enum cf_int4_1_enum = 678 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text); 679 680 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2, 681 rx_cf_text); 682 683 static const struct soc_enum cf_int5_1_enum = 684 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text); 685 686 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2, 687 rx_cf_text); 688 689 static const struct soc_enum cf_int6_1_enum = 690 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text); 691 692 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2, 693 rx_cf_text); 694 695 static const struct soc_enum cf_int7_1_enum = 696 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text); 697 698 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2, 699 rx_cf_text); 700 701 static const struct soc_enum cf_int8_1_enum = 702 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text); 703 704 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2, 705 rx_cf_text); 706 707 static const struct soc_enum rx_hph_mode_mux_enum = 708 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text), 709 rx_hph_mode_mux_text); 710 711 static const struct soc_enum slim_rx_mux_enum = 712 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text); 713 714 static const struct soc_enum rx_int0_2_mux_chain_enum = 715 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10, 716 rx_int0_7_mix_mux_text); 717 718 static const struct soc_enum rx_int1_2_mux_chain_enum = 719 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9, 720 rx_int_mix_mux_text); 721 722 static const struct soc_enum rx_int2_2_mux_chain_enum = 723 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9, 724 rx_int_mix_mux_text); 725 726 static const struct soc_enum rx_int3_2_mux_chain_enum = 727 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9, 728 rx_int_mix_mux_text); 729 730 static const struct soc_enum rx_int4_2_mux_chain_enum = 731 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9, 732 rx_int_mix_mux_text); 733 734 static const struct soc_enum rx_int5_2_mux_chain_enum = 735 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9, 736 rx_int_mix_mux_text); 737 738 static const struct soc_enum rx_int6_2_mux_chain_enum = 739 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9, 740 rx_int_mix_mux_text); 741 742 static const struct soc_enum rx_int7_2_mux_chain_enum = 743 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10, 744 rx_int0_7_mix_mux_text); 745 746 static const struct soc_enum rx_int8_2_mux_chain_enum = 747 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9, 748 rx_int_mix_mux_text); 749 750 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum = 751 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13, 752 rx_prim_mix_text); 753 754 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum = 755 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13, 756 rx_prim_mix_text); 757 758 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum = 759 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13, 760 rx_prim_mix_text); 761 762 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum = 763 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13, 764 rx_prim_mix_text); 765 766 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum = 767 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13, 768 rx_prim_mix_text); 769 770 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum = 771 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13, 772 rx_prim_mix_text); 773 774 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum = 775 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13, 776 rx_prim_mix_text); 777 778 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum = 779 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13, 780 rx_prim_mix_text); 781 782 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum = 783 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13, 784 rx_prim_mix_text); 785 786 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum = 787 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13, 788 rx_prim_mix_text); 789 790 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum = 791 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13, 792 rx_prim_mix_text); 793 794 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum = 795 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13, 796 rx_prim_mix_text); 797 798 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum = 799 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13, 800 rx_prim_mix_text); 801 802 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum = 803 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13, 804 rx_prim_mix_text); 805 806 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum = 807 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13, 808 rx_prim_mix_text); 809 810 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum = 811 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13, 812 rx_prim_mix_text); 813 814 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum = 815 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13, 816 rx_prim_mix_text); 817 818 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum = 819 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13, 820 rx_prim_mix_text); 821 822 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum = 823 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13, 824 rx_prim_mix_text); 825 826 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum = 827 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13, 828 rx_prim_mix_text); 829 830 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum = 831 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13, 832 rx_prim_mix_text); 833 834 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum = 835 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13, 836 rx_prim_mix_text); 837 838 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum = 839 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13, 840 rx_prim_mix_text); 841 842 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum = 843 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13, 844 rx_prim_mix_text); 845 846 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum = 847 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13, 848 rx_prim_mix_text); 849 850 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum = 851 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13, 852 rx_prim_mix_text); 853 854 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum = 855 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13, 856 rx_prim_mix_text); 857 858 static const struct soc_enum rx_int0_dem_inp_mux_enum = 859 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0, 860 ARRAY_SIZE(rx_int_dem_inp_mux_text), 861 rx_int_dem_inp_mux_text); 862 863 static const struct soc_enum rx_int1_dem_inp_mux_enum = 864 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0, 865 ARRAY_SIZE(rx_int_dem_inp_mux_text), 866 rx_int_dem_inp_mux_text); 867 868 static const struct soc_enum rx_int2_dem_inp_mux_enum = 869 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0, 870 ARRAY_SIZE(rx_int_dem_inp_mux_text), 871 rx_int_dem_inp_mux_text); 872 873 static const struct soc_enum rx_int0_interp_mux_enum = 874 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2, 875 rx_int0_interp_mux_text); 876 877 static const struct soc_enum rx_int1_interp_mux_enum = 878 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2, 879 rx_int1_interp_mux_text); 880 881 static const struct soc_enum rx_int2_interp_mux_enum = 882 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2, 883 rx_int2_interp_mux_text); 884 885 static const struct soc_enum rx_int3_interp_mux_enum = 886 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2, 887 rx_int3_interp_mux_text); 888 889 static const struct soc_enum rx_int4_interp_mux_enum = 890 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2, 891 rx_int4_interp_mux_text); 892 893 static const struct soc_enum rx_int5_interp_mux_enum = 894 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2, 895 rx_int5_interp_mux_text); 896 897 static const struct soc_enum rx_int6_interp_mux_enum = 898 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2, 899 rx_int6_interp_mux_text); 900 901 static const struct soc_enum rx_int7_interp_mux_enum = 902 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2, 903 rx_int7_interp_mux_text); 904 905 static const struct soc_enum rx_int8_interp_mux_enum = 906 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2, 907 rx_int8_interp_mux_text); 908 909 static const struct soc_enum tx_adc_mux0_chain_enum = 910 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4, 911 adc_mux_text); 912 913 static const struct soc_enum tx_adc_mux1_chain_enum = 914 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4, 915 adc_mux_text); 916 917 static const struct soc_enum tx_adc_mux2_chain_enum = 918 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4, 919 adc_mux_text); 920 921 static const struct soc_enum tx_adc_mux3_chain_enum = 922 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4, 923 adc_mux_text); 924 925 static const struct soc_enum tx_adc_mux4_chain_enum = 926 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4, 927 adc_mux_text); 928 929 static const struct soc_enum tx_adc_mux5_chain_enum = 930 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4, 931 adc_mux_text); 932 933 static const struct soc_enum tx_adc_mux6_chain_enum = 934 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4, 935 adc_mux_text); 936 937 static const struct soc_enum tx_adc_mux7_chain_enum = 938 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4, 939 adc_mux_text); 940 941 static const struct soc_enum tx_adc_mux8_chain_enum = 942 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4, 943 adc_mux_text); 944 945 static const struct soc_enum tx_dmic_mux0_enum = 946 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11, 947 dmic_mux_text); 948 949 static const struct soc_enum tx_dmic_mux1_enum = 950 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11, 951 dmic_mux_text); 952 953 static const struct soc_enum tx_dmic_mux2_enum = 954 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11, 955 dmic_mux_text); 956 957 static const struct soc_enum tx_dmic_mux3_enum = 958 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11, 959 dmic_mux_text); 960 961 static const struct soc_enum tx_dmic_mux4_enum = 962 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7, 963 dmic_mux_alt_text); 964 965 static const struct soc_enum tx_dmic_mux5_enum = 966 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7, 967 dmic_mux_alt_text); 968 969 static const struct soc_enum tx_dmic_mux6_enum = 970 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7, 971 dmic_mux_alt_text); 972 973 static const struct soc_enum tx_dmic_mux7_enum = 974 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7, 975 dmic_mux_alt_text); 976 977 static const struct soc_enum tx_dmic_mux8_enum = 978 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7, 979 dmic_mux_alt_text); 980 981 static const struct soc_enum tx_amic_mux0_enum = 982 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7, 983 amic_mux_text); 984 985 static const struct soc_enum tx_amic_mux1_enum = 986 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7, 987 amic_mux_text); 988 989 static const struct soc_enum tx_amic_mux2_enum = 990 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7, 991 amic_mux_text); 992 993 static const struct soc_enum tx_amic_mux3_enum = 994 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7, 995 amic_mux_text); 996 997 static const struct soc_enum tx_amic_mux4_enum = 998 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7, 999 amic_mux_text); 1000 1001 static const struct soc_enum tx_amic_mux5_enum = 1002 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7, 1003 amic_mux_text); 1004 1005 static const struct soc_enum tx_amic_mux6_enum = 1006 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7, 1007 amic_mux_text); 1008 1009 static const struct soc_enum tx_amic_mux7_enum = 1010 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7, 1011 amic_mux_text); 1012 1013 static const struct soc_enum tx_amic_mux8_enum = 1014 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7, 1015 amic_mux_text); 1016 1017 static const struct soc_enum sb_tx0_mux_enum = 1018 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4, 1019 sb_tx0_mux_text); 1020 1021 static const struct soc_enum sb_tx1_mux_enum = 1022 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4, 1023 sb_tx1_mux_text); 1024 1025 static const struct soc_enum sb_tx2_mux_enum = 1026 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4, 1027 sb_tx2_mux_text); 1028 1029 static const struct soc_enum sb_tx3_mux_enum = 1030 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4, 1031 sb_tx3_mux_text); 1032 1033 static const struct soc_enum sb_tx4_mux_enum = 1034 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4, 1035 sb_tx4_mux_text); 1036 1037 static const struct soc_enum sb_tx5_mux_enum = 1038 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4, 1039 sb_tx5_mux_text); 1040 1041 static const struct soc_enum sb_tx6_mux_enum = 1042 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4, 1043 sb_tx6_mux_text); 1044 1045 static const struct soc_enum sb_tx7_mux_enum = 1046 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4, 1047 sb_tx7_mux_text); 1048 1049 static const struct soc_enum sb_tx8_mux_enum = 1050 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4, 1051 sb_tx8_mux_text); 1052 1053 static const struct snd_kcontrol_new rx_int0_2_mux = 1054 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum); 1055 1056 static const struct snd_kcontrol_new rx_int1_2_mux = 1057 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum); 1058 1059 static const struct snd_kcontrol_new rx_int2_2_mux = 1060 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum); 1061 1062 static const struct snd_kcontrol_new rx_int3_2_mux = 1063 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum); 1064 1065 static const struct snd_kcontrol_new rx_int4_2_mux = 1066 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum); 1067 1068 static const struct snd_kcontrol_new rx_int5_2_mux = 1069 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum); 1070 1071 static const struct snd_kcontrol_new rx_int6_2_mux = 1072 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum); 1073 1074 static const struct snd_kcontrol_new rx_int7_2_mux = 1075 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum); 1076 1077 static const struct snd_kcontrol_new rx_int8_2_mux = 1078 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum); 1079 1080 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 1081 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum); 1082 1083 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 1084 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum); 1085 1086 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 1087 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum); 1088 1089 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 1090 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum); 1091 1092 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 1093 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum); 1094 1095 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 1096 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum); 1097 1098 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 1099 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum); 1100 1101 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 1102 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum); 1103 1104 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 1105 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum); 1106 1107 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux = 1108 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum); 1109 1110 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux = 1111 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum); 1112 1113 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux = 1114 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum); 1115 1116 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux = 1117 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum); 1118 1119 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux = 1120 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum); 1121 1122 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux = 1123 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum); 1124 1125 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux = 1126 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum); 1127 1128 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux = 1129 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum); 1130 1131 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux = 1132 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum); 1133 1134 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux = 1135 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum); 1136 1137 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux = 1138 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum); 1139 1140 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux = 1141 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum); 1142 1143 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux = 1144 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum); 1145 1146 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux = 1147 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum); 1148 1149 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux = 1150 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum); 1151 1152 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux = 1153 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum); 1154 1155 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux = 1156 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum); 1157 1158 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux = 1159 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum); 1160 1161 static const struct snd_kcontrol_new rx_int0_interp_mux = 1162 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum); 1163 1164 static const struct snd_kcontrol_new rx_int1_interp_mux = 1165 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum); 1166 1167 static const struct snd_kcontrol_new rx_int2_interp_mux = 1168 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum); 1169 1170 static const struct snd_kcontrol_new rx_int3_interp_mux = 1171 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum); 1172 1173 static const struct snd_kcontrol_new rx_int4_interp_mux = 1174 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum); 1175 1176 static const struct snd_kcontrol_new rx_int5_interp_mux = 1177 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum); 1178 1179 static const struct snd_kcontrol_new rx_int6_interp_mux = 1180 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum); 1181 1182 static const struct snd_kcontrol_new rx_int7_interp_mux = 1183 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum); 1184 1185 static const struct snd_kcontrol_new rx_int8_interp_mux = 1186 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum); 1187 1188 static const struct snd_kcontrol_new tx_dmic_mux0 = 1189 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum); 1190 1191 static const struct snd_kcontrol_new tx_dmic_mux1 = 1192 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum); 1193 1194 static const struct snd_kcontrol_new tx_dmic_mux2 = 1195 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum); 1196 1197 static const struct snd_kcontrol_new tx_dmic_mux3 = 1198 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum); 1199 1200 static const struct snd_kcontrol_new tx_dmic_mux4 = 1201 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum); 1202 1203 static const struct snd_kcontrol_new tx_dmic_mux5 = 1204 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum); 1205 1206 static const struct snd_kcontrol_new tx_dmic_mux6 = 1207 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum); 1208 1209 static const struct snd_kcontrol_new tx_dmic_mux7 = 1210 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum); 1211 1212 static const struct snd_kcontrol_new tx_dmic_mux8 = 1213 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum); 1214 1215 static const struct snd_kcontrol_new tx_amic_mux0 = 1216 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum); 1217 1218 static const struct snd_kcontrol_new tx_amic_mux1 = 1219 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum); 1220 1221 static const struct snd_kcontrol_new tx_amic_mux2 = 1222 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum); 1223 1224 static const struct snd_kcontrol_new tx_amic_mux3 = 1225 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum); 1226 1227 static const struct snd_kcontrol_new tx_amic_mux4 = 1228 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum); 1229 1230 static const struct snd_kcontrol_new tx_amic_mux5 = 1231 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum); 1232 1233 static const struct snd_kcontrol_new tx_amic_mux6 = 1234 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum); 1235 1236 static const struct snd_kcontrol_new tx_amic_mux7 = 1237 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum); 1238 1239 static const struct snd_kcontrol_new tx_amic_mux8 = 1240 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum); 1241 1242 static const struct snd_kcontrol_new sb_tx0_mux = 1243 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum); 1244 1245 static const struct snd_kcontrol_new sb_tx1_mux = 1246 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum); 1247 1248 static const struct snd_kcontrol_new sb_tx2_mux = 1249 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum); 1250 1251 static const struct snd_kcontrol_new sb_tx3_mux = 1252 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum); 1253 1254 static const struct snd_kcontrol_new sb_tx4_mux = 1255 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum); 1256 1257 static const struct snd_kcontrol_new sb_tx5_mux = 1258 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum); 1259 1260 static const struct snd_kcontrol_new sb_tx6_mux = 1261 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum); 1262 1263 static const struct snd_kcontrol_new sb_tx7_mux = 1264 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum); 1265 1266 static const struct snd_kcontrol_new sb_tx8_mux = 1267 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum); 1268 1269 static int slim_rx_mux_get(struct snd_kcontrol *kc, 1270 struct snd_ctl_elem_value *ucontrol) 1271 { 1272 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1273 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev); 1274 1275 ucontrol->value.enumerated.item[0] = wcd->rx_port_value; 1276 1277 return 0; 1278 } 1279 1280 static int slim_rx_mux_put(struct snd_kcontrol *kc, 1281 struct snd_ctl_elem_value *ucontrol) 1282 { 1283 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc); 1284 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev); 1285 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1286 struct snd_soc_dapm_update *update = NULL; 1287 u32 port_id = w->shift; 1288 1289 wcd->rx_port_value = ucontrol->value.enumerated.item[0]; 1290 1291 switch (wcd->rx_port_value) { 1292 case 0: 1293 list_del_init(&wcd->rx_chs[port_id].list); 1294 break; 1295 case 1: 1296 list_add_tail(&wcd->rx_chs[port_id].list, 1297 &wcd->dai[AIF1_PB].slim_ch_list); 1298 break; 1299 case 2: 1300 list_add_tail(&wcd->rx_chs[port_id].list, 1301 &wcd->dai[AIF2_PB].slim_ch_list); 1302 break; 1303 case 3: 1304 list_add_tail(&wcd->rx_chs[port_id].list, 1305 &wcd->dai[AIF3_PB].slim_ch_list); 1306 break; 1307 case 4: 1308 list_add_tail(&wcd->rx_chs[port_id].list, 1309 &wcd->dai[AIF4_PB].slim_ch_list); 1310 break; 1311 default: 1312 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value); 1313 goto err; 1314 } 1315 1316 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value, 1317 e, update); 1318 1319 return 0; 1320 err: 1321 return -EINVAL; 1322 } 1323 1324 static int slim_tx_mixer_get(struct snd_kcontrol *kc, 1325 struct snd_ctl_elem_value *ucontrol) 1326 { 1327 1328 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1329 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev); 1330 1331 ucontrol->value.integer.value[0] = wcd->tx_port_value; 1332 1333 return 0; 1334 } 1335 1336 static int slim_tx_mixer_put(struct snd_kcontrol *kc, 1337 struct snd_ctl_elem_value *ucontrol) 1338 { 1339 1340 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc); 1341 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev); 1342 struct snd_soc_dapm_update *update = NULL; 1343 struct soc_mixer_control *mixer = 1344 (struct soc_mixer_control *)kc->private_value; 1345 int enable = ucontrol->value.integer.value[0]; 1346 int dai_id = widget->shift; 1347 int port_id = mixer->shift; 1348 1349 switch (dai_id) { 1350 case AIF1_CAP: 1351 case AIF2_CAP: 1352 case AIF3_CAP: 1353 /* only add to the list if value not set */ 1354 if (enable && !(wcd->tx_port_value & BIT(port_id))) { 1355 wcd->tx_port_value |= BIT(port_id); 1356 list_add_tail(&wcd->tx_chs[port_id].list, 1357 &wcd->dai[dai_id].slim_ch_list); 1358 } else if (!enable && (wcd->tx_port_value & BIT(port_id))) { 1359 wcd->tx_port_value &= ~BIT(port_id); 1360 list_del_init(&wcd->tx_chs[port_id].list); 1361 } 1362 break; 1363 default: 1364 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id); 1365 return -EINVAL; 1366 } 1367 1368 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update); 1369 1370 return 0; 1371 } 1372 1373 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = { 1374 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum, 1375 slim_rx_mux_get, slim_rx_mux_put), 1376 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum, 1377 slim_rx_mux_get, slim_rx_mux_put), 1378 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum, 1379 slim_rx_mux_get, slim_rx_mux_put), 1380 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum, 1381 slim_rx_mux_get, slim_rx_mux_put), 1382 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum, 1383 slim_rx_mux_get, slim_rx_mux_put), 1384 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum, 1385 slim_rx_mux_get, slim_rx_mux_put), 1386 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum, 1387 slim_rx_mux_get, slim_rx_mux_put), 1388 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum, 1389 slim_rx_mux_get, slim_rx_mux_put), 1390 }; 1391 1392 static const struct snd_kcontrol_new aif1_cap_mixer[] = { 1393 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1394 slim_tx_mixer_get, slim_tx_mixer_put), 1395 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1396 slim_tx_mixer_get, slim_tx_mixer_put), 1397 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1398 slim_tx_mixer_get, slim_tx_mixer_put), 1399 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1400 slim_tx_mixer_get, slim_tx_mixer_put), 1401 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1402 slim_tx_mixer_get, slim_tx_mixer_put), 1403 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1404 slim_tx_mixer_get, slim_tx_mixer_put), 1405 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1406 slim_tx_mixer_get, slim_tx_mixer_put), 1407 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1408 slim_tx_mixer_get, slim_tx_mixer_put), 1409 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1410 slim_tx_mixer_get, slim_tx_mixer_put), 1411 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1412 slim_tx_mixer_get, slim_tx_mixer_put), 1413 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1414 slim_tx_mixer_get, slim_tx_mixer_put), 1415 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1416 slim_tx_mixer_get, slim_tx_mixer_put), 1417 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1418 slim_tx_mixer_get, slim_tx_mixer_put), 1419 }; 1420 1421 static const struct snd_kcontrol_new aif2_cap_mixer[] = { 1422 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1423 slim_tx_mixer_get, slim_tx_mixer_put), 1424 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1425 slim_tx_mixer_get, slim_tx_mixer_put), 1426 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1427 slim_tx_mixer_get, slim_tx_mixer_put), 1428 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1429 slim_tx_mixer_get, slim_tx_mixer_put), 1430 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1431 slim_tx_mixer_get, slim_tx_mixer_put), 1432 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1433 slim_tx_mixer_get, slim_tx_mixer_put), 1434 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1435 slim_tx_mixer_get, slim_tx_mixer_put), 1436 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1437 slim_tx_mixer_get, slim_tx_mixer_put), 1438 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1439 slim_tx_mixer_get, slim_tx_mixer_put), 1440 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0, 1441 slim_tx_mixer_get, slim_tx_mixer_put), 1442 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0, 1443 slim_tx_mixer_get, slim_tx_mixer_put), 1444 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0, 1445 slim_tx_mixer_get, slim_tx_mixer_put), 1446 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0, 1447 slim_tx_mixer_get, slim_tx_mixer_put), 1448 }; 1449 1450 static const struct snd_kcontrol_new aif3_cap_mixer[] = { 1451 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0, 1452 slim_tx_mixer_get, slim_tx_mixer_put), 1453 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0, 1454 slim_tx_mixer_get, slim_tx_mixer_put), 1455 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0, 1456 slim_tx_mixer_get, slim_tx_mixer_put), 1457 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0, 1458 slim_tx_mixer_get, slim_tx_mixer_put), 1459 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0, 1460 slim_tx_mixer_get, slim_tx_mixer_put), 1461 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0, 1462 slim_tx_mixer_get, slim_tx_mixer_put), 1463 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0, 1464 slim_tx_mixer_get, slim_tx_mixer_put), 1465 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0, 1466 slim_tx_mixer_get, slim_tx_mixer_put), 1467 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0, 1468 slim_tx_mixer_get, slim_tx_mixer_put), 1469 }; 1470 1471 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc, 1472 struct snd_ctl_elem_value *ucontrol) 1473 { 1474 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc); 1475 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); 1476 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1477 unsigned int val, reg, sel; 1478 1479 val = ucontrol->value.enumerated.item[0]; 1480 1481 switch (e->reg) { 1482 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1: 1483 reg = WCD9335_CDC_TX0_TX_PATH_CFG0; 1484 break; 1485 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1: 1486 reg = WCD9335_CDC_TX1_TX_PATH_CFG0; 1487 break; 1488 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1: 1489 reg = WCD9335_CDC_TX2_TX_PATH_CFG0; 1490 break; 1491 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1: 1492 reg = WCD9335_CDC_TX3_TX_PATH_CFG0; 1493 break; 1494 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0: 1495 reg = WCD9335_CDC_TX4_TX_PATH_CFG0; 1496 break; 1497 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0: 1498 reg = WCD9335_CDC_TX5_TX_PATH_CFG0; 1499 break; 1500 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0: 1501 reg = WCD9335_CDC_TX6_TX_PATH_CFG0; 1502 break; 1503 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0: 1504 reg = WCD9335_CDC_TX7_TX_PATH_CFG0; 1505 break; 1506 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0: 1507 reg = WCD9335_CDC_TX8_TX_PATH_CFG0; 1508 break; 1509 default: 1510 return -EINVAL; 1511 } 1512 1513 /* AMIC: 0, DMIC: 1 */ 1514 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL; 1515 snd_soc_component_update_bits(component, reg, 1516 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK, 1517 sel); 1518 1519 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1520 } 1521 1522 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc, 1523 struct snd_ctl_elem_value *ucontrol) 1524 { 1525 struct soc_enum *e = (struct soc_enum *)kc->private_value; 1526 struct snd_soc_component *component; 1527 int reg, val; 1528 1529 component = snd_soc_dapm_kcontrol_component(kc); 1530 val = ucontrol->value.enumerated.item[0]; 1531 1532 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0) 1533 reg = WCD9335_CDC_RX0_RX_PATH_CFG0; 1534 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0) 1535 reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 1536 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0) 1537 reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 1538 else 1539 return -EINVAL; 1540 1541 /* Set Look Ahead Delay */ 1542 snd_soc_component_update_bits(component, reg, 1543 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK, 1544 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0); 1545 /* Set DEM INP Select */ 1546 return snd_soc_dapm_put_enum_double(kc, ucontrol); 1547 } 1548 1549 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 1550 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum, 1551 snd_soc_dapm_get_enum_double, 1552 wcd9335_int_dem_inp_mux_put); 1553 1554 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 1555 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum, 1556 snd_soc_dapm_get_enum_double, 1557 wcd9335_int_dem_inp_mux_put); 1558 1559 static const struct snd_kcontrol_new rx_int2_dem_inp_mux = 1560 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum, 1561 snd_soc_dapm_get_enum_double, 1562 wcd9335_int_dem_inp_mux_put); 1563 1564 static const struct snd_kcontrol_new tx_adc_mux0 = 1565 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum, 1566 snd_soc_dapm_get_enum_double, 1567 wcd9335_put_dec_enum); 1568 1569 static const struct snd_kcontrol_new tx_adc_mux1 = 1570 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum, 1571 snd_soc_dapm_get_enum_double, 1572 wcd9335_put_dec_enum); 1573 1574 static const struct snd_kcontrol_new tx_adc_mux2 = 1575 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum, 1576 snd_soc_dapm_get_enum_double, 1577 wcd9335_put_dec_enum); 1578 1579 static const struct snd_kcontrol_new tx_adc_mux3 = 1580 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum, 1581 snd_soc_dapm_get_enum_double, 1582 wcd9335_put_dec_enum); 1583 1584 static const struct snd_kcontrol_new tx_adc_mux4 = 1585 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum, 1586 snd_soc_dapm_get_enum_double, 1587 wcd9335_put_dec_enum); 1588 1589 static const struct snd_kcontrol_new tx_adc_mux5 = 1590 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum, 1591 snd_soc_dapm_get_enum_double, 1592 wcd9335_put_dec_enum); 1593 1594 static const struct snd_kcontrol_new tx_adc_mux6 = 1595 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum, 1596 snd_soc_dapm_get_enum_double, 1597 wcd9335_put_dec_enum); 1598 1599 static const struct snd_kcontrol_new tx_adc_mux7 = 1600 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum, 1601 snd_soc_dapm_get_enum_double, 1602 wcd9335_put_dec_enum); 1603 1604 static const struct snd_kcontrol_new tx_adc_mux8 = 1605 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum, 1606 snd_soc_dapm_get_enum_double, 1607 wcd9335_put_dec_enum); 1608 1609 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1610 int rate_val, 1611 u32 rate) 1612 { 1613 struct snd_soc_component *component = dai->component; 1614 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 1615 struct wcd9335_slim_ch *ch; 1616 int val, j; 1617 1618 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1619 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1620 val = snd_soc_component_read32(component, 1621 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) & 1622 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1623 1624 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) 1625 snd_soc_component_update_bits(component, 1626 WCD9335_CDC_RX_PATH_MIX_CTL(j), 1627 WCD9335_CDC_MIX_PCM_RATE_MASK, 1628 rate_val); 1629 } 1630 } 1631 1632 return 0; 1633 } 1634 1635 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1636 u8 rate_val, 1637 u32 rate) 1638 { 1639 struct snd_soc_component *comp = dai->component; 1640 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 1641 struct wcd9335_slim_ch *ch; 1642 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel; 1643 int inp, j; 1644 1645 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1646 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0; 1647 /* 1648 * Loop through all interpolator MUX inputs and find out 1649 * to which interpolator input, the slim rx port 1650 * is connected 1651 */ 1652 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) { 1653 cfg0 = snd_soc_component_read32(comp, 1654 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j)); 1655 cfg1 = snd_soc_component_read32(comp, 1656 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)); 1657 1658 inp0_sel = cfg0 & 1659 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1660 inp1_sel = (cfg0 >> 4) & 1661 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1662 inp2_sel = (cfg1 >> 4) & 1663 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK; 1664 1665 if ((inp0_sel == inp) || (inp1_sel == inp) || 1666 (inp2_sel == inp)) { 1667 /* rate is in Hz */ 1668 if ((j == 0) && (rate == 44100)) 1669 dev_info(wcd->dev, 1670 "Cannot set 44.1KHz on INT0\n"); 1671 else 1672 snd_soc_component_update_bits(comp, 1673 WCD9335_CDC_RX_PATH_CTL(j), 1674 WCD9335_CDC_MIX_PCM_RATE_MASK, 1675 rate_val); 1676 } 1677 } 1678 } 1679 1680 return 0; 1681 } 1682 1683 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate) 1684 { 1685 int i; 1686 1687 /* set mixing path rate */ 1688 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) { 1689 if (rate == int_mix_rate_val[i].rate) { 1690 wcd9335_set_mix_interpolator_rate(dai, 1691 int_mix_rate_val[i].rate_val, rate); 1692 break; 1693 } 1694 } 1695 1696 /* set primary path sample rate */ 1697 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) { 1698 if (rate == int_prim_rate_val[i].rate) { 1699 wcd9335_set_prim_interpolator_rate(dai, 1700 int_prim_rate_val[i].rate_val, rate); 1701 break; 1702 } 1703 } 1704 1705 return 0; 1706 } 1707 1708 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd, 1709 struct wcd_slim_codec_dai_data *dai_data, 1710 int direction) 1711 { 1712 struct list_head *slim_ch_list = &dai_data->slim_ch_list; 1713 struct slim_stream_config *cfg = &dai_data->sconfig; 1714 struct wcd9335_slim_ch *ch; 1715 u16 payload = 0; 1716 int ret, i; 1717 1718 cfg->ch_count = 0; 1719 cfg->direction = direction; 1720 cfg->port_mask = 0; 1721 1722 /* Configure slave interface device */ 1723 list_for_each_entry(ch, slim_ch_list, list) { 1724 cfg->ch_count++; 1725 payload |= 1 << ch->shift; 1726 cfg->port_mask |= BIT(ch->port); 1727 } 1728 1729 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL); 1730 if (!cfg->chs) 1731 return -ENOMEM; 1732 1733 i = 0; 1734 list_for_each_entry(ch, slim_ch_list, list) { 1735 cfg->chs[i++] = ch->ch_num; 1736 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1737 /* write to interface device */ 1738 ret = regmap_write(wcd->if_regmap, 1739 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port), 1740 payload); 1741 1742 if (ret < 0) 1743 goto err; 1744 1745 /* configure the slave port for water mark and enable*/ 1746 ret = regmap_write(wcd->if_regmap, 1747 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port), 1748 WCD9335_SLIM_WATER_MARK_VAL); 1749 if (ret < 0) 1750 goto err; 1751 } else { 1752 ret = regmap_write(wcd->if_regmap, 1753 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port), 1754 payload & 0x00FF); 1755 if (ret < 0) 1756 goto err; 1757 1758 /* ports 8,9 */ 1759 ret = regmap_write(wcd->if_regmap, 1760 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port), 1761 (payload & 0xFF00)>>8); 1762 if (ret < 0) 1763 goto err; 1764 1765 /* configure the slave port for water mark and enable*/ 1766 ret = regmap_write(wcd->if_regmap, 1767 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port), 1768 WCD9335_SLIM_WATER_MARK_VAL); 1769 1770 if (ret < 0) 1771 goto err; 1772 } 1773 } 1774 1775 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM"); 1776 1777 return 0; 1778 1779 err: 1780 dev_err(wcd->dev, "Error Setting slim hw params\n"); 1781 kfree(cfg->chs); 1782 cfg->chs = NULL; 1783 1784 return ret; 1785 } 1786 1787 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai, 1788 u8 rate_val, u32 rate) 1789 { 1790 struct snd_soc_component *comp = dai->component; 1791 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 1792 u8 shift = 0, shift_val = 0, tx_mux_sel; 1793 struct wcd9335_slim_ch *ch; 1794 int tx_port, tx_port_reg; 1795 int decimator = -1; 1796 1797 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) { 1798 tx_port = ch->port; 1799 if ((tx_port == 12) || (tx_port >= 14)) { 1800 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n", 1801 tx_port, dai->id); 1802 return -EINVAL; 1803 } 1804 /* Find the SB TX MUX input - which decimator is connected */ 1805 if (tx_port < 4) { 1806 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0; 1807 shift = (tx_port << 1); 1808 shift_val = 0x03; 1809 } else if ((tx_port >= 4) && (tx_port < 8)) { 1810 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1; 1811 shift = ((tx_port - 4) << 1); 1812 shift_val = 0x03; 1813 } else if ((tx_port >= 8) && (tx_port < 11)) { 1814 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2; 1815 shift = ((tx_port - 8) << 1); 1816 shift_val = 0x03; 1817 } else if (tx_port == 11) { 1818 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1819 shift = 0; 1820 shift_val = 0x0F; 1821 } else if (tx_port == 13) { 1822 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3; 1823 shift = 4; 1824 shift_val = 0x03; 1825 } else { 1826 return -EINVAL; 1827 } 1828 1829 tx_mux_sel = snd_soc_component_read32(comp, tx_port_reg) & 1830 (shift_val << shift); 1831 1832 tx_mux_sel = tx_mux_sel >> shift; 1833 if (tx_port <= 8) { 1834 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3)) 1835 decimator = tx_port; 1836 } else if (tx_port <= 10) { 1837 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1838 decimator = ((tx_port == 9) ? 7 : 6); 1839 } else if (tx_port == 11) { 1840 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7)) 1841 decimator = tx_mux_sel - 1; 1842 } else if (tx_port == 13) { 1843 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2)) 1844 decimator = 5; 1845 } 1846 1847 if (decimator >= 0) { 1848 snd_soc_component_update_bits(comp, 1849 WCD9335_CDC_TX_PATH_CTL(decimator), 1850 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK, 1851 rate_val); 1852 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) { 1853 /* Check if the TX Mux input is RX MIX TXn */ 1854 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n", 1855 tx_port, tx_port); 1856 } else { 1857 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n", 1858 decimator); 1859 return -EINVAL; 1860 } 1861 } 1862 1863 return 0; 1864 } 1865 1866 static int wcd9335_hw_params(struct snd_pcm_substream *substream, 1867 struct snd_pcm_hw_params *params, 1868 struct snd_soc_dai *dai) 1869 { 1870 struct wcd9335_codec *wcd; 1871 int ret, tx_fs_rate = 0; 1872 1873 wcd = snd_soc_component_get_drvdata(dai->component); 1874 1875 switch (substream->stream) { 1876 case SNDRV_PCM_STREAM_PLAYBACK: 1877 ret = wcd9335_set_interpolator_rate(dai, params_rate(params)); 1878 if (ret) { 1879 dev_err(wcd->dev, "cannot set sample rate: %u\n", 1880 params_rate(params)); 1881 return ret; 1882 } 1883 switch (params_width(params)) { 1884 case 16 ... 24: 1885 wcd->dai[dai->id].sconfig.bps = params_width(params); 1886 break; 1887 default: 1888 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1889 __func__, params_width(params)); 1890 return -EINVAL; 1891 } 1892 break; 1893 1894 case SNDRV_PCM_STREAM_CAPTURE: 1895 switch (params_rate(params)) { 1896 case 8000: 1897 tx_fs_rate = 0; 1898 break; 1899 case 16000: 1900 tx_fs_rate = 1; 1901 break; 1902 case 32000: 1903 tx_fs_rate = 3; 1904 break; 1905 case 48000: 1906 tx_fs_rate = 4; 1907 break; 1908 case 96000: 1909 tx_fs_rate = 5; 1910 break; 1911 case 192000: 1912 tx_fs_rate = 6; 1913 break; 1914 case 384000: 1915 tx_fs_rate = 7; 1916 break; 1917 default: 1918 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n", 1919 __func__, params_rate(params)); 1920 return -EINVAL; 1921 1922 }; 1923 1924 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate, 1925 params_rate(params)); 1926 if (ret < 0) { 1927 dev_err(wcd->dev, "Cannot set TX Decimator rate\n"); 1928 return ret; 1929 } 1930 switch (params_width(params)) { 1931 case 16 ... 32: 1932 wcd->dai[dai->id].sconfig.bps = params_width(params); 1933 break; 1934 default: 1935 dev_err(wcd->dev, "%s: Invalid format 0x%x\n", 1936 __func__, params_width(params)); 1937 return -EINVAL; 1938 }; 1939 break; 1940 default: 1941 dev_err(wcd->dev, "Invalid stream type %d\n", 1942 substream->stream); 1943 return -EINVAL; 1944 }; 1945 1946 wcd->dai[dai->id].sconfig.rate = params_rate(params); 1947 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream); 1948 1949 return 0; 1950 } 1951 1952 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd, 1953 struct snd_soc_dai *dai) 1954 { 1955 struct wcd_slim_codec_dai_data *dai_data; 1956 struct wcd9335_codec *wcd; 1957 struct slim_stream_config *cfg; 1958 1959 wcd = snd_soc_component_get_drvdata(dai->component); 1960 1961 dai_data = &wcd->dai[dai->id]; 1962 1963 switch (cmd) { 1964 case SNDRV_PCM_TRIGGER_START: 1965 case SNDRV_PCM_TRIGGER_RESUME: 1966 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1967 cfg = &dai_data->sconfig; 1968 slim_stream_prepare(dai_data->sruntime, cfg); 1969 slim_stream_enable(dai_data->sruntime); 1970 break; 1971 case SNDRV_PCM_TRIGGER_STOP: 1972 case SNDRV_PCM_TRIGGER_SUSPEND: 1973 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1974 slim_stream_unprepare(dai_data->sruntime); 1975 slim_stream_disable(dai_data->sruntime); 1976 break; 1977 default: 1978 break; 1979 } 1980 1981 return 0; 1982 } 1983 1984 static int wcd9335_set_channel_map(struct snd_soc_dai *dai, 1985 unsigned int tx_num, unsigned int *tx_slot, 1986 unsigned int rx_num, unsigned int *rx_slot) 1987 { 1988 struct wcd9335_codec *wcd; 1989 int i; 1990 1991 wcd = snd_soc_component_get_drvdata(dai->component); 1992 1993 if (!tx_slot || !rx_slot) { 1994 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n", 1995 tx_slot, rx_slot); 1996 return -EINVAL; 1997 } 1998 1999 wcd->num_rx_port = rx_num; 2000 for (i = 0; i < rx_num; i++) { 2001 wcd->rx_chs[i].ch_num = rx_slot[i]; 2002 INIT_LIST_HEAD(&wcd->rx_chs[i].list); 2003 } 2004 2005 wcd->num_tx_port = tx_num; 2006 for (i = 0; i < tx_num; i++) { 2007 wcd->tx_chs[i].ch_num = tx_slot[i]; 2008 INIT_LIST_HEAD(&wcd->tx_chs[i].list); 2009 } 2010 2011 return 0; 2012 } 2013 2014 static int wcd9335_get_channel_map(struct snd_soc_dai *dai, 2015 unsigned int *tx_num, unsigned int *tx_slot, 2016 unsigned int *rx_num, unsigned int *rx_slot) 2017 { 2018 struct wcd9335_slim_ch *ch; 2019 struct wcd9335_codec *wcd; 2020 int i = 0; 2021 2022 wcd = snd_soc_component_get_drvdata(dai->component); 2023 2024 switch (dai->id) { 2025 case AIF1_PB: 2026 case AIF2_PB: 2027 case AIF3_PB: 2028 case AIF4_PB: 2029 if (!rx_slot || !rx_num) { 2030 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n", 2031 rx_slot, rx_num); 2032 return -EINVAL; 2033 } 2034 2035 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2036 rx_slot[i++] = ch->ch_num; 2037 2038 *rx_num = i; 2039 break; 2040 case AIF1_CAP: 2041 case AIF2_CAP: 2042 case AIF3_CAP: 2043 if (!tx_slot || !tx_num) { 2044 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n", 2045 tx_slot, tx_num); 2046 return -EINVAL; 2047 } 2048 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) 2049 tx_slot[i++] = ch->ch_num; 2050 2051 *tx_num = i; 2052 break; 2053 default: 2054 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id); 2055 break; 2056 } 2057 2058 return 0; 2059 } 2060 2061 static struct snd_soc_dai_ops wcd9335_dai_ops = { 2062 .hw_params = wcd9335_hw_params, 2063 .trigger = wcd9335_trigger, 2064 .set_channel_map = wcd9335_set_channel_map, 2065 .get_channel_map = wcd9335_get_channel_map, 2066 }; 2067 2068 static struct snd_soc_dai_driver wcd9335_slim_dais[] = { 2069 [0] = { 2070 .name = "wcd9335_rx1", 2071 .id = AIF1_PB, 2072 .playback = { 2073 .stream_name = "AIF1 Playback", 2074 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2075 SNDRV_PCM_RATE_384000, 2076 .formats = WCD9335_FORMATS_S16_S24_LE, 2077 .rate_max = 384000, 2078 .rate_min = 8000, 2079 .channels_min = 1, 2080 .channels_max = 2, 2081 }, 2082 .ops = &wcd9335_dai_ops, 2083 }, 2084 [1] = { 2085 .name = "wcd9335_tx1", 2086 .id = AIF1_CAP, 2087 .capture = { 2088 .stream_name = "AIF1 Capture", 2089 .rates = WCD9335_RATES_MASK, 2090 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2091 .rate_min = 8000, 2092 .rate_max = 192000, 2093 .channels_min = 1, 2094 .channels_max = 4, 2095 }, 2096 .ops = &wcd9335_dai_ops, 2097 }, 2098 [2] = { 2099 .name = "wcd9335_rx2", 2100 .id = AIF2_PB, 2101 .playback = { 2102 .stream_name = "AIF2 Playback", 2103 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2104 SNDRV_PCM_RATE_384000, 2105 .formats = WCD9335_FORMATS_S16_S24_LE, 2106 .rate_min = 8000, 2107 .rate_max = 384000, 2108 .channels_min = 1, 2109 .channels_max = 2, 2110 }, 2111 .ops = &wcd9335_dai_ops, 2112 }, 2113 [3] = { 2114 .name = "wcd9335_tx2", 2115 .id = AIF2_CAP, 2116 .capture = { 2117 .stream_name = "AIF2 Capture", 2118 .rates = WCD9335_RATES_MASK, 2119 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2120 .rate_min = 8000, 2121 .rate_max = 192000, 2122 .channels_min = 1, 2123 .channels_max = 4, 2124 }, 2125 .ops = &wcd9335_dai_ops, 2126 }, 2127 [4] = { 2128 .name = "wcd9335_rx3", 2129 .id = AIF3_PB, 2130 .playback = { 2131 .stream_name = "AIF3 Playback", 2132 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2133 SNDRV_PCM_RATE_384000, 2134 .formats = WCD9335_FORMATS_S16_S24_LE, 2135 .rate_min = 8000, 2136 .rate_max = 384000, 2137 .channels_min = 1, 2138 .channels_max = 2, 2139 }, 2140 .ops = &wcd9335_dai_ops, 2141 }, 2142 [5] = { 2143 .name = "wcd9335_tx3", 2144 .id = AIF3_CAP, 2145 .capture = { 2146 .stream_name = "AIF3 Capture", 2147 .rates = WCD9335_RATES_MASK, 2148 .formats = SNDRV_PCM_FMTBIT_S16_LE, 2149 .rate_min = 8000, 2150 .rate_max = 192000, 2151 .channels_min = 1, 2152 .channels_max = 4, 2153 }, 2154 .ops = &wcd9335_dai_ops, 2155 }, 2156 [6] = { 2157 .name = "wcd9335_rx4", 2158 .id = AIF4_PB, 2159 .playback = { 2160 .stream_name = "AIF4 Playback", 2161 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK | 2162 SNDRV_PCM_RATE_384000, 2163 .formats = WCD9335_FORMATS_S16_S24_LE, 2164 .rate_min = 8000, 2165 .rate_max = 384000, 2166 .channels_min = 1, 2167 .channels_max = 2, 2168 }, 2169 .ops = &wcd9335_dai_ops, 2170 }, 2171 }; 2172 2173 static int wcd9335_get_compander(struct snd_kcontrol *kc, 2174 struct snd_ctl_elem_value *ucontrol) 2175 { 2176 2177 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2178 int comp = ((struct soc_mixer_control *)kc->private_value)->shift; 2179 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2180 2181 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp]; 2182 return 0; 2183 } 2184 2185 static int wcd9335_set_compander(struct snd_kcontrol *kc, 2186 struct snd_ctl_elem_value *ucontrol) 2187 { 2188 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2189 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2190 int comp = ((struct soc_mixer_control *) kc->private_value)->shift; 2191 int value = ucontrol->value.integer.value[0]; 2192 int sel; 2193 2194 wcd->comp_enabled[comp] = value; 2195 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER : 2196 WCD9335_HPH_GAIN_SRC_SEL_REGISTER; 2197 2198 /* Any specific register configuration for compander */ 2199 switch (comp) { 2200 case COMPANDER_1: 2201 /* Set Gain Source Select based on compander enable/disable */ 2202 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 2203 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2204 break; 2205 case COMPANDER_2: 2206 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 2207 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2208 break; 2209 case COMPANDER_5: 2210 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN, 2211 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2212 break; 2213 case COMPANDER_6: 2214 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN, 2215 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel); 2216 break; 2217 default: 2218 break; 2219 }; 2220 2221 return 0; 2222 } 2223 2224 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc, 2225 struct snd_ctl_elem_value *ucontrol) 2226 { 2227 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2228 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2229 2230 ucontrol->value.enumerated.item[0] = wcd->hph_mode; 2231 2232 return 0; 2233 } 2234 2235 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc, 2236 struct snd_ctl_elem_value *ucontrol) 2237 { 2238 struct snd_soc_component *component = snd_soc_kcontrol_component(kc); 2239 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 2240 u32 mode_val; 2241 2242 mode_val = ucontrol->value.enumerated.item[0]; 2243 2244 if (mode_val == 0) { 2245 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n"); 2246 mode_val = CLS_H_HIFI; 2247 } 2248 wcd->hph_mode = mode_val; 2249 2250 return 0; 2251 } 2252 2253 static const struct snd_kcontrol_new wcd9335_snd_controls[] = { 2254 /* -84dB min - 40dB max */ 2255 SOC_SINGLE_SX_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL, 2256 0, -84, 40, digital_gain), 2257 SOC_SINGLE_SX_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL, 2258 0, -84, 40, digital_gain), 2259 SOC_SINGLE_SX_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL, 2260 0, -84, 40, digital_gain), 2261 SOC_SINGLE_SX_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL, 2262 0, -84, 40, digital_gain), 2263 SOC_SINGLE_SX_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL, 2264 0, -84, 40, digital_gain), 2265 SOC_SINGLE_SX_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL, 2266 0, -84, 40, digital_gain), 2267 SOC_SINGLE_SX_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL, 2268 0, -84, 40, digital_gain), 2269 SOC_SINGLE_SX_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL, 2270 0, -84, 40, digital_gain), 2271 SOC_SINGLE_SX_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL, 2272 0, -84, 40, digital_gain), 2273 SOC_SINGLE_SX_TLV("RX0 Mix Digital Volume", 2274 WCD9335_CDC_RX0_RX_VOL_MIX_CTL, 2275 0, -84, 40, digital_gain), 2276 SOC_SINGLE_SX_TLV("RX1 Mix Digital Volume", 2277 WCD9335_CDC_RX1_RX_VOL_MIX_CTL, 2278 0, -84, 40, digital_gain), 2279 SOC_SINGLE_SX_TLV("RX2 Mix Digital Volume", 2280 WCD9335_CDC_RX2_RX_VOL_MIX_CTL, 2281 0, -84, 40, digital_gain), 2282 SOC_SINGLE_SX_TLV("RX3 Mix Digital Volume", 2283 WCD9335_CDC_RX3_RX_VOL_MIX_CTL, 2284 0, -84, 40, digital_gain), 2285 SOC_SINGLE_SX_TLV("RX4 Mix Digital Volume", 2286 WCD9335_CDC_RX4_RX_VOL_MIX_CTL, 2287 0, -84, 40, digital_gain), 2288 SOC_SINGLE_SX_TLV("RX5 Mix Digital Volume", 2289 WCD9335_CDC_RX5_RX_VOL_MIX_CTL, 2290 0, -84, 40, digital_gain), 2291 SOC_SINGLE_SX_TLV("RX6 Mix Digital Volume", 2292 WCD9335_CDC_RX6_RX_VOL_MIX_CTL, 2293 0, -84, 40, digital_gain), 2294 SOC_SINGLE_SX_TLV("RX7 Mix Digital Volume", 2295 WCD9335_CDC_RX7_RX_VOL_MIX_CTL, 2296 0, -84, 40, digital_gain), 2297 SOC_SINGLE_SX_TLV("RX8 Mix Digital Volume", 2298 WCD9335_CDC_RX8_RX_VOL_MIX_CTL, 2299 0, -84, 40, digital_gain), 2300 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum), 2301 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum), 2302 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum), 2303 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum), 2304 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum), 2305 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum), 2306 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum), 2307 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum), 2308 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum), 2309 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum), 2310 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum), 2311 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum), 2312 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum), 2313 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum), 2314 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum), 2315 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum), 2316 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum), 2317 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum), 2318 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0, 2319 wcd9335_get_compander, wcd9335_set_compander), 2320 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0, 2321 wcd9335_get_compander, wcd9335_set_compander), 2322 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0, 2323 wcd9335_get_compander, wcd9335_set_compander), 2324 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0, 2325 wcd9335_get_compander, wcd9335_set_compander), 2326 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0, 2327 wcd9335_get_compander, wcd9335_set_compander), 2328 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0, 2329 wcd9335_get_compander, wcd9335_set_compander), 2330 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0, 2331 wcd9335_get_compander, wcd9335_set_compander), 2332 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0, 2333 wcd9335_get_compander, wcd9335_set_compander), 2334 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum, 2335 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put), 2336 2337 /* Gain Controls */ 2338 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1, 2339 ear_pa_gain), 2340 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1, 2341 line_gain), 2342 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1, 2343 line_gain), 2344 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER, 2345 3, 16, 1, line_gain), 2346 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER, 2347 3, 16, 1, line_gain), 2348 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1, 2349 line_gain), 2350 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1, 2351 line_gain), 2352 2353 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0, 2354 analog_gain), 2355 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0, 2356 analog_gain), 2357 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0, 2358 analog_gain), 2359 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0, 2360 analog_gain), 2361 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0, 2362 analog_gain), 2363 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0, 2364 analog_gain), 2365 2366 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum), 2367 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), 2368 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), 2369 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), 2370 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), 2371 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum), 2372 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum), 2373 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum), 2374 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum), 2375 }; 2376 2377 static const struct snd_soc_dapm_route wcd9335_audio_map[] = { 2378 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"}, 2379 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"}, 2380 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"}, 2381 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"}, 2382 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"}, 2383 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"}, 2384 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"}, 2385 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"}, 2386 2387 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"}, 2388 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"}, 2389 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"}, 2390 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"}, 2391 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"}, 2392 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"}, 2393 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"}, 2394 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"}, 2395 2396 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"}, 2397 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"}, 2398 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"}, 2399 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"}, 2400 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"}, 2401 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"}, 2402 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"}, 2403 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"}, 2404 2405 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"}, 2406 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"}, 2407 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"}, 2408 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"}, 2409 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"}, 2410 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"}, 2411 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"}, 2412 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"}, 2413 2414 {"SLIM RX0", NULL, "SLIM RX0 MUX"}, 2415 {"SLIM RX1", NULL, "SLIM RX1 MUX"}, 2416 {"SLIM RX2", NULL, "SLIM RX2 MUX"}, 2417 {"SLIM RX3", NULL, "SLIM RX3 MUX"}, 2418 {"SLIM RX4", NULL, "SLIM RX4 MUX"}, 2419 {"SLIM RX5", NULL, "SLIM RX5 MUX"}, 2420 {"SLIM RX6", NULL, "SLIM RX6 MUX"}, 2421 {"SLIM RX7", NULL, "SLIM RX7 MUX"}, 2422 2423 WCD9335_INTERPOLATOR_PATH(0), 2424 WCD9335_INTERPOLATOR_PATH(1), 2425 WCD9335_INTERPOLATOR_PATH(2), 2426 WCD9335_INTERPOLATOR_PATH(3), 2427 WCD9335_INTERPOLATOR_PATH(4), 2428 WCD9335_INTERPOLATOR_PATH(5), 2429 WCD9335_INTERPOLATOR_PATH(6), 2430 WCD9335_INTERPOLATOR_PATH(7), 2431 WCD9335_INTERPOLATOR_PATH(8), 2432 2433 /* EAR PA */ 2434 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"}, 2435 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"}, 2436 {"RX INT0 DAC", NULL, "RX_BIAS"}, 2437 {"EAR PA", NULL, "RX INT0 DAC"}, 2438 {"EAR", NULL, "EAR PA"}, 2439 2440 /* HPHL */ 2441 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"}, 2442 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"}, 2443 {"RX INT1 DAC", NULL, "RX_BIAS"}, 2444 {"HPHL PA", NULL, "RX INT1 DAC"}, 2445 {"HPHL", NULL, "HPHL PA"}, 2446 2447 /* HPHR */ 2448 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"}, 2449 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"}, 2450 {"RX INT2 DAC", NULL, "RX_BIAS"}, 2451 {"HPHR PA", NULL, "RX INT2 DAC"}, 2452 {"HPHR", NULL, "HPHR PA"}, 2453 2454 /* LINEOUT1 */ 2455 {"RX INT3 DAC", NULL, "RX INT3 INTERP"}, 2456 {"RX INT3 DAC", NULL, "RX_BIAS"}, 2457 {"LINEOUT1 PA", NULL, "RX INT3 DAC"}, 2458 {"LINEOUT1", NULL, "LINEOUT1 PA"}, 2459 2460 /* LINEOUT2 */ 2461 {"RX INT4 DAC", NULL, "RX INT4 INTERP"}, 2462 {"RX INT4 DAC", NULL, "RX_BIAS"}, 2463 {"LINEOUT2 PA", NULL, "RX INT4 DAC"}, 2464 {"LINEOUT2", NULL, "LINEOUT2 PA"}, 2465 2466 /* LINEOUT3 */ 2467 {"RX INT5 DAC", NULL, "RX INT5 INTERP"}, 2468 {"RX INT5 DAC", NULL, "RX_BIAS"}, 2469 {"LINEOUT3 PA", NULL, "RX INT5 DAC"}, 2470 {"LINEOUT3", NULL, "LINEOUT3 PA"}, 2471 2472 /* LINEOUT4 */ 2473 {"RX INT6 DAC", NULL, "RX INT6 INTERP"}, 2474 {"RX INT6 DAC", NULL, "RX_BIAS"}, 2475 {"LINEOUT4 PA", NULL, "RX INT6 DAC"}, 2476 {"LINEOUT4", NULL, "LINEOUT4 PA"}, 2477 2478 /* SLIMBUS Connections */ 2479 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"}, 2480 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"}, 2481 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"}, 2482 2483 /* ADC Mux */ 2484 WCD9335_ADC_MUX_PATH(0), 2485 WCD9335_ADC_MUX_PATH(1), 2486 WCD9335_ADC_MUX_PATH(2), 2487 WCD9335_ADC_MUX_PATH(3), 2488 WCD9335_ADC_MUX_PATH(4), 2489 WCD9335_ADC_MUX_PATH(5), 2490 WCD9335_ADC_MUX_PATH(6), 2491 WCD9335_ADC_MUX_PATH(7), 2492 WCD9335_ADC_MUX_PATH(8), 2493 2494 /* ADC Connections */ 2495 {"ADC1", NULL, "AMIC1"}, 2496 {"ADC2", NULL, "AMIC2"}, 2497 {"ADC3", NULL, "AMIC3"}, 2498 {"ADC4", NULL, "AMIC4"}, 2499 {"ADC5", NULL, "AMIC5"}, 2500 {"ADC6", NULL, "AMIC6"}, 2501 }; 2502 2503 static int wcd9335_micbias_control(struct snd_soc_component *component, 2504 int micb_num, int req, bool is_dapm) 2505 { 2506 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component); 2507 int micb_index = micb_num - 1; 2508 u16 micb_reg; 2509 2510 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) { 2511 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n", 2512 micb_index); 2513 return -EINVAL; 2514 } 2515 2516 switch (micb_num) { 2517 case MIC_BIAS_1: 2518 micb_reg = WCD9335_ANA_MICB1; 2519 break; 2520 case MIC_BIAS_2: 2521 micb_reg = WCD9335_ANA_MICB2; 2522 break; 2523 case MIC_BIAS_3: 2524 micb_reg = WCD9335_ANA_MICB3; 2525 break; 2526 case MIC_BIAS_4: 2527 micb_reg = WCD9335_ANA_MICB4; 2528 break; 2529 default: 2530 dev_err(component->dev, "%s: Invalid micbias number: %d\n", 2531 __func__, micb_num); 2532 return -EINVAL; 2533 } 2534 2535 switch (req) { 2536 case MICB_PULLUP_ENABLE: 2537 wcd->pullup_ref[micb_index]++; 2538 if ((wcd->pullup_ref[micb_index] == 1) && 2539 (wcd->micb_ref[micb_index] == 0)) 2540 snd_soc_component_update_bits(component, micb_reg, 2541 0xC0, 0x80); 2542 break; 2543 case MICB_PULLUP_DISABLE: 2544 wcd->pullup_ref[micb_index]--; 2545 if ((wcd->pullup_ref[micb_index] == 0) && 2546 (wcd->micb_ref[micb_index] == 0)) 2547 snd_soc_component_update_bits(component, micb_reg, 2548 0xC0, 0x00); 2549 break; 2550 case MICB_ENABLE: 2551 wcd->micb_ref[micb_index]++; 2552 if (wcd->micb_ref[micb_index] == 1) 2553 snd_soc_component_update_bits(component, micb_reg, 2554 0xC0, 0x40); 2555 break; 2556 case MICB_DISABLE: 2557 wcd->micb_ref[micb_index]--; 2558 if ((wcd->micb_ref[micb_index] == 0) && 2559 (wcd->pullup_ref[micb_index] > 0)) 2560 snd_soc_component_update_bits(component, micb_reg, 2561 0xC0, 0x80); 2562 else if ((wcd->micb_ref[micb_index] == 0) && 2563 (wcd->pullup_ref[micb_index] == 0)) { 2564 snd_soc_component_update_bits(component, micb_reg, 2565 0xC0, 0x00); 2566 } 2567 break; 2568 }; 2569 2570 return 0; 2571 } 2572 2573 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2574 int event) 2575 { 2576 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2577 int micb_num; 2578 2579 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1"))) 2580 micb_num = MIC_BIAS_1; 2581 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2"))) 2582 micb_num = MIC_BIAS_2; 2583 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3"))) 2584 micb_num = MIC_BIAS_3; 2585 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4"))) 2586 micb_num = MIC_BIAS_4; 2587 else 2588 return -EINVAL; 2589 2590 switch (event) { 2591 case SND_SOC_DAPM_PRE_PMU: 2592 /* 2593 * MIC BIAS can also be requested by MBHC, 2594 * so use ref count to handle micbias pullup 2595 * and enable requests 2596 */ 2597 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true); 2598 break; 2599 case SND_SOC_DAPM_POST_PMU: 2600 /* wait for cnp time */ 2601 usleep_range(1000, 1100); 2602 break; 2603 case SND_SOC_DAPM_POST_PMD: 2604 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true); 2605 break; 2606 }; 2607 2608 return 0; 2609 } 2610 2611 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w, 2612 struct snd_kcontrol *kc, int event) 2613 { 2614 return __wcd9335_codec_enable_micbias(w, event); 2615 } 2616 2617 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp, 2618 u16 amic_reg, bool set) 2619 { 2620 u8 mask = 0x20; 2621 u8 val; 2622 2623 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 || 2624 amic_reg == WCD9335_ANA_AMIC5) 2625 mask = 0x40; 2626 2627 val = set ? mask : 0x00; 2628 2629 switch (amic_reg) { 2630 case WCD9335_ANA_AMIC1: 2631 case WCD9335_ANA_AMIC2: 2632 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask, 2633 val); 2634 break; 2635 case WCD9335_ANA_AMIC3: 2636 case WCD9335_ANA_AMIC4: 2637 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask, 2638 val); 2639 break; 2640 case WCD9335_ANA_AMIC5: 2641 case WCD9335_ANA_AMIC6: 2642 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask, 2643 val); 2644 break; 2645 default: 2646 dev_err(comp->dev, "%s: invalid amic: %d\n", 2647 __func__, amic_reg); 2648 break; 2649 } 2650 } 2651 2652 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w, 2653 struct snd_kcontrol *kc, int event) 2654 { 2655 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2656 2657 switch (event) { 2658 case SND_SOC_DAPM_PRE_PMU: 2659 wcd9335_codec_set_tx_hold(comp, w->reg, true); 2660 break; 2661 default: 2662 break; 2663 } 2664 2665 return 0; 2666 } 2667 2668 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp, 2669 int adc_mux_n) 2670 { 2671 int mux_sel, reg, mreg; 2672 2673 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX || 2674 adc_mux_n == WCD9335_INVALID_ADC_MUX) 2675 return 0; 2676 2677 /* Check whether adc mux input is AMIC or DMIC */ 2678 if (adc_mux_n < 4) { 2679 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n; 2680 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n; 2681 mux_sel = snd_soc_component_read32(comp, reg) & 0x3; 2682 } else { 2683 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4; 2684 mreg = reg; 2685 mux_sel = snd_soc_component_read32(comp, reg) >> 6; 2686 } 2687 2688 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC) 2689 return 0; 2690 2691 return snd_soc_component_read32(comp, mreg) & 0x07; 2692 } 2693 2694 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp, 2695 int amic) 2696 { 2697 u16 pwr_level_reg = 0; 2698 2699 switch (amic) { 2700 case 1: 2701 case 2: 2702 pwr_level_reg = WCD9335_ANA_AMIC1; 2703 break; 2704 2705 case 3: 2706 case 4: 2707 pwr_level_reg = WCD9335_ANA_AMIC3; 2708 break; 2709 2710 case 5: 2711 case 6: 2712 pwr_level_reg = WCD9335_ANA_AMIC5; 2713 break; 2714 default: 2715 dev_err(comp->dev, "invalid amic: %d\n", amic); 2716 break; 2717 } 2718 2719 return pwr_level_reg; 2720 } 2721 2722 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w, 2723 struct snd_kcontrol *kc, int event) 2724 { 2725 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2726 unsigned int decimator; 2727 char *dec_adc_mux_name = NULL; 2728 char *widget_name = NULL; 2729 char *wname; 2730 int ret = 0, amic_n; 2731 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg; 2732 u16 tx_gain_ctl_reg; 2733 char *dec; 2734 u8 hpf_coff_freq; 2735 2736 widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL); 2737 if (!widget_name) 2738 return -ENOMEM; 2739 2740 wname = widget_name; 2741 dec_adc_mux_name = strsep(&widget_name, " "); 2742 if (!dec_adc_mux_name) { 2743 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2744 __func__, w->name); 2745 ret = -EINVAL; 2746 goto out; 2747 } 2748 dec_adc_mux_name = widget_name; 2749 2750 dec = strpbrk(dec_adc_mux_name, "012345678"); 2751 if (!dec) { 2752 dev_err(comp->dev, "%s: decimator index not found\n", 2753 __func__); 2754 ret = -EINVAL; 2755 goto out; 2756 } 2757 2758 ret = kstrtouint(dec, 10, &decimator); 2759 if (ret < 0) { 2760 dev_err(comp->dev, "%s: Invalid decimator = %s\n", 2761 __func__, wname); 2762 ret = -EINVAL; 2763 goto out; 2764 } 2765 2766 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator; 2767 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator; 2768 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator; 2769 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator; 2770 2771 switch (event) { 2772 case SND_SOC_DAPM_PRE_PMU: 2773 amic_n = wcd9335_codec_find_amic_input(comp, decimator); 2774 if (amic_n) 2775 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp, 2776 amic_n); 2777 2778 if (pwr_level_reg) { 2779 switch ((snd_soc_component_read32(comp, pwr_level_reg) & 2780 WCD9335_AMIC_PWR_LVL_MASK) >> 2781 WCD9335_AMIC_PWR_LVL_SHIFT) { 2782 case WCD9335_AMIC_PWR_LEVEL_LP: 2783 snd_soc_component_update_bits(comp, dec_cfg_reg, 2784 WCD9335_DEC_PWR_LVL_MASK, 2785 WCD9335_DEC_PWR_LVL_LP); 2786 break; 2787 2788 case WCD9335_AMIC_PWR_LEVEL_HP: 2789 snd_soc_component_update_bits(comp, dec_cfg_reg, 2790 WCD9335_DEC_PWR_LVL_MASK, 2791 WCD9335_DEC_PWR_LVL_HP); 2792 break; 2793 case WCD9335_AMIC_PWR_LEVEL_DEFAULT: 2794 default: 2795 snd_soc_component_update_bits(comp, dec_cfg_reg, 2796 WCD9335_DEC_PWR_LVL_MASK, 2797 WCD9335_DEC_PWR_LVL_DF); 2798 break; 2799 } 2800 } 2801 hpf_coff_freq = (snd_soc_component_read32(comp, dec_cfg_reg) & 2802 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2803 2804 if (hpf_coff_freq != CF_MIN_3DB_150HZ) 2805 snd_soc_component_update_bits(comp, dec_cfg_reg, 2806 TX_HPF_CUT_OFF_FREQ_MASK, 2807 CF_MIN_3DB_150HZ << 5); 2808 /* Enable TX PGA Mute */ 2809 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2810 0x10, 0x10); 2811 /* Enable APC */ 2812 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08); 2813 break; 2814 case SND_SOC_DAPM_POST_PMU: 2815 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00); 2816 2817 if (decimator == 0) { 2818 snd_soc_component_write(comp, 2819 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2820 snd_soc_component_write(comp, 2821 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3); 2822 snd_soc_component_write(comp, 2823 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83); 2824 snd_soc_component_write(comp, 2825 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03); 2826 } 2827 2828 snd_soc_component_update_bits(comp, hpf_gate_reg, 2829 0x01, 0x01); 2830 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 2831 0x10, 0x00); 2832 snd_soc_component_write(comp, tx_gain_ctl_reg, 2833 snd_soc_component_read32(comp, tx_gain_ctl_reg)); 2834 break; 2835 case SND_SOC_DAPM_PRE_PMD: 2836 hpf_coff_freq = (snd_soc_component_read32(comp, dec_cfg_reg) & 2837 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 2838 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10); 2839 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00); 2840 if (hpf_coff_freq != CF_MIN_3DB_150HZ) { 2841 snd_soc_component_update_bits(comp, dec_cfg_reg, 2842 TX_HPF_CUT_OFF_FREQ_MASK, 2843 hpf_coff_freq << 5); 2844 } 2845 break; 2846 case SND_SOC_DAPM_POST_PMD: 2847 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00); 2848 break; 2849 }; 2850 out: 2851 kfree(wname); 2852 return ret; 2853 } 2854 2855 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component, 2856 u32 mclk_rate, u32 dmic_clk_rate) 2857 { 2858 u32 div_factor; 2859 u8 dmic_ctl_val; 2860 2861 dev_err(component->dev, 2862 "%s: mclk_rate = %d, dmic_sample_rate = %d\n", 2863 __func__, mclk_rate, dmic_clk_rate); 2864 2865 /* Default value to return in case of error */ 2866 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 2867 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2868 else 2869 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2870 2871 if (dmic_clk_rate == 0) { 2872 dev_err(component->dev, 2873 "%s: dmic_sample_rate cannot be 0\n", 2874 __func__); 2875 goto done; 2876 } 2877 2878 div_factor = mclk_rate / dmic_clk_rate; 2879 switch (div_factor) { 2880 case 2: 2881 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2; 2882 break; 2883 case 3: 2884 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3; 2885 break; 2886 case 4: 2887 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4; 2888 break; 2889 case 6: 2890 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6; 2891 break; 2892 case 8: 2893 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8; 2894 break; 2895 case 16: 2896 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16; 2897 break; 2898 default: 2899 dev_err(component->dev, 2900 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n", 2901 __func__, div_factor, mclk_rate, dmic_clk_rate); 2902 break; 2903 } 2904 2905 done: 2906 return dmic_ctl_val; 2907 } 2908 2909 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w, 2910 struct snd_kcontrol *kc, int event) 2911 { 2912 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 2913 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 2914 u8 dmic_clk_en = 0x01; 2915 u16 dmic_clk_reg; 2916 s32 *dmic_clk_cnt; 2917 u8 dmic_rate_val, dmic_rate_shift = 1; 2918 unsigned int dmic; 2919 int ret; 2920 char *wname; 2921 2922 wname = strpbrk(w->name, "012345"); 2923 if (!wname) { 2924 dev_err(comp->dev, "%s: widget not found\n", __func__); 2925 return -EINVAL; 2926 } 2927 2928 ret = kstrtouint(wname, 10, &dmic); 2929 if (ret < 0) { 2930 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n", 2931 __func__); 2932 return -EINVAL; 2933 } 2934 2935 switch (dmic) { 2936 case 0: 2937 case 1: 2938 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt); 2939 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL; 2940 break; 2941 case 2: 2942 case 3: 2943 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt); 2944 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL; 2945 break; 2946 case 4: 2947 case 5: 2948 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt); 2949 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL; 2950 break; 2951 default: 2952 dev_err(comp->dev, "%s: Invalid DMIC Selection\n", 2953 __func__); 2954 return -EINVAL; 2955 }; 2956 2957 switch (event) { 2958 case SND_SOC_DAPM_PRE_PMU: 2959 dmic_rate_val = 2960 wcd9335_get_dmic_clk_val(comp, 2961 wcd->mclk_rate, 2962 wcd->dmic_sample_rate); 2963 2964 (*dmic_clk_cnt)++; 2965 if (*dmic_clk_cnt == 1) { 2966 snd_soc_component_update_bits(comp, dmic_clk_reg, 2967 0x07 << dmic_rate_shift, 2968 dmic_rate_val << dmic_rate_shift); 2969 snd_soc_component_update_bits(comp, dmic_clk_reg, 2970 dmic_clk_en, dmic_clk_en); 2971 } 2972 2973 break; 2974 case SND_SOC_DAPM_POST_PMD: 2975 dmic_rate_val = 2976 wcd9335_get_dmic_clk_val(comp, 2977 wcd->mclk_rate, 2978 wcd->mad_dmic_sample_rate); 2979 (*dmic_clk_cnt)--; 2980 if (*dmic_clk_cnt == 0) { 2981 snd_soc_component_update_bits(comp, dmic_clk_reg, 2982 dmic_clk_en, 0); 2983 snd_soc_component_update_bits(comp, dmic_clk_reg, 2984 0x07 << dmic_rate_shift, 2985 dmic_rate_val << dmic_rate_shift); 2986 } 2987 break; 2988 }; 2989 2990 return 0; 2991 } 2992 2993 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai, 2994 struct snd_soc_component *component) 2995 { 2996 int port_num = 0; 2997 unsigned short reg = 0; 2998 unsigned int val = 0; 2999 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3000 struct wcd9335_slim_ch *ch; 3001 3002 list_for_each_entry(ch, &dai->slim_ch_list, list) { 3003 if (ch->port >= WCD9335_RX_START) { 3004 port_num = ch->port - WCD9335_RX_START; 3005 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8); 3006 } else { 3007 port_num = ch->port; 3008 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8); 3009 } 3010 3011 regmap_read(wcd->if_regmap, reg, &val); 3012 if (!(val & BIT(port_num % 8))) 3013 regmap_write(wcd->if_regmap, reg, 3014 val | BIT(port_num % 8)); 3015 } 3016 } 3017 3018 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w, 3019 struct snd_kcontrol *kc, 3020 int event) 3021 { 3022 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3023 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp); 3024 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift]; 3025 3026 switch (event) { 3027 case SND_SOC_DAPM_POST_PMU: 3028 wcd9335_codec_enable_int_port(dai, comp); 3029 break; 3030 case SND_SOC_DAPM_POST_PMD: 3031 kfree(dai->sconfig.chs); 3032 3033 break; 3034 } 3035 3036 return 0; 3037 } 3038 3039 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w, 3040 struct snd_kcontrol *kc, int event) 3041 { 3042 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3043 u16 gain_reg; 3044 int offset_val = 0; 3045 int val = 0; 3046 3047 switch (w->reg) { 3048 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3049 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL; 3050 break; 3051 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3052 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL; 3053 break; 3054 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3055 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL; 3056 break; 3057 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3058 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL; 3059 break; 3060 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3061 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL; 3062 break; 3063 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3064 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL; 3065 break; 3066 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3067 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL; 3068 break; 3069 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3070 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL; 3071 break; 3072 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3073 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL; 3074 break; 3075 default: 3076 dev_err(comp->dev, "%s: No gain register avail for %s\n", 3077 __func__, w->name); 3078 return 0; 3079 }; 3080 3081 switch (event) { 3082 case SND_SOC_DAPM_POST_PMU: 3083 val = snd_soc_component_read32(comp, gain_reg); 3084 val += offset_val; 3085 snd_soc_component_write(comp, gain_reg, val); 3086 break; 3087 case SND_SOC_DAPM_POST_PMD: 3088 break; 3089 }; 3090 3091 return 0; 3092 } 3093 3094 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind) 3095 { 3096 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3097 3098 switch (reg) { 3099 case WCD9335_CDC_RX0_RX_PATH_CTL: 3100 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL: 3101 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3102 *ind = 0; 3103 break; 3104 case WCD9335_CDC_RX1_RX_PATH_CTL: 3105 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL: 3106 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3107 *ind = 1; 3108 break; 3109 case WCD9335_CDC_RX2_RX_PATH_CTL: 3110 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL: 3111 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3112 *ind = 2; 3113 break; 3114 case WCD9335_CDC_RX3_RX_PATH_CTL: 3115 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL: 3116 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3117 *ind = 3; 3118 break; 3119 case WCD9335_CDC_RX4_RX_PATH_CTL: 3120 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL: 3121 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3122 *ind = 4; 3123 break; 3124 case WCD9335_CDC_RX5_RX_PATH_CTL: 3125 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL: 3126 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3127 *ind = 5; 3128 break; 3129 case WCD9335_CDC_RX6_RX_PATH_CTL: 3130 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL: 3131 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3132 *ind = 6; 3133 break; 3134 case WCD9335_CDC_RX7_RX_PATH_CTL: 3135 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL: 3136 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3137 *ind = 7; 3138 break; 3139 case WCD9335_CDC_RX8_RX_PATH_CTL: 3140 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL: 3141 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3142 *ind = 8; 3143 break; 3144 }; 3145 3146 return prim_int_reg; 3147 } 3148 3149 static void wcd9335_codec_hd2_control(struct snd_soc_component *component, 3150 u16 prim_int_reg, int event) 3151 { 3152 u16 hd2_scale_reg; 3153 u16 hd2_enable_reg = 0; 3154 3155 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) { 3156 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3; 3157 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0; 3158 } 3159 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) { 3160 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3; 3161 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0; 3162 } 3163 3164 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 3165 snd_soc_component_update_bits(component, hd2_scale_reg, 3166 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3167 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500); 3168 snd_soc_component_update_bits(component, hd2_scale_reg, 3169 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3170 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2); 3171 snd_soc_component_update_bits(component, hd2_enable_reg, 3172 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3173 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE); 3174 } 3175 3176 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 3177 snd_soc_component_update_bits(component, hd2_enable_reg, 3178 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK, 3179 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE); 3180 snd_soc_component_update_bits(component, hd2_scale_reg, 3181 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK, 3182 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1); 3183 snd_soc_component_update_bits(component, hd2_scale_reg, 3184 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK, 3185 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000); 3186 } 3187 } 3188 3189 static int wcd9335_codec_enable_prim_interpolator( 3190 struct snd_soc_component *comp, 3191 u16 reg, int event) 3192 { 3193 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3194 u16 ind = 0; 3195 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind); 3196 3197 switch (event) { 3198 case SND_SOC_DAPM_PRE_PMU: 3199 wcd->prim_int_users[ind]++; 3200 if (wcd->prim_int_users[ind] == 1) { 3201 snd_soc_component_update_bits(comp, prim_int_reg, 3202 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3203 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3204 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3205 snd_soc_component_update_bits(comp, prim_int_reg, 3206 WCD9335_CDC_RX_CLK_EN_MASK, 3207 WCD9335_CDC_RX_CLK_ENABLE); 3208 } 3209 3210 if ((reg != prim_int_reg) && 3211 ((snd_soc_component_read32(comp, prim_int_reg)) & 3212 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)) 3213 snd_soc_component_update_bits(comp, reg, 3214 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3215 WCD9335_CDC_RX_PGA_MUTE_ENABLE); 3216 break; 3217 case SND_SOC_DAPM_POST_PMD: 3218 wcd->prim_int_users[ind]--; 3219 if (wcd->prim_int_users[ind] == 0) { 3220 snd_soc_component_update_bits(comp, prim_int_reg, 3221 WCD9335_CDC_RX_CLK_EN_MASK, 3222 WCD9335_CDC_RX_CLK_DISABLE); 3223 snd_soc_component_update_bits(comp, prim_int_reg, 3224 WCD9335_CDC_RX_RESET_MASK, 3225 WCD9335_CDC_RX_RESET_ENABLE); 3226 snd_soc_component_update_bits(comp, prim_int_reg, 3227 WCD9335_CDC_RX_RESET_MASK, 3228 WCD9335_CDC_RX_RESET_DISABLE); 3229 wcd9335_codec_hd2_control(comp, prim_int_reg, event); 3230 } 3231 break; 3232 }; 3233 3234 return 0; 3235 } 3236 3237 static int wcd9335_config_compander(struct snd_soc_component *component, 3238 int interp_n, int event) 3239 { 3240 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3241 int comp; 3242 u16 comp_ctl0_reg, rx_path_cfg0_reg; 3243 3244 /* EAR does not have compander */ 3245 if (!interp_n) 3246 return 0; 3247 3248 comp = interp_n - 1; 3249 if (!wcd->comp_enabled[comp]) 3250 return 0; 3251 3252 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp); 3253 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp); 3254 3255 if (SND_SOC_DAPM_EVENT_ON(event)) { 3256 /* Enable Compander Clock */ 3257 snd_soc_component_update_bits(component, comp_ctl0_reg, 3258 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3259 WCD9335_CDC_COMPANDER_CLK_ENABLE); 3260 /* Reset comander */ 3261 snd_soc_component_update_bits(component, comp_ctl0_reg, 3262 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3263 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3264 snd_soc_component_update_bits(component, comp_ctl0_reg, 3265 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3266 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3267 /* Enables DRE in this path */ 3268 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3269 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3270 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE); 3271 } 3272 3273 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3274 snd_soc_component_update_bits(component, comp_ctl0_reg, 3275 WCD9335_CDC_COMPANDER_HALT_MASK, 3276 WCD9335_CDC_COMPANDER_HALT); 3277 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 3278 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK, 3279 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE); 3280 3281 snd_soc_component_update_bits(component, comp_ctl0_reg, 3282 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3283 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE); 3284 snd_soc_component_update_bits(component, comp_ctl0_reg, 3285 WCD9335_CDC_COMPANDER_SOFT_RST_MASK, 3286 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE); 3287 snd_soc_component_update_bits(component, comp_ctl0_reg, 3288 WCD9335_CDC_COMPANDER_CLK_EN_MASK, 3289 WCD9335_CDC_COMPANDER_CLK_DISABLE); 3290 snd_soc_component_update_bits(component, comp_ctl0_reg, 3291 WCD9335_CDC_COMPANDER_HALT_MASK, 3292 WCD9335_CDC_COMPANDER_NOHALT); 3293 } 3294 3295 return 0; 3296 } 3297 3298 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w, 3299 struct snd_kcontrol *kc, int event) 3300 { 3301 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3302 u16 gain_reg; 3303 u16 reg; 3304 int val; 3305 int offset_val = 0; 3306 3307 if (!(strcmp(w->name, "RX INT0 INTERP"))) { 3308 reg = WCD9335_CDC_RX0_RX_PATH_CTL; 3309 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL; 3310 } else if (!(strcmp(w->name, "RX INT1 INTERP"))) { 3311 reg = WCD9335_CDC_RX1_RX_PATH_CTL; 3312 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL; 3313 } else if (!(strcmp(w->name, "RX INT2 INTERP"))) { 3314 reg = WCD9335_CDC_RX2_RX_PATH_CTL; 3315 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL; 3316 } else if (!(strcmp(w->name, "RX INT3 INTERP"))) { 3317 reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3318 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL; 3319 } else if (!(strcmp(w->name, "RX INT4 INTERP"))) { 3320 reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3321 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL; 3322 } else if (!(strcmp(w->name, "RX INT5 INTERP"))) { 3323 reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3324 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL; 3325 } else if (!(strcmp(w->name, "RX INT6 INTERP"))) { 3326 reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3327 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL; 3328 } else if (!(strcmp(w->name, "RX INT7 INTERP"))) { 3329 reg = WCD9335_CDC_RX7_RX_PATH_CTL; 3330 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL; 3331 } else if (!(strcmp(w->name, "RX INT8 INTERP"))) { 3332 reg = WCD9335_CDC_RX8_RX_PATH_CTL; 3333 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL; 3334 } else { 3335 dev_err(comp->dev, "%s: Interpolator reg not found\n", 3336 __func__); 3337 return -EINVAL; 3338 } 3339 3340 switch (event) { 3341 case SND_SOC_DAPM_PRE_PMU: 3342 /* Reset if needed */ 3343 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3344 break; 3345 case SND_SOC_DAPM_POST_PMU: 3346 wcd9335_config_compander(comp, w->shift, event); 3347 val = snd_soc_component_read32(comp, gain_reg); 3348 val += offset_val; 3349 snd_soc_component_write(comp, gain_reg, val); 3350 break; 3351 case SND_SOC_DAPM_POST_PMD: 3352 wcd9335_config_compander(comp, w->shift, event); 3353 wcd9335_codec_enable_prim_interpolator(comp, reg, event); 3354 break; 3355 }; 3356 3357 return 0; 3358 } 3359 3360 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component, 3361 u8 gain) 3362 { 3363 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 3364 u8 hph_l_en, hph_r_en; 3365 u8 l_val, r_val; 3366 u8 hph_pa_status; 3367 bool is_hphl_pa, is_hphr_pa; 3368 3369 hph_pa_status = snd_soc_component_read32(component, WCD9335_ANA_HPH); 3370 is_hphl_pa = hph_pa_status >> 7; 3371 is_hphr_pa = (hph_pa_status & 0x40) >> 6; 3372 3373 hph_l_en = snd_soc_component_read32(component, WCD9335_HPH_L_EN); 3374 hph_r_en = snd_soc_component_read32(component, WCD9335_HPH_R_EN); 3375 3376 l_val = (hph_l_en & 0xC0) | 0x20 | gain; 3377 r_val = (hph_r_en & 0xC0) | 0x20 | gain; 3378 3379 /* 3380 * Set HPH_L & HPH_R gain source selection to REGISTER 3381 * for better click and pop only if corresponding PAs are 3382 * not enabled. Also cache the values of the HPHL/R 3383 * PA gains to be applied after PAs are enabled 3384 */ 3385 if ((l_val != hph_l_en) && !is_hphl_pa) { 3386 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val); 3387 wcd->hph_l_gain = hph_l_en & 0x1F; 3388 } 3389 3390 if ((r_val != hph_r_en) && !is_hphr_pa) { 3391 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val); 3392 wcd->hph_r_gain = hph_r_en & 0x1F; 3393 } 3394 } 3395 3396 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp, 3397 int event) 3398 { 3399 if (SND_SOC_DAPM_EVENT_ON(event)) { 3400 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3401 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3402 0x06); 3403 snd_soc_component_update_bits(comp, 3404 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3405 0xF0, 0x40); 3406 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3407 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3408 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3409 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3410 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3411 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3412 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3413 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3414 0x0C); 3415 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3416 } 3417 3418 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3419 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3420 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3421 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3422 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3423 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3424 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3425 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 3426 0x8A); 3427 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA, 3428 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK, 3429 0x0A); 3430 } 3431 } 3432 3433 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp, 3434 int event) 3435 { 3436 if (SND_SOC_DAPM_EVENT_ON(event)) { 3437 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3438 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3439 0x0C); 3440 wcd9335_codec_hph_mode_gain_opt(comp, 0x10); 3441 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3442 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3443 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3444 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3445 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3446 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3447 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3448 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3449 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE); 3450 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3451 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3452 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE); 3453 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3454 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK, 3455 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60); 3456 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL, 3457 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK, 3458 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60); 3459 snd_soc_component_update_bits(comp, 3460 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01); 3461 snd_soc_component_update_bits(comp, 3462 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10); 3463 } 3464 3465 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3466 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO, 3467 0x88); 3468 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL, 3469 0x33); 3470 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3471 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK, 3472 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE); 3473 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3474 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK, 3475 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE); 3476 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3477 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3478 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3479 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3480 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3481 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3482 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN, 3483 WCD9335_HPH_CONST_SEL_L_MASK, 3484 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3485 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN, 3486 WCD9335_HPH_CONST_SEL_L_MASK, 3487 WCD9335_HPH_CONST_SEL_L_HQ_PATH); 3488 } 3489 } 3490 3491 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp, 3492 int event) 3493 { 3494 if (SND_SOC_DAPM_EVENT_ON(event)) { 3495 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3496 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3497 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000); 3498 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3499 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3500 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE); 3501 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1, 3502 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3503 0x0C); 3504 wcd9335_codec_hph_mode_gain_opt(comp, 0x11); 3505 } 3506 3507 if (SND_SOC_DAPM_EVENT_OFF(event)) { 3508 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2, 3509 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK, 3510 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE); 3511 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL, 3512 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK, 3513 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500); 3514 } 3515 } 3516 3517 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component, 3518 int event, int mode) 3519 { 3520 switch (mode) { 3521 case CLS_H_LP: 3522 wcd9335_codec_hph_lp_config(component, event); 3523 break; 3524 case CLS_H_LOHIFI: 3525 wcd9335_codec_hph_lohifi_config(component, event); 3526 break; 3527 case CLS_H_HIFI: 3528 wcd9335_codec_hph_hifi_config(component, event); 3529 break; 3530 } 3531 } 3532 3533 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, 3534 struct snd_kcontrol *kc, 3535 int event) 3536 { 3537 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3538 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3539 int hph_mode = wcd->hph_mode; 3540 u8 dem_inp; 3541 3542 switch (event) { 3543 case SND_SOC_DAPM_PRE_PMU: 3544 /* Read DEM INP Select */ 3545 dem_inp = snd_soc_component_read32(comp, 3546 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03; 3547 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3548 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3549 dev_err(comp->dev, "Incorrect DEM Input\n"); 3550 return -EINVAL; 3551 } 3552 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3553 WCD_CLSH_STATE_HPHL, 3554 ((hph_mode == CLS_H_LOHIFI) ? 3555 CLS_H_HIFI : hph_mode)); 3556 3557 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3558 3559 break; 3560 case SND_SOC_DAPM_POST_PMU: 3561 usleep_range(1000, 1100); 3562 break; 3563 case SND_SOC_DAPM_PRE_PMD: 3564 break; 3565 case SND_SOC_DAPM_POST_PMD: 3566 /* 1000us required as per HW requirement */ 3567 usleep_range(1000, 1100); 3568 3569 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3570 WCD_CLSH_STATE_HPHR)) 3571 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3572 3573 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3574 WCD_CLSH_STATE_HPHL, 3575 ((hph_mode == CLS_H_LOHIFI) ? 3576 CLS_H_HIFI : hph_mode)); 3577 break; 3578 }; 3579 3580 return 0; 3581 } 3582 3583 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w, 3584 struct snd_kcontrol *kc, int event) 3585 { 3586 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3587 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3588 3589 switch (event) { 3590 case SND_SOC_DAPM_PRE_PMU: 3591 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3592 WCD_CLSH_STATE_LO, CLS_AB); 3593 break; 3594 case SND_SOC_DAPM_POST_PMD: 3595 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3596 WCD_CLSH_STATE_LO, CLS_AB); 3597 break; 3598 } 3599 3600 return 0; 3601 } 3602 3603 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w, 3604 struct snd_kcontrol *kc, int event) 3605 { 3606 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3607 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3608 3609 switch (event) { 3610 case SND_SOC_DAPM_PRE_PMU: 3611 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC, 3612 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3613 3614 break; 3615 case SND_SOC_DAPM_POST_PMD: 3616 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3617 WCD_CLSH_STATE_EAR, CLS_H_NORMAL); 3618 break; 3619 }; 3620 3621 return 0; 3622 } 3623 3624 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd, 3625 int mode, int event) 3626 { 3627 u8 scale_val = 0; 3628 3629 switch (event) { 3630 case SND_SOC_DAPM_POST_PMU: 3631 switch (mode) { 3632 case CLS_H_HIFI: 3633 scale_val = 0x3; 3634 break; 3635 case CLS_H_LOHIFI: 3636 scale_val = 0x1; 3637 break; 3638 } 3639 break; 3640 case SND_SOC_DAPM_PRE_PMD: 3641 scale_val = 0x6; 3642 break; 3643 } 3644 3645 if (scale_val) 3646 snd_soc_component_update_bits(wcd->component, 3647 WCD9335_HPH_PA_CTL1, 3648 WCD9335_HPH_PA_GM3_IB_SCALE_MASK, 3649 scale_val << 1); 3650 if (SND_SOC_DAPM_EVENT_ON(event)) { 3651 if (wcd->comp_enabled[COMPANDER_1] || 3652 wcd->comp_enabled[COMPANDER_2]) { 3653 /* GAIN Source Selection */ 3654 snd_soc_component_update_bits(wcd->component, 3655 WCD9335_HPH_L_EN, 3656 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3657 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3658 snd_soc_component_update_bits(wcd->component, 3659 WCD9335_HPH_R_EN, 3660 WCD9335_HPH_GAIN_SRC_SEL_MASK, 3661 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER); 3662 snd_soc_component_update_bits(wcd->component, 3663 WCD9335_HPH_AUTO_CHOP, 3664 WCD9335_HPH_AUTO_CHOP_MASK, 3665 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE); 3666 } 3667 snd_soc_component_update_bits(wcd->component, 3668 WCD9335_HPH_L_EN, 3669 WCD9335_HPH_PA_GAIN_MASK, 3670 wcd->hph_l_gain); 3671 snd_soc_component_update_bits(wcd->component, 3672 WCD9335_HPH_R_EN, 3673 WCD9335_HPH_PA_GAIN_MASK, 3674 wcd->hph_r_gain); 3675 } 3676 3677 if (SND_SOC_DAPM_EVENT_OFF(event)) 3678 snd_soc_component_update_bits(wcd->component, 3679 WCD9335_HPH_AUTO_CHOP, 3680 WCD9335_HPH_AUTO_CHOP_MASK, 3681 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN); 3682 } 3683 3684 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, 3685 struct snd_kcontrol *kc, 3686 int event) 3687 { 3688 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3689 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3690 int hph_mode = wcd->hph_mode; 3691 u8 dem_inp; 3692 3693 switch (event) { 3694 case SND_SOC_DAPM_PRE_PMU: 3695 3696 /* Read DEM INP Select */ 3697 dem_inp = snd_soc_component_read32(comp, 3698 WCD9335_CDC_RX2_RX_PATH_SEC0) & 3699 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK; 3700 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) || 3701 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) { 3702 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n", 3703 hph_mode); 3704 return -EINVAL; 3705 } 3706 3707 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, 3708 WCD_CLSH_EVENT_PRE_DAC, 3709 WCD_CLSH_STATE_HPHR, 3710 ((hph_mode == CLS_H_LOHIFI) ? 3711 CLS_H_HIFI : hph_mode)); 3712 3713 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3714 3715 break; 3716 case SND_SOC_DAPM_POST_PMD: 3717 /* 1000us required as per HW requirement */ 3718 usleep_range(1000, 1100); 3719 3720 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) & 3721 WCD_CLSH_STATE_HPHL)) 3722 wcd9335_codec_hph_mode_config(comp, event, hph_mode); 3723 3724 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA, 3725 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ? 3726 CLS_H_HIFI : hph_mode)); 3727 break; 3728 }; 3729 3730 return 0; 3731 } 3732 3733 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, 3734 struct snd_kcontrol *kc, 3735 int event) 3736 { 3737 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3738 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3739 int hph_mode = wcd->hph_mode; 3740 3741 switch (event) { 3742 case SND_SOC_DAPM_PRE_PMU: 3743 break; 3744 case SND_SOC_DAPM_POST_PMU: 3745 /* 3746 * 7ms sleep is required after PA is enabled as per 3747 * HW requirement 3748 */ 3749 usleep_range(7000, 7100); 3750 3751 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3752 snd_soc_component_update_bits(comp, 3753 WCD9335_CDC_RX1_RX_PATH_CTL, 3754 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3755 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3756 3757 /* Remove mix path mute if it is enabled */ 3758 if ((snd_soc_component_read32(comp, 3759 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) & 3760 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3761 snd_soc_component_update_bits(comp, 3762 WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 3763 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3764 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3765 3766 break; 3767 case SND_SOC_DAPM_PRE_PMD: 3768 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3769 break; 3770 case SND_SOC_DAPM_POST_PMD: 3771 /* 5ms sleep is required after PA is disabled as per 3772 * HW requirement 3773 */ 3774 usleep_range(5000, 5500); 3775 break; 3776 }; 3777 3778 return 0; 3779 } 3780 3781 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w, 3782 struct snd_kcontrol *kc, 3783 int event) 3784 { 3785 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3786 int vol_reg = 0, mix_vol_reg = 0; 3787 3788 if (w->reg == WCD9335_ANA_LO_1_2) { 3789 if (w->shift == 7) { 3790 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL; 3791 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL; 3792 } else if (w->shift == 6) { 3793 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL; 3794 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL; 3795 } 3796 } else if (w->reg == WCD9335_ANA_LO_3_4) { 3797 if (w->shift == 7) { 3798 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL; 3799 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL; 3800 } else if (w->shift == 6) { 3801 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL; 3802 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL; 3803 } 3804 } else { 3805 dev_err(comp->dev, "Error enabling lineout PA\n"); 3806 return -EINVAL; 3807 } 3808 3809 switch (event) { 3810 case SND_SOC_DAPM_POST_PMU: 3811 /* 5ms sleep is required after PA is enabled as per 3812 * HW requirement 3813 */ 3814 usleep_range(5000, 5500); 3815 snd_soc_component_update_bits(comp, vol_reg, 3816 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3817 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3818 3819 /* Remove mix path mute if it is enabled */ 3820 if ((snd_soc_component_read32(comp, mix_vol_reg)) & 3821 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3822 snd_soc_component_update_bits(comp, mix_vol_reg, 3823 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3824 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3825 break; 3826 case SND_SOC_DAPM_POST_PMD: 3827 /* 5ms sleep is required after PA is disabled as per 3828 * HW requirement 3829 */ 3830 usleep_range(5000, 5500); 3831 break; 3832 }; 3833 3834 return 0; 3835 } 3836 3837 static void wcd9335_codec_init_flyback(struct snd_soc_component *component) 3838 { 3839 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN, 3840 WCD9335_HPH_CONST_SEL_L_MASK, 3841 WCD9335_HPH_CONST_SEL_L_BYPASS); 3842 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN, 3843 WCD9335_HPH_CONST_SEL_L_MASK, 3844 WCD9335_HPH_CONST_SEL_L_BYPASS); 3845 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3846 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK, 3847 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3848 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF, 3849 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK, 3850 WCD9335_RX_BIAS_FLYB_I_0P0_UA); 3851 } 3852 3853 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w, 3854 struct snd_kcontrol *kc, int event) 3855 { 3856 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3857 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3858 3859 switch (event) { 3860 case SND_SOC_DAPM_PRE_PMU: 3861 wcd->rx_bias_count++; 3862 if (wcd->rx_bias_count == 1) { 3863 wcd9335_codec_init_flyback(comp); 3864 snd_soc_component_update_bits(comp, 3865 WCD9335_ANA_RX_SUPPLIES, 3866 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3867 WCD9335_ANA_RX_BIAS_ENABLE); 3868 } 3869 break; 3870 case SND_SOC_DAPM_POST_PMD: 3871 wcd->rx_bias_count--; 3872 if (!wcd->rx_bias_count) 3873 snd_soc_component_update_bits(comp, 3874 WCD9335_ANA_RX_SUPPLIES, 3875 WCD9335_ANA_RX_BIAS_ENABLE_MASK, 3876 WCD9335_ANA_RX_BIAS_DISABLE); 3877 break; 3878 }; 3879 3880 return 0; 3881 } 3882 3883 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w, 3884 struct snd_kcontrol *kc, int event) 3885 { 3886 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3887 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 3888 int hph_mode = wcd->hph_mode; 3889 3890 switch (event) { 3891 case SND_SOC_DAPM_PRE_PMU: 3892 break; 3893 case SND_SOC_DAPM_POST_PMU: 3894 /* 3895 * 7ms sleep is required after PA is enabled as per 3896 * HW requirement 3897 */ 3898 usleep_range(7000, 7100); 3899 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3900 snd_soc_component_update_bits(comp, 3901 WCD9335_CDC_RX2_RX_PATH_CTL, 3902 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3903 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3904 /* Remove mix path mute if it is enabled */ 3905 if ((snd_soc_component_read32(comp, 3906 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) & 3907 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3908 snd_soc_component_update_bits(comp, 3909 WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 3910 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3911 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3912 3913 break; 3914 3915 case SND_SOC_DAPM_PRE_PMD: 3916 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event); 3917 break; 3918 case SND_SOC_DAPM_POST_PMD: 3919 /* 5ms sleep is required after PA is disabled as per 3920 * HW requirement 3921 */ 3922 usleep_range(5000, 5500); 3923 break; 3924 }; 3925 3926 return 0; 3927 } 3928 3929 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, 3930 struct snd_kcontrol *kc, int event) 3931 { 3932 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 3933 3934 switch (event) { 3935 case SND_SOC_DAPM_POST_PMU: 3936 /* 5ms sleep is required after PA is enabled as per 3937 * HW requirement 3938 */ 3939 usleep_range(5000, 5500); 3940 snd_soc_component_update_bits(comp, 3941 WCD9335_CDC_RX0_RX_PATH_CTL, 3942 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3943 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3944 /* Remove mix path mute if it is enabled */ 3945 if ((snd_soc_component_read32(comp, 3946 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) & 3947 WCD9335_CDC_RX_PGA_MUTE_EN_MASK) 3948 snd_soc_component_update_bits(comp, 3949 WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 3950 WCD9335_CDC_RX_PGA_MUTE_EN_MASK, 3951 WCD9335_CDC_RX_PGA_MUTE_DISABLE); 3952 break; 3953 case SND_SOC_DAPM_POST_PMD: 3954 /* 5ms sleep is required after PA is disabled as per 3955 * HW requirement 3956 */ 3957 usleep_range(5000, 5500); 3958 3959 break; 3960 }; 3961 3962 return 0; 3963 } 3964 3965 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data) 3966 { 3967 struct wcd9335_codec *wcd = data; 3968 unsigned long status = 0; 3969 int i, j, port_id; 3970 unsigned int val, int_val = 0; 3971 irqreturn_t ret = IRQ_NONE; 3972 bool tx; 3973 unsigned short reg = 0; 3974 3975 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0; 3976 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) { 3977 regmap_read(wcd->if_regmap, i, &val); 3978 status |= ((u32)val << (8 * j)); 3979 } 3980 3981 for_each_set_bit(j, &status, 32) { 3982 tx = (j >= 16 ? true : false); 3983 port_id = (tx ? j - 16 : j); 3984 regmap_read(wcd->if_regmap, 3985 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val); 3986 if (val) { 3987 if (!tx) 3988 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 3989 (port_id / 8); 3990 else 3991 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 3992 (port_id / 8); 3993 regmap_read( 3994 wcd->if_regmap, reg, &int_val); 3995 /* 3996 * Ignore interrupts for ports for which the 3997 * interrupts are not specifically enabled. 3998 */ 3999 if (!(int_val & (1 << (port_id % 8)))) 4000 continue; 4001 } 4002 4003 if (val & WCD9335_SLIM_IRQ_OVERFLOW) 4004 dev_err_ratelimited(wcd->dev, 4005 "%s: overflow error on %s port %d, value %x\n", 4006 __func__, (tx ? "TX" : "RX"), port_id, val); 4007 4008 if (val & WCD9335_SLIM_IRQ_UNDERFLOW) 4009 dev_err_ratelimited(wcd->dev, 4010 "%s: underflow error on %s port %d, value %x\n", 4011 __func__, (tx ? "TX" : "RX"), port_id, val); 4012 4013 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) || 4014 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) { 4015 if (!tx) 4016 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + 4017 (port_id / 8); 4018 else 4019 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + 4020 (port_id / 8); 4021 regmap_read( 4022 wcd->if_regmap, reg, &int_val); 4023 if (int_val & (1 << (port_id % 8))) { 4024 int_val = int_val ^ (1 << (port_id % 8)); 4025 regmap_write(wcd->if_regmap, 4026 reg, int_val); 4027 } 4028 } 4029 4030 regmap_write(wcd->if_regmap, 4031 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8), 4032 BIT(j % 8)); 4033 ret = IRQ_HANDLED; 4034 } 4035 4036 return ret; 4037 } 4038 4039 static struct wcd9335_irq wcd9335_irqs[] = { 4040 { 4041 .irq = WCD9335_IRQ_SLIMBUS, 4042 .handler = wcd9335_slimbus_irq, 4043 .name = "SLIM Slave", 4044 }, 4045 }; 4046 4047 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd) 4048 { 4049 int irq, ret, i; 4050 4051 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) { 4052 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq); 4053 if (irq < 0) { 4054 dev_err(wcd->dev, "Failed to get %s\n", 4055 wcd9335_irqs[i].name); 4056 return irq; 4057 } 4058 4059 ret = devm_request_threaded_irq(wcd->dev, irq, NULL, 4060 wcd9335_irqs[i].handler, 4061 IRQF_TRIGGER_RISING | 4062 IRQF_ONESHOT, 4063 wcd9335_irqs[i].name, wcd); 4064 if (ret) { 4065 dev_err(wcd->dev, "Failed to request %s\n", 4066 wcd9335_irqs[i].name); 4067 return ret; 4068 } 4069 } 4070 4071 /* enable interrupts on all slave ports */ 4072 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++) 4073 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i, 4074 0xFF); 4075 4076 return ret; 4077 } 4078 4079 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd, 4080 bool ccl_flag) 4081 { 4082 struct snd_soc_component *comp = wcd->component; 4083 4084 if (ccl_flag) { 4085 if (++wcd->sido_ccl_cnt == 1) 4086 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4087 WCD9335_SIDO_SIDO_CCL_DEF_VALUE); 4088 } else { 4089 if (wcd->sido_ccl_cnt == 0) { 4090 dev_err(wcd->dev, "sido_ccl already disabled\n"); 4091 return; 4092 } 4093 if (--wcd->sido_ccl_cnt == 0) 4094 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10, 4095 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF); 4096 } 4097 } 4098 4099 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd) 4100 { 4101 wcd->master_bias_users++; 4102 if (wcd->master_bias_users == 1) { 4103 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4104 WCD9335_ANA_BIAS_EN_MASK, 4105 WCD9335_ANA_BIAS_ENABLE); 4106 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4107 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4108 WCD9335_ANA_BIAS_PRECHRG_ENABLE); 4109 /* 4110 * 1ms delay is required after pre-charge is enabled 4111 * as per HW requirement 4112 */ 4113 usleep_range(1000, 1100); 4114 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4115 WCD9335_ANA_BIAS_PRECHRG_EN_MASK, 4116 WCD9335_ANA_BIAS_PRECHRG_DISABLE); 4117 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4118 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4119 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4120 } 4121 4122 return 0; 4123 } 4124 4125 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd) 4126 { 4127 /* Enable mclk requires master bias to be enabled first */ 4128 if (wcd->master_bias_users <= 0) 4129 return -EINVAL; 4130 4131 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) || 4132 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) { 4133 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n", 4134 wcd->clk_type); 4135 return -EINVAL; 4136 } 4137 4138 if (++wcd->clk_mclk_users == 1) { 4139 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4140 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4141 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE); 4142 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4143 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4144 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL); 4145 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4146 WCD9335_ANA_CLK_MCLK_EN_MASK, 4147 WCD9335_ANA_CLK_MCLK_ENABLE); 4148 regmap_update_bits(wcd->regmap, 4149 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 4150 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK, 4151 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE); 4152 regmap_update_bits(wcd->regmap, 4153 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL, 4154 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK, 4155 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE); 4156 /* 4157 * 10us sleep is required after clock is enabled 4158 * as per HW requirement 4159 */ 4160 usleep_range(10, 15); 4161 } 4162 4163 wcd->clk_type = WCD_CLK_MCLK; 4164 4165 return 0; 4166 } 4167 4168 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd) 4169 { 4170 if (wcd->clk_mclk_users <= 0) 4171 return -EINVAL; 4172 4173 if (--wcd->clk_mclk_users == 0) { 4174 if (wcd->clk_rco_users > 0) { 4175 /* MCLK to RCO switch */ 4176 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4177 WCD9335_ANA_CLK_MCLK_SRC_MASK, 4178 WCD9335_ANA_CLK_MCLK_SRC_RCO); 4179 wcd->clk_type = WCD_CLK_RCO; 4180 } else { 4181 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4182 WCD9335_ANA_CLK_MCLK_EN_MASK, 4183 WCD9335_ANA_CLK_MCLK_DISABLE); 4184 wcd->clk_type = WCD_CLK_OFF; 4185 } 4186 4187 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP, 4188 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK, 4189 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE); 4190 } 4191 4192 return 0; 4193 } 4194 4195 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd) 4196 { 4197 if (wcd->master_bias_users <= 0) 4198 return -EINVAL; 4199 4200 wcd->master_bias_users--; 4201 if (wcd->master_bias_users == 0) { 4202 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4203 WCD9335_ANA_BIAS_EN_MASK, 4204 WCD9335_ANA_BIAS_DISABLE); 4205 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS, 4206 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE, 4207 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL); 4208 } 4209 return 0; 4210 } 4211 4212 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd, 4213 bool enable) 4214 { 4215 int ret = 0; 4216 4217 if (enable) { 4218 wcd9335_cdc_sido_ccl_enable(wcd, true); 4219 ret = clk_prepare_enable(wcd->mclk); 4220 if (ret) { 4221 dev_err(wcd->dev, "%s: ext clk enable failed\n", 4222 __func__); 4223 goto err; 4224 } 4225 /* get BG */ 4226 wcd9335_enable_master_bias(wcd); 4227 /* get MCLK */ 4228 wcd9335_enable_mclk(wcd); 4229 4230 } else { 4231 /* put MCLK */ 4232 wcd9335_disable_mclk(wcd); 4233 /* put BG */ 4234 wcd9335_disable_master_bias(wcd); 4235 clk_disable_unprepare(wcd->mclk); 4236 wcd9335_cdc_sido_ccl_enable(wcd, false); 4237 } 4238 err: 4239 return ret; 4240 } 4241 4242 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd, 4243 enum wcd9335_sido_voltage req_mv) 4244 { 4245 struct snd_soc_component *comp = wcd->component; 4246 int vout_d_val; 4247 4248 if (req_mv == wcd->sido_voltage) 4249 return; 4250 4251 /* compute the vout_d step value */ 4252 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) & 4253 WCD9335_ANA_BUCK_VOUT_MASK; 4254 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val); 4255 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4256 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4257 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE); 4258 4259 /* 1 msec sleep required after SIDO Vout_D voltage change */ 4260 usleep_range(1000, 1100); 4261 wcd->sido_voltage = req_mv; 4262 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL, 4263 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK, 4264 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE); 4265 } 4266 4267 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd, 4268 enum wcd9335_sido_voltage req_mv) 4269 { 4270 int ret = 0; 4271 4272 /* enable mclk before setting SIDO voltage */ 4273 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4274 if (ret) { 4275 dev_err(wcd->dev, "Ext clk enable failed\n"); 4276 goto err; 4277 } 4278 4279 wcd9335_codec_apply_sido_voltage(wcd, req_mv); 4280 wcd9335_cdc_req_mclk_enable(wcd, false); 4281 4282 err: 4283 return ret; 4284 } 4285 4286 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component, 4287 int enable) 4288 { 4289 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4290 int ret; 4291 4292 if (enable) { 4293 ret = wcd9335_cdc_req_mclk_enable(wcd, true); 4294 if (ret) 4295 return ret; 4296 4297 wcd9335_codec_apply_sido_voltage(wcd, 4298 SIDO_VOLTAGE_NOMINAL_MV); 4299 } else { 4300 wcd9335_codec_update_sido_voltage(wcd, 4301 wcd->sido_voltage); 4302 wcd9335_cdc_req_mclk_enable(wcd, false); 4303 } 4304 4305 return 0; 4306 } 4307 4308 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w, 4309 struct snd_kcontrol *kc, int event) 4310 { 4311 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 4312 4313 switch (event) { 4314 case SND_SOC_DAPM_PRE_PMU: 4315 return _wcd9335_codec_enable_mclk(comp, true); 4316 case SND_SOC_DAPM_POST_PMD: 4317 return _wcd9335_codec_enable_mclk(comp, false); 4318 } 4319 4320 return 0; 4321 } 4322 4323 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = { 4324 /* TODO SPK1 & SPK2 OUT*/ 4325 SND_SOC_DAPM_OUTPUT("EAR"), 4326 SND_SOC_DAPM_OUTPUT("HPHL"), 4327 SND_SOC_DAPM_OUTPUT("HPHR"), 4328 SND_SOC_DAPM_OUTPUT("LINEOUT1"), 4329 SND_SOC_DAPM_OUTPUT("LINEOUT2"), 4330 SND_SOC_DAPM_OUTPUT("LINEOUT3"), 4331 SND_SOC_DAPM_OUTPUT("LINEOUT4"), 4332 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM, 4333 AIF1_PB, 0, wcd9335_codec_enable_slim, 4334 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4335 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM, 4336 AIF2_PB, 0, wcd9335_codec_enable_slim, 4337 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4338 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM, 4339 AIF3_PB, 0, wcd9335_codec_enable_slim, 4340 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4341 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM, 4342 AIF4_PB, 0, wcd9335_codec_enable_slim, 4343 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4344 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0, 4345 &slim_rx_mux[WCD9335_RX0]), 4346 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0, 4347 &slim_rx_mux[WCD9335_RX1]), 4348 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0, 4349 &slim_rx_mux[WCD9335_RX2]), 4350 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0, 4351 &slim_rx_mux[WCD9335_RX3]), 4352 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0, 4353 &slim_rx_mux[WCD9335_RX4]), 4354 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0, 4355 &slim_rx_mux[WCD9335_RX5]), 4356 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0, 4357 &slim_rx_mux[WCD9335_RX6]), 4358 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0, 4359 &slim_rx_mux[WCD9335_RX7]), 4360 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 4361 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4362 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4363 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 4364 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 4365 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 4366 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0), 4367 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0), 4368 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 4369 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path, 4370 SND_SOC_DAPM_POST_PMU), 4371 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 4372 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path, 4373 SND_SOC_DAPM_POST_PMU), 4374 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 4375 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path, 4376 SND_SOC_DAPM_POST_PMU), 4377 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL, 4378 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path, 4379 SND_SOC_DAPM_POST_PMU), 4380 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL, 4381 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path, 4382 SND_SOC_DAPM_POST_PMU), 4383 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL, 4384 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path, 4385 SND_SOC_DAPM_POST_PMU), 4386 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL, 4387 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path, 4388 SND_SOC_DAPM_POST_PMU), 4389 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL, 4390 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path, 4391 SND_SOC_DAPM_POST_PMU), 4392 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL, 4393 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path, 4394 SND_SOC_DAPM_POST_PMU), 4395 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4396 &rx_int0_1_mix_inp0_mux), 4397 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4398 &rx_int0_1_mix_inp1_mux), 4399 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4400 &rx_int0_1_mix_inp2_mux), 4401 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4402 &rx_int1_1_mix_inp0_mux), 4403 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4404 &rx_int1_1_mix_inp1_mux), 4405 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4406 &rx_int1_1_mix_inp2_mux), 4407 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4408 &rx_int2_1_mix_inp0_mux), 4409 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4410 &rx_int2_1_mix_inp1_mux), 4411 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4412 &rx_int2_1_mix_inp2_mux), 4413 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4414 &rx_int3_1_mix_inp0_mux), 4415 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4416 &rx_int3_1_mix_inp1_mux), 4417 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4418 &rx_int3_1_mix_inp2_mux), 4419 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4420 &rx_int4_1_mix_inp0_mux), 4421 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4422 &rx_int4_1_mix_inp1_mux), 4423 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4424 &rx_int4_1_mix_inp2_mux), 4425 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4426 &rx_int5_1_mix_inp0_mux), 4427 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4428 &rx_int5_1_mix_inp1_mux), 4429 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4430 &rx_int5_1_mix_inp2_mux), 4431 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4432 &rx_int6_1_mix_inp0_mux), 4433 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4434 &rx_int6_1_mix_inp1_mux), 4435 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4436 &rx_int6_1_mix_inp2_mux), 4437 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4438 &rx_int7_1_mix_inp0_mux), 4439 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4440 &rx_int7_1_mix_inp1_mux), 4441 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4442 &rx_int7_1_mix_inp2_mux), 4443 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, 4444 &rx_int8_1_mix_inp0_mux), 4445 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, 4446 &rx_int8_1_mix_inp1_mux), 4447 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, 4448 &rx_int8_1_mix_inp2_mux), 4449 4450 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4451 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4452 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4453 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4454 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4455 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4456 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4457 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4458 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4459 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4460 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4461 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4462 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4463 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4464 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4465 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4466 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 4467 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 4468 4469 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4470 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4471 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4472 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4473 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4474 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4475 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4476 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4477 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 4478 4479 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 4480 &rx_int0_dem_inp_mux), 4481 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 4482 &rx_int1_dem_inp_mux), 4483 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0, 4484 &rx_int2_dem_inp_mux), 4485 4486 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM, 4487 INTERP_EAR, 0, &rx_int0_interp_mux, 4488 wcd9335_codec_enable_interpolator, 4489 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4490 SND_SOC_DAPM_POST_PMD), 4491 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM, 4492 INTERP_HPHL, 0, &rx_int1_interp_mux, 4493 wcd9335_codec_enable_interpolator, 4494 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4495 SND_SOC_DAPM_POST_PMD), 4496 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM, 4497 INTERP_HPHR, 0, &rx_int2_interp_mux, 4498 wcd9335_codec_enable_interpolator, 4499 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4500 SND_SOC_DAPM_POST_PMD), 4501 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM, 4502 INTERP_LO1, 0, &rx_int3_interp_mux, 4503 wcd9335_codec_enable_interpolator, 4504 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4505 SND_SOC_DAPM_POST_PMD), 4506 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM, 4507 INTERP_LO2, 0, &rx_int4_interp_mux, 4508 wcd9335_codec_enable_interpolator, 4509 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4510 SND_SOC_DAPM_POST_PMD), 4511 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM, 4512 INTERP_LO3, 0, &rx_int5_interp_mux, 4513 wcd9335_codec_enable_interpolator, 4514 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4515 SND_SOC_DAPM_POST_PMD), 4516 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM, 4517 INTERP_LO4, 0, &rx_int6_interp_mux, 4518 wcd9335_codec_enable_interpolator, 4519 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4520 SND_SOC_DAPM_POST_PMD), 4521 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM, 4522 INTERP_SPKR1, 0, &rx_int7_interp_mux, 4523 wcd9335_codec_enable_interpolator, 4524 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4525 SND_SOC_DAPM_POST_PMD), 4526 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM, 4527 INTERP_SPKR2, 0, &rx_int8_interp_mux, 4528 wcd9335_codec_enable_interpolator, 4529 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4530 SND_SOC_DAPM_POST_PMD), 4531 4532 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM, 4533 0, 0, wcd9335_codec_ear_dac_event, 4534 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4535 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4536 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH, 4537 5, 0, wcd9335_codec_hphl_dac_event, 4538 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4539 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4540 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH, 4541 4, 0, wcd9335_codec_hphr_dac_event, 4542 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4543 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4544 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM, 4545 0, 0, wcd9335_codec_lineout_dac_event, 4546 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4547 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM, 4548 0, 0, wcd9335_codec_lineout_dac_event, 4549 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4550 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM, 4551 0, 0, wcd9335_codec_lineout_dac_event, 4552 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4553 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM, 4554 0, 0, wcd9335_codec_lineout_dac_event, 4555 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 4556 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0, 4557 wcd9335_codec_enable_hphl_pa, 4558 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4559 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4560 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0, 4561 wcd9335_codec_enable_hphr_pa, 4562 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4563 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4564 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0, 4565 wcd9335_codec_enable_ear_pa, 4566 SND_SOC_DAPM_POST_PMU | 4567 SND_SOC_DAPM_POST_PMD), 4568 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0, 4569 wcd9335_codec_enable_lineout_pa, 4570 SND_SOC_DAPM_POST_PMU | 4571 SND_SOC_DAPM_POST_PMD), 4572 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0, 4573 wcd9335_codec_enable_lineout_pa, 4574 SND_SOC_DAPM_POST_PMU | 4575 SND_SOC_DAPM_POST_PMD), 4576 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0, 4577 wcd9335_codec_enable_lineout_pa, 4578 SND_SOC_DAPM_POST_PMU | 4579 SND_SOC_DAPM_POST_PMD), 4580 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0, 4581 wcd9335_codec_enable_lineout_pa, 4582 SND_SOC_DAPM_POST_PMU | 4583 SND_SOC_DAPM_POST_PMD), 4584 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0, 4585 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU | 4586 SND_SOC_DAPM_POST_PMD), 4587 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, 4588 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU | 4589 SND_SOC_DAPM_POST_PMD), 4590 4591 /* TX */ 4592 SND_SOC_DAPM_INPUT("AMIC1"), 4593 SND_SOC_DAPM_INPUT("AMIC2"), 4594 SND_SOC_DAPM_INPUT("AMIC3"), 4595 SND_SOC_DAPM_INPUT("AMIC4"), 4596 SND_SOC_DAPM_INPUT("AMIC5"), 4597 SND_SOC_DAPM_INPUT("AMIC6"), 4598 4599 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM, 4600 AIF1_CAP, 0, wcd9335_codec_enable_slim, 4601 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4602 4603 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM, 4604 AIF2_CAP, 0, wcd9335_codec_enable_slim, 4605 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4606 4607 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM, 4608 AIF3_CAP, 0, wcd9335_codec_enable_slim, 4609 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4610 4611 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0, 4612 wcd9335_codec_enable_micbias, 4613 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4614 SND_SOC_DAPM_POST_PMD), 4615 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0, 4616 wcd9335_codec_enable_micbias, 4617 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4618 SND_SOC_DAPM_POST_PMD), 4619 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0, 4620 wcd9335_codec_enable_micbias, 4621 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4622 SND_SOC_DAPM_POST_PMD), 4623 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0, 4624 wcd9335_codec_enable_micbias, 4625 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4626 SND_SOC_DAPM_POST_PMD), 4627 4628 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0, 4629 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4630 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0, 4631 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4632 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0, 4633 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4634 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0, 4635 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4636 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0, 4637 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4638 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0, 4639 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU), 4640 4641 /* Digital Mic Inputs */ 4642 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0, 4643 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4644 SND_SOC_DAPM_POST_PMD), 4645 4646 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, 4647 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4648 SND_SOC_DAPM_POST_PMD), 4649 4650 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, 4651 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4652 SND_SOC_DAPM_POST_PMD), 4653 4654 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0, 4655 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4656 SND_SOC_DAPM_POST_PMD), 4657 4658 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0, 4659 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4660 SND_SOC_DAPM_POST_PMD), 4661 4662 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0, 4663 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | 4664 SND_SOC_DAPM_POST_PMD), 4665 4666 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, 4667 &tx_dmic_mux0), 4668 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, 4669 &tx_dmic_mux1), 4670 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, 4671 &tx_dmic_mux2), 4672 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, 4673 &tx_dmic_mux3), 4674 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, 4675 &tx_dmic_mux4), 4676 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, 4677 &tx_dmic_mux5), 4678 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, 4679 &tx_dmic_mux6), 4680 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, 4681 &tx_dmic_mux7), 4682 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, 4683 &tx_dmic_mux8), 4684 4685 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, 4686 &tx_amic_mux0), 4687 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, 4688 &tx_amic_mux1), 4689 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, 4690 &tx_amic_mux2), 4691 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, 4692 &tx_amic_mux3), 4693 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, 4694 &tx_amic_mux4), 4695 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, 4696 &tx_amic_mux5), 4697 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, 4698 &tx_amic_mux6), 4699 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, 4700 &tx_amic_mux7), 4701 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, 4702 &tx_amic_mux8), 4703 4704 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0, 4705 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)), 4706 4707 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0, 4708 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)), 4709 4710 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0, 4711 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)), 4712 4713 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0, 4714 &sb_tx0_mux), 4715 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0, 4716 &sb_tx1_mux), 4717 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0, 4718 &sb_tx2_mux), 4719 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0, 4720 &sb_tx3_mux), 4721 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0, 4722 &sb_tx4_mux), 4723 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0, 4724 &sb_tx5_mux), 4725 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0, 4726 &sb_tx6_mux), 4727 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0, 4728 &sb_tx7_mux), 4729 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0, 4730 &sb_tx8_mux), 4731 4732 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0, 4733 &tx_adc_mux0, wcd9335_codec_enable_dec, 4734 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4735 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4736 4737 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0, 4738 &tx_adc_mux1, wcd9335_codec_enable_dec, 4739 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4740 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4741 4742 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0, 4743 &tx_adc_mux2, wcd9335_codec_enable_dec, 4744 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4745 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4746 4747 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0, 4748 &tx_adc_mux3, wcd9335_codec_enable_dec, 4749 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4750 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4751 4752 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0, 4753 &tx_adc_mux4, wcd9335_codec_enable_dec, 4754 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4755 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4756 4757 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0, 4758 &tx_adc_mux5, wcd9335_codec_enable_dec, 4759 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4760 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4761 4762 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0, 4763 &tx_adc_mux6, wcd9335_codec_enable_dec, 4764 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4765 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4766 4767 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0, 4768 &tx_adc_mux7, wcd9335_codec_enable_dec, 4769 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4770 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4771 4772 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0, 4773 &tx_adc_mux8, wcd9335_codec_enable_dec, 4774 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 4775 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 4776 }; 4777 4778 static void wcd9335_enable_sido_buck(struct snd_soc_component *component) 4779 { 4780 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4781 4782 snd_soc_component_update_bits(component, WCD9335_ANA_RCO, 4783 WCD9335_ANA_RCO_BG_EN_MASK, 4784 WCD9335_ANA_RCO_BG_ENABLE); 4785 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4786 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK, 4787 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT); 4788 /* 100us sleep needed after IREF settings */ 4789 usleep_range(100, 110); 4790 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL, 4791 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK, 4792 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT); 4793 /* 100us sleep needed after VREF settings */ 4794 usleep_range(100, 110); 4795 wcd->sido_input_src = SIDO_SOURCE_RCO_BG; 4796 } 4797 4798 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp) 4799 { 4800 _wcd9335_codec_enable_mclk(comp, true); 4801 snd_soc_component_update_bits(comp, 4802 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 4803 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK, 4804 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE); 4805 /* 4806 * 5ms sleep required after enabling efuse control 4807 * before checking the status. 4808 */ 4809 usleep_range(5000, 5500); 4810 4811 if (!(snd_soc_component_read32(comp, 4812 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) & 4813 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK)) 4814 WARN(1, "%s: Efuse sense is not complete\n", __func__); 4815 4816 wcd9335_enable_sido_buck(comp); 4817 _wcd9335_codec_enable_mclk(comp, false); 4818 4819 return 0; 4820 } 4821 4822 static void wcd9335_codec_init(struct snd_soc_component *component) 4823 { 4824 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4825 int i; 4826 4827 /* ungate MCLK and set clk rate */ 4828 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE, 4829 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0); 4830 4831 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4832 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4833 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4834 4835 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++) 4836 snd_soc_component_update_bits(component, 4837 wcd9335_codec_reg_init[i].reg, 4838 wcd9335_codec_reg_init[i].mask, 4839 wcd9335_codec_reg_init[i].val); 4840 4841 wcd9335_enable_efuse_sensing(component); 4842 } 4843 4844 static int wcd9335_codec_probe(struct snd_soc_component *component) 4845 { 4846 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev); 4847 int i; 4848 4849 snd_soc_component_init_regmap(component, wcd->regmap); 4850 /* Class-H Init*/ 4851 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version); 4852 if (IS_ERR(wcd->clsh_ctrl)) 4853 return PTR_ERR(wcd->clsh_ctrl); 4854 4855 /* Default HPH Mode to Class-H HiFi */ 4856 wcd->hph_mode = CLS_H_HIFI; 4857 wcd->component = component; 4858 4859 wcd9335_codec_init(component); 4860 4861 for (i = 0; i < NUM_CODEC_DAIS; i++) 4862 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list); 4863 4864 return wcd9335_setup_irqs(wcd); 4865 } 4866 4867 static void wcd9335_codec_remove(struct snd_soc_component *comp) 4868 { 4869 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4870 4871 wcd_clsh_ctrl_free(wcd->clsh_ctrl); 4872 free_irq(regmap_irq_get_virq(wcd->irq_data, WCD9335_IRQ_SLIMBUS), wcd); 4873 } 4874 4875 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp, 4876 int clk_id, int source, 4877 unsigned int freq, int dir) 4878 { 4879 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev); 4880 4881 wcd->mclk_rate = freq; 4882 4883 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ) 4884 snd_soc_component_update_bits(comp, 4885 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4886 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4887 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ); 4888 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ) 4889 snd_soc_component_update_bits(comp, 4890 WCD9335_CODEC_RPM_CLK_MCLK_CFG, 4891 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK, 4892 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ); 4893 4894 return clk_set_rate(wcd->mclk, freq); 4895 } 4896 4897 static const struct snd_soc_component_driver wcd9335_component_drv = { 4898 .probe = wcd9335_codec_probe, 4899 .remove = wcd9335_codec_remove, 4900 .set_sysclk = wcd9335_codec_set_sysclk, 4901 .controls = wcd9335_snd_controls, 4902 .num_controls = ARRAY_SIZE(wcd9335_snd_controls), 4903 .dapm_widgets = wcd9335_dapm_widgets, 4904 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets), 4905 .dapm_routes = wcd9335_audio_map, 4906 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map), 4907 }; 4908 4909 static int wcd9335_probe(struct wcd9335_codec *wcd) 4910 { 4911 struct device *dev = wcd->dev; 4912 4913 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs)); 4914 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs)); 4915 4916 wcd->sido_input_src = SIDO_SOURCE_INTERNAL; 4917 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV; 4918 4919 return devm_snd_soc_register_component(dev, &wcd9335_component_drv, 4920 wcd9335_slim_dais, 4921 ARRAY_SIZE(wcd9335_slim_dais)); 4922 } 4923 4924 static const struct regmap_range_cfg wcd9335_ranges[] = { 4925 { 4926 .name = "WCD9335", 4927 .range_min = 0x0, 4928 .range_max = WCD9335_MAX_REGISTER, 4929 .selector_reg = WCD9335_REG(0x0, 0), 4930 .selector_mask = 0xff, 4931 .selector_shift = 0, 4932 .window_start = 0x0, 4933 .window_len = 0x1000, 4934 }, 4935 }; 4936 4937 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg) 4938 { 4939 switch (reg) { 4940 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3: 4941 case WCD9335_ANA_MBHC_RESULT_3: 4942 case WCD9335_ANA_MBHC_RESULT_2: 4943 case WCD9335_ANA_MBHC_RESULT_1: 4944 case WCD9335_ANA_MBHC_MECH: 4945 case WCD9335_ANA_MBHC_ELECT: 4946 case WCD9335_ANA_MBHC_ZDET: 4947 case WCD9335_ANA_MICB2: 4948 case WCD9335_ANA_RCO: 4949 case WCD9335_ANA_BIAS: 4950 return true; 4951 default: 4952 return false; 4953 } 4954 } 4955 4956 static struct regmap_config wcd9335_regmap_config = { 4957 .reg_bits = 16, 4958 .val_bits = 8, 4959 .cache_type = REGCACHE_RBTREE, 4960 .max_register = WCD9335_MAX_REGISTER, 4961 .can_multi_write = true, 4962 .ranges = wcd9335_ranges, 4963 .num_ranges = ARRAY_SIZE(wcd9335_ranges), 4964 .volatile_reg = wcd9335_is_volatile_register, 4965 }; 4966 4967 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = { 4968 { 4969 .name = "WCD9335-IFC-DEV", 4970 .range_min = 0x0, 4971 .range_max = WCD9335_REG(0, 0x7ff), 4972 .selector_reg = WCD9335_REG(0, 0x0), 4973 .selector_mask = 0xff, 4974 .selector_shift = 0, 4975 .window_start = 0x0, 4976 .window_len = 0x1000, 4977 }, 4978 }; 4979 4980 static struct regmap_config wcd9335_ifc_regmap_config = { 4981 .reg_bits = 16, 4982 .val_bits = 8, 4983 .can_multi_write = true, 4984 .max_register = WCD9335_REG(0, 0x7FF), 4985 .ranges = wcd9335_ifc_ranges, 4986 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges), 4987 }; 4988 4989 static const struct regmap_irq wcd9335_codec_irqs[] = { 4990 /* INTR_REG 0 */ 4991 [WCD9335_IRQ_SLIMBUS] = { 4992 .reg_offset = 0, 4993 .mask = BIT(0), 4994 .type = { 4995 .type_reg_offset = 0, 4996 .types_supported = IRQ_TYPE_EDGE_BOTH, 4997 .type_reg_mask = BIT(0), 4998 }, 4999 }, 5000 }; 5001 5002 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = { 5003 .name = "wcd9335_pin1_irq", 5004 .status_base = WCD9335_INTR_PIN1_STATUS0, 5005 .mask_base = WCD9335_INTR_PIN1_MASK0, 5006 .ack_base = WCD9335_INTR_PIN1_CLEAR0, 5007 .type_base = WCD9335_INTR_LEVEL0, 5008 .num_type_reg = 4, 5009 .num_regs = 4, 5010 .irqs = wcd9335_codec_irqs, 5011 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs), 5012 }; 5013 5014 static int wcd9335_parse_dt(struct wcd9335_codec *wcd) 5015 { 5016 struct device *dev = wcd->dev; 5017 struct device_node *np = dev->of_node; 5018 int ret; 5019 5020 wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0); 5021 if (wcd->reset_gpio < 0) { 5022 dev_err(dev, "Reset GPIO missing from DT\n"); 5023 return wcd->reset_gpio; 5024 } 5025 5026 wcd->mclk = devm_clk_get(dev, "mclk"); 5027 if (IS_ERR(wcd->mclk)) { 5028 dev_err(dev, "mclk not found\n"); 5029 return PTR_ERR(wcd->mclk); 5030 } 5031 5032 wcd->native_clk = devm_clk_get(dev, "slimbus"); 5033 if (IS_ERR(wcd->native_clk)) { 5034 dev_err(dev, "slimbus clock not found\n"); 5035 return PTR_ERR(wcd->native_clk); 5036 } 5037 5038 wcd->supplies[0].supply = "vdd-buck"; 5039 wcd->supplies[1].supply = "vdd-buck-sido"; 5040 wcd->supplies[2].supply = "vdd-tx"; 5041 wcd->supplies[3].supply = "vdd-rx"; 5042 wcd->supplies[4].supply = "vdd-io"; 5043 5044 ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies); 5045 if (ret) { 5046 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5047 return ret; 5048 } 5049 5050 return 0; 5051 } 5052 5053 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd) 5054 { 5055 struct device *dev = wcd->dev; 5056 int ret; 5057 5058 ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies); 5059 if (ret) { 5060 dev_err(dev, "Failed to get supplies: err = %d\n", ret); 5061 return ret; 5062 } 5063 5064 /* 5065 * For WCD9335, it takes about 600us for the Vout_A and 5066 * Vout_D to be ready after BUCK_SIDO is powered up. 5067 * SYS_RST_N shouldn't be pulled high during this time 5068 * Toggle the reset line to make sure the reset pulse is 5069 * correctly applied 5070 */ 5071 usleep_range(600, 650); 5072 5073 gpio_direction_output(wcd->reset_gpio, 0); 5074 msleep(20); 5075 gpio_set_value(wcd->reset_gpio, 1); 5076 msleep(20); 5077 5078 return 0; 5079 } 5080 5081 static int wcd9335_bring_up(struct wcd9335_codec *wcd) 5082 { 5083 struct regmap *rm = wcd->regmap; 5084 int val, byte0; 5085 5086 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val); 5087 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0); 5088 5089 if ((val < 0) || (byte0 < 0)) { 5090 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n"); 5091 return -EINVAL; 5092 } 5093 5094 if (byte0 == 0x1) { 5095 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n"); 5096 wcd->version = WCD9335_VERSION_2_0; 5097 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01); 5098 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00); 5099 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F); 5100 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65); 5101 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5); 5102 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7); 5103 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3); 5104 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3); 5105 } else { 5106 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n"); 5107 return -EINVAL; 5108 } 5109 5110 return 0; 5111 } 5112 5113 static int wcd9335_irq_init(struct wcd9335_codec *wcd) 5114 { 5115 int ret; 5116 5117 /* 5118 * INTR1 consists of all possible interrupt sources Ear OCP, 5119 * HPH OCP, MBHC, MAD, VBAT, and SVA 5120 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA 5121 */ 5122 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1"); 5123 if (wcd->intr1 < 0) { 5124 if (wcd->intr1 != -EPROBE_DEFER) 5125 dev_err(wcd->dev, "Unable to configure IRQ\n"); 5126 5127 return wcd->intr1; 5128 } 5129 5130 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1, 5131 IRQF_TRIGGER_HIGH, 0, 5132 &wcd9335_regmap_irq1_chip, &wcd->irq_data); 5133 if (ret) 5134 dev_err(wcd->dev, "Failed to register IRQ chip: %d\n", ret); 5135 5136 return ret; 5137 } 5138 5139 static int wcd9335_slim_probe(struct slim_device *slim) 5140 { 5141 struct device *dev = &slim->dev; 5142 struct wcd9335_codec *wcd; 5143 int ret; 5144 5145 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL); 5146 if (!wcd) 5147 return -ENOMEM; 5148 5149 wcd->dev = dev; 5150 ret = wcd9335_parse_dt(wcd); 5151 if (ret) { 5152 dev_err(dev, "Error parsing DT: %d\n", ret); 5153 return ret; 5154 } 5155 5156 ret = wcd9335_power_on_reset(wcd); 5157 if (ret) 5158 return ret; 5159 5160 dev_set_drvdata(dev, wcd); 5161 5162 return 0; 5163 } 5164 5165 static int wcd9335_slim_status(struct slim_device *sdev, 5166 enum slim_device_status status) 5167 { 5168 struct device *dev = &sdev->dev; 5169 struct device_node *ifc_dev_np; 5170 struct wcd9335_codec *wcd; 5171 int ret; 5172 5173 wcd = dev_get_drvdata(dev); 5174 5175 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0); 5176 if (!ifc_dev_np) { 5177 dev_err(dev, "No Interface device found\n"); 5178 return -EINVAL; 5179 } 5180 5181 wcd->slim = sdev; 5182 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np); 5183 of_node_put(ifc_dev_np); 5184 if (!wcd->slim_ifc_dev) { 5185 dev_err(dev, "Unable to get SLIM Interface device\n"); 5186 return -EINVAL; 5187 } 5188 5189 slim_get_logical_addr(wcd->slim_ifc_dev); 5190 5191 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config); 5192 if (IS_ERR(wcd->regmap)) { 5193 dev_err(dev, "Failed to allocate slim register map\n"); 5194 return PTR_ERR(wcd->regmap); 5195 } 5196 5197 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev, 5198 &wcd9335_ifc_regmap_config); 5199 if (IS_ERR(wcd->if_regmap)) { 5200 dev_err(dev, "Failed to allocate ifc register map\n"); 5201 return PTR_ERR(wcd->if_regmap); 5202 } 5203 5204 ret = wcd9335_bring_up(wcd); 5205 if (ret) { 5206 dev_err(dev, "Failed to bringup WCD9335\n"); 5207 return ret; 5208 } 5209 5210 ret = wcd9335_irq_init(wcd); 5211 if (ret) 5212 return ret; 5213 5214 wcd9335_probe(wcd); 5215 5216 return ret; 5217 } 5218 5219 static const struct slim_device_id wcd9335_slim_id[] = { 5220 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0}, 5221 {} 5222 }; 5223 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id); 5224 5225 static struct slim_driver wcd9335_slim_driver = { 5226 .driver = { 5227 .name = "wcd9335-slim", 5228 }, 5229 .probe = wcd9335_slim_probe, 5230 .device_status = wcd9335_slim_status, 5231 .id_table = wcd9335_slim_id, 5232 }; 5233 5234 module_slim_driver(wcd9335_slim_driver); 5235 MODULE_DESCRIPTION("WCD9335 slim driver"); 5236 MODULE_LICENSE("GPL v2"); 5237 MODULE_ALIAS("slim:217:1a0:*"); 5238