1 /* 2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com> 9 * 10 * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC 11 * codec model. 12 * 13 * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org> 14 * Copyright 2005 Openedhand Ltd. 15 */ 16 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/types.h> 20 #include <linux/slab.h> 21 #include <linux/errno.h> 22 #include <linux/gpio.h> 23 #include <linux/delay.h> 24 #include <linux/i2c.h> 25 #include <linux/workqueue.h> 26 #include <sound/core.h> 27 #include <sound/control.h> 28 #include <sound/initval.h> 29 #include <sound/soc.h> 30 #include <sound/tlv.h> 31 #include <sound/uda1380.h> 32 33 #include "uda1380.h" 34 35 /* codec private data */ 36 struct uda1380_priv { 37 struct snd_soc_codec *codec; 38 unsigned int dac_clk; 39 struct work_struct work; 40 void *control_data; 41 }; 42 43 /* 44 * uda1380 register cache 45 */ 46 static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = { 47 0x0502, 0x0000, 0x0000, 0x3f3f, 48 0x0202, 0x0000, 0x0000, 0x0000, 49 0x0000, 0x0000, 0x0000, 0x0000, 50 0x0000, 0x0000, 0x0000, 0x0000, 51 0x0000, 0xff00, 0x0000, 0x4800, 52 0x0000, 0x0000, 0x0000, 0x0000, 53 0x0000, 0x0000, 0x0000, 0x0000, 54 0x0000, 0x0000, 0x0000, 0x0000, 55 0x0000, 0x8000, 0x0002, 0x0000, 56 }; 57 58 static unsigned long uda1380_cache_dirty; 59 60 /* 61 * read uda1380 register cache 62 */ 63 static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec, 64 unsigned int reg) 65 { 66 u16 *cache = codec->reg_cache; 67 if (reg == UDA1380_RESET) 68 return 0; 69 if (reg >= UDA1380_CACHEREGNUM) 70 return -1; 71 return cache[reg]; 72 } 73 74 /* 75 * write uda1380 register cache 76 */ 77 static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec, 78 u16 reg, unsigned int value) 79 { 80 u16 *cache = codec->reg_cache; 81 82 if (reg >= UDA1380_CACHEREGNUM) 83 return; 84 if ((reg >= 0x10) && (cache[reg] != value)) 85 set_bit(reg - 0x10, &uda1380_cache_dirty); 86 cache[reg] = value; 87 } 88 89 /* 90 * write to the UDA1380 register space 91 */ 92 static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg, 93 unsigned int value) 94 { 95 u8 data[3]; 96 97 /* data is 98 * data[0] is register offset 99 * data[1] is MS byte 100 * data[2] is LS byte 101 */ 102 data[0] = reg; 103 data[1] = (value & 0xff00) >> 8; 104 data[2] = value & 0x00ff; 105 106 uda1380_write_reg_cache(codec, reg, value); 107 108 /* the interpolator & decimator regs must only be written when the 109 * codec DAI is active. 110 */ 111 if (!snd_soc_codec_is_active(codec) && (reg >= UDA1380_MVOL)) 112 return 0; 113 pr_debug("uda1380: hw write %x val %x\n", reg, value); 114 if (codec->hw_write(codec->control_data, data, 3) == 3) { 115 unsigned int val; 116 i2c_master_send(codec->control_data, data, 1); 117 i2c_master_recv(codec->control_data, data, 2); 118 val = (data[0]<<8) | data[1]; 119 if (val != value) { 120 pr_debug("uda1380: READ BACK VAL %x\n", 121 (data[0]<<8) | data[1]); 122 return -EIO; 123 } 124 if (reg >= 0x10) 125 clear_bit(reg - 0x10, &uda1380_cache_dirty); 126 return 0; 127 } else 128 return -EIO; 129 } 130 131 static void uda1380_sync_cache(struct snd_soc_codec *codec) 132 { 133 int reg; 134 u8 data[3]; 135 u16 *cache = codec->reg_cache; 136 137 /* Sync reg_cache with the hardware */ 138 for (reg = 0; reg < UDA1380_MVOL; reg++) { 139 data[0] = reg; 140 data[1] = (cache[reg] & 0xff00) >> 8; 141 data[2] = cache[reg] & 0x00ff; 142 if (codec->hw_write(codec->control_data, data, 3) != 3) 143 dev_err(codec->dev, "%s: write to reg 0x%x failed\n", 144 __func__, reg); 145 } 146 } 147 148 static int uda1380_reset(struct snd_soc_codec *codec) 149 { 150 struct uda1380_platform_data *pdata = codec->dev->platform_data; 151 152 if (gpio_is_valid(pdata->gpio_reset)) { 153 gpio_set_value(pdata->gpio_reset, 1); 154 mdelay(1); 155 gpio_set_value(pdata->gpio_reset, 0); 156 } else { 157 u8 data[3]; 158 159 data[0] = UDA1380_RESET; 160 data[1] = 0; 161 data[2] = 0; 162 163 if (codec->hw_write(codec->control_data, data, 3) != 3) { 164 dev_err(codec->dev, "%s: failed\n", __func__); 165 return -EIO; 166 } 167 } 168 169 return 0; 170 } 171 172 static void uda1380_flush_work(struct work_struct *work) 173 { 174 struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work); 175 struct snd_soc_codec *uda1380_codec = uda1380->codec; 176 int bit, reg; 177 178 for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) { 179 reg = 0x10 + bit; 180 pr_debug("uda1380: flush reg %x val %x:\n", reg, 181 uda1380_read_reg_cache(uda1380_codec, reg)); 182 uda1380_write(uda1380_codec, reg, 183 uda1380_read_reg_cache(uda1380_codec, reg)); 184 clear_bit(bit, &uda1380_cache_dirty); 185 } 186 187 } 188 189 /* declarations of ALSA reg_elem_REAL controls */ 190 static const char *uda1380_deemp[] = { 191 "None", 192 "32kHz", 193 "44.1kHz", 194 "48kHz", 195 "96kHz", 196 }; 197 static const char *uda1380_input_sel[] = { 198 "Line", 199 "Mic + Line R", 200 "Line L", 201 "Mic", 202 }; 203 static const char *uda1380_output_sel[] = { 204 "DAC", 205 "Analog Mixer", 206 }; 207 static const char *uda1380_spf_mode[] = { 208 "Flat", 209 "Minimum1", 210 "Minimum2", 211 "Maximum" 212 }; 213 static const char *uda1380_capture_sel[] = { 214 "ADC", 215 "Digital Mixer" 216 }; 217 static const char *uda1380_sel_ns[] = { 218 "3rd-order", 219 "5th-order" 220 }; 221 static const char *uda1380_mix_control[] = { 222 "off", 223 "PCM only", 224 "before sound processing", 225 "after sound processing" 226 }; 227 static const char *uda1380_sdet_setting[] = { 228 "3200", 229 "4800", 230 "9600", 231 "19200" 232 }; 233 static const char *uda1380_os_setting[] = { 234 "single-speed", 235 "double-speed (no mixing)", 236 "quad-speed (no mixing)" 237 }; 238 239 static const struct soc_enum uda1380_deemp_enum[] = { 240 SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, ARRAY_SIZE(uda1380_deemp), 241 uda1380_deemp), 242 SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, ARRAY_SIZE(uda1380_deemp), 243 uda1380_deemp), 244 }; 245 static SOC_ENUM_SINGLE_DECL(uda1380_input_sel_enum, 246 UDA1380_ADC, 2, uda1380_input_sel); /* SEL_MIC, SEL_LNA */ 247 static SOC_ENUM_SINGLE_DECL(uda1380_output_sel_enum, 248 UDA1380_PM, 7, uda1380_output_sel); /* R02_EN_AVC */ 249 static SOC_ENUM_SINGLE_DECL(uda1380_spf_enum, 250 UDA1380_MODE, 14, uda1380_spf_mode); /* M */ 251 static SOC_ENUM_SINGLE_DECL(uda1380_capture_sel_enum, 252 UDA1380_IFACE, 6, uda1380_capture_sel); /* SEL_SOURCE */ 253 static SOC_ENUM_SINGLE_DECL(uda1380_sel_ns_enum, 254 UDA1380_MIXER, 14, uda1380_sel_ns); /* SEL_NS */ 255 static SOC_ENUM_SINGLE_DECL(uda1380_mix_enum, 256 UDA1380_MIXER, 12, uda1380_mix_control); /* MIX, MIX_POS */ 257 static SOC_ENUM_SINGLE_DECL(uda1380_sdet_enum, 258 UDA1380_MIXER, 4, uda1380_sdet_setting); /* SD_VALUE */ 259 static SOC_ENUM_SINGLE_DECL(uda1380_os_enum, 260 UDA1380_MIXER, 0, uda1380_os_setting); /* OS */ 261 262 /* 263 * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB) 264 */ 265 static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1); 266 267 /* 268 * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored), 269 * from -66 dB in 0.5 dB steps (2 dB steps, really) and 270 * from -52 dB in 0.25 dB steps 271 */ 272 static const DECLARE_TLV_DB_RANGE(mvol_tlv, 273 0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1), 274 16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0), 275 44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0) 276 ); 277 278 /* 279 * from -72 dB in 1.5 dB steps (6 dB steps really), 280 * from -66 dB in 0.75 dB steps (3 dB steps really), 281 * from -60 dB in 0.5 dB steps (2 dB steps really) and 282 * from -46 dB in 0.25 dB steps 283 */ 284 static const DECLARE_TLV_DB_RANGE(vc_tlv, 285 0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1), 286 8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0), 287 16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0), 288 44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0) 289 ); 290 291 /* from 0 to 6 dB in 2 dB steps if SPF mode != flat */ 292 static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0); 293 294 /* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts 295 * off at 18 dB max) */ 296 static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0); 297 298 /* from -63 to 24 dB in 0.5 dB steps (-128...48) */ 299 static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1); 300 301 /* from 0 to 24 dB in 3 dB steps */ 302 static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0); 303 304 /* from 0 to 30 dB in 2 dB steps */ 305 static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0); 306 307 static const struct snd_kcontrol_new uda1380_snd_controls[] = { 308 SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */ 309 SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */ 310 SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */ 311 SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */ 312 SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */ 313 SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */ 314 SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */ 315 /**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */ 316 SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */ 317 SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */ 318 SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */ 319 SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */ 320 SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */ 321 SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */ 322 SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */ 323 SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */ 324 SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */ 325 SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */ 326 SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */ 327 /**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */ 328 SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */ 329 SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */ 330 SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */ 331 SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */ 332 SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */ 333 SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */ 334 SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */ 335 /* -5.5, -8, -11.5, -14 dBFS */ 336 SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0), 337 }; 338 339 /* Input mux */ 340 static const struct snd_kcontrol_new uda1380_input_mux_control = 341 SOC_DAPM_ENUM("Route", uda1380_input_sel_enum); 342 343 /* Output mux */ 344 static const struct snd_kcontrol_new uda1380_output_mux_control = 345 SOC_DAPM_ENUM("Route", uda1380_output_sel_enum); 346 347 /* Capture mux */ 348 static const struct snd_kcontrol_new uda1380_capture_mux_control = 349 SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum); 350 351 352 static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = { 353 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0, 354 &uda1380_input_mux_control), 355 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0, 356 &uda1380_output_mux_control), 357 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, 358 &uda1380_capture_mux_control), 359 SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0), 360 SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0), 361 SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0), 362 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0), 363 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0), 364 SND_SOC_DAPM_INPUT("VINM"), 365 SND_SOC_DAPM_INPUT("VINL"), 366 SND_SOC_DAPM_INPUT("VINR"), 367 SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0), 368 SND_SOC_DAPM_OUTPUT("VOUTLHP"), 369 SND_SOC_DAPM_OUTPUT("VOUTRHP"), 370 SND_SOC_DAPM_OUTPUT("VOUTL"), 371 SND_SOC_DAPM_OUTPUT("VOUTR"), 372 SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0), 373 SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0), 374 }; 375 376 static const struct snd_soc_dapm_route uda1380_dapm_routes[] = { 377 378 /* output mux */ 379 {"HeadPhone Driver", NULL, "Output Mux"}, 380 {"VOUTR", NULL, "Output Mux"}, 381 {"VOUTL", NULL, "Output Mux"}, 382 383 {"Analog Mixer", NULL, "VINR"}, 384 {"Analog Mixer", NULL, "VINL"}, 385 {"Analog Mixer", NULL, "DAC"}, 386 387 {"Output Mux", "DAC", "DAC"}, 388 {"Output Mux", "Analog Mixer", "Analog Mixer"}, 389 390 /* {"DAC", "Digital Mixer", "I2S" } */ 391 392 /* headphone driver */ 393 {"VOUTLHP", NULL, "HeadPhone Driver"}, 394 {"VOUTRHP", NULL, "HeadPhone Driver"}, 395 396 /* input mux */ 397 {"Left ADC", NULL, "Input Mux"}, 398 {"Input Mux", "Mic", "Mic LNA"}, 399 {"Input Mux", "Mic + Line R", "Mic LNA"}, 400 {"Input Mux", "Line L", "Left PGA"}, 401 {"Input Mux", "Line", "Left PGA"}, 402 403 /* right input */ 404 {"Right ADC", "Mic + Line R", "Right PGA"}, 405 {"Right ADC", "Line", "Right PGA"}, 406 407 /* inputs */ 408 {"Mic LNA", NULL, "VINM"}, 409 {"Left PGA", NULL, "VINL"}, 410 {"Right PGA", NULL, "VINR"}, 411 }; 412 413 static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai, 414 unsigned int fmt) 415 { 416 struct snd_soc_codec *codec = codec_dai->codec; 417 int iface; 418 419 /* set up DAI based upon fmt */ 420 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE); 421 iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK); 422 423 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 424 case SND_SOC_DAIFMT_I2S: 425 iface |= R01_SFORI_I2S | R01_SFORO_I2S; 426 break; 427 case SND_SOC_DAIFMT_LSB: 428 iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16; 429 break; 430 case SND_SOC_DAIFMT_MSB: 431 iface |= R01_SFORI_MSB | R01_SFORO_MSB; 432 } 433 434 /* DATAI is slave only, so in single-link mode, this has to be slave */ 435 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) 436 return -EINVAL; 437 438 uda1380_write_reg_cache(codec, UDA1380_IFACE, iface); 439 440 return 0; 441 } 442 443 static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai, 444 unsigned int fmt) 445 { 446 struct snd_soc_codec *codec = codec_dai->codec; 447 int iface; 448 449 /* set up DAI based upon fmt */ 450 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE); 451 iface &= ~R01_SFORI_MASK; 452 453 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 454 case SND_SOC_DAIFMT_I2S: 455 iface |= R01_SFORI_I2S; 456 break; 457 case SND_SOC_DAIFMT_LSB: 458 iface |= R01_SFORI_LSB16; 459 break; 460 case SND_SOC_DAIFMT_MSB: 461 iface |= R01_SFORI_MSB; 462 } 463 464 /* DATAI is slave only, so this has to be slave */ 465 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) 466 return -EINVAL; 467 468 uda1380_write(codec, UDA1380_IFACE, iface); 469 470 return 0; 471 } 472 473 static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai, 474 unsigned int fmt) 475 { 476 struct snd_soc_codec *codec = codec_dai->codec; 477 int iface; 478 479 /* set up DAI based upon fmt */ 480 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE); 481 iface &= ~(R01_SIM | R01_SFORO_MASK); 482 483 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 484 case SND_SOC_DAIFMT_I2S: 485 iface |= R01_SFORO_I2S; 486 break; 487 case SND_SOC_DAIFMT_LSB: 488 iface |= R01_SFORO_LSB16; 489 break; 490 case SND_SOC_DAIFMT_MSB: 491 iface |= R01_SFORO_MSB; 492 } 493 494 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM) 495 iface |= R01_SIM; 496 497 uda1380_write(codec, UDA1380_IFACE, iface); 498 499 return 0; 500 } 501 502 static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd, 503 struct snd_soc_dai *dai) 504 { 505 struct snd_soc_codec *codec = dai->codec; 506 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec); 507 int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER); 508 509 switch (cmd) { 510 case SNDRV_PCM_TRIGGER_START: 511 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 512 uda1380_write_reg_cache(codec, UDA1380_MIXER, 513 mixer & ~R14_SILENCE); 514 schedule_work(&uda1380->work); 515 break; 516 case SNDRV_PCM_TRIGGER_STOP: 517 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 518 uda1380_write_reg_cache(codec, UDA1380_MIXER, 519 mixer | R14_SILENCE); 520 schedule_work(&uda1380->work); 521 break; 522 } 523 return 0; 524 } 525 526 static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream, 527 struct snd_pcm_hw_params *params, 528 struct snd_soc_dai *dai) 529 { 530 struct snd_soc_codec *codec = dai->codec; 531 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK); 532 533 /* set WSPLL power and divider if running from this clock */ 534 if (clk & R00_DAC_CLK) { 535 int rate = params_rate(params); 536 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM); 537 clk &= ~0x3; /* clear SEL_LOOP_DIV */ 538 switch (rate) { 539 case 6250 ... 12500: 540 clk |= 0x0; 541 break; 542 case 12501 ... 25000: 543 clk |= 0x1; 544 break; 545 case 25001 ... 50000: 546 clk |= 0x2; 547 break; 548 case 50001 ... 100000: 549 clk |= 0x3; 550 break; 551 } 552 uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm); 553 } 554 555 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 556 clk |= R00_EN_DAC | R00_EN_INT; 557 else 558 clk |= R00_EN_ADC | R00_EN_DEC; 559 560 uda1380_write(codec, UDA1380_CLK, clk); 561 return 0; 562 } 563 564 static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream, 565 struct snd_soc_dai *dai) 566 { 567 struct snd_soc_codec *codec = dai->codec; 568 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK); 569 570 /* shut down WSPLL power if running from this clock */ 571 if (clk & R00_DAC_CLK) { 572 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM); 573 uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm); 574 } 575 576 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 577 clk &= ~(R00_EN_DAC | R00_EN_INT); 578 else 579 clk &= ~(R00_EN_ADC | R00_EN_DEC); 580 581 uda1380_write(codec, UDA1380_CLK, clk); 582 } 583 584 static int uda1380_set_bias_level(struct snd_soc_codec *codec, 585 enum snd_soc_bias_level level) 586 { 587 int pm = uda1380_read_reg_cache(codec, UDA1380_PM); 588 int reg; 589 struct uda1380_platform_data *pdata = codec->dev->platform_data; 590 591 switch (level) { 592 case SND_SOC_BIAS_ON: 593 case SND_SOC_BIAS_PREPARE: 594 /* ADC, DAC on */ 595 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm); 596 break; 597 case SND_SOC_BIAS_STANDBY: 598 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { 599 if (gpio_is_valid(pdata->gpio_power)) { 600 gpio_set_value(pdata->gpio_power, 1); 601 mdelay(1); 602 uda1380_reset(codec); 603 } 604 605 uda1380_sync_cache(codec); 606 } 607 uda1380_write(codec, UDA1380_PM, 0x0); 608 break; 609 case SND_SOC_BIAS_OFF: 610 if (!gpio_is_valid(pdata->gpio_power)) 611 break; 612 613 gpio_set_value(pdata->gpio_power, 0); 614 615 /* Mark mixer regs cache dirty to sync them with 616 * codec regs on power on. 617 */ 618 for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++) 619 set_bit(reg - 0x10, &uda1380_cache_dirty); 620 } 621 return 0; 622 } 623 624 #define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 625 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ 626 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 627 628 static const struct snd_soc_dai_ops uda1380_dai_ops = { 629 .hw_params = uda1380_pcm_hw_params, 630 .shutdown = uda1380_pcm_shutdown, 631 .trigger = uda1380_trigger, 632 .set_fmt = uda1380_set_dai_fmt_both, 633 }; 634 635 static const struct snd_soc_dai_ops uda1380_dai_ops_playback = { 636 .hw_params = uda1380_pcm_hw_params, 637 .shutdown = uda1380_pcm_shutdown, 638 .trigger = uda1380_trigger, 639 .set_fmt = uda1380_set_dai_fmt_playback, 640 }; 641 642 static const struct snd_soc_dai_ops uda1380_dai_ops_capture = { 643 .hw_params = uda1380_pcm_hw_params, 644 .shutdown = uda1380_pcm_shutdown, 645 .trigger = uda1380_trigger, 646 .set_fmt = uda1380_set_dai_fmt_capture, 647 }; 648 649 static struct snd_soc_dai_driver uda1380_dai[] = { 650 { 651 .name = "uda1380-hifi", 652 .playback = { 653 .stream_name = "Playback", 654 .channels_min = 1, 655 .channels_max = 2, 656 .rates = UDA1380_RATES, 657 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 658 .capture = { 659 .stream_name = "Capture", 660 .channels_min = 1, 661 .channels_max = 2, 662 .rates = UDA1380_RATES, 663 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 664 .ops = &uda1380_dai_ops, 665 }, 666 { /* playback only - dual interface */ 667 .name = "uda1380-hifi-playback", 668 .playback = { 669 .stream_name = "Playback", 670 .channels_min = 1, 671 .channels_max = 2, 672 .rates = UDA1380_RATES, 673 .formats = SNDRV_PCM_FMTBIT_S16_LE, 674 }, 675 .ops = &uda1380_dai_ops_playback, 676 }, 677 { /* capture only - dual interface*/ 678 .name = "uda1380-hifi-capture", 679 .capture = { 680 .stream_name = "Capture", 681 .channels_min = 1, 682 .channels_max = 2, 683 .rates = UDA1380_RATES, 684 .formats = SNDRV_PCM_FMTBIT_S16_LE, 685 }, 686 .ops = &uda1380_dai_ops_capture, 687 }, 688 }; 689 690 static int uda1380_probe(struct snd_soc_codec *codec) 691 { 692 struct uda1380_platform_data *pdata =codec->dev->platform_data; 693 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec); 694 int ret; 695 696 uda1380->codec = codec; 697 698 codec->hw_write = (hw_write_t)i2c_master_send; 699 codec->control_data = uda1380->control_data; 700 701 if (!gpio_is_valid(pdata->gpio_power)) { 702 ret = uda1380_reset(codec); 703 if (ret) 704 return ret; 705 } 706 707 INIT_WORK(&uda1380->work, uda1380_flush_work); 708 709 /* set clock input */ 710 switch (pdata->dac_clk) { 711 case UDA1380_DAC_CLK_SYSCLK: 712 uda1380_write_reg_cache(codec, UDA1380_CLK, 0); 713 break; 714 case UDA1380_DAC_CLK_WSPLL: 715 uda1380_write_reg_cache(codec, UDA1380_CLK, 716 R00_DAC_CLK); 717 break; 718 } 719 720 return 0; 721 } 722 723 static struct snd_soc_codec_driver soc_codec_dev_uda1380 = { 724 .probe = uda1380_probe, 725 .read = uda1380_read_reg_cache, 726 .write = uda1380_write, 727 .set_bias_level = uda1380_set_bias_level, 728 .suspend_bias_off = true, 729 730 .reg_cache_size = ARRAY_SIZE(uda1380_reg), 731 .reg_word_size = sizeof(u16), 732 .reg_cache_default = uda1380_reg, 733 .reg_cache_step = 1, 734 735 .component_driver = { 736 .controls = uda1380_snd_controls, 737 .num_controls = ARRAY_SIZE(uda1380_snd_controls), 738 .dapm_widgets = uda1380_dapm_widgets, 739 .num_dapm_widgets = ARRAY_SIZE(uda1380_dapm_widgets), 740 .dapm_routes = uda1380_dapm_routes, 741 .num_dapm_routes = ARRAY_SIZE(uda1380_dapm_routes), 742 }, 743 }; 744 745 static int uda1380_i2c_probe(struct i2c_client *i2c, 746 const struct i2c_device_id *id) 747 { 748 struct uda1380_platform_data *pdata = i2c->dev.platform_data; 749 struct uda1380_priv *uda1380; 750 int ret; 751 752 if (!pdata) 753 return -EINVAL; 754 755 uda1380 = devm_kzalloc(&i2c->dev, sizeof(struct uda1380_priv), 756 GFP_KERNEL); 757 if (uda1380 == NULL) 758 return -ENOMEM; 759 760 if (gpio_is_valid(pdata->gpio_reset)) { 761 ret = devm_gpio_request_one(&i2c->dev, pdata->gpio_reset, 762 GPIOF_OUT_INIT_LOW, "uda1380 reset"); 763 if (ret) 764 return ret; 765 } 766 767 if (gpio_is_valid(pdata->gpio_power)) { 768 ret = devm_gpio_request_one(&i2c->dev, pdata->gpio_power, 769 GPIOF_OUT_INIT_LOW, "uda1380 power"); 770 if (ret) 771 return ret; 772 } 773 774 i2c_set_clientdata(i2c, uda1380); 775 uda1380->control_data = i2c; 776 777 ret = snd_soc_register_codec(&i2c->dev, 778 &soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai)); 779 return ret; 780 } 781 782 static int uda1380_i2c_remove(struct i2c_client *i2c) 783 { 784 snd_soc_unregister_codec(&i2c->dev); 785 return 0; 786 } 787 788 static const struct i2c_device_id uda1380_i2c_id[] = { 789 { "uda1380", 0 }, 790 { } 791 }; 792 MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id); 793 794 static const struct of_device_id uda1380_of_match[] = { 795 { .compatible = "nxp,uda1380", }, 796 { } 797 }; 798 MODULE_DEVICE_TABLE(of, uda1380_of_match); 799 800 static struct i2c_driver uda1380_i2c_driver = { 801 .driver = { 802 .name = "uda1380-codec", 803 .of_match_table = uda1380_of_match, 804 }, 805 .probe = uda1380_i2c_probe, 806 .remove = uda1380_i2c_remove, 807 .id_table = uda1380_i2c_id, 808 }; 809 810 module_i2c_driver(uda1380_i2c_driver); 811 812 MODULE_AUTHOR("Giorgio Padrin"); 813 MODULE_DESCRIPTION("Audio support for codec Philips UDA1380"); 814 MODULE_LICENSE("GPL"); 815