xref: /openbmc/linux/sound/soc/codecs/twl4030.c (revision bc000245)
1 /*
2  * ALSA SoC TWL4030 codec driver
3  *
4  * Author:      Steve Sakoman, <steve@sakoman.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * version 2 as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18  * 02110-1301 USA
19  *
20  */
21 
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/pm.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/of.h>
30 #include <linux/of_gpio.h>
31 #include <linux/i2c/twl.h>
32 #include <linux/slab.h>
33 #include <linux/gpio.h>
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/soc.h>
38 #include <sound/initval.h>
39 #include <sound/tlv.h>
40 
41 /* Register descriptions are here */
42 #include <linux/mfd/twl4030-audio.h>
43 
44 /* TWL4030 PMBR1 Register */
45 #define TWL4030_PMBR1_REG		0x0D
46 /* TWL4030 PMBR1 Register GPIO6 mux bits */
47 #define TWL4030_GPIO6_PWM0_MUTE(value)	((value & 0x03) << 2)
48 
49 #define TWL4030_CACHEREGNUM	(TWL4030_REG_MISC_SET_2 + 1)
50 
51 /*
52  * twl4030 register cache & default register settings
53  */
54 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
55 	0x00, /* this register not used		*/
56 	0x00, /* REG_CODEC_MODE		(0x1)	*/
57 	0x00, /* REG_OPTION		(0x2)	*/
58 	0x00, /* REG_UNKNOWN		(0x3)	*/
59 	0x00, /* REG_MICBIAS_CTL	(0x4)	*/
60 	0x00, /* REG_ANAMICL		(0x5)	*/
61 	0x00, /* REG_ANAMICR		(0x6)	*/
62 	0x00, /* REG_AVADC_CTL		(0x7)	*/
63 	0x00, /* REG_ADCMICSEL		(0x8)	*/
64 	0x00, /* REG_DIGMIXING		(0x9)	*/
65 	0x0f, /* REG_ATXL1PGA		(0xA)	*/
66 	0x0f, /* REG_ATXR1PGA		(0xB)	*/
67 	0x0f, /* REG_AVTXL2PGA		(0xC)	*/
68 	0x0f, /* REG_AVTXR2PGA		(0xD)	*/
69 	0x00, /* REG_AUDIO_IF		(0xE)	*/
70 	0x00, /* REG_VOICE_IF		(0xF)	*/
71 	0x3f, /* REG_ARXR1PGA		(0x10)	*/
72 	0x3f, /* REG_ARXL1PGA		(0x11)	*/
73 	0x3f, /* REG_ARXR2PGA		(0x12)	*/
74 	0x3f, /* REG_ARXL2PGA		(0x13)	*/
75 	0x25, /* REG_VRXPGA		(0x14)	*/
76 	0x00, /* REG_VSTPGA		(0x15)	*/
77 	0x00, /* REG_VRX2ARXPGA		(0x16)	*/
78 	0x00, /* REG_AVDAC_CTL		(0x17)	*/
79 	0x00, /* REG_ARX2VTXPGA		(0x18)	*/
80 	0x32, /* REG_ARXL1_APGA_CTL	(0x19)	*/
81 	0x32, /* REG_ARXR1_APGA_CTL	(0x1A)	*/
82 	0x32, /* REG_ARXL2_APGA_CTL	(0x1B)	*/
83 	0x32, /* REG_ARXR2_APGA_CTL	(0x1C)	*/
84 	0x00, /* REG_ATX2ARXPGA		(0x1D)	*/
85 	0x00, /* REG_BT_IF		(0x1E)	*/
86 	0x55, /* REG_BTPGA		(0x1F)	*/
87 	0x00, /* REG_BTSTPGA		(0x20)	*/
88 	0x00, /* REG_EAR_CTL		(0x21)	*/
89 	0x00, /* REG_HS_SEL		(0x22)	*/
90 	0x00, /* REG_HS_GAIN_SET	(0x23)	*/
91 	0x00, /* REG_HS_POPN_SET	(0x24)	*/
92 	0x00, /* REG_PREDL_CTL		(0x25)	*/
93 	0x00, /* REG_PREDR_CTL		(0x26)	*/
94 	0x00, /* REG_PRECKL_CTL		(0x27)	*/
95 	0x00, /* REG_PRECKR_CTL		(0x28)	*/
96 	0x00, /* REG_HFL_CTL		(0x29)	*/
97 	0x00, /* REG_HFR_CTL		(0x2A)	*/
98 	0x05, /* REG_ALC_CTL		(0x2B)	*/
99 	0x00, /* REG_ALC_SET1		(0x2C)	*/
100 	0x00, /* REG_ALC_SET2		(0x2D)	*/
101 	0x00, /* REG_BOOST_CTL		(0x2E)	*/
102 	0x00, /* REG_SOFTVOL_CTL	(0x2F)	*/
103 	0x13, /* REG_DTMF_FREQSEL	(0x30)	*/
104 	0x00, /* REG_DTMF_TONEXT1H	(0x31)	*/
105 	0x00, /* REG_DTMF_TONEXT1L	(0x32)	*/
106 	0x00, /* REG_DTMF_TONEXT2H	(0x33)	*/
107 	0x00, /* REG_DTMF_TONEXT2L	(0x34)	*/
108 	0x79, /* REG_DTMF_TONOFF	(0x35)	*/
109 	0x11, /* REG_DTMF_WANONOFF	(0x36)	*/
110 	0x00, /* REG_I2S_RX_SCRAMBLE_H	(0x37)	*/
111 	0x00, /* REG_I2S_RX_SCRAMBLE_M	(0x38)	*/
112 	0x00, /* REG_I2S_RX_SCRAMBLE_L	(0x39)	*/
113 	0x06, /* REG_APLL_CTL		(0x3A)	*/
114 	0x00, /* REG_DTMF_CTL		(0x3B)	*/
115 	0x44, /* REG_DTMF_PGA_CTL2	(0x3C)	*/
116 	0x69, /* REG_DTMF_PGA_CTL1	(0x3D)	*/
117 	0x00, /* REG_MISC_SET_1		(0x3E)	*/
118 	0x00, /* REG_PCMBTMUX		(0x3F)	*/
119 	0x00, /* not used		(0x40)	*/
120 	0x00, /* not used		(0x41)	*/
121 	0x00, /* not used		(0x42)	*/
122 	0x00, /* REG_RX_PATH_SEL	(0x43)	*/
123 	0x32, /* REG_VDL_APGA_CTL	(0x44)	*/
124 	0x00, /* REG_VIBRA_CTL		(0x45)	*/
125 	0x00, /* REG_VIBRA_SET		(0x46)	*/
126 	0x00, /* REG_VIBRA_PWM_SET	(0x47)	*/
127 	0x00, /* REG_ANAMIC_GAIN	(0x48)	*/
128 	0x00, /* REG_MISC_SET_2		(0x49)	*/
129 };
130 
131 /* codec private data */
132 struct twl4030_priv {
133 	unsigned int codec_powered;
134 
135 	/* reference counts of AIF/APLL users */
136 	unsigned int apll_enabled;
137 
138 	struct snd_pcm_substream *master_substream;
139 	struct snd_pcm_substream *slave_substream;
140 
141 	unsigned int configured;
142 	unsigned int rate;
143 	unsigned int sample_bits;
144 	unsigned int channels;
145 
146 	unsigned int sysclk;
147 
148 	/* Output (with associated amp) states */
149 	u8 hsl_enabled, hsr_enabled;
150 	u8 earpiece_enabled;
151 	u8 predrivel_enabled, predriver_enabled;
152 	u8 carkitl_enabled, carkitr_enabled;
153 
154 	struct twl4030_codec_data *pdata;
155 };
156 
157 /*
158  * read twl4030 register cache
159  */
160 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
161 	unsigned int reg)
162 {
163 	u8 *cache = codec->reg_cache;
164 
165 	if (reg >= TWL4030_CACHEREGNUM)
166 		return -EIO;
167 
168 	return cache[reg];
169 }
170 
171 /*
172  * write twl4030 register cache
173  */
174 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
175 						u8 reg, u8 value)
176 {
177 	u8 *cache = codec->reg_cache;
178 
179 	if (reg >= TWL4030_CACHEREGNUM)
180 		return;
181 	cache[reg] = value;
182 }
183 
184 /*
185  * write to the twl4030 register space
186  */
187 static int twl4030_write(struct snd_soc_codec *codec,
188 			unsigned int reg, unsigned int value)
189 {
190 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
191 	int write_to_reg = 0;
192 
193 	twl4030_write_reg_cache(codec, reg, value);
194 	/* Decide if the given register can be written */
195 	switch (reg) {
196 	case TWL4030_REG_EAR_CTL:
197 		if (twl4030->earpiece_enabled)
198 			write_to_reg = 1;
199 		break;
200 	case TWL4030_REG_PREDL_CTL:
201 		if (twl4030->predrivel_enabled)
202 			write_to_reg = 1;
203 		break;
204 	case TWL4030_REG_PREDR_CTL:
205 		if (twl4030->predriver_enabled)
206 			write_to_reg = 1;
207 		break;
208 	case TWL4030_REG_PRECKL_CTL:
209 		if (twl4030->carkitl_enabled)
210 			write_to_reg = 1;
211 		break;
212 	case TWL4030_REG_PRECKR_CTL:
213 		if (twl4030->carkitr_enabled)
214 			write_to_reg = 1;
215 		break;
216 	case TWL4030_REG_HS_GAIN_SET:
217 		if (twl4030->hsl_enabled || twl4030->hsr_enabled)
218 			write_to_reg = 1;
219 		break;
220 	default:
221 		/* All other register can be written */
222 		write_to_reg = 1;
223 		break;
224 	}
225 	if (write_to_reg)
226 		return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
227 					    value, reg);
228 
229 	return 0;
230 }
231 
232 static inline void twl4030_wait_ms(int time)
233 {
234 	if (time < 60) {
235 		time *= 1000;
236 		usleep_range(time, time + 500);
237 	} else {
238 		msleep(time);
239 	}
240 }
241 
242 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
243 {
244 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
245 	int mode;
246 
247 	if (enable == twl4030->codec_powered)
248 		return;
249 
250 	if (enable)
251 		mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
252 	else
253 		mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
254 
255 	if (mode >= 0) {
256 		twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
257 		twl4030->codec_powered = enable;
258 	}
259 
260 	/* REVISIT: this delay is present in TI sample drivers */
261 	/* but there seems to be no TRM requirement for it     */
262 	udelay(10);
263 }
264 
265 static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
266 {
267 	int i, difference = 0;
268 	u8 val;
269 
270 	dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
271 	for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
272 		twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
273 		if (val != twl4030_reg[i]) {
274 			difference++;
275 			dev_dbg(codec->dev,
276 				 "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
277 				 i, val, twl4030_reg[i]);
278 		}
279 	}
280 	dev_dbg(codec->dev, "Found %d non-matching registers. %s\n",
281 		 difference, difference ? "Not OK" : "OK");
282 }
283 
284 static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
285 {
286 	int i;
287 
288 	/* set all audio section registers to reasonable defaults */
289 	for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
290 		if (i != TWL4030_REG_APLL_CTL)
291 			twl4030_write(codec, i, twl4030_reg[i]);
292 
293 }
294 
295 static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
296 				   struct device_node *node)
297 {
298 	int value;
299 
300 	of_property_read_u32(node, "ti,digimic_delay",
301 			     &pdata->digimic_delay);
302 	of_property_read_u32(node, "ti,ramp_delay_value",
303 			     &pdata->ramp_delay_value);
304 	of_property_read_u32(node, "ti,offset_cncl_path",
305 			     &pdata->offset_cncl_path);
306 	if (!of_property_read_u32(node, "ti,hs_extmute", &value))
307 		pdata->hs_extmute = value;
308 
309 	pdata->hs_extmute_gpio = of_get_named_gpio(node,
310 						   "ti,hs_extmute_gpio", 0);
311 	if (gpio_is_valid(pdata->hs_extmute_gpio))
312 		pdata->hs_extmute = 1;
313 }
314 
315 static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec)
316 {
317 	struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
318 	struct device_node *twl4030_codec_node = NULL;
319 
320 	twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node,
321 						  "codec");
322 
323 	if (!pdata && twl4030_codec_node) {
324 		pdata = devm_kzalloc(codec->dev,
325 				     sizeof(struct twl4030_codec_data),
326 				     GFP_KERNEL);
327 		if (!pdata) {
328 			dev_err(codec->dev, "Can not allocate memory\n");
329 			return NULL;
330 		}
331 		twl4030_setup_pdata_of(pdata, twl4030_codec_node);
332 	}
333 
334 	return pdata;
335 }
336 
337 static void twl4030_init_chip(struct snd_soc_codec *codec)
338 {
339 	struct twl4030_codec_data *pdata;
340 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
341 	u8 reg, byte;
342 	int i = 0;
343 
344 	pdata = twl4030_get_pdata(codec);
345 
346 	if (pdata && pdata->hs_extmute) {
347 		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
348 			int ret;
349 
350 			if (!pdata->hs_extmute_gpio)
351 				dev_warn(codec->dev,
352 					"Extmute GPIO is 0 is this correct?\n");
353 
354 			ret = gpio_request_one(pdata->hs_extmute_gpio,
355 					       GPIOF_OUT_INIT_LOW,
356 					       "hs_extmute");
357 			if (ret) {
358 				dev_err(codec->dev,
359 					"Failed to get hs_extmute GPIO\n");
360 				pdata->hs_extmute_gpio = -1;
361 			}
362 		} else {
363 			u8 pin_mux;
364 
365 			/* Set TWL4030 GPIO6 as EXTMUTE signal */
366 			twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux,
367 					TWL4030_PMBR1_REG);
368 			pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03);
369 			pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02);
370 			twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux,
371 					 TWL4030_PMBR1_REG);
372 		}
373 	}
374 
375 	/* Check defaults, if instructed before anything else */
376 	if (pdata && pdata->check_defaults)
377 		twl4030_check_defaults(codec);
378 
379 	/* Reset registers, if no setup data or if instructed to do so */
380 	if (!pdata || (pdata && pdata->reset_registers))
381 		twl4030_reset_registers(codec);
382 
383 	/* Refresh APLL_CTL register from HW */
384 	twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
385 			    TWL4030_REG_APLL_CTL);
386 	twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
387 
388 	/* anti-pop when changing analog gain */
389 	reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
390 	twl4030_write(codec, TWL4030_REG_MISC_SET_1,
391 		reg | TWL4030_SMOOTH_ANAVOL_EN);
392 
393 	twl4030_write(codec, TWL4030_REG_OPTION,
394 		TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
395 		TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
396 
397 	/* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
398 	twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
399 
400 	/* Machine dependent setup */
401 	if (!pdata)
402 		return;
403 
404 	twl4030->pdata = pdata;
405 
406 	reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
407 	reg &= ~TWL4030_RAMP_DELAY;
408 	reg |= (pdata->ramp_delay_value << 2);
409 	twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
410 
411 	/* initiate offset cancellation */
412 	twl4030_codec_enable(codec, 1);
413 
414 	reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
415 	reg &= ~TWL4030_OFFSET_CNCL_SEL;
416 	reg |= pdata->offset_cncl_path;
417 	twl4030_write(codec, TWL4030_REG_ANAMICL,
418 		reg | TWL4030_CNCL_OFFSET_START);
419 
420 	/*
421 	 * Wait for offset cancellation to complete.
422 	 * Since this takes a while, do not slam the i2c.
423 	 * Start polling the status after ~20ms.
424 	 */
425 	msleep(20);
426 	do {
427 		usleep_range(1000, 2000);
428 		twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
429 				    TWL4030_REG_ANAMICL);
430 	} while ((i++ < 100) &&
431 		 ((byte & TWL4030_CNCL_OFFSET_START) ==
432 		  TWL4030_CNCL_OFFSET_START));
433 
434 	/* Make sure that the reg_cache has the same value as the HW */
435 	twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
436 
437 	twl4030_codec_enable(codec, 0);
438 }
439 
440 static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
441 {
442 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
443 	int status = -1;
444 
445 	if (enable) {
446 		twl4030->apll_enabled++;
447 		if (twl4030->apll_enabled == 1)
448 			status = twl4030_audio_enable_resource(
449 							TWL4030_AUDIO_RES_APLL);
450 	} else {
451 		twl4030->apll_enabled--;
452 		if (!twl4030->apll_enabled)
453 			status = twl4030_audio_disable_resource(
454 							TWL4030_AUDIO_RES_APLL);
455 	}
456 
457 	if (status >= 0)
458 		twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
459 }
460 
461 /* Earpiece */
462 static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
463 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
464 	SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
465 	SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
466 	SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
467 };
468 
469 /* PreDrive Left */
470 static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
471 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
472 	SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
473 	SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
474 	SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
475 };
476 
477 /* PreDrive Right */
478 static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
479 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
480 	SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
481 	SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
482 	SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
483 };
484 
485 /* Headset Left */
486 static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
487 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
488 	SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
489 	SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
490 };
491 
492 /* Headset Right */
493 static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
494 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
495 	SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
496 	SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
497 };
498 
499 /* Carkit Left */
500 static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
501 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
502 	SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
503 	SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
504 };
505 
506 /* Carkit Right */
507 static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
508 	SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
509 	SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
510 	SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
511 };
512 
513 /* Handsfree Left */
514 static const char *twl4030_handsfreel_texts[] =
515 		{"Voice", "AudioL1", "AudioL2", "AudioR2"};
516 
517 static const struct soc_enum twl4030_handsfreel_enum =
518 	SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
519 			ARRAY_SIZE(twl4030_handsfreel_texts),
520 			twl4030_handsfreel_texts);
521 
522 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
523 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
524 
525 /* Handsfree Left virtual mute */
526 static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
527 	SOC_DAPM_SINGLE_VIRT("Switch", 1);
528 
529 /* Handsfree Right */
530 static const char *twl4030_handsfreer_texts[] =
531 		{"Voice", "AudioR1", "AudioR2", "AudioL2"};
532 
533 static const struct soc_enum twl4030_handsfreer_enum =
534 	SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
535 			ARRAY_SIZE(twl4030_handsfreer_texts),
536 			twl4030_handsfreer_texts);
537 
538 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
539 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
540 
541 /* Handsfree Right virtual mute */
542 static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
543 	SOC_DAPM_SINGLE_VIRT("Switch", 1);
544 
545 /* Vibra */
546 /* Vibra audio path selection */
547 static const char *twl4030_vibra_texts[] =
548 		{"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
549 
550 static const struct soc_enum twl4030_vibra_enum =
551 	SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
552 			ARRAY_SIZE(twl4030_vibra_texts),
553 			twl4030_vibra_texts);
554 
555 static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
556 SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
557 
558 /* Vibra path selection: local vibrator (PWM) or audio driven */
559 static const char *twl4030_vibrapath_texts[] =
560 		{"Local vibrator", "Audio"};
561 
562 static const struct soc_enum twl4030_vibrapath_enum =
563 	SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
564 			ARRAY_SIZE(twl4030_vibrapath_texts),
565 			twl4030_vibrapath_texts);
566 
567 static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
568 SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
569 
570 /* Left analog microphone selection */
571 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
572 	SOC_DAPM_SINGLE("Main Mic Capture Switch",
573 			TWL4030_REG_ANAMICL, 0, 1, 0),
574 	SOC_DAPM_SINGLE("Headset Mic Capture Switch",
575 			TWL4030_REG_ANAMICL, 1, 1, 0),
576 	SOC_DAPM_SINGLE("AUXL Capture Switch",
577 			TWL4030_REG_ANAMICL, 2, 1, 0),
578 	SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
579 			TWL4030_REG_ANAMICL, 3, 1, 0),
580 };
581 
582 /* Right analog microphone selection */
583 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
584 	SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
585 	SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
586 };
587 
588 /* TX1 L/R Analog/Digital microphone selection */
589 static const char *twl4030_micpathtx1_texts[] =
590 		{"Analog", "Digimic0"};
591 
592 static const struct soc_enum twl4030_micpathtx1_enum =
593 	SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
594 			ARRAY_SIZE(twl4030_micpathtx1_texts),
595 			twl4030_micpathtx1_texts);
596 
597 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
598 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
599 
600 /* TX2 L/R Analog/Digital microphone selection */
601 static const char *twl4030_micpathtx2_texts[] =
602 		{"Analog", "Digimic1"};
603 
604 static const struct soc_enum twl4030_micpathtx2_enum =
605 	SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
606 			ARRAY_SIZE(twl4030_micpathtx2_texts),
607 			twl4030_micpathtx2_texts);
608 
609 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
610 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
611 
612 /* Analog bypass for AudioR1 */
613 static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
614 	SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
615 
616 /* Analog bypass for AudioL1 */
617 static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
618 	SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
619 
620 /* Analog bypass for AudioR2 */
621 static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
622 	SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
623 
624 /* Analog bypass for AudioL2 */
625 static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
626 	SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
627 
628 /* Analog bypass for Voice */
629 static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
630 	SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
631 
632 /* Digital bypass gain, mute instead of -30dB */
633 static const unsigned int twl4030_dapm_dbypass_tlv[] = {
634 	TLV_DB_RANGE_HEAD(3),
635 	0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
636 	2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
637 	4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
638 };
639 
640 /* Digital bypass left (TX1L -> RX2L) */
641 static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
642 	SOC_DAPM_SINGLE_TLV("Volume",
643 			TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
644 			twl4030_dapm_dbypass_tlv);
645 
646 /* Digital bypass right (TX1R -> RX2R) */
647 static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
648 	SOC_DAPM_SINGLE_TLV("Volume",
649 			TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
650 			twl4030_dapm_dbypass_tlv);
651 
652 /*
653  * Voice Sidetone GAIN volume control:
654  * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
655  */
656 static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
657 
658 /* Digital bypass voice: sidetone (VUL -> VDL)*/
659 static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
660 	SOC_DAPM_SINGLE_TLV("Volume",
661 			TWL4030_REG_VSTPGA, 0, 0x29, 0,
662 			twl4030_dapm_dbypassv_tlv);
663 
664 /*
665  * Output PGA builder:
666  * Handle the muting and unmuting of the given output (turning off the
667  * amplifier associated with the output pin)
668  * On mute bypass the reg_cache and write 0 to the register
669  * On unmute: restore the register content from the reg_cache
670  * Outputs handled in this way:  Earpiece, PreDrivL/R, CarkitL/R
671  */
672 #define TWL4030_OUTPUT_PGA(pin_name, reg, mask)				\
673 static int pin_name##pga_event(struct snd_soc_dapm_widget *w,		\
674 		struct snd_kcontrol *kcontrol, int event)		\
675 {									\
676 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
677 									\
678 	switch (event) {						\
679 	case SND_SOC_DAPM_POST_PMU:					\
680 		twl4030->pin_name##_enabled = 1;			\
681 		twl4030_write(w->codec, reg,				\
682 			twl4030_read_reg_cache(w->codec, reg));		\
683 		break;							\
684 	case SND_SOC_DAPM_POST_PMD:					\
685 		twl4030->pin_name##_enabled = 0;			\
686 		twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,		\
687 					0, reg);			\
688 		break;							\
689 	}								\
690 	return 0;							\
691 }
692 
693 TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
694 TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
695 TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
696 TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
697 TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
698 
699 static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
700 {
701 	unsigned char hs_ctl;
702 
703 	hs_ctl = twl4030_read_reg_cache(codec, reg);
704 
705 	if (ramp) {
706 		/* HF ramp-up */
707 		hs_ctl |= TWL4030_HF_CTL_REF_EN;
708 		twl4030_write(codec, reg, hs_ctl);
709 		udelay(10);
710 		hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
711 		twl4030_write(codec, reg, hs_ctl);
712 		udelay(40);
713 		hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
714 		hs_ctl |= TWL4030_HF_CTL_HB_EN;
715 		twl4030_write(codec, reg, hs_ctl);
716 	} else {
717 		/* HF ramp-down */
718 		hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
719 		hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
720 		twl4030_write(codec, reg, hs_ctl);
721 		hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
722 		twl4030_write(codec, reg, hs_ctl);
723 		udelay(40);
724 		hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
725 		twl4030_write(codec, reg, hs_ctl);
726 	}
727 }
728 
729 static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
730 		struct snd_kcontrol *kcontrol, int event)
731 {
732 	switch (event) {
733 	case SND_SOC_DAPM_POST_PMU:
734 		handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
735 		break;
736 	case SND_SOC_DAPM_POST_PMD:
737 		handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
738 		break;
739 	}
740 	return 0;
741 }
742 
743 static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
744 		struct snd_kcontrol *kcontrol, int event)
745 {
746 	switch (event) {
747 	case SND_SOC_DAPM_POST_PMU:
748 		handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
749 		break;
750 	case SND_SOC_DAPM_POST_PMD:
751 		handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
752 		break;
753 	}
754 	return 0;
755 }
756 
757 static int vibramux_event(struct snd_soc_dapm_widget *w,
758 		struct snd_kcontrol *kcontrol, int event)
759 {
760 	twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
761 	return 0;
762 }
763 
764 static int apll_event(struct snd_soc_dapm_widget *w,
765 		struct snd_kcontrol *kcontrol, int event)
766 {
767 	switch (event) {
768 	case SND_SOC_DAPM_PRE_PMU:
769 		twl4030_apll_enable(w->codec, 1);
770 		break;
771 	case SND_SOC_DAPM_POST_PMD:
772 		twl4030_apll_enable(w->codec, 0);
773 		break;
774 	}
775 	return 0;
776 }
777 
778 static int aif_event(struct snd_soc_dapm_widget *w,
779 		struct snd_kcontrol *kcontrol, int event)
780 {
781 	u8 audio_if;
782 
783 	audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
784 	switch (event) {
785 	case SND_SOC_DAPM_PRE_PMU:
786 		/* Enable AIF */
787 		/* enable the PLL before we use it to clock the DAI */
788 		twl4030_apll_enable(w->codec, 1);
789 
790 		twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
791 						audio_if | TWL4030_AIF_EN);
792 		break;
793 	case SND_SOC_DAPM_POST_PMD:
794 		/* disable the DAI before we stop it's source PLL */
795 		twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
796 						audio_if &  ~TWL4030_AIF_EN);
797 		twl4030_apll_enable(w->codec, 0);
798 		break;
799 	}
800 	return 0;
801 }
802 
803 static void headset_ramp(struct snd_soc_codec *codec, int ramp)
804 {
805 	unsigned char hs_gain, hs_pop;
806 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
807 	struct twl4030_codec_data *pdata = twl4030->pdata;
808 	/* Base values for ramp delay calculation: 2^19 - 2^26 */
809 	unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
810 				    8388608, 16777216, 33554432, 67108864};
811 	unsigned int delay;
812 
813 	hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
814 	hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
815 	delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
816 		twl4030->sysclk) + 1;
817 
818 	/* Enable external mute control, this dramatically reduces
819 	 * the pop-noise */
820 	if (pdata && pdata->hs_extmute) {
821 		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
822 			gpio_set_value(pdata->hs_extmute_gpio, 1);
823 		} else {
824 			hs_pop |= TWL4030_EXTMUTE;
825 			twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
826 		}
827 	}
828 
829 	if (ramp) {
830 		/* Headset ramp-up according to the TRM */
831 		hs_pop |= TWL4030_VMID_EN;
832 		twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
833 		/* Actually write to the register */
834 		twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
835 					hs_gain,
836 					TWL4030_REG_HS_GAIN_SET);
837 		hs_pop |= TWL4030_RAMP_EN;
838 		twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
839 		/* Wait ramp delay time + 1, so the VMID can settle */
840 		twl4030_wait_ms(delay);
841 	} else {
842 		/* Headset ramp-down _not_ according to
843 		 * the TRM, but in a way that it is working */
844 		hs_pop &= ~TWL4030_RAMP_EN;
845 		twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
846 		/* Wait ramp delay time + 1, so the VMID can settle */
847 		twl4030_wait_ms(delay);
848 		/* Bypass the reg_cache to mute the headset */
849 		twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
850 					hs_gain & (~0x0f),
851 					TWL4030_REG_HS_GAIN_SET);
852 
853 		hs_pop &= ~TWL4030_VMID_EN;
854 		twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
855 	}
856 
857 	/* Disable external mute */
858 	if (pdata && pdata->hs_extmute) {
859 		if (gpio_is_valid(pdata->hs_extmute_gpio)) {
860 			gpio_set_value(pdata->hs_extmute_gpio, 0);
861 		} else {
862 			hs_pop &= ~TWL4030_EXTMUTE;
863 			twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
864 		}
865 	}
866 }
867 
868 static int headsetlpga_event(struct snd_soc_dapm_widget *w,
869 		struct snd_kcontrol *kcontrol, int event)
870 {
871 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
872 
873 	switch (event) {
874 	case SND_SOC_DAPM_POST_PMU:
875 		/* Do the ramp-up only once */
876 		if (!twl4030->hsr_enabled)
877 			headset_ramp(w->codec, 1);
878 
879 		twl4030->hsl_enabled = 1;
880 		break;
881 	case SND_SOC_DAPM_POST_PMD:
882 		/* Do the ramp-down only if both headsetL/R is disabled */
883 		if (!twl4030->hsr_enabled)
884 			headset_ramp(w->codec, 0);
885 
886 		twl4030->hsl_enabled = 0;
887 		break;
888 	}
889 	return 0;
890 }
891 
892 static int headsetrpga_event(struct snd_soc_dapm_widget *w,
893 		struct snd_kcontrol *kcontrol, int event)
894 {
895 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
896 
897 	switch (event) {
898 	case SND_SOC_DAPM_POST_PMU:
899 		/* Do the ramp-up only once */
900 		if (!twl4030->hsl_enabled)
901 			headset_ramp(w->codec, 1);
902 
903 		twl4030->hsr_enabled = 1;
904 		break;
905 	case SND_SOC_DAPM_POST_PMD:
906 		/* Do the ramp-down only if both headsetL/R is disabled */
907 		if (!twl4030->hsl_enabled)
908 			headset_ramp(w->codec, 0);
909 
910 		twl4030->hsr_enabled = 0;
911 		break;
912 	}
913 	return 0;
914 }
915 
916 static int digimic_event(struct snd_soc_dapm_widget *w,
917 		struct snd_kcontrol *kcontrol, int event)
918 {
919 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
920 	struct twl4030_codec_data *pdata = twl4030->pdata;
921 
922 	if (pdata && pdata->digimic_delay)
923 		twl4030_wait_ms(pdata->digimic_delay);
924 	return 0;
925 }
926 
927 /*
928  * Some of the gain controls in TWL (mostly those which are associated with
929  * the outputs) are implemented in an interesting way:
930  * 0x0 : Power down (mute)
931  * 0x1 : 6dB
932  * 0x2 : 0 dB
933  * 0x3 : -6 dB
934  * Inverting not going to help with these.
935  * Custom volsw and volsw_2r get/put functions to handle these gain bits.
936  */
937 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
938 	struct snd_ctl_elem_value *ucontrol)
939 {
940 	struct soc_mixer_control *mc =
941 		(struct soc_mixer_control *)kcontrol->private_value;
942 	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
943 	unsigned int reg = mc->reg;
944 	unsigned int shift = mc->shift;
945 	unsigned int rshift = mc->rshift;
946 	int max = mc->max;
947 	int mask = (1 << fls(max)) - 1;
948 
949 	ucontrol->value.integer.value[0] =
950 		(snd_soc_read(codec, reg) >> shift) & mask;
951 	if (ucontrol->value.integer.value[0])
952 		ucontrol->value.integer.value[0] =
953 			max + 1 - ucontrol->value.integer.value[0];
954 
955 	if (shift != rshift) {
956 		ucontrol->value.integer.value[1] =
957 			(snd_soc_read(codec, reg) >> rshift) & mask;
958 		if (ucontrol->value.integer.value[1])
959 			ucontrol->value.integer.value[1] =
960 				max + 1 - ucontrol->value.integer.value[1];
961 	}
962 
963 	return 0;
964 }
965 
966 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
967 	struct snd_ctl_elem_value *ucontrol)
968 {
969 	struct soc_mixer_control *mc =
970 		(struct soc_mixer_control *)kcontrol->private_value;
971 	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
972 	unsigned int reg = mc->reg;
973 	unsigned int shift = mc->shift;
974 	unsigned int rshift = mc->rshift;
975 	int max = mc->max;
976 	int mask = (1 << fls(max)) - 1;
977 	unsigned short val, val2, val_mask;
978 
979 	val = (ucontrol->value.integer.value[0] & mask);
980 
981 	val_mask = mask << shift;
982 	if (val)
983 		val = max + 1 - val;
984 	val = val << shift;
985 	if (shift != rshift) {
986 		val2 = (ucontrol->value.integer.value[1] & mask);
987 		val_mask |= mask << rshift;
988 		if (val2)
989 			val2 = max + 1 - val2;
990 		val |= val2 << rshift;
991 	}
992 	return snd_soc_update_bits(codec, reg, val_mask, val);
993 }
994 
995 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
996 	struct snd_ctl_elem_value *ucontrol)
997 {
998 	struct soc_mixer_control *mc =
999 		(struct soc_mixer_control *)kcontrol->private_value;
1000 	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1001 	unsigned int reg = mc->reg;
1002 	unsigned int reg2 = mc->rreg;
1003 	unsigned int shift = mc->shift;
1004 	int max = mc->max;
1005 	int mask = (1<<fls(max))-1;
1006 
1007 	ucontrol->value.integer.value[0] =
1008 		(snd_soc_read(codec, reg) >> shift) & mask;
1009 	ucontrol->value.integer.value[1] =
1010 		(snd_soc_read(codec, reg2) >> shift) & mask;
1011 
1012 	if (ucontrol->value.integer.value[0])
1013 		ucontrol->value.integer.value[0] =
1014 			max + 1 - ucontrol->value.integer.value[0];
1015 	if (ucontrol->value.integer.value[1])
1016 		ucontrol->value.integer.value[1] =
1017 			max + 1 - ucontrol->value.integer.value[1];
1018 
1019 	return 0;
1020 }
1021 
1022 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
1023 	struct snd_ctl_elem_value *ucontrol)
1024 {
1025 	struct soc_mixer_control *mc =
1026 		(struct soc_mixer_control *)kcontrol->private_value;
1027 	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1028 	unsigned int reg = mc->reg;
1029 	unsigned int reg2 = mc->rreg;
1030 	unsigned int shift = mc->shift;
1031 	int max = mc->max;
1032 	int mask = (1 << fls(max)) - 1;
1033 	int err;
1034 	unsigned short val, val2, val_mask;
1035 
1036 	val_mask = mask << shift;
1037 	val = (ucontrol->value.integer.value[0] & mask);
1038 	val2 = (ucontrol->value.integer.value[1] & mask);
1039 
1040 	if (val)
1041 		val = max + 1 - val;
1042 	if (val2)
1043 		val2 = max + 1 - val2;
1044 
1045 	val = val << shift;
1046 	val2 = val2 << shift;
1047 
1048 	err = snd_soc_update_bits(codec, reg, val_mask, val);
1049 	if (err < 0)
1050 		return err;
1051 
1052 	err = snd_soc_update_bits(codec, reg2, val_mask, val2);
1053 	return err;
1054 }
1055 
1056 /* Codec operation modes */
1057 static const char *twl4030_op_modes_texts[] = {
1058 	"Option 2 (voice/audio)", "Option 1 (audio)"
1059 };
1060 
1061 static const struct soc_enum twl4030_op_modes_enum =
1062 	SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1063 			ARRAY_SIZE(twl4030_op_modes_texts),
1064 			twl4030_op_modes_texts);
1065 
1066 static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
1067 	struct snd_ctl_elem_value *ucontrol)
1068 {
1069 	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1070 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1071 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1072 	unsigned short val;
1073 	unsigned short mask;
1074 
1075 	if (twl4030->configured) {
1076 		dev_err(codec->dev,
1077 			"operation mode cannot be changed on-the-fly\n");
1078 		return -EBUSY;
1079 	}
1080 
1081 	if (ucontrol->value.enumerated.item[0] > e->max - 1)
1082 		return -EINVAL;
1083 
1084 	val = ucontrol->value.enumerated.item[0] << e->shift_l;
1085 	mask = e->mask << e->shift_l;
1086 	if (e->shift_l != e->shift_r) {
1087 		if (ucontrol->value.enumerated.item[1] > e->max - 1)
1088 			return -EINVAL;
1089 		val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1090 		mask |= e->mask << e->shift_r;
1091 	}
1092 
1093 	return snd_soc_update_bits(codec, e->reg, mask, val);
1094 }
1095 
1096 /*
1097  * FGAIN volume control:
1098  * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1099  */
1100 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
1101 
1102 /*
1103  * CGAIN volume control:
1104  * 0 dB to 12 dB in 6 dB steps
1105  * value 2 and 3 means 12 dB
1106  */
1107 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1108 
1109 /*
1110  * Voice Downlink GAIN volume control:
1111  * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1112  */
1113 static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1114 
1115 /*
1116  * Analog playback gain
1117  * -24 dB to 12 dB in 2 dB steps
1118  */
1119 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
1120 
1121 /*
1122  * Gain controls tied to outputs
1123  * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1124  */
1125 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1126 
1127 /*
1128  * Gain control for earpiece amplifier
1129  * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1130  */
1131 static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1132 
1133 /*
1134  * Capture gain after the ADCs
1135  * from 0 dB to 31 dB in 1 dB steps
1136  */
1137 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1138 
1139 /*
1140  * Gain control for input amplifiers
1141  * 0 dB to 30 dB in 6 dB steps
1142  */
1143 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1144 
1145 /* AVADC clock priority */
1146 static const char *twl4030_avadc_clk_priority_texts[] = {
1147 	"Voice high priority", "HiFi high priority"
1148 };
1149 
1150 static const struct soc_enum twl4030_avadc_clk_priority_enum =
1151 	SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1152 			ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1153 			twl4030_avadc_clk_priority_texts);
1154 
1155 static const char *twl4030_rampdelay_texts[] = {
1156 	"27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1157 	"437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1158 	"3495/2581/1748 ms"
1159 };
1160 
1161 static const struct soc_enum twl4030_rampdelay_enum =
1162 	SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1163 			ARRAY_SIZE(twl4030_rampdelay_texts),
1164 			twl4030_rampdelay_texts);
1165 
1166 /* Vibra H-bridge direction mode */
1167 static const char *twl4030_vibradirmode_texts[] = {
1168 	"Vibra H-bridge direction", "Audio data MSB",
1169 };
1170 
1171 static const struct soc_enum twl4030_vibradirmode_enum =
1172 	SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1173 			ARRAY_SIZE(twl4030_vibradirmode_texts),
1174 			twl4030_vibradirmode_texts);
1175 
1176 /* Vibra H-bridge direction */
1177 static const char *twl4030_vibradir_texts[] = {
1178 	"Positive polarity", "Negative polarity",
1179 };
1180 
1181 static const struct soc_enum twl4030_vibradir_enum =
1182 	SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1183 			ARRAY_SIZE(twl4030_vibradir_texts),
1184 			twl4030_vibradir_texts);
1185 
1186 /* Digimic Left and right swapping */
1187 static const char *twl4030_digimicswap_texts[] = {
1188 	"Not swapped", "Swapped",
1189 };
1190 
1191 static const struct soc_enum twl4030_digimicswap_enum =
1192 	SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1193 			ARRAY_SIZE(twl4030_digimicswap_texts),
1194 			twl4030_digimicswap_texts);
1195 
1196 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
1197 	/* Codec operation mode control */
1198 	SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1199 		snd_soc_get_enum_double,
1200 		snd_soc_put_twl4030_opmode_enum_double),
1201 
1202 	/* Common playback gain controls */
1203 	SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1204 		TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1205 		0, 0x3f, 0, digital_fine_tlv),
1206 	SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1207 		TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1208 		0, 0x3f, 0, digital_fine_tlv),
1209 
1210 	SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1211 		TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1212 		6, 0x2, 0, digital_coarse_tlv),
1213 	SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1214 		TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1215 		6, 0x2, 0, digital_coarse_tlv),
1216 
1217 	SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1218 		TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1219 		3, 0x12, 1, analog_tlv),
1220 	SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1221 		TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1222 		3, 0x12, 1, analog_tlv),
1223 	SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1224 		TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1225 		1, 1, 0),
1226 	SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1227 		TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1228 		1, 1, 0),
1229 
1230 	/* Common voice downlink gain controls */
1231 	SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1232 		TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1233 
1234 	SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1235 		TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1236 
1237 	SOC_SINGLE("DAC Voice Analog Downlink Switch",
1238 		TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1239 
1240 	/* Separate output gain controls */
1241 	SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
1242 		TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1243 		4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1244 		snd_soc_put_volsw_r2_twl4030, output_tvl),
1245 
1246 	SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1247 		TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1248 		snd_soc_put_volsw_twl4030, output_tvl),
1249 
1250 	SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
1251 		TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1252 		4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1253 		snd_soc_put_volsw_r2_twl4030, output_tvl),
1254 
1255 	SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1256 		TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1257 		snd_soc_put_volsw_twl4030, output_ear_tvl),
1258 
1259 	/* Common capture gain controls */
1260 	SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
1261 		TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1262 		0, 0x1f, 0, digital_capture_tlv),
1263 	SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1264 		TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1265 		0, 0x1f, 0, digital_capture_tlv),
1266 
1267 	SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
1268 		0, 3, 5, 0, input_gain_tlv),
1269 
1270 	SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1271 
1272 	SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
1273 
1274 	SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1275 	SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
1276 
1277 	SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
1278 };
1279 
1280 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1281 	/* Left channel inputs */
1282 	SND_SOC_DAPM_INPUT("MAINMIC"),
1283 	SND_SOC_DAPM_INPUT("HSMIC"),
1284 	SND_SOC_DAPM_INPUT("AUXL"),
1285 	SND_SOC_DAPM_INPUT("CARKITMIC"),
1286 	/* Right channel inputs */
1287 	SND_SOC_DAPM_INPUT("SUBMIC"),
1288 	SND_SOC_DAPM_INPUT("AUXR"),
1289 	/* Digital microphones (Stereo) */
1290 	SND_SOC_DAPM_INPUT("DIGIMIC0"),
1291 	SND_SOC_DAPM_INPUT("DIGIMIC1"),
1292 
1293 	/* Outputs */
1294 	SND_SOC_DAPM_OUTPUT("EARPIECE"),
1295 	SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1296 	SND_SOC_DAPM_OUTPUT("PREDRIVER"),
1297 	SND_SOC_DAPM_OUTPUT("HSOL"),
1298 	SND_SOC_DAPM_OUTPUT("HSOR"),
1299 	SND_SOC_DAPM_OUTPUT("CARKITL"),
1300 	SND_SOC_DAPM_OUTPUT("CARKITR"),
1301 	SND_SOC_DAPM_OUTPUT("HFL"),
1302 	SND_SOC_DAPM_OUTPUT("HFR"),
1303 	SND_SOC_DAPM_OUTPUT("VIBRA"),
1304 
1305 	/* AIF and APLL clocks for running DAIs (including loopback) */
1306 	SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1307 	SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1308 	SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1309 
1310 	/* DACs */
1311 	SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1312 	SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1313 	SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1314 	SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1315 	SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
1316 
1317 	SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0,
1318 			    TWL4030_REG_VOICE_IF, 6, 0),
1319 
1320 	/* Analog bypasses */
1321 	SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1322 			&twl4030_dapm_abypassr1_control),
1323 	SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1324 			&twl4030_dapm_abypassl1_control),
1325 	SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1326 			&twl4030_dapm_abypassr2_control),
1327 	SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1328 			&twl4030_dapm_abypassl2_control),
1329 	SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1330 			&twl4030_dapm_abypassv_control),
1331 
1332 	/* Master analog loopback switch */
1333 	SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1334 			    NULL, 0),
1335 
1336 	/* Digital bypasses */
1337 	SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1338 			&twl4030_dapm_dbypassl_control),
1339 	SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1340 			&twl4030_dapm_dbypassr_control),
1341 	SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1342 			&twl4030_dapm_dbypassv_control),
1343 
1344 	/* Digital mixers, power control for the physical DACs */
1345 	SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1346 			TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1347 	SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1348 			TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1349 	SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1350 			TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1351 	SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1352 			TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1353 	SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1354 			TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1355 
1356 	/* Analog mixers, power control for the physical PGAs */
1357 	SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1358 			TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1359 	SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1360 			TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1361 	SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1362 			TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1363 	SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1364 			TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1365 	SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1366 			TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
1367 
1368 	SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1369 			    SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1370 
1371 	SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1372 			    SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1373 
1374 	/* Output MIXER controls */
1375 	/* Earpiece */
1376 	SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1377 			&twl4030_dapm_earpiece_controls[0],
1378 			ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
1379 	SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1380 			0, 0, NULL, 0, earpiecepga_event,
1381 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1382 	/* PreDrivL/R */
1383 	SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1384 			&twl4030_dapm_predrivel_controls[0],
1385 			ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1386 	SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1387 			0, 0, NULL, 0, predrivelpga_event,
1388 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1389 	SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1390 			&twl4030_dapm_predriver_controls[0],
1391 			ARRAY_SIZE(twl4030_dapm_predriver_controls)),
1392 	SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1393 			0, 0, NULL, 0, predriverpga_event,
1394 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1395 	/* HeadsetL/R */
1396 	SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1397 			&twl4030_dapm_hsol_controls[0],
1398 			ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1399 	SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1400 			0, 0, NULL, 0, headsetlpga_event,
1401 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1402 	SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1403 			&twl4030_dapm_hsor_controls[0],
1404 			ARRAY_SIZE(twl4030_dapm_hsor_controls)),
1405 	SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1406 			0, 0, NULL, 0, headsetrpga_event,
1407 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1408 	/* CarkitL/R */
1409 	SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1410 			&twl4030_dapm_carkitl_controls[0],
1411 			ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1412 	SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1413 			0, 0, NULL, 0, carkitlpga_event,
1414 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1415 	SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1416 			&twl4030_dapm_carkitr_controls[0],
1417 			ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1418 	SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1419 			0, 0, NULL, 0, carkitrpga_event,
1420 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1421 
1422 	/* Output MUX controls */
1423 	/* HandsfreeL/R */
1424 	SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1425 		&twl4030_dapm_handsfreel_control),
1426 	SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
1427 			&twl4030_dapm_handsfreelmute_control),
1428 	SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1429 			0, 0, NULL, 0, handsfreelpga_event,
1430 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1431 	SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1432 		&twl4030_dapm_handsfreer_control),
1433 	SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
1434 			&twl4030_dapm_handsfreermute_control),
1435 	SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1436 			0, 0, NULL, 0, handsfreerpga_event,
1437 			SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1438 	/* Vibra */
1439 	SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1440 			   &twl4030_dapm_vibra_control, vibramux_event,
1441 			   SND_SOC_DAPM_PRE_PMU),
1442 	SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1443 		&twl4030_dapm_vibrapath_control),
1444 
1445 	/* Introducing four virtual ADC, since TWL4030 have four channel for
1446 	   capture */
1447 	SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1448 	SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1449 	SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1450 	SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
1451 
1452 	SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0,
1453 			     TWL4030_REG_VOICE_IF, 5, 0),
1454 
1455 	/* Analog/Digital mic path selection.
1456 	   TX1 Left/Right: either analog Left/Right or Digimic0
1457 	   TX2 Left/Right: either analog Left/Right or Digimic1 */
1458 	SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1459 		&twl4030_dapm_micpathtx1_control),
1460 	SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1461 		&twl4030_dapm_micpathtx2_control),
1462 
1463 	/* Analog input mixers for the capture amplifiers */
1464 	SND_SOC_DAPM_MIXER("Analog Left",
1465 		TWL4030_REG_ANAMICL, 4, 0,
1466 		&twl4030_dapm_analoglmic_controls[0],
1467 		ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1468 	SND_SOC_DAPM_MIXER("Analog Right",
1469 		TWL4030_REG_ANAMICR, 4, 0,
1470 		&twl4030_dapm_analogrmic_controls[0],
1471 		ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
1472 
1473 	SND_SOC_DAPM_PGA("ADC Physical Left",
1474 		TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1475 	SND_SOC_DAPM_PGA("ADC Physical Right",
1476 		TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
1477 
1478 	SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1479 		TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1480 		digimic_event, SND_SOC_DAPM_POST_PMU),
1481 	SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1482 		TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1483 		digimic_event, SND_SOC_DAPM_POST_PMU),
1484 
1485 	SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1486 			    NULL, 0),
1487 	SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1488 			    NULL, 0),
1489 
1490 	/* Microphone bias */
1491 	SND_SOC_DAPM_SUPPLY("Mic Bias 1",
1492 			    TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0),
1493 	SND_SOC_DAPM_SUPPLY("Mic Bias 2",
1494 			    TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0),
1495 	SND_SOC_DAPM_SUPPLY("Headset Mic Bias",
1496 			    TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0),
1497 
1498 	SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0),
1499 };
1500 
1501 static const struct snd_soc_dapm_route intercon[] = {
1502 	/* Stream -> DAC mapping */
1503 	{"DAC Right1", NULL, "HiFi Playback"},
1504 	{"DAC Left1", NULL, "HiFi Playback"},
1505 	{"DAC Right2", NULL, "HiFi Playback"},
1506 	{"DAC Left2", NULL, "HiFi Playback"},
1507 	{"DAC Voice", NULL, "VAIFIN"},
1508 
1509 	/* ADC -> Stream mapping */
1510 	{"HiFi Capture", NULL, "ADC Virtual Left1"},
1511 	{"HiFi Capture", NULL, "ADC Virtual Right1"},
1512 	{"HiFi Capture", NULL, "ADC Virtual Left2"},
1513 	{"HiFi Capture", NULL, "ADC Virtual Right2"},
1514 	{"VAIFOUT", NULL, "ADC Virtual Left2"},
1515 	{"VAIFOUT", NULL, "ADC Virtual Right2"},
1516 	{"VAIFOUT", NULL, "VIF Enable"},
1517 
1518 	{"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1519 	{"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1520 	{"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1521 	{"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1522 	{"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1523 
1524 	/* Supply for the digital part (APLL) */
1525 	{"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1526 
1527 	{"DAC Left1", NULL, "AIF Enable"},
1528 	{"DAC Right1", NULL, "AIF Enable"},
1529 	{"DAC Left2", NULL, "AIF Enable"},
1530 	{"DAC Right1", NULL, "AIF Enable"},
1531 	{"DAC Voice", NULL, "VIF Enable"},
1532 
1533 	{"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1534 	{"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1535 
1536 	{"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1537 	{"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1538 	{"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1539 	{"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1540 	{"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1541 
1542 	/* Internal playback routings */
1543 	/* Earpiece */
1544 	{"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1545 	{"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1546 	{"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1547 	{"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1548 	{"Earpiece PGA", NULL, "Earpiece Mixer"},
1549 	/* PreDrivL */
1550 	{"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1551 	{"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1552 	{"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1553 	{"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1554 	{"PredriveL PGA", NULL, "PredriveL Mixer"},
1555 	/* PreDrivR */
1556 	{"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1557 	{"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1558 	{"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1559 	{"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1560 	{"PredriveR PGA", NULL, "PredriveR Mixer"},
1561 	/* HeadsetL */
1562 	{"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1563 	{"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1564 	{"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1565 	{"HeadsetL PGA", NULL, "HeadsetL Mixer"},
1566 	/* HeadsetR */
1567 	{"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1568 	{"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1569 	{"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1570 	{"HeadsetR PGA", NULL, "HeadsetR Mixer"},
1571 	/* CarkitL */
1572 	{"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1573 	{"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1574 	{"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1575 	{"CarkitL PGA", NULL, "CarkitL Mixer"},
1576 	/* CarkitR */
1577 	{"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1578 	{"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1579 	{"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1580 	{"CarkitR PGA", NULL, "CarkitR Mixer"},
1581 	/* HandsfreeL */
1582 	{"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1583 	{"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1584 	{"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1585 	{"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
1586 	{"HandsfreeL", "Switch", "HandsfreeL Mux"},
1587 	{"HandsfreeL PGA", NULL, "HandsfreeL"},
1588 	/* HandsfreeR */
1589 	{"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1590 	{"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1591 	{"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1592 	{"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
1593 	{"HandsfreeR", "Switch", "HandsfreeR Mux"},
1594 	{"HandsfreeR PGA", NULL, "HandsfreeR"},
1595 	/* Vibra */
1596 	{"Vibra Mux", "AudioL1", "DAC Left1"},
1597 	{"Vibra Mux", "AudioR1", "DAC Right1"},
1598 	{"Vibra Mux", "AudioL2", "DAC Left2"},
1599 	{"Vibra Mux", "AudioR2", "DAC Right2"},
1600 
1601 	/* outputs */
1602 	/* Must be always connected (for AIF and APLL) */
1603 	{"Virtual HiFi OUT", NULL, "DAC Left1"},
1604 	{"Virtual HiFi OUT", NULL, "DAC Right1"},
1605 	{"Virtual HiFi OUT", NULL, "DAC Left2"},
1606 	{"Virtual HiFi OUT", NULL, "DAC Right2"},
1607 	/* Must be always connected (for APLL) */
1608 	{"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1609 	/* Physical outputs */
1610 	{"EARPIECE", NULL, "Earpiece PGA"},
1611 	{"PREDRIVEL", NULL, "PredriveL PGA"},
1612 	{"PREDRIVER", NULL, "PredriveR PGA"},
1613 	{"HSOL", NULL, "HeadsetL PGA"},
1614 	{"HSOR", NULL, "HeadsetR PGA"},
1615 	{"CARKITL", NULL, "CarkitL PGA"},
1616 	{"CARKITR", NULL, "CarkitR PGA"},
1617 	{"HFL", NULL, "HandsfreeL PGA"},
1618 	{"HFR", NULL, "HandsfreeR PGA"},
1619 	{"Vibra Route", "Audio", "Vibra Mux"},
1620 	{"VIBRA", NULL, "Vibra Route"},
1621 
1622 	/* Capture path */
1623 	/* Must be always connected (for AIF and APLL) */
1624 	{"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1625 	{"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1626 	{"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1627 	{"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1628 	/* Physical inputs */
1629 	{"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1630 	{"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1631 	{"Analog Left", "AUXL Capture Switch", "AUXL"},
1632 	{"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
1633 
1634 	{"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1635 	{"Analog Right", "AUXR Capture Switch", "AUXR"},
1636 
1637 	{"ADC Physical Left", NULL, "Analog Left"},
1638 	{"ADC Physical Right", NULL, "Analog Right"},
1639 
1640 	{"Digimic0 Enable", NULL, "DIGIMIC0"},
1641 	{"Digimic1 Enable", NULL, "DIGIMIC1"},
1642 
1643 	{"DIGIMIC0", NULL, "micbias1 select"},
1644 	{"DIGIMIC1", NULL, "micbias2 select"},
1645 
1646 	/* TX1 Left capture path */
1647 	{"TX1 Capture Route", "Analog", "ADC Physical Left"},
1648 	{"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1649 	/* TX1 Right capture path */
1650 	{"TX1 Capture Route", "Analog", "ADC Physical Right"},
1651 	{"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1652 	/* TX2 Left capture path */
1653 	{"TX2 Capture Route", "Analog", "ADC Physical Left"},
1654 	{"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1655 	/* TX2 Right capture path */
1656 	{"TX2 Capture Route", "Analog", "ADC Physical Right"},
1657 	{"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1658 
1659 	{"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1660 	{"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1661 	{"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1662 	{"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1663 
1664 	{"ADC Virtual Left1", NULL, "AIF Enable"},
1665 	{"ADC Virtual Right1", NULL, "AIF Enable"},
1666 	{"ADC Virtual Left2", NULL, "AIF Enable"},
1667 	{"ADC Virtual Right2", NULL, "AIF Enable"},
1668 
1669 	/* Analog bypass routes */
1670 	{"Right1 Analog Loopback", "Switch", "Analog Right"},
1671 	{"Left1 Analog Loopback", "Switch", "Analog Left"},
1672 	{"Right2 Analog Loopback", "Switch", "Analog Right"},
1673 	{"Left2 Analog Loopback", "Switch", "Analog Left"},
1674 	{"Voice Analog Loopback", "Switch", "Analog Left"},
1675 
1676 	/* Supply for the Analog loopbacks */
1677 	{"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1678 	{"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1679 	{"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1680 	{"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1681 	{"Voice Analog Loopback", NULL, "FM Loop Enable"},
1682 
1683 	{"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1684 	{"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1685 	{"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1686 	{"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1687 	{"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
1688 
1689 	/* Digital bypass routes */
1690 	{"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1691 	{"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1692 	{"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
1693 
1694 	{"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1695 	{"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1696 	{"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
1697 
1698 };
1699 
1700 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1701 				  enum snd_soc_bias_level level)
1702 {
1703 	switch (level) {
1704 	case SND_SOC_BIAS_ON:
1705 		break;
1706 	case SND_SOC_BIAS_PREPARE:
1707 		break;
1708 	case SND_SOC_BIAS_STANDBY:
1709 		if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1710 			twl4030_codec_enable(codec, 1);
1711 		break;
1712 	case SND_SOC_BIAS_OFF:
1713 		twl4030_codec_enable(codec, 0);
1714 		break;
1715 	}
1716 	codec->dapm.bias_level = level;
1717 
1718 	return 0;
1719 }
1720 
1721 static void twl4030_constraints(struct twl4030_priv *twl4030,
1722 				struct snd_pcm_substream *mst_substream)
1723 {
1724 	struct snd_pcm_substream *slv_substream;
1725 
1726 	/* Pick the stream, which need to be constrained */
1727 	if (mst_substream == twl4030->master_substream)
1728 		slv_substream = twl4030->slave_substream;
1729 	else if (mst_substream == twl4030->slave_substream)
1730 		slv_substream = twl4030->master_substream;
1731 	else /* This should not happen.. */
1732 		return;
1733 
1734 	/* Set the constraints according to the already configured stream */
1735 	snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1736 				SNDRV_PCM_HW_PARAM_RATE,
1737 				twl4030->rate,
1738 				twl4030->rate);
1739 
1740 	snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1741 				SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1742 				twl4030->sample_bits,
1743 				twl4030->sample_bits);
1744 
1745 	snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1746 				SNDRV_PCM_HW_PARAM_CHANNELS,
1747 				twl4030->channels,
1748 				twl4030->channels);
1749 }
1750 
1751 /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1752  * capture has to be enabled/disabled. */
1753 static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1754 				int enable)
1755 {
1756 	u8 reg, mask;
1757 
1758 	reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1759 
1760 	if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1761 		mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1762 	else
1763 		mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1764 
1765 	if (enable)
1766 		reg |= mask;
1767 	else
1768 		reg &= ~mask;
1769 
1770 	twl4030_write(codec, TWL4030_REG_OPTION, reg);
1771 }
1772 
1773 static int twl4030_startup(struct snd_pcm_substream *substream,
1774 			   struct snd_soc_dai *dai)
1775 {
1776 	struct snd_soc_codec *codec = dai->codec;
1777 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1778 
1779 	if (twl4030->master_substream) {
1780 		twl4030->slave_substream = substream;
1781 		/* The DAI has one configuration for playback and capture, so
1782 		 * if the DAI has been already configured then constrain this
1783 		 * substream to match it. */
1784 		if (twl4030->configured)
1785 			twl4030_constraints(twl4030, twl4030->master_substream);
1786 	} else {
1787 		if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1788 			TWL4030_OPTION_1)) {
1789 			/* In option2 4 channel is not supported, set the
1790 			 * constraint for the first stream for channels, the
1791 			 * second stream will 'inherit' this cosntraint */
1792 			snd_pcm_hw_constraint_minmax(substream->runtime,
1793 						SNDRV_PCM_HW_PARAM_CHANNELS,
1794 						2, 2);
1795 		}
1796 		twl4030->master_substream = substream;
1797 	}
1798 
1799 	return 0;
1800 }
1801 
1802 static void twl4030_shutdown(struct snd_pcm_substream *substream,
1803 			     struct snd_soc_dai *dai)
1804 {
1805 	struct snd_soc_codec *codec = dai->codec;
1806 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1807 
1808 	if (twl4030->master_substream == substream)
1809 		twl4030->master_substream = twl4030->slave_substream;
1810 
1811 	twl4030->slave_substream = NULL;
1812 
1813 	/* If all streams are closed, or the remaining stream has not yet
1814 	 * been configured than set the DAI as not configured. */
1815 	if (!twl4030->master_substream)
1816 		twl4030->configured = 0;
1817 	 else if (!twl4030->master_substream->runtime->channels)
1818 		twl4030->configured = 0;
1819 
1820 	 /* If the closing substream had 4 channel, do the necessary cleanup */
1821 	if (substream->runtime->channels == 4)
1822 		twl4030_tdm_enable(codec, substream->stream, 0);
1823 }
1824 
1825 static int twl4030_hw_params(struct snd_pcm_substream *substream,
1826 			   struct snd_pcm_hw_params *params,
1827 			   struct snd_soc_dai *dai)
1828 {
1829 	struct snd_soc_codec *codec = dai->codec;
1830 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1831 	u8 mode, old_mode, format, old_format;
1832 
1833 	 /* If the substream has 4 channel, do the necessary setup */
1834 	if (params_channels(params) == 4) {
1835 		format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1836 		mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1837 
1838 		/* Safety check: are we in the correct operating mode and
1839 		 * the interface is in TDM mode? */
1840 		if ((mode & TWL4030_OPTION_1) &&
1841 		    ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
1842 			twl4030_tdm_enable(codec, substream->stream, 1);
1843 		else
1844 			return -EINVAL;
1845 	}
1846 
1847 	if (twl4030->configured)
1848 		/* Ignoring hw_params for already configured DAI */
1849 		return 0;
1850 
1851 	/* bit rate */
1852 	old_mode = twl4030_read_reg_cache(codec,
1853 			TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1854 	mode = old_mode & ~TWL4030_APLL_RATE;
1855 
1856 	switch (params_rate(params)) {
1857 	case 8000:
1858 		mode |= TWL4030_APLL_RATE_8000;
1859 		break;
1860 	case 11025:
1861 		mode |= TWL4030_APLL_RATE_11025;
1862 		break;
1863 	case 12000:
1864 		mode |= TWL4030_APLL_RATE_12000;
1865 		break;
1866 	case 16000:
1867 		mode |= TWL4030_APLL_RATE_16000;
1868 		break;
1869 	case 22050:
1870 		mode |= TWL4030_APLL_RATE_22050;
1871 		break;
1872 	case 24000:
1873 		mode |= TWL4030_APLL_RATE_24000;
1874 		break;
1875 	case 32000:
1876 		mode |= TWL4030_APLL_RATE_32000;
1877 		break;
1878 	case 44100:
1879 		mode |= TWL4030_APLL_RATE_44100;
1880 		break;
1881 	case 48000:
1882 		mode |= TWL4030_APLL_RATE_48000;
1883 		break;
1884 	case 96000:
1885 		mode |= TWL4030_APLL_RATE_96000;
1886 		break;
1887 	default:
1888 		dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
1889 			params_rate(params));
1890 		return -EINVAL;
1891 	}
1892 
1893 	/* sample size */
1894 	old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1895 	format = old_format;
1896 	format &= ~TWL4030_DATA_WIDTH;
1897 	switch (params_format(params)) {
1898 	case SNDRV_PCM_FORMAT_S16_LE:
1899 		format |= TWL4030_DATA_WIDTH_16S_16W;
1900 		break;
1901 	case SNDRV_PCM_FORMAT_S32_LE:
1902 		format |= TWL4030_DATA_WIDTH_32S_24W;
1903 		break;
1904 	default:
1905 		dev_err(codec->dev, "%s: unknown format %d\n", __func__,
1906 			params_format(params));
1907 		return -EINVAL;
1908 	}
1909 
1910 	if (format != old_format || mode != old_mode) {
1911 		if (twl4030->codec_powered) {
1912 			/*
1913 			 * If the codec is powered, than we need to toggle the
1914 			 * codec power.
1915 			 */
1916 			twl4030_codec_enable(codec, 0);
1917 			twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1918 			twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1919 			twl4030_codec_enable(codec, 1);
1920 		} else {
1921 			twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1922 			twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1923 		}
1924 	}
1925 
1926 	/* Store the important parameters for the DAI configuration and set
1927 	 * the DAI as configured */
1928 	twl4030->configured = 1;
1929 	twl4030->rate = params_rate(params);
1930 	twl4030->sample_bits = hw_param_interval(params,
1931 					SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1932 	twl4030->channels = params_channels(params);
1933 
1934 	/* If both playback and capture streams are open, and one of them
1935 	 * is setting the hw parameters right now (since we are here), set
1936 	 * constraints to the other stream to match the current one. */
1937 	if (twl4030->slave_substream)
1938 		twl4030_constraints(twl4030, substream);
1939 
1940 	return 0;
1941 }
1942 
1943 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1944 		int clk_id, unsigned int freq, int dir)
1945 {
1946 	struct snd_soc_codec *codec = codec_dai->codec;
1947 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1948 
1949 	switch (freq) {
1950 	case 19200000:
1951 	case 26000000:
1952 	case 38400000:
1953 		break;
1954 	default:
1955 		dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
1956 		return -EINVAL;
1957 	}
1958 
1959 	if ((freq / 1000) != twl4030->sysclk) {
1960 		dev_err(codec->dev,
1961 			"Mismatch in HFCLKIN: %u (configured: %u)\n",
1962 			freq, twl4030->sysclk * 1000);
1963 		return -EINVAL;
1964 	}
1965 
1966 	return 0;
1967 }
1968 
1969 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1970 			     unsigned int fmt)
1971 {
1972 	struct snd_soc_codec *codec = codec_dai->codec;
1973 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1974 	u8 old_format, format;
1975 
1976 	/* get format */
1977 	old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1978 	format = old_format;
1979 
1980 	/* set master/slave audio interface */
1981 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1982 	case SND_SOC_DAIFMT_CBM_CFM:
1983 		format &= ~(TWL4030_AIF_SLAVE_EN);
1984 		format &= ~(TWL4030_CLK256FS_EN);
1985 		break;
1986 	case SND_SOC_DAIFMT_CBS_CFS:
1987 		format |= TWL4030_AIF_SLAVE_EN;
1988 		format |= TWL4030_CLK256FS_EN;
1989 		break;
1990 	default:
1991 		return -EINVAL;
1992 	}
1993 
1994 	/* interface format */
1995 	format &= ~TWL4030_AIF_FORMAT;
1996 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1997 	case SND_SOC_DAIFMT_I2S:
1998 		format |= TWL4030_AIF_FORMAT_CODEC;
1999 		break;
2000 	case SND_SOC_DAIFMT_DSP_A:
2001 		format |= TWL4030_AIF_FORMAT_TDM;
2002 		break;
2003 	default:
2004 		return -EINVAL;
2005 	}
2006 
2007 	if (format != old_format) {
2008 		if (twl4030->codec_powered) {
2009 			/*
2010 			 * If the codec is powered, than we need to toggle the
2011 			 * codec power.
2012 			 */
2013 			twl4030_codec_enable(codec, 0);
2014 			twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
2015 			twl4030_codec_enable(codec, 1);
2016 		} else {
2017 			twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
2018 		}
2019 	}
2020 
2021 	return 0;
2022 }
2023 
2024 static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
2025 {
2026 	struct snd_soc_codec *codec = dai->codec;
2027 	u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
2028 
2029 	if (tristate)
2030 		reg |= TWL4030_AIF_TRI_EN;
2031 	else
2032 		reg &= ~TWL4030_AIF_TRI_EN;
2033 
2034 	return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
2035 }
2036 
2037 /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
2038  * (VTXL, VTXR) for uplink has to be enabled/disabled. */
2039 static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
2040 				int enable)
2041 {
2042 	u8 reg, mask;
2043 
2044 	reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
2045 
2046 	if (direction == SNDRV_PCM_STREAM_PLAYBACK)
2047 		mask = TWL4030_ARXL1_VRX_EN;
2048 	else
2049 		mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
2050 
2051 	if (enable)
2052 		reg |= mask;
2053 	else
2054 		reg &= ~mask;
2055 
2056 	twl4030_write(codec, TWL4030_REG_OPTION, reg);
2057 }
2058 
2059 static int twl4030_voice_startup(struct snd_pcm_substream *substream,
2060 		struct snd_soc_dai *dai)
2061 {
2062 	struct snd_soc_codec *codec = dai->codec;
2063 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2064 	u8 mode;
2065 
2066 	/* If the system master clock is not 26MHz, the voice PCM interface is
2067 	 * not available.
2068 	 */
2069 	if (twl4030->sysclk != 26000) {
2070 		dev_err(codec->dev,
2071 			"%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2072 			__func__, twl4030->sysclk);
2073 		return -EINVAL;
2074 	}
2075 
2076 	/* If the codec mode is not option2, the voice PCM interface is not
2077 	 * available.
2078 	 */
2079 	mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2080 		& TWL4030_OPT_MODE;
2081 
2082 	if (mode != TWL4030_OPTION_2) {
2083 		dev_err(codec->dev, "%s: the codec mode is not option2\n",
2084 			__func__);
2085 		return -EINVAL;
2086 	}
2087 
2088 	return 0;
2089 }
2090 
2091 static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2092 				struct snd_soc_dai *dai)
2093 {
2094 	struct snd_soc_codec *codec = dai->codec;
2095 
2096 	/* Enable voice digital filters */
2097 	twl4030_voice_enable(codec, substream->stream, 0);
2098 }
2099 
2100 static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2101 		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2102 {
2103 	struct snd_soc_codec *codec = dai->codec;
2104 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2105 	u8 old_mode, mode;
2106 
2107 	/* Enable voice digital filters */
2108 	twl4030_voice_enable(codec, substream->stream, 1);
2109 
2110 	/* bit rate */
2111 	old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2112 		& ~(TWL4030_CODECPDZ);
2113 	mode = old_mode;
2114 
2115 	switch (params_rate(params)) {
2116 	case 8000:
2117 		mode &= ~(TWL4030_SEL_16K);
2118 		break;
2119 	case 16000:
2120 		mode |= TWL4030_SEL_16K;
2121 		break;
2122 	default:
2123 		dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
2124 			params_rate(params));
2125 		return -EINVAL;
2126 	}
2127 
2128 	if (mode != old_mode) {
2129 		if (twl4030->codec_powered) {
2130 			/*
2131 			 * If the codec is powered, than we need to toggle the
2132 			 * codec power.
2133 			 */
2134 			twl4030_codec_enable(codec, 0);
2135 			twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2136 			twl4030_codec_enable(codec, 1);
2137 		} else {
2138 			twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2139 		}
2140 	}
2141 
2142 	return 0;
2143 }
2144 
2145 static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2146 		int clk_id, unsigned int freq, int dir)
2147 {
2148 	struct snd_soc_codec *codec = codec_dai->codec;
2149 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2150 
2151 	if (freq != 26000000) {
2152 		dev_err(codec->dev,
2153 			"%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2154 			__func__, freq / 1000);
2155 		return -EINVAL;
2156 	}
2157 	if ((freq / 1000) != twl4030->sysclk) {
2158 		dev_err(codec->dev,
2159 			"Mismatch in HFCLKIN: %u (configured: %u)\n",
2160 			freq, twl4030->sysclk * 1000);
2161 		return -EINVAL;
2162 	}
2163 	return 0;
2164 }
2165 
2166 static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2167 		unsigned int fmt)
2168 {
2169 	struct snd_soc_codec *codec = codec_dai->codec;
2170 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2171 	u8 old_format, format;
2172 
2173 	/* get format */
2174 	old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2175 	format = old_format;
2176 
2177 	/* set master/slave audio interface */
2178 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2179 	case SND_SOC_DAIFMT_CBM_CFM:
2180 		format &= ~(TWL4030_VIF_SLAVE_EN);
2181 		break;
2182 	case SND_SOC_DAIFMT_CBS_CFS:
2183 		format |= TWL4030_VIF_SLAVE_EN;
2184 		break;
2185 	default:
2186 		return -EINVAL;
2187 	}
2188 
2189 	/* clock inversion */
2190 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2191 	case SND_SOC_DAIFMT_IB_NF:
2192 		format &= ~(TWL4030_VIF_FORMAT);
2193 		break;
2194 	case SND_SOC_DAIFMT_NB_IF:
2195 		format |= TWL4030_VIF_FORMAT;
2196 		break;
2197 	default:
2198 		return -EINVAL;
2199 	}
2200 
2201 	if (format != old_format) {
2202 		if (twl4030->codec_powered) {
2203 			/*
2204 			 * If the codec is powered, than we need to toggle the
2205 			 * codec power.
2206 			 */
2207 			twl4030_codec_enable(codec, 0);
2208 			twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2209 			twl4030_codec_enable(codec, 1);
2210 		} else {
2211 			twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2212 		}
2213 	}
2214 
2215 	return 0;
2216 }
2217 
2218 static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2219 {
2220 	struct snd_soc_codec *codec = dai->codec;
2221 	u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2222 
2223 	if (tristate)
2224 		reg |= TWL4030_VIF_TRI_EN;
2225 	else
2226 		reg &= ~TWL4030_VIF_TRI_EN;
2227 
2228 	return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2229 }
2230 
2231 #define TWL4030_RATES	 (SNDRV_PCM_RATE_8000_48000)
2232 #define TWL4030_FORMATS	 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2233 
2234 static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
2235 	.startup	= twl4030_startup,
2236 	.shutdown	= twl4030_shutdown,
2237 	.hw_params	= twl4030_hw_params,
2238 	.set_sysclk	= twl4030_set_dai_sysclk,
2239 	.set_fmt	= twl4030_set_dai_fmt,
2240 	.set_tristate	= twl4030_set_tristate,
2241 };
2242 
2243 static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2244 	.startup	= twl4030_voice_startup,
2245 	.shutdown	= twl4030_voice_shutdown,
2246 	.hw_params	= twl4030_voice_hw_params,
2247 	.set_sysclk	= twl4030_voice_set_dai_sysclk,
2248 	.set_fmt	= twl4030_voice_set_dai_fmt,
2249 	.set_tristate	= twl4030_voice_set_tristate,
2250 };
2251 
2252 static struct snd_soc_dai_driver twl4030_dai[] = {
2253 {
2254 	.name = "twl4030-hifi",
2255 	.playback = {
2256 		.stream_name = "HiFi Playback",
2257 		.channels_min = 2,
2258 		.channels_max = 4,
2259 		.rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
2260 		.formats = TWL4030_FORMATS,
2261 		.sig_bits = 24,},
2262 	.capture = {
2263 		.stream_name = "HiFi Capture",
2264 		.channels_min = 2,
2265 		.channels_max = 4,
2266 		.rates = TWL4030_RATES,
2267 		.formats = TWL4030_FORMATS,
2268 		.sig_bits = 24,},
2269 	.ops = &twl4030_dai_hifi_ops,
2270 },
2271 {
2272 	.name = "twl4030-voice",
2273 	.playback = {
2274 		.stream_name = "Voice Playback",
2275 		.channels_min = 1,
2276 		.channels_max = 1,
2277 		.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2278 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
2279 	.capture = {
2280 		.stream_name = "Voice Capture",
2281 		.channels_min = 1,
2282 		.channels_max = 2,
2283 		.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2284 		.formats = SNDRV_PCM_FMTBIT_S16_LE,},
2285 	.ops = &twl4030_dai_voice_ops,
2286 },
2287 };
2288 
2289 static int twl4030_soc_probe(struct snd_soc_codec *codec)
2290 {
2291 	struct twl4030_priv *twl4030;
2292 
2293 	twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
2294 			       GFP_KERNEL);
2295 	if (twl4030 == NULL) {
2296 		dev_err(codec->dev, "Can not allocate memory\n");
2297 		return -ENOMEM;
2298 	}
2299 	snd_soc_codec_set_drvdata(codec, twl4030);
2300 	/* Set the defaults, and power up the codec */
2301 	twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
2302 
2303 	twl4030_init_chip(codec);
2304 
2305 	return 0;
2306 }
2307 
2308 static int twl4030_soc_remove(struct snd_soc_codec *codec)
2309 {
2310 	struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2311 	struct twl4030_codec_data *pdata = twl4030->pdata;
2312 
2313 	/* Reset registers to their chip default before leaving */
2314 	twl4030_reset_registers(codec);
2315 	twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2316 
2317 	if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2318 		gpio_free(pdata->hs_extmute_gpio);
2319 
2320 	return 0;
2321 }
2322 
2323 static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2324 	.probe = twl4030_soc_probe,
2325 	.remove = twl4030_soc_remove,
2326 	.read = twl4030_read_reg_cache,
2327 	.write = twl4030_write,
2328 	.set_bias_level = twl4030_set_bias_level,
2329 	.idle_bias_off = true,
2330 	.reg_cache_size = sizeof(twl4030_reg),
2331 	.reg_word_size = sizeof(u8),
2332 	.reg_cache_default = twl4030_reg,
2333 
2334 	.controls = twl4030_snd_controls,
2335 	.num_controls = ARRAY_SIZE(twl4030_snd_controls),
2336 	.dapm_widgets = twl4030_dapm_widgets,
2337 	.num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2338 	.dapm_routes = intercon,
2339 	.num_dapm_routes = ARRAY_SIZE(intercon),
2340 };
2341 
2342 static int twl4030_codec_probe(struct platform_device *pdev)
2343 {
2344 	return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
2345 			twl4030_dai, ARRAY_SIZE(twl4030_dai));
2346 }
2347 
2348 static int twl4030_codec_remove(struct platform_device *pdev)
2349 {
2350 	snd_soc_unregister_codec(&pdev->dev);
2351 	return 0;
2352 }
2353 
2354 MODULE_ALIAS("platform:twl4030-codec");
2355 
2356 static struct platform_driver twl4030_codec_driver = {
2357 	.probe		= twl4030_codec_probe,
2358 	.remove		= twl4030_codec_remove,
2359 	.driver		= {
2360 		.name	= "twl4030-codec",
2361 		.owner	= THIS_MODULE,
2362 	},
2363 };
2364 
2365 module_platform_driver(twl4030_codec_driver);
2366 
2367 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2368 MODULE_AUTHOR("Steve Sakoman");
2369 MODULE_LICENSE("GPL");
2370