1 /* 2 * ALSA SoC TWL4030 codec driver 3 * 4 * Author: Steve Sakoman, <steve@sakoman.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 18 * 02110-1301 USA 19 * 20 */ 21 22 #include <linux/module.h> 23 #include <linux/moduleparam.h> 24 #include <linux/init.h> 25 #include <linux/delay.h> 26 #include <linux/pm.h> 27 #include <linux/i2c.h> 28 #include <linux/platform_device.h> 29 #include <linux/i2c/twl4030.h> 30 #include <sound/core.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/soc.h> 34 #include <sound/soc-dapm.h> 35 #include <sound/initval.h> 36 #include <sound/tlv.h> 37 38 #include "twl4030.h" 39 40 /* 41 * twl4030 register cache & default register settings 42 */ 43 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { 44 0x00, /* this register not used */ 45 0x91, /* REG_CODEC_MODE (0x1) */ 46 0xc3, /* REG_OPTION (0x2) */ 47 0x00, /* REG_UNKNOWN (0x3) */ 48 0x00, /* REG_MICBIAS_CTL (0x4) */ 49 0x20, /* REG_ANAMICL (0x5) */ 50 0x00, /* REG_ANAMICR (0x6) */ 51 0x00, /* REG_AVADC_CTL (0x7) */ 52 0x00, /* REG_ADCMICSEL (0x8) */ 53 0x00, /* REG_DIGMIXING (0x9) */ 54 0x0c, /* REG_ATXL1PGA (0xA) */ 55 0x0c, /* REG_ATXR1PGA (0xB) */ 56 0x00, /* REG_AVTXL2PGA (0xC) */ 57 0x00, /* REG_AVTXR2PGA (0xD) */ 58 0x01, /* REG_AUDIO_IF (0xE) */ 59 0x00, /* REG_VOICE_IF (0xF) */ 60 0x00, /* REG_ARXR1PGA (0x10) */ 61 0x00, /* REG_ARXL1PGA (0x11) */ 62 0x6c, /* REG_ARXR2PGA (0x12) */ 63 0x6c, /* REG_ARXL2PGA (0x13) */ 64 0x00, /* REG_VRXPGA (0x14) */ 65 0x00, /* REG_VSTPGA (0x15) */ 66 0x00, /* REG_VRX2ARXPGA (0x16) */ 67 0x0c, /* REG_AVDAC_CTL (0x17) */ 68 0x00, /* REG_ARX2VTXPGA (0x18) */ 69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ 70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ 71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */ 72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */ 73 0x00, /* REG_ATX2ARXPGA (0x1D) */ 74 0x00, /* REG_BT_IF (0x1E) */ 75 0x00, /* REG_BTPGA (0x1F) */ 76 0x00, /* REG_BTSTPGA (0x20) */ 77 0x00, /* REG_EAR_CTL (0x21) */ 78 0x24, /* REG_HS_SEL (0x22) */ 79 0x0a, /* REG_HS_GAIN_SET (0x23) */ 80 0x00, /* REG_HS_POPN_SET (0x24) */ 81 0x00, /* REG_PREDL_CTL (0x25) */ 82 0x00, /* REG_PREDR_CTL (0x26) */ 83 0x00, /* REG_PRECKL_CTL (0x27) */ 84 0x00, /* REG_PRECKR_CTL (0x28) */ 85 0x00, /* REG_HFL_CTL (0x29) */ 86 0x00, /* REG_HFR_CTL (0x2A) */ 87 0x00, /* REG_ALC_CTL (0x2B) */ 88 0x00, /* REG_ALC_SET1 (0x2C) */ 89 0x00, /* REG_ALC_SET2 (0x2D) */ 90 0x00, /* REG_BOOST_CTL (0x2E) */ 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */ 92 0x00, /* REG_DTMF_FREQSEL (0x30) */ 93 0x00, /* REG_DTMF_TONEXT1H (0x31) */ 94 0x00, /* REG_DTMF_TONEXT1L (0x32) */ 95 0x00, /* REG_DTMF_TONEXT2H (0x33) */ 96 0x00, /* REG_DTMF_TONEXT2L (0x34) */ 97 0x00, /* REG_DTMF_TONOFF (0x35) */ 98 0x00, /* REG_DTMF_WANONOFF (0x36) */ 99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ 100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ 101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ 102 0x16, /* REG_APLL_CTL (0x3A) */ 103 0x00, /* REG_DTMF_CTL (0x3B) */ 104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ 105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ 106 0x00, /* REG_MISC_SET_1 (0x3E) */ 107 0x00, /* REG_PCMBTMUX (0x3F) */ 108 0x00, /* not used (0x40) */ 109 0x00, /* not used (0x41) */ 110 0x00, /* not used (0x42) */ 111 0x00, /* REG_RX_PATH_SEL (0x43) */ 112 0x00, /* REG_VDL_APGA_CTL (0x44) */ 113 0x00, /* REG_VIBRA_CTL (0x45) */ 114 0x00, /* REG_VIBRA_SET (0x46) */ 115 0x00, /* REG_VIBRA_PWM_SET (0x47) */ 116 0x00, /* REG_ANAMIC_GAIN (0x48) */ 117 0x00, /* REG_MISC_SET_2 (0x49) */ 118 }; 119 120 /* codec private data */ 121 struct twl4030_priv { 122 unsigned int bypass_state; 123 unsigned int codec_powered; 124 unsigned int codec_muted; 125 }; 126 127 /* 128 * read twl4030 register cache 129 */ 130 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, 131 unsigned int reg) 132 { 133 u8 *cache = codec->reg_cache; 134 135 if (reg >= TWL4030_CACHEREGNUM) 136 return -EIO; 137 138 return cache[reg]; 139 } 140 141 /* 142 * write twl4030 register cache 143 */ 144 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, 145 u8 reg, u8 value) 146 { 147 u8 *cache = codec->reg_cache; 148 149 if (reg >= TWL4030_CACHEREGNUM) 150 return; 151 cache[reg] = value; 152 } 153 154 /* 155 * write to the twl4030 register space 156 */ 157 static int twl4030_write(struct snd_soc_codec *codec, 158 unsigned int reg, unsigned int value) 159 { 160 twl4030_write_reg_cache(codec, reg, value); 161 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); 162 } 163 164 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) 165 { 166 struct twl4030_priv *twl4030 = codec->private_data; 167 u8 mode; 168 169 if (enable == twl4030->codec_powered) 170 return; 171 172 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); 173 if (enable) 174 mode |= TWL4030_CODECPDZ; 175 else 176 mode &= ~TWL4030_CODECPDZ; 177 178 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); 179 twl4030->codec_powered = enable; 180 181 /* REVISIT: this delay is present in TI sample drivers */ 182 /* but there seems to be no TRM requirement for it */ 183 udelay(10); 184 } 185 186 static void twl4030_init_chip(struct snd_soc_codec *codec) 187 { 188 int i; 189 190 /* clear CODECPDZ prior to setting register defaults */ 191 twl4030_codec_enable(codec, 0); 192 193 /* set all audio section registers to reasonable defaults */ 194 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++) 195 twl4030_write(codec, i, twl4030_reg[i]); 196 197 } 198 199 static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute) 200 { 201 struct twl4030_priv *twl4030 = codec->private_data; 202 u8 reg_val; 203 204 if (mute == twl4030->codec_muted) 205 return; 206 207 if (mute) { 208 /* Bypass the reg_cache and mute the volumes 209 * Headset mute is done in it's own event handler 210 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R 211 */ 212 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL); 213 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 214 reg_val & (~TWL4030_EAR_GAIN), 215 TWL4030_REG_EAR_CTL); 216 217 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL); 218 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 219 reg_val & (~TWL4030_PREDL_GAIN), 220 TWL4030_REG_PREDL_CTL); 221 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL); 222 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 223 reg_val & (~TWL4030_PREDR_GAIN), 224 TWL4030_REG_PREDL_CTL); 225 226 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL); 227 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 228 reg_val & (~TWL4030_PRECKL_GAIN), 229 TWL4030_REG_PRECKL_CTL); 230 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL); 231 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 232 reg_val & (~TWL4030_PRECKL_GAIN), 233 TWL4030_REG_PRECKR_CTL); 234 235 /* Disable PLL */ 236 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL); 237 reg_val &= ~TWL4030_APLL_EN; 238 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val); 239 } else { 240 /* Restore the volumes 241 * Headset mute is done in it's own event handler 242 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R 243 */ 244 twl4030_write(codec, TWL4030_REG_EAR_CTL, 245 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL)); 246 247 twl4030_write(codec, TWL4030_REG_PREDL_CTL, 248 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL)); 249 twl4030_write(codec, TWL4030_REG_PREDR_CTL, 250 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL)); 251 252 twl4030_write(codec, TWL4030_REG_PRECKL_CTL, 253 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL)); 254 twl4030_write(codec, TWL4030_REG_PRECKR_CTL, 255 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL)); 256 257 /* Enable PLL */ 258 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL); 259 reg_val |= TWL4030_APLL_EN; 260 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val); 261 } 262 263 twl4030->codec_muted = mute; 264 } 265 266 static void twl4030_power_up(struct snd_soc_codec *codec) 267 { 268 struct twl4030_priv *twl4030 = codec->private_data; 269 u8 anamicl, regmisc1, byte; 270 int i = 0; 271 272 if (twl4030->codec_powered) 273 return; 274 275 /* set CODECPDZ to turn on codec */ 276 twl4030_codec_enable(codec, 1); 277 278 /* initiate offset cancellation */ 279 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL); 280 twl4030_write(codec, TWL4030_REG_ANAMICL, 281 anamicl | TWL4030_CNCL_OFFSET_START); 282 283 /* wait for offset cancellation to complete */ 284 do { 285 /* this takes a little while, so don't slam i2c */ 286 udelay(2000); 287 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, 288 TWL4030_REG_ANAMICL); 289 } while ((i++ < 100) && 290 ((byte & TWL4030_CNCL_OFFSET_START) == 291 TWL4030_CNCL_OFFSET_START)); 292 293 /* Make sure that the reg_cache has the same value as the HW */ 294 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte); 295 296 /* anti-pop when changing analog gain */ 297 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1); 298 twl4030_write(codec, TWL4030_REG_MISC_SET_1, 299 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN); 300 301 /* toggle CODECPDZ as per TRM */ 302 twl4030_codec_enable(codec, 0); 303 twl4030_codec_enable(codec, 1); 304 } 305 306 /* 307 * Unconditional power down 308 */ 309 static void twl4030_power_down(struct snd_soc_codec *codec) 310 { 311 /* power down */ 312 twl4030_codec_enable(codec, 0); 313 } 314 315 /* Earpiece */ 316 static const char *twl4030_earpiece_texts[] = 317 {"Off", "DACL1", "DACL2", "DACR1"}; 318 319 static const unsigned int twl4030_earpiece_values[] = 320 {0x0, 0x1, 0x2, 0x4}; 321 322 static const struct soc_enum twl4030_earpiece_enum = 323 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7, 324 ARRAY_SIZE(twl4030_earpiece_texts), 325 twl4030_earpiece_texts, 326 twl4030_earpiece_values); 327 328 static const struct snd_kcontrol_new twl4030_dapm_earpiece_control = 329 SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum); 330 331 /* PreDrive Left */ 332 static const char *twl4030_predrivel_texts[] = 333 {"Off", "DACL1", "DACL2", "DACR2"}; 334 335 static const unsigned int twl4030_predrivel_values[] = 336 {0x0, 0x1, 0x2, 0x4}; 337 338 static const struct soc_enum twl4030_predrivel_enum = 339 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7, 340 ARRAY_SIZE(twl4030_predrivel_texts), 341 twl4030_predrivel_texts, 342 twl4030_predrivel_values); 343 344 static const struct snd_kcontrol_new twl4030_dapm_predrivel_control = 345 SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum); 346 347 /* PreDrive Right */ 348 static const char *twl4030_predriver_texts[] = 349 {"Off", "DACR1", "DACR2", "DACL2"}; 350 351 static const unsigned int twl4030_predriver_values[] = 352 {0x0, 0x1, 0x2, 0x4}; 353 354 static const struct soc_enum twl4030_predriver_enum = 355 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7, 356 ARRAY_SIZE(twl4030_predriver_texts), 357 twl4030_predriver_texts, 358 twl4030_predriver_values); 359 360 static const struct snd_kcontrol_new twl4030_dapm_predriver_control = 361 SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum); 362 363 /* Headset Left */ 364 static const char *twl4030_hsol_texts[] = 365 {"Off", "DACL1", "DACL2"}; 366 367 static const struct soc_enum twl4030_hsol_enum = 368 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1, 369 ARRAY_SIZE(twl4030_hsol_texts), 370 twl4030_hsol_texts); 371 372 static const struct snd_kcontrol_new twl4030_dapm_hsol_control = 373 SOC_DAPM_ENUM("Route", twl4030_hsol_enum); 374 375 /* Headset Right */ 376 static const char *twl4030_hsor_texts[] = 377 {"Off", "DACR1", "DACR2"}; 378 379 static const struct soc_enum twl4030_hsor_enum = 380 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4, 381 ARRAY_SIZE(twl4030_hsor_texts), 382 twl4030_hsor_texts); 383 384 static const struct snd_kcontrol_new twl4030_dapm_hsor_control = 385 SOC_DAPM_ENUM("Route", twl4030_hsor_enum); 386 387 /* Carkit Left */ 388 static const char *twl4030_carkitl_texts[] = 389 {"Off", "DACL1", "DACL2"}; 390 391 static const struct soc_enum twl4030_carkitl_enum = 392 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1, 393 ARRAY_SIZE(twl4030_carkitl_texts), 394 twl4030_carkitl_texts); 395 396 static const struct snd_kcontrol_new twl4030_dapm_carkitl_control = 397 SOC_DAPM_ENUM("Route", twl4030_carkitl_enum); 398 399 /* Carkit Right */ 400 static const char *twl4030_carkitr_texts[] = 401 {"Off", "DACR1", "DACR2"}; 402 403 static const struct soc_enum twl4030_carkitr_enum = 404 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1, 405 ARRAY_SIZE(twl4030_carkitr_texts), 406 twl4030_carkitr_texts); 407 408 static const struct snd_kcontrol_new twl4030_dapm_carkitr_control = 409 SOC_DAPM_ENUM("Route", twl4030_carkitr_enum); 410 411 /* Handsfree Left */ 412 static const char *twl4030_handsfreel_texts[] = 413 {"Voice", "DACL1", "DACL2", "DACR2"}; 414 415 static const struct soc_enum twl4030_handsfreel_enum = 416 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0, 417 ARRAY_SIZE(twl4030_handsfreel_texts), 418 twl4030_handsfreel_texts); 419 420 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control = 421 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum); 422 423 /* Handsfree Right */ 424 static const char *twl4030_handsfreer_texts[] = 425 {"Voice", "DACR1", "DACR2", "DACL2"}; 426 427 static const struct soc_enum twl4030_handsfreer_enum = 428 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0, 429 ARRAY_SIZE(twl4030_handsfreer_texts), 430 twl4030_handsfreer_texts); 431 432 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control = 433 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum); 434 435 /* Left analog microphone selection */ 436 static const char *twl4030_analoglmic_texts[] = 437 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"}; 438 439 static const unsigned int twl4030_analoglmic_values[] = 440 {0x0, 0x1, 0x2, 0x4, 0x8}; 441 442 static const struct soc_enum twl4030_analoglmic_enum = 443 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf, 444 ARRAY_SIZE(twl4030_analoglmic_texts), 445 twl4030_analoglmic_texts, 446 twl4030_analoglmic_values); 447 448 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control = 449 SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum); 450 451 /* Right analog microphone selection */ 452 static const char *twl4030_analogrmic_texts[] = 453 {"Off", "Sub mic", "AUXR"}; 454 455 static const unsigned int twl4030_analogrmic_values[] = 456 {0x0, 0x1, 0x4}; 457 458 static const struct soc_enum twl4030_analogrmic_enum = 459 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5, 460 ARRAY_SIZE(twl4030_analogrmic_texts), 461 twl4030_analogrmic_texts, 462 twl4030_analogrmic_values); 463 464 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control = 465 SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum); 466 467 /* TX1 L/R Analog/Digital microphone selection */ 468 static const char *twl4030_micpathtx1_texts[] = 469 {"Analog", "Digimic0"}; 470 471 static const struct soc_enum twl4030_micpathtx1_enum = 472 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0, 473 ARRAY_SIZE(twl4030_micpathtx1_texts), 474 twl4030_micpathtx1_texts); 475 476 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control = 477 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum); 478 479 /* TX2 L/R Analog/Digital microphone selection */ 480 static const char *twl4030_micpathtx2_texts[] = 481 {"Analog", "Digimic1"}; 482 483 static const struct soc_enum twl4030_micpathtx2_enum = 484 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2, 485 ARRAY_SIZE(twl4030_micpathtx2_texts), 486 twl4030_micpathtx2_texts); 487 488 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control = 489 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum); 490 491 /* Analog bypass for AudioR1 */ 492 static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control = 493 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0); 494 495 /* Analog bypass for AudioL1 */ 496 static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control = 497 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0); 498 499 /* Analog bypass for AudioR2 */ 500 static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control = 501 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0); 502 503 /* Analog bypass for AudioL2 */ 504 static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control = 505 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0); 506 507 /* Digital bypass gain, 0 mutes the bypass */ 508 static const unsigned int twl4030_dapm_dbypass_tlv[] = { 509 TLV_DB_RANGE_HEAD(2), 510 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1), 511 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0), 512 }; 513 514 /* Digital bypass left (TX1L -> RX2L) */ 515 static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control = 516 SOC_DAPM_SINGLE_TLV("Volume", 517 TWL4030_REG_ATX2ARXPGA, 3, 7, 0, 518 twl4030_dapm_dbypass_tlv); 519 520 /* Digital bypass right (TX1R -> RX2R) */ 521 static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control = 522 SOC_DAPM_SINGLE_TLV("Volume", 523 TWL4030_REG_ATX2ARXPGA, 0, 7, 0, 524 twl4030_dapm_dbypass_tlv); 525 526 static int micpath_event(struct snd_soc_dapm_widget *w, 527 struct snd_kcontrol *kcontrol, int event) 528 { 529 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value; 530 unsigned char adcmicsel, micbias_ctl; 531 532 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL); 533 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL); 534 /* Prepare the bits for the given TX path: 535 * shift_l == 0: TX1 microphone path 536 * shift_l == 2: TX2 microphone path */ 537 if (e->shift_l) { 538 /* TX2 microphone path */ 539 if (adcmicsel & TWL4030_TX2IN_SEL) 540 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */ 541 else 542 micbias_ctl &= ~TWL4030_MICBIAS2_CTL; 543 } else { 544 /* TX1 microphone path */ 545 if (adcmicsel & TWL4030_TX1IN_SEL) 546 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */ 547 else 548 micbias_ctl &= ~TWL4030_MICBIAS1_CTL; 549 } 550 551 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl); 552 553 return 0; 554 } 555 556 static int handsfree_event(struct snd_soc_dapm_widget *w, 557 struct snd_kcontrol *kcontrol, int event) 558 { 559 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value; 560 unsigned char hs_ctl; 561 562 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg); 563 564 if (hs_ctl & TWL4030_HF_CTL_REF_EN) { 565 hs_ctl |= TWL4030_HF_CTL_RAMP_EN; 566 twl4030_write(w->codec, e->reg, hs_ctl); 567 hs_ctl |= TWL4030_HF_CTL_LOOP_EN; 568 twl4030_write(w->codec, e->reg, hs_ctl); 569 hs_ctl |= TWL4030_HF_CTL_HB_EN; 570 twl4030_write(w->codec, e->reg, hs_ctl); 571 } else { 572 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN 573 | TWL4030_HF_CTL_HB_EN); 574 twl4030_write(w->codec, e->reg, hs_ctl); 575 } 576 577 return 0; 578 } 579 580 static int headsetl_event(struct snd_soc_dapm_widget *w, 581 struct snd_kcontrol *kcontrol, int event) 582 { 583 unsigned char hs_gain, hs_pop; 584 585 /* Save the current volume */ 586 hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET); 587 hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET); 588 589 switch (event) { 590 case SND_SOC_DAPM_POST_PMU: 591 /* Do the anti-pop/bias ramp enable according to the TRM */ 592 hs_pop |= TWL4030_VMID_EN; 593 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); 594 /* Is this needed? Can we just use whatever gain here? */ 595 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, 596 (hs_gain & (~0x0f)) | 0x0a); 597 hs_pop |= TWL4030_RAMP_EN; 598 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); 599 600 /* Restore the original volume */ 601 twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain); 602 break; 603 case SND_SOC_DAPM_POST_PMD: 604 /* Do the anti-pop/bias ramp disable according to the TRM */ 605 hs_pop &= ~TWL4030_RAMP_EN; 606 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); 607 /* Bypass the reg_cache to mute the headset */ 608 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 609 hs_gain & (~0x0f), 610 TWL4030_REG_HS_GAIN_SET); 611 hs_pop &= ~TWL4030_VMID_EN; 612 twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop); 613 break; 614 } 615 return 0; 616 } 617 618 static int bypass_event(struct snd_soc_dapm_widget *w, 619 struct snd_kcontrol *kcontrol, int event) 620 { 621 struct soc_mixer_control *m = 622 (struct soc_mixer_control *)w->kcontrols->private_value; 623 struct twl4030_priv *twl4030 = w->codec->private_data; 624 unsigned char reg; 625 626 reg = twl4030_read_reg_cache(w->codec, m->reg); 627 628 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) { 629 /* Analog bypass */ 630 if (reg & (1 << m->shift)) 631 twl4030->bypass_state |= 632 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL)); 633 else 634 twl4030->bypass_state &= 635 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL)); 636 } else { 637 /* Digital bypass */ 638 if (reg & (0x7 << m->shift)) 639 twl4030->bypass_state |= (1 << (m->shift ? 5 : 4)); 640 else 641 twl4030->bypass_state &= ~(1 << (m->shift ? 5 : 4)); 642 } 643 644 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) { 645 if (twl4030->bypass_state) 646 twl4030_codec_mute(w->codec, 0); 647 else 648 twl4030_codec_mute(w->codec, 1); 649 } 650 return 0; 651 } 652 653 /* 654 * Some of the gain controls in TWL (mostly those which are associated with 655 * the outputs) are implemented in an interesting way: 656 * 0x0 : Power down (mute) 657 * 0x1 : 6dB 658 * 0x2 : 0 dB 659 * 0x3 : -6 dB 660 * Inverting not going to help with these. 661 * Custom volsw and volsw_2r get/put functions to handle these gain bits. 662 */ 663 #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\ 664 xinvert, tlv_array) \ 665 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ 666 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 667 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 668 .tlv.p = (tlv_array), \ 669 .info = snd_soc_info_volsw, \ 670 .get = snd_soc_get_volsw_twl4030, \ 671 .put = snd_soc_put_volsw_twl4030, \ 672 .private_value = (unsigned long)&(struct soc_mixer_control) \ 673 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\ 674 .max = xmax, .invert = xinvert} } 675 #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\ 676 xinvert, tlv_array) \ 677 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ 678 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 679 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 680 .tlv.p = (tlv_array), \ 681 .info = snd_soc_info_volsw_2r, \ 682 .get = snd_soc_get_volsw_r2_twl4030,\ 683 .put = snd_soc_put_volsw_r2_twl4030, \ 684 .private_value = (unsigned long)&(struct soc_mixer_control) \ 685 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \ 686 .rshift = xshift, .max = xmax, .invert = xinvert} } 687 #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \ 688 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \ 689 xinvert, tlv_array) 690 691 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol, 692 struct snd_ctl_elem_value *ucontrol) 693 { 694 struct soc_mixer_control *mc = 695 (struct soc_mixer_control *)kcontrol->private_value; 696 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 697 unsigned int reg = mc->reg; 698 unsigned int shift = mc->shift; 699 unsigned int rshift = mc->rshift; 700 int max = mc->max; 701 int mask = (1 << fls(max)) - 1; 702 703 ucontrol->value.integer.value[0] = 704 (snd_soc_read(codec, reg) >> shift) & mask; 705 if (ucontrol->value.integer.value[0]) 706 ucontrol->value.integer.value[0] = 707 max + 1 - ucontrol->value.integer.value[0]; 708 709 if (shift != rshift) { 710 ucontrol->value.integer.value[1] = 711 (snd_soc_read(codec, reg) >> rshift) & mask; 712 if (ucontrol->value.integer.value[1]) 713 ucontrol->value.integer.value[1] = 714 max + 1 - ucontrol->value.integer.value[1]; 715 } 716 717 return 0; 718 } 719 720 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol, 721 struct snd_ctl_elem_value *ucontrol) 722 { 723 struct soc_mixer_control *mc = 724 (struct soc_mixer_control *)kcontrol->private_value; 725 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 726 unsigned int reg = mc->reg; 727 unsigned int shift = mc->shift; 728 unsigned int rshift = mc->rshift; 729 int max = mc->max; 730 int mask = (1 << fls(max)) - 1; 731 unsigned short val, val2, val_mask; 732 733 val = (ucontrol->value.integer.value[0] & mask); 734 735 val_mask = mask << shift; 736 if (val) 737 val = max + 1 - val; 738 val = val << shift; 739 if (shift != rshift) { 740 val2 = (ucontrol->value.integer.value[1] & mask); 741 val_mask |= mask << rshift; 742 if (val2) 743 val2 = max + 1 - val2; 744 val |= val2 << rshift; 745 } 746 return snd_soc_update_bits(codec, reg, val_mask, val); 747 } 748 749 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, 750 struct snd_ctl_elem_value *ucontrol) 751 { 752 struct soc_mixer_control *mc = 753 (struct soc_mixer_control *)kcontrol->private_value; 754 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 755 unsigned int reg = mc->reg; 756 unsigned int reg2 = mc->rreg; 757 unsigned int shift = mc->shift; 758 int max = mc->max; 759 int mask = (1<<fls(max))-1; 760 761 ucontrol->value.integer.value[0] = 762 (snd_soc_read(codec, reg) >> shift) & mask; 763 ucontrol->value.integer.value[1] = 764 (snd_soc_read(codec, reg2) >> shift) & mask; 765 766 if (ucontrol->value.integer.value[0]) 767 ucontrol->value.integer.value[0] = 768 max + 1 - ucontrol->value.integer.value[0]; 769 if (ucontrol->value.integer.value[1]) 770 ucontrol->value.integer.value[1] = 771 max + 1 - ucontrol->value.integer.value[1]; 772 773 return 0; 774 } 775 776 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, 777 struct snd_ctl_elem_value *ucontrol) 778 { 779 struct soc_mixer_control *mc = 780 (struct soc_mixer_control *)kcontrol->private_value; 781 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 782 unsigned int reg = mc->reg; 783 unsigned int reg2 = mc->rreg; 784 unsigned int shift = mc->shift; 785 int max = mc->max; 786 int mask = (1 << fls(max)) - 1; 787 int err; 788 unsigned short val, val2, val_mask; 789 790 val_mask = mask << shift; 791 val = (ucontrol->value.integer.value[0] & mask); 792 val2 = (ucontrol->value.integer.value[1] & mask); 793 794 if (val) 795 val = max + 1 - val; 796 if (val2) 797 val2 = max + 1 - val2; 798 799 val = val << shift; 800 val2 = val2 << shift; 801 802 err = snd_soc_update_bits(codec, reg, val_mask, val); 803 if (err < 0) 804 return err; 805 806 err = snd_soc_update_bits(codec, reg2, val_mask, val2); 807 return err; 808 } 809 810 /* 811 * FGAIN volume control: 812 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB) 813 */ 814 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1); 815 816 /* 817 * CGAIN volume control: 818 * 0 dB to 12 dB in 6 dB steps 819 * value 2 and 3 means 12 dB 820 */ 821 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0); 822 823 /* 824 * Analog playback gain 825 * -24 dB to 12 dB in 2 dB steps 826 */ 827 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0); 828 829 /* 830 * Gain controls tied to outputs 831 * -6 dB to 6 dB in 6 dB steps (mute instead of -12) 832 */ 833 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1); 834 835 /* 836 * Capture gain after the ADCs 837 * from 0 dB to 31 dB in 1 dB steps 838 */ 839 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0); 840 841 /* 842 * Gain control for input amplifiers 843 * 0 dB to 30 dB in 6 dB steps 844 */ 845 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0); 846 847 static const char *twl4030_rampdelay_texts[] = { 848 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms", 849 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms", 850 "3495/2581/1748 ms" 851 }; 852 853 static const struct soc_enum twl4030_rampdelay_enum = 854 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2, 855 ARRAY_SIZE(twl4030_rampdelay_texts), 856 twl4030_rampdelay_texts); 857 858 static const struct snd_kcontrol_new twl4030_snd_controls[] = { 859 /* Common playback gain controls */ 860 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume", 861 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, 862 0, 0x3f, 0, digital_fine_tlv), 863 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume", 864 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, 865 0, 0x3f, 0, digital_fine_tlv), 866 867 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume", 868 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, 869 6, 0x2, 0, digital_coarse_tlv), 870 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume", 871 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, 872 6, 0x2, 0, digital_coarse_tlv), 873 874 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume", 875 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, 876 3, 0x12, 1, analog_tlv), 877 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume", 878 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, 879 3, 0x12, 1, analog_tlv), 880 SOC_DOUBLE_R("DAC1 Analog Playback Switch", 881 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, 882 1, 1, 0), 883 SOC_DOUBLE_R("DAC2 Analog Playback Switch", 884 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, 885 1, 1, 0), 886 887 /* Separate output gain controls */ 888 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume", 889 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL, 890 4, 3, 0, output_tvl), 891 892 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume", 893 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl), 894 895 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume", 896 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL, 897 4, 3, 0, output_tvl), 898 899 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume", 900 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl), 901 902 /* Common capture gain controls */ 903 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume", 904 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA, 905 0, 0x1f, 0, digital_capture_tlv), 906 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume", 907 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA, 908 0, 0x1f, 0, digital_capture_tlv), 909 910 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN, 911 0, 3, 5, 0, input_gain_tlv), 912 913 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum), 914 }; 915 916 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { 917 /* Left channel inputs */ 918 SND_SOC_DAPM_INPUT("MAINMIC"), 919 SND_SOC_DAPM_INPUT("HSMIC"), 920 SND_SOC_DAPM_INPUT("AUXL"), 921 SND_SOC_DAPM_INPUT("CARKITMIC"), 922 /* Right channel inputs */ 923 SND_SOC_DAPM_INPUT("SUBMIC"), 924 SND_SOC_DAPM_INPUT("AUXR"), 925 /* Digital microphones (Stereo) */ 926 SND_SOC_DAPM_INPUT("DIGIMIC0"), 927 SND_SOC_DAPM_INPUT("DIGIMIC1"), 928 929 /* Outputs */ 930 SND_SOC_DAPM_OUTPUT("OUTL"), 931 SND_SOC_DAPM_OUTPUT("OUTR"), 932 SND_SOC_DAPM_OUTPUT("EARPIECE"), 933 SND_SOC_DAPM_OUTPUT("PREDRIVEL"), 934 SND_SOC_DAPM_OUTPUT("PREDRIVER"), 935 SND_SOC_DAPM_OUTPUT("HSOL"), 936 SND_SOC_DAPM_OUTPUT("HSOR"), 937 SND_SOC_DAPM_OUTPUT("CARKITL"), 938 SND_SOC_DAPM_OUTPUT("CARKITR"), 939 SND_SOC_DAPM_OUTPUT("HFL"), 940 SND_SOC_DAPM_OUTPUT("HFR"), 941 942 /* DACs */ 943 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback", 944 SND_SOC_NOPM, 0, 0), 945 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback", 946 SND_SOC_NOPM, 0, 0), 947 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback", 948 SND_SOC_NOPM, 0, 0), 949 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback", 950 SND_SOC_NOPM, 0, 0), 951 952 /* Analog PGAs */ 953 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL, 954 0, 0, NULL, 0), 955 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL, 956 0, 0, NULL, 0), 957 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL, 958 0, 0, NULL, 0), 959 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL, 960 0, 0, NULL, 0), 961 962 /* Analog bypasses */ 963 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0, 964 &twl4030_dapm_abypassr1_control, bypass_event, 965 SND_SOC_DAPM_POST_REG), 966 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0, 967 &twl4030_dapm_abypassl1_control, 968 bypass_event, SND_SOC_DAPM_POST_REG), 969 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0, 970 &twl4030_dapm_abypassr2_control, 971 bypass_event, SND_SOC_DAPM_POST_REG), 972 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0, 973 &twl4030_dapm_abypassl2_control, 974 bypass_event, SND_SOC_DAPM_POST_REG), 975 976 /* Digital bypasses */ 977 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0, 978 &twl4030_dapm_dbypassl_control, bypass_event, 979 SND_SOC_DAPM_POST_REG), 980 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0, 981 &twl4030_dapm_dbypassr_control, bypass_event, 982 SND_SOC_DAPM_POST_REG), 983 984 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL, 985 0, 0, NULL, 0), 986 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL, 987 1, 0, NULL, 0), 988 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL, 989 2, 0, NULL, 0), 990 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL, 991 3, 0, NULL, 0), 992 993 /* Output MUX controls */ 994 /* Earpiece */ 995 SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0, 996 &twl4030_dapm_earpiece_control), 997 /* PreDrivL/R */ 998 SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0, 999 &twl4030_dapm_predrivel_control), 1000 SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0, 1001 &twl4030_dapm_predriver_control), 1002 /* HeadsetL/R */ 1003 SND_SOC_DAPM_MUX_E("HeadsetL Mux", SND_SOC_NOPM, 0, 0, 1004 &twl4030_dapm_hsol_control, headsetl_event, 1005 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1006 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0, 1007 &twl4030_dapm_hsor_control), 1008 /* CarkitL/R */ 1009 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0, 1010 &twl4030_dapm_carkitl_control), 1011 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0, 1012 &twl4030_dapm_carkitr_control), 1013 /* HandsfreeL/R */ 1014 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0, 1015 &twl4030_dapm_handsfreel_control, handsfree_event, 1016 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1017 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0, 1018 &twl4030_dapm_handsfreer_control, handsfree_event, 1019 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), 1020 1021 /* Introducing four virtual ADC, since TWL4030 have four channel for 1022 capture */ 1023 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture", 1024 SND_SOC_NOPM, 0, 0), 1025 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture", 1026 SND_SOC_NOPM, 0, 0), 1027 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture", 1028 SND_SOC_NOPM, 0, 0), 1029 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture", 1030 SND_SOC_NOPM, 0, 0), 1031 1032 /* Analog/Digital mic path selection. 1033 TX1 Left/Right: either analog Left/Right or Digimic0 1034 TX2 Left/Right: either analog Left/Right or Digimic1 */ 1035 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0, 1036 &twl4030_dapm_micpathtx1_control, micpath_event, 1037 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| 1038 SND_SOC_DAPM_POST_REG), 1039 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0, 1040 &twl4030_dapm_micpathtx2_control, micpath_event, 1041 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| 1042 SND_SOC_DAPM_POST_REG), 1043 1044 /* Analog input muxes with switch for the capture amplifiers */ 1045 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route", 1046 TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control), 1047 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route", 1048 TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control), 1049 1050 SND_SOC_DAPM_PGA("ADC Physical Left", 1051 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0), 1052 SND_SOC_DAPM_PGA("ADC Physical Right", 1053 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0), 1054 1055 SND_SOC_DAPM_PGA("Digimic0 Enable", 1056 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0), 1057 SND_SOC_DAPM_PGA("Digimic1 Enable", 1058 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0), 1059 1060 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0), 1061 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0), 1062 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0), 1063 1064 }; 1065 1066 static const struct snd_soc_dapm_route intercon[] = { 1067 {"Analog L1 Playback Mixer", NULL, "DAC Left1"}, 1068 {"Analog R1 Playback Mixer", NULL, "DAC Right1"}, 1069 {"Analog L2 Playback Mixer", NULL, "DAC Left2"}, 1070 {"Analog R2 Playback Mixer", NULL, "DAC Right2"}, 1071 1072 {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"}, 1073 {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"}, 1074 {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"}, 1075 {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"}, 1076 1077 /* Internal playback routings */ 1078 /* Earpiece */ 1079 {"Earpiece Mux", "DACL1", "ARXL1_APGA"}, 1080 {"Earpiece Mux", "DACL2", "ARXL2_APGA"}, 1081 {"Earpiece Mux", "DACR1", "ARXR1_APGA"}, 1082 /* PreDrivL */ 1083 {"PredriveL Mux", "DACL1", "ARXL1_APGA"}, 1084 {"PredriveL Mux", "DACL2", "ARXL2_APGA"}, 1085 {"PredriveL Mux", "DACR2", "ARXR2_APGA"}, 1086 /* PreDrivR */ 1087 {"PredriveR Mux", "DACR1", "ARXR1_APGA"}, 1088 {"PredriveR Mux", "DACR2", "ARXR2_APGA"}, 1089 {"PredriveR Mux", "DACL2", "ARXL2_APGA"}, 1090 /* HeadsetL */ 1091 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"}, 1092 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"}, 1093 /* HeadsetR */ 1094 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"}, 1095 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"}, 1096 /* CarkitL */ 1097 {"CarkitL Mux", "DACL1", "ARXL1_APGA"}, 1098 {"CarkitL Mux", "DACL2", "ARXL2_APGA"}, 1099 /* CarkitR */ 1100 {"CarkitR Mux", "DACR1", "ARXR1_APGA"}, 1101 {"CarkitR Mux", "DACR2", "ARXR2_APGA"}, 1102 /* HandsfreeL */ 1103 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"}, 1104 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"}, 1105 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"}, 1106 /* HandsfreeR */ 1107 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"}, 1108 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"}, 1109 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"}, 1110 1111 /* outputs */ 1112 {"OUTL", NULL, "ARXL2_APGA"}, 1113 {"OUTR", NULL, "ARXR2_APGA"}, 1114 {"EARPIECE", NULL, "Earpiece Mux"}, 1115 {"PREDRIVEL", NULL, "PredriveL Mux"}, 1116 {"PREDRIVER", NULL, "PredriveR Mux"}, 1117 {"HSOL", NULL, "HeadsetL Mux"}, 1118 {"HSOR", NULL, "HeadsetR Mux"}, 1119 {"CARKITL", NULL, "CarkitL Mux"}, 1120 {"CARKITR", NULL, "CarkitR Mux"}, 1121 {"HFL", NULL, "HandsfreeL Mux"}, 1122 {"HFR", NULL, "HandsfreeR Mux"}, 1123 1124 /* Capture path */ 1125 {"Analog Left Capture Route", "Main mic", "MAINMIC"}, 1126 {"Analog Left Capture Route", "Headset mic", "HSMIC"}, 1127 {"Analog Left Capture Route", "AUXL", "AUXL"}, 1128 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"}, 1129 1130 {"Analog Right Capture Route", "Sub mic", "SUBMIC"}, 1131 {"Analog Right Capture Route", "AUXR", "AUXR"}, 1132 1133 {"ADC Physical Left", NULL, "Analog Left Capture Route"}, 1134 {"ADC Physical Right", NULL, "Analog Right Capture Route"}, 1135 1136 {"Digimic0 Enable", NULL, "DIGIMIC0"}, 1137 {"Digimic1 Enable", NULL, "DIGIMIC1"}, 1138 1139 /* TX1 Left capture path */ 1140 {"TX1 Capture Route", "Analog", "ADC Physical Left"}, 1141 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, 1142 /* TX1 Right capture path */ 1143 {"TX1 Capture Route", "Analog", "ADC Physical Right"}, 1144 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, 1145 /* TX2 Left capture path */ 1146 {"TX2 Capture Route", "Analog", "ADC Physical Left"}, 1147 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, 1148 /* TX2 Right capture path */ 1149 {"TX2 Capture Route", "Analog", "ADC Physical Right"}, 1150 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, 1151 1152 {"ADC Virtual Left1", NULL, "TX1 Capture Route"}, 1153 {"ADC Virtual Right1", NULL, "TX1 Capture Route"}, 1154 {"ADC Virtual Left2", NULL, "TX2 Capture Route"}, 1155 {"ADC Virtual Right2", NULL, "TX2 Capture Route"}, 1156 1157 /* Analog bypass routes */ 1158 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"}, 1159 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"}, 1160 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"}, 1161 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"}, 1162 1163 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"}, 1164 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"}, 1165 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"}, 1166 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"}, 1167 1168 /* Digital bypass routes */ 1169 {"Right Digital Loopback", "Volume", "TX1 Capture Route"}, 1170 {"Left Digital Loopback", "Volume", "TX1 Capture Route"}, 1171 1172 {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"}, 1173 {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"}, 1174 1175 }; 1176 1177 static int twl4030_add_widgets(struct snd_soc_codec *codec) 1178 { 1179 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets, 1180 ARRAY_SIZE(twl4030_dapm_widgets)); 1181 1182 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 1183 1184 snd_soc_dapm_new_widgets(codec); 1185 return 0; 1186 } 1187 1188 static int twl4030_set_bias_level(struct snd_soc_codec *codec, 1189 enum snd_soc_bias_level level) 1190 { 1191 struct twl4030_priv *twl4030 = codec->private_data; 1192 1193 switch (level) { 1194 case SND_SOC_BIAS_ON: 1195 twl4030_codec_mute(codec, 0); 1196 break; 1197 case SND_SOC_BIAS_PREPARE: 1198 twl4030_power_up(codec); 1199 if (twl4030->bypass_state) 1200 twl4030_codec_mute(codec, 0); 1201 else 1202 twl4030_codec_mute(codec, 1); 1203 break; 1204 case SND_SOC_BIAS_STANDBY: 1205 twl4030_power_up(codec); 1206 if (twl4030->bypass_state) 1207 twl4030_codec_mute(codec, 0); 1208 else 1209 twl4030_codec_mute(codec, 1); 1210 break; 1211 case SND_SOC_BIAS_OFF: 1212 twl4030_power_down(codec); 1213 break; 1214 } 1215 codec->bias_level = level; 1216 1217 return 0; 1218 } 1219 1220 static int twl4030_hw_params(struct snd_pcm_substream *substream, 1221 struct snd_pcm_hw_params *params, 1222 struct snd_soc_dai *dai) 1223 { 1224 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1225 struct snd_soc_device *socdev = rtd->socdev; 1226 struct snd_soc_codec *codec = socdev->card->codec; 1227 u8 mode, old_mode, format, old_format; 1228 1229 /* bit rate */ 1230 old_mode = twl4030_read_reg_cache(codec, 1231 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; 1232 mode = old_mode & ~TWL4030_APLL_RATE; 1233 1234 switch (params_rate(params)) { 1235 case 8000: 1236 mode |= TWL4030_APLL_RATE_8000; 1237 break; 1238 case 11025: 1239 mode |= TWL4030_APLL_RATE_11025; 1240 break; 1241 case 12000: 1242 mode |= TWL4030_APLL_RATE_12000; 1243 break; 1244 case 16000: 1245 mode |= TWL4030_APLL_RATE_16000; 1246 break; 1247 case 22050: 1248 mode |= TWL4030_APLL_RATE_22050; 1249 break; 1250 case 24000: 1251 mode |= TWL4030_APLL_RATE_24000; 1252 break; 1253 case 32000: 1254 mode |= TWL4030_APLL_RATE_32000; 1255 break; 1256 case 44100: 1257 mode |= TWL4030_APLL_RATE_44100; 1258 break; 1259 case 48000: 1260 mode |= TWL4030_APLL_RATE_48000; 1261 break; 1262 default: 1263 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n", 1264 params_rate(params)); 1265 return -EINVAL; 1266 } 1267 1268 if (mode != old_mode) { 1269 /* change rate and set CODECPDZ */ 1270 twl4030_codec_enable(codec, 0); 1271 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); 1272 twl4030_codec_enable(codec, 1); 1273 } 1274 1275 /* sample size */ 1276 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); 1277 format = old_format; 1278 format &= ~TWL4030_DATA_WIDTH; 1279 switch (params_format(params)) { 1280 case SNDRV_PCM_FORMAT_S16_LE: 1281 format |= TWL4030_DATA_WIDTH_16S_16W; 1282 break; 1283 case SNDRV_PCM_FORMAT_S24_LE: 1284 format |= TWL4030_DATA_WIDTH_32S_24W; 1285 break; 1286 default: 1287 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n", 1288 params_format(params)); 1289 return -EINVAL; 1290 } 1291 1292 if (format != old_format) { 1293 1294 /* clear CODECPDZ before changing format (codec requirement) */ 1295 twl4030_codec_enable(codec, 0); 1296 1297 /* change format */ 1298 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); 1299 1300 /* set CODECPDZ afterwards */ 1301 twl4030_codec_enable(codec, 1); 1302 } 1303 return 0; 1304 } 1305 1306 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1307 int clk_id, unsigned int freq, int dir) 1308 { 1309 struct snd_soc_codec *codec = codec_dai->codec; 1310 u8 infreq; 1311 1312 switch (freq) { 1313 case 19200000: 1314 infreq = TWL4030_APLL_INFREQ_19200KHZ; 1315 break; 1316 case 26000000: 1317 infreq = TWL4030_APLL_INFREQ_26000KHZ; 1318 break; 1319 case 38400000: 1320 infreq = TWL4030_APLL_INFREQ_38400KHZ; 1321 break; 1322 default: 1323 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n", 1324 freq); 1325 return -EINVAL; 1326 } 1327 1328 infreq |= TWL4030_APLL_EN; 1329 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq); 1330 1331 return 0; 1332 } 1333 1334 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, 1335 unsigned int fmt) 1336 { 1337 struct snd_soc_codec *codec = codec_dai->codec; 1338 u8 old_format, format; 1339 1340 /* get format */ 1341 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); 1342 format = old_format; 1343 1344 /* set master/slave audio interface */ 1345 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1346 case SND_SOC_DAIFMT_CBM_CFM: 1347 format &= ~(TWL4030_AIF_SLAVE_EN); 1348 format &= ~(TWL4030_CLK256FS_EN); 1349 break; 1350 case SND_SOC_DAIFMT_CBS_CFS: 1351 format |= TWL4030_AIF_SLAVE_EN; 1352 format |= TWL4030_CLK256FS_EN; 1353 break; 1354 default: 1355 return -EINVAL; 1356 } 1357 1358 /* interface format */ 1359 format &= ~TWL4030_AIF_FORMAT; 1360 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1361 case SND_SOC_DAIFMT_I2S: 1362 format |= TWL4030_AIF_FORMAT_CODEC; 1363 break; 1364 default: 1365 return -EINVAL; 1366 } 1367 1368 if (format != old_format) { 1369 1370 /* clear CODECPDZ before changing format (codec requirement) */ 1371 twl4030_codec_enable(codec, 0); 1372 1373 /* change format */ 1374 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); 1375 1376 /* set CODECPDZ afterwards */ 1377 twl4030_codec_enable(codec, 1); 1378 } 1379 1380 return 0; 1381 } 1382 1383 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) 1384 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) 1385 1386 static struct snd_soc_dai_ops twl4030_dai_ops = { 1387 .hw_params = twl4030_hw_params, 1388 .set_sysclk = twl4030_set_dai_sysclk, 1389 .set_fmt = twl4030_set_dai_fmt, 1390 }; 1391 1392 struct snd_soc_dai twl4030_dai = { 1393 .name = "twl4030", 1394 .playback = { 1395 .stream_name = "Playback", 1396 .channels_min = 2, 1397 .channels_max = 2, 1398 .rates = TWL4030_RATES, 1399 .formats = TWL4030_FORMATS,}, 1400 .capture = { 1401 .stream_name = "Capture", 1402 .channels_min = 2, 1403 .channels_max = 2, 1404 .rates = TWL4030_RATES, 1405 .formats = TWL4030_FORMATS,}, 1406 .ops = &twl4030_dai_ops, 1407 }; 1408 EXPORT_SYMBOL_GPL(twl4030_dai); 1409 1410 static int twl4030_suspend(struct platform_device *pdev, pm_message_t state) 1411 { 1412 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1413 struct snd_soc_codec *codec = socdev->card->codec; 1414 1415 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); 1416 1417 return 0; 1418 } 1419 1420 static int twl4030_resume(struct platform_device *pdev) 1421 { 1422 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1423 struct snd_soc_codec *codec = socdev->card->codec; 1424 1425 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1426 twl4030_set_bias_level(codec, codec->suspend_bias_level); 1427 return 0; 1428 } 1429 1430 /* 1431 * initialize the driver 1432 * register the mixer and dsp interfaces with the kernel 1433 */ 1434 1435 static int twl4030_init(struct snd_soc_device *socdev) 1436 { 1437 struct snd_soc_codec *codec = socdev->card->codec; 1438 int ret = 0; 1439 1440 printk(KERN_INFO "TWL4030 Audio Codec init \n"); 1441 1442 codec->name = "twl4030"; 1443 codec->owner = THIS_MODULE; 1444 codec->read = twl4030_read_reg_cache; 1445 codec->write = twl4030_write; 1446 codec->set_bias_level = twl4030_set_bias_level; 1447 codec->dai = &twl4030_dai; 1448 codec->num_dai = 1; 1449 codec->reg_cache_size = sizeof(twl4030_reg); 1450 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), 1451 GFP_KERNEL); 1452 if (codec->reg_cache == NULL) 1453 return -ENOMEM; 1454 1455 /* register pcms */ 1456 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1457 if (ret < 0) { 1458 printk(KERN_ERR "twl4030: failed to create pcms\n"); 1459 goto pcm_err; 1460 } 1461 1462 twl4030_init_chip(codec); 1463 1464 /* power on device */ 1465 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1466 1467 snd_soc_add_controls(codec, twl4030_snd_controls, 1468 ARRAY_SIZE(twl4030_snd_controls)); 1469 twl4030_add_widgets(codec); 1470 1471 ret = snd_soc_init_card(socdev); 1472 if (ret < 0) { 1473 printk(KERN_ERR "twl4030: failed to register card\n"); 1474 goto card_err; 1475 } 1476 1477 return ret; 1478 1479 card_err: 1480 snd_soc_free_pcms(socdev); 1481 snd_soc_dapm_free(socdev); 1482 pcm_err: 1483 kfree(codec->reg_cache); 1484 return ret; 1485 } 1486 1487 static struct snd_soc_device *twl4030_socdev; 1488 1489 static int twl4030_probe(struct platform_device *pdev) 1490 { 1491 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1492 struct snd_soc_codec *codec; 1493 struct twl4030_priv *twl4030; 1494 1495 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL); 1496 if (codec == NULL) 1497 return -ENOMEM; 1498 1499 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL); 1500 if (twl4030 == NULL) { 1501 kfree(codec); 1502 return -ENOMEM; 1503 } 1504 1505 codec->private_data = twl4030; 1506 socdev->card->codec = codec; 1507 mutex_init(&codec->mutex); 1508 INIT_LIST_HEAD(&codec->dapm_widgets); 1509 INIT_LIST_HEAD(&codec->dapm_paths); 1510 1511 twl4030_socdev = socdev; 1512 twl4030_init(socdev); 1513 1514 return 0; 1515 } 1516 1517 static int twl4030_remove(struct platform_device *pdev) 1518 { 1519 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1520 struct snd_soc_codec *codec = socdev->card->codec; 1521 1522 printk(KERN_INFO "TWL4030 Audio Codec remove\n"); 1523 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); 1524 snd_soc_free_pcms(socdev); 1525 snd_soc_dapm_free(socdev); 1526 kfree(codec->private_data); 1527 kfree(codec); 1528 1529 return 0; 1530 } 1531 1532 struct snd_soc_codec_device soc_codec_dev_twl4030 = { 1533 .probe = twl4030_probe, 1534 .remove = twl4030_remove, 1535 .suspend = twl4030_suspend, 1536 .resume = twl4030_resume, 1537 }; 1538 EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); 1539 1540 static int __init twl4030_modinit(void) 1541 { 1542 return snd_soc_register_dai(&twl4030_dai); 1543 } 1544 module_init(twl4030_modinit); 1545 1546 static void __exit twl4030_exit(void) 1547 { 1548 snd_soc_unregister_dai(&twl4030_dai); 1549 } 1550 module_exit(twl4030_exit); 1551 1552 MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); 1553 MODULE_AUTHOR("Steve Sakoman"); 1554 MODULE_LICENSE("GPL"); 1555