1 // SPDX-License-Identifier: GPL-2.0 2 // tscs42xx.c -- TSCS42xx ALSA SoC Audio driver 3 // Copyright 2017 Tempo Semiconductor, Inc. 4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com> 5 6 #include <linux/i2c.h> 7 #include <linux/module.h> 8 #include <linux/mutex.h> 9 #include <linux/regmap.h> 10 #include <sound/pcm_params.h> 11 #include <sound/soc.h> 12 #include <sound/soc-dapm.h> 13 #include <sound/tlv.h> 14 15 #include "tscs42xx.h" 16 17 #define COEFF_SIZE 3 18 #define BIQUAD_COEFF_COUNT 5 19 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT) 20 21 #define COEFF_RAM_MAX_ADDR 0xcd 22 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1) 23 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT) 24 25 struct tscs42xx { 26 27 int bclk_ratio; 28 int samplerate; 29 unsigned int blrcm; 30 struct mutex audio_params_lock; 31 32 u8 coeff_ram[COEFF_RAM_SIZE]; 33 bool coeff_ram_synced; 34 struct mutex coeff_ram_lock; 35 36 struct mutex pll_lock; 37 38 struct regmap *regmap; 39 40 struct device *dev; 41 }; 42 43 struct coeff_ram_ctl { 44 unsigned int addr; 45 struct soc_bytes_ext bytes_ext; 46 }; 47 48 static bool tscs42xx_volatile(struct device *dev, unsigned int reg) 49 { 50 switch (reg) { 51 case R_DACCRWRL: 52 case R_DACCRWRM: 53 case R_DACCRWRH: 54 case R_DACCRRDL: 55 case R_DACCRRDM: 56 case R_DACCRRDH: 57 case R_DACCRSTAT: 58 case R_DACCRADDR: 59 case R_PLLCTL0: 60 return true; 61 default: 62 return false; 63 }; 64 } 65 66 static bool tscs42xx_precious(struct device *dev, unsigned int reg) 67 { 68 switch (reg) { 69 case R_DACCRWRL: 70 case R_DACCRWRM: 71 case R_DACCRWRH: 72 case R_DACCRRDL: 73 case R_DACCRRDM: 74 case R_DACCRRDH: 75 return true; 76 default: 77 return false; 78 }; 79 } 80 81 static const struct regmap_config tscs42xx_regmap = { 82 .reg_bits = 8, 83 .val_bits = 8, 84 85 .volatile_reg = tscs42xx_volatile, 86 .precious_reg = tscs42xx_precious, 87 .max_register = R_DACMBCREL3H, 88 89 .cache_type = REGCACHE_RBTREE, 90 .can_multi_write = true, 91 }; 92 93 #define MAX_PLL_LOCK_20MS_WAITS 1 94 static bool plls_locked(struct snd_soc_codec *codec) 95 { 96 int ret; 97 int count = MAX_PLL_LOCK_20MS_WAITS; 98 99 do { 100 ret = snd_soc_read(codec, R_PLLCTL0); 101 if (ret < 0) { 102 dev_err(codec->dev, 103 "Failed to read PLL lock status (%d)\n", ret); 104 return false; 105 } else if (ret > 0) { 106 return true; 107 } 108 msleep(20); 109 } while (count--); 110 111 return false; 112 } 113 114 static int sample_rate_to_pll_freq_out(int sample_rate) 115 { 116 switch (sample_rate) { 117 case 11025: 118 case 22050: 119 case 44100: 120 case 88200: 121 return 112896000; 122 case 8000: 123 case 16000: 124 case 32000: 125 case 48000: 126 case 96000: 127 return 122880000; 128 default: 129 return -EINVAL; 130 } 131 } 132 133 #define DACCRSTAT_MAX_TRYS 10 134 static int write_coeff_ram(struct snd_soc_codec *codec, u8 *coeff_ram, 135 unsigned int addr, unsigned int coeff_cnt) 136 { 137 struct tscs42xx *tscs42xx = snd_soc_codec_get_drvdata(codec); 138 int cnt; 139 int trys; 140 int ret; 141 142 for (cnt = 0; cnt < coeff_cnt; cnt++, addr++) { 143 144 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) { 145 ret = snd_soc_read(codec, R_DACCRSTAT); 146 if (ret < 0) { 147 dev_err(codec->dev, 148 "Failed to read stat (%d)\n", ret); 149 return ret; 150 } 151 if (!ret) 152 break; 153 } 154 155 if (trys == DACCRSTAT_MAX_TRYS) { 156 ret = -EIO; 157 dev_err(codec->dev, 158 "dac coefficient write error (%d)\n", ret); 159 return ret; 160 } 161 162 ret = regmap_write(tscs42xx->regmap, R_DACCRADDR, addr); 163 if (ret < 0) { 164 dev_err(codec->dev, 165 "Failed to write dac ram address (%d)\n", ret); 166 return ret; 167 } 168 169 ret = regmap_bulk_write(tscs42xx->regmap, R_DACCRWRL, 170 &coeff_ram[addr * COEFF_SIZE], 171 COEFF_SIZE); 172 if (ret < 0) { 173 dev_err(codec->dev, 174 "Failed to write dac ram (%d)\n", ret); 175 return ret; 176 } 177 } 178 179 return 0; 180 } 181 182 static int power_up_audio_plls(struct snd_soc_codec *codec) 183 { 184 struct tscs42xx *tscs42xx = snd_soc_codec_get_drvdata(codec); 185 int freq_out; 186 int ret; 187 unsigned int mask; 188 unsigned int val; 189 190 freq_out = sample_rate_to_pll_freq_out(tscs42xx->samplerate); 191 switch (freq_out) { 192 case 122880000: /* 48k */ 193 mask = RM_PLLCTL1C_PDB_PLL1; 194 val = RV_PLLCTL1C_PDB_PLL1_ENABLE; 195 break; 196 case 112896000: /* 44.1k */ 197 mask = RM_PLLCTL1C_PDB_PLL2; 198 val = RV_PLLCTL1C_PDB_PLL2_ENABLE; 199 break; 200 default: 201 ret = -EINVAL; 202 dev_err(codec->dev, "Unrecognized PLL output freq (%d)\n", ret); 203 return ret; 204 } 205 206 mutex_lock(&tscs42xx->pll_lock); 207 208 ret = snd_soc_update_bits(codec, R_PLLCTL1C, mask, val); 209 if (ret < 0) { 210 dev_err(codec->dev, "Failed to turn PLL on (%d)\n", ret); 211 goto exit; 212 } 213 214 if (!plls_locked(codec)) { 215 dev_err(codec->dev, "Failed to lock plls\n"); 216 ret = -ENOMSG; 217 goto exit; 218 } 219 220 ret = 0; 221 exit: 222 mutex_unlock(&tscs42xx->pll_lock); 223 224 return ret; 225 } 226 227 static int power_down_audio_plls(struct snd_soc_codec *codec) 228 { 229 struct tscs42xx *tscs42xx = snd_soc_codec_get_drvdata(codec); 230 int ret; 231 232 mutex_lock(&tscs42xx->pll_lock); 233 234 ret = snd_soc_update_bits(codec, R_PLLCTL1C, 235 RM_PLLCTL1C_PDB_PLL1, 236 RV_PLLCTL1C_PDB_PLL1_DISABLE); 237 if (ret < 0) { 238 dev_err(codec->dev, "Failed to turn PLL off (%d)\n", ret); 239 goto exit; 240 } 241 ret = snd_soc_update_bits(codec, R_PLLCTL1C, 242 RM_PLLCTL1C_PDB_PLL2, 243 RV_PLLCTL1C_PDB_PLL2_DISABLE); 244 if (ret < 0) { 245 dev_err(codec->dev, "Failed to turn PLL off (%d)\n", ret); 246 goto exit; 247 } 248 249 ret = 0; 250 exit: 251 mutex_unlock(&tscs42xx->pll_lock); 252 253 return ret; 254 } 255 256 static int coeff_ram_get(struct snd_kcontrol *kcontrol, 257 struct snd_ctl_elem_value *ucontrol) 258 { 259 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 260 struct tscs42xx *tscs42xx = snd_soc_codec_get_drvdata(codec); 261 struct coeff_ram_ctl *ctl = 262 (struct coeff_ram_ctl *)kcontrol->private_value; 263 struct soc_bytes_ext *params = &ctl->bytes_ext; 264 265 mutex_lock(&tscs42xx->coeff_ram_lock); 266 267 memcpy(ucontrol->value.bytes.data, 268 &tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], params->max); 269 270 mutex_unlock(&tscs42xx->coeff_ram_lock); 271 272 return 0; 273 } 274 275 static int coeff_ram_put(struct snd_kcontrol *kcontrol, 276 struct snd_ctl_elem_value *ucontrol) 277 { 278 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 279 struct tscs42xx *tscs42xx = snd_soc_codec_get_drvdata(codec); 280 struct coeff_ram_ctl *ctl = 281 (struct coeff_ram_ctl *)kcontrol->private_value; 282 struct soc_bytes_ext *params = &ctl->bytes_ext; 283 unsigned int coeff_cnt = params->max / COEFF_SIZE; 284 int ret; 285 286 mutex_lock(&tscs42xx->coeff_ram_lock); 287 288 tscs42xx->coeff_ram_synced = false; 289 290 memcpy(&tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], 291 ucontrol->value.bytes.data, params->max); 292 293 mutex_lock(&tscs42xx->pll_lock); 294 295 if (plls_locked(codec)) { 296 ret = write_coeff_ram(codec, tscs42xx->coeff_ram, 297 ctl->addr, coeff_cnt); 298 if (ret < 0) { 299 dev_err(codec->dev, 300 "Failed to flush coeff ram cache (%d)\n", ret); 301 goto exit; 302 } 303 tscs42xx->coeff_ram_synced = true; 304 } 305 306 ret = 0; 307 exit: 308 mutex_unlock(&tscs42xx->pll_lock); 309 310 mutex_unlock(&tscs42xx->coeff_ram_lock); 311 312 return ret; 313 } 314 315 /* Input L Capture Route */ 316 static char const * const input_select_text[] = { 317 "Line 1", "Line 2", "Line 3", "D2S" 318 }; 319 320 static const struct soc_enum left_input_select_enum = 321 SOC_ENUM_SINGLE(R_INSELL, FB_INSELL, ARRAY_SIZE(input_select_text), 322 input_select_text); 323 324 static const struct snd_kcontrol_new left_input_select = 325 SOC_DAPM_ENUM("LEFT_INPUT_SELECT_ENUM", left_input_select_enum); 326 327 /* Input R Capture Route */ 328 static const struct soc_enum right_input_select_enum = 329 SOC_ENUM_SINGLE(R_INSELR, FB_INSELR, ARRAY_SIZE(input_select_text), 330 input_select_text); 331 332 static const struct snd_kcontrol_new right_input_select = 333 SOC_DAPM_ENUM("RIGHT_INPUT_SELECT_ENUM", right_input_select_enum); 334 335 /* Input Channel Mapping */ 336 static char const * const ch_map_select_text[] = { 337 "Normal", "Left to Right", "Right to Left", "Swap" 338 }; 339 340 static const struct soc_enum ch_map_select_enum = 341 SOC_ENUM_SINGLE(R_AIC2, FB_AIC2_ADCDSEL, ARRAY_SIZE(ch_map_select_text), 342 ch_map_select_text); 343 344 static int dapm_vref_event(struct snd_soc_dapm_widget *w, 345 struct snd_kcontrol *kcontrol, int event) 346 { 347 msleep(20); 348 return 0; 349 } 350 351 static int dapm_micb_event(struct snd_soc_dapm_widget *w, 352 struct snd_kcontrol *kcontrol, int event) 353 { 354 msleep(20); 355 return 0; 356 } 357 358 static int pll_event(struct snd_soc_dapm_widget *w, 359 struct snd_kcontrol *kcontrol, int event) 360 { 361 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 362 int ret; 363 364 if (SND_SOC_DAPM_EVENT_ON(event)) 365 ret = power_up_audio_plls(codec); 366 else 367 ret = power_down_audio_plls(codec); 368 369 return ret; 370 } 371 372 static int dac_event(struct snd_soc_dapm_widget *w, 373 struct snd_kcontrol *kcontrol, int event) 374 { 375 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 376 struct tscs42xx *tscs42xx = snd_soc_codec_get_drvdata(codec); 377 int ret; 378 379 mutex_lock(&tscs42xx->coeff_ram_lock); 380 381 if (tscs42xx->coeff_ram_synced == false) { 382 ret = write_coeff_ram(codec, tscs42xx->coeff_ram, 0x00, 383 COEFF_RAM_COEFF_COUNT); 384 if (ret < 0) 385 goto exit; 386 tscs42xx->coeff_ram_synced = true; 387 } 388 389 ret = 0; 390 exit: 391 mutex_unlock(&tscs42xx->coeff_ram_lock); 392 393 return ret; 394 } 395 396 static const struct snd_soc_dapm_widget tscs42xx_dapm_widgets[] = { 397 /* Vref */ 398 SND_SOC_DAPM_SUPPLY_S("Vref", 1, R_PWRM2, FB_PWRM2_VREF, 0, 399 dapm_vref_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 400 401 /* PLL */ 402 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, pll_event, 403 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 404 405 /* Headphone */ 406 SND_SOC_DAPM_DAC_E("DAC L", "HiFi Playback", R_PWRM2, FB_PWRM2_HPL, 0, 407 dac_event, SND_SOC_DAPM_POST_PMU), 408 SND_SOC_DAPM_DAC_E("DAC R", "HiFi Playback", R_PWRM2, FB_PWRM2_HPR, 0, 409 dac_event, SND_SOC_DAPM_POST_PMU), 410 SND_SOC_DAPM_OUTPUT("Headphone L"), 411 SND_SOC_DAPM_OUTPUT("Headphone R"), 412 413 /* Speaker */ 414 SND_SOC_DAPM_DAC_E("ClassD L", "HiFi Playback", 415 R_PWRM2, FB_PWRM2_SPKL, 0, 416 dac_event, SND_SOC_DAPM_POST_PMU), 417 SND_SOC_DAPM_DAC_E("ClassD R", "HiFi Playback", 418 R_PWRM2, FB_PWRM2_SPKR, 0, 419 dac_event, SND_SOC_DAPM_POST_PMU), 420 SND_SOC_DAPM_OUTPUT("Speaker L"), 421 SND_SOC_DAPM_OUTPUT("Speaker R"), 422 423 /* Capture */ 424 SND_SOC_DAPM_PGA("Analog In PGA L", R_PWRM1, FB_PWRM1_PGAL, 0, NULL, 0), 425 SND_SOC_DAPM_PGA("Analog In PGA R", R_PWRM1, FB_PWRM1_PGAR, 0, NULL, 0), 426 SND_SOC_DAPM_PGA("Analog Boost L", R_PWRM1, FB_PWRM1_BSTL, 0, NULL, 0), 427 SND_SOC_DAPM_PGA("Analog Boost R", R_PWRM1, FB_PWRM1_BSTR, 0, NULL, 0), 428 SND_SOC_DAPM_PGA("ADC Mute", R_CNVRTR0, FB_CNVRTR0_HPOR, true, NULL, 0), 429 SND_SOC_DAPM_ADC("ADC L", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCL, 0), 430 SND_SOC_DAPM_ADC("ADC R", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCR, 0), 431 432 /* Capture Input */ 433 SND_SOC_DAPM_MUX("Input L Capture Route", R_PWRM2, 434 FB_PWRM2_INSELL, 0, &left_input_select), 435 SND_SOC_DAPM_MUX("Input R Capture Route", R_PWRM2, 436 FB_PWRM2_INSELR, 0, &right_input_select), 437 438 /* Digital Mic */ 439 SND_SOC_DAPM_SUPPLY_S("Digital Mic Enable", 2, R_DMICCTL, 440 FB_DMICCTL_DMICEN, 0, NULL, 441 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 442 443 /* Analog Mic */ 444 SND_SOC_DAPM_SUPPLY_S("Mic Bias", 2, R_PWRM1, FB_PWRM1_MICB, 445 0, dapm_micb_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 446 447 /* Line In */ 448 SND_SOC_DAPM_INPUT("Line In 1 L"), 449 SND_SOC_DAPM_INPUT("Line In 1 R"), 450 SND_SOC_DAPM_INPUT("Line In 2 L"), 451 SND_SOC_DAPM_INPUT("Line In 2 R"), 452 SND_SOC_DAPM_INPUT("Line In 3 L"), 453 SND_SOC_DAPM_INPUT("Line In 3 R"), 454 }; 455 456 static const struct snd_soc_dapm_route tscs42xx_intercon[] = { 457 {"DAC L", NULL, "PLL"}, 458 {"DAC R", NULL, "PLL"}, 459 {"DAC L", NULL, "Vref"}, 460 {"DAC R", NULL, "Vref"}, 461 {"Headphone L", NULL, "DAC L"}, 462 {"Headphone R", NULL, "DAC R"}, 463 464 {"ClassD L", NULL, "PLL"}, 465 {"ClassD R", NULL, "PLL"}, 466 {"ClassD L", NULL, "Vref"}, 467 {"ClassD R", NULL, "Vref"}, 468 {"Speaker L", NULL, "ClassD L"}, 469 {"Speaker R", NULL, "ClassD R"}, 470 471 {"Input L Capture Route", NULL, "Vref"}, 472 {"Input R Capture Route", NULL, "Vref"}, 473 474 {"Mic Bias", NULL, "Vref"}, 475 476 {"Input L Capture Route", "Line 1", "Line In 1 L"}, 477 {"Input R Capture Route", "Line 1", "Line In 1 R"}, 478 {"Input L Capture Route", "Line 2", "Line In 2 L"}, 479 {"Input R Capture Route", "Line 2", "Line In 2 R"}, 480 {"Input L Capture Route", "Line 3", "Line In 3 L"}, 481 {"Input R Capture Route", "Line 3", "Line In 3 R"}, 482 483 {"Analog In PGA L", NULL, "Input L Capture Route"}, 484 {"Analog In PGA R", NULL, "Input R Capture Route"}, 485 {"Analog Boost L", NULL, "Analog In PGA L"}, 486 {"Analog Boost R", NULL, "Analog In PGA R"}, 487 {"ADC Mute", NULL, "Analog Boost L"}, 488 {"ADC Mute", NULL, "Analog Boost R"}, 489 {"ADC L", NULL, "PLL"}, 490 {"ADC R", NULL, "PLL"}, 491 {"ADC L", NULL, "ADC Mute"}, 492 {"ADC R", NULL, "ADC Mute"}, 493 }; 494 495 /************ 496 * CONTROLS * 497 ************/ 498 499 static char const * const eq_band_enable_text[] = { 500 "Prescale only", 501 "Band1", 502 "Band1:2", 503 "Band1:3", 504 "Band1:4", 505 "Band1:5", 506 "Band1:6", 507 }; 508 509 static char const * const level_detection_text[] = { 510 "Average", 511 "Peak", 512 }; 513 514 static char const * const level_detection_window_text[] = { 515 "512 Samples", 516 "64 Samples", 517 }; 518 519 static char const * const compressor_ratio_text[] = { 520 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1", 521 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1", 522 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1", 523 }; 524 525 static DECLARE_TLV_DB_SCALE(hpvol_scale, -8850, 75, 0); 526 static DECLARE_TLV_DB_SCALE(spkvol_scale, -7725, 75, 0); 527 static DECLARE_TLV_DB_SCALE(dacvol_scale, -9563, 38, 0); 528 static DECLARE_TLV_DB_SCALE(adcvol_scale, -7125, 38, 0); 529 static DECLARE_TLV_DB_SCALE(invol_scale, -1725, 75, 0); 530 static DECLARE_TLV_DB_SCALE(mic_boost_scale, 0, 1000, 0); 531 static DECLARE_TLV_DB_MINMAX(mugain_scale, 0, 4650); 532 static DECLARE_TLV_DB_MINMAX(compth_scale, -9562, 0); 533 534 static const struct soc_enum eq1_band_enable_enum = 535 SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ1_BE, 536 ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text); 537 538 static const struct soc_enum eq2_band_enable_enum = 539 SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ2_BE, 540 ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text); 541 542 static const struct soc_enum cle_level_detection_enum = 543 SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_LVL_MODE, 544 ARRAY_SIZE(level_detection_text), 545 level_detection_text); 546 547 static const struct soc_enum cle_level_detection_window_enum = 548 SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_WINDOWSEL, 549 ARRAY_SIZE(level_detection_window_text), 550 level_detection_window_text); 551 552 static const struct soc_enum mbc_level_detection_enums[] = { 553 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1, 554 ARRAY_SIZE(level_detection_text), 555 level_detection_text), 556 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2, 557 ARRAY_SIZE(level_detection_text), 558 level_detection_text), 559 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3, 560 ARRAY_SIZE(level_detection_text), 561 level_detection_text), 562 }; 563 564 static const struct soc_enum mbc_level_detection_window_enums[] = { 565 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1, 566 ARRAY_SIZE(level_detection_window_text), 567 level_detection_window_text), 568 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2, 569 ARRAY_SIZE(level_detection_window_text), 570 level_detection_window_text), 571 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3, 572 ARRAY_SIZE(level_detection_window_text), 573 level_detection_window_text), 574 }; 575 576 static const struct soc_enum compressor_ratio_enum = 577 SOC_ENUM_SINGLE(R_CMPRAT, FB_CMPRAT, 578 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 579 580 static const struct soc_enum dac_mbc1_compressor_ratio_enum = 581 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT1_RATIO, 582 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 583 584 static const struct soc_enum dac_mbc2_compressor_ratio_enum = 585 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT2_RATIO, 586 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 587 588 static const struct soc_enum dac_mbc3_compressor_ratio_enum = 589 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT3_RATIO, 590 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 591 592 static int bytes_info_ext(struct snd_kcontrol *kcontrol, 593 struct snd_ctl_elem_info *ucontrol) 594 { 595 struct coeff_ram_ctl *ctl = 596 (struct coeff_ram_ctl *)kcontrol->private_value; 597 struct soc_bytes_ext *params = &ctl->bytes_ext; 598 599 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 600 ucontrol->count = params->max; 601 602 return 0; 603 } 604 605 #define COEFF_RAM_CTL(xname, xcount, xaddr) \ 606 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 607 .info = bytes_info_ext, \ 608 .get = coeff_ram_get, .put = coeff_ram_put, \ 609 .private_value = (unsigned long)&(struct coeff_ram_ctl) { \ 610 .addr = xaddr, \ 611 .bytes_ext = {.max = xcount, }, \ 612 } \ 613 } 614 615 static const struct snd_kcontrol_new tscs42xx_snd_controls[] = { 616 /* Volumes */ 617 SOC_DOUBLE_R_TLV("Headphone Playback Volume", R_HPVOLL, R_HPVOLR, 618 FB_HPVOLL, 0x7F, 0, hpvol_scale), 619 SOC_DOUBLE_R_TLV("Speaker Playback Volume", R_SPKVOLL, R_SPKVOLR, 620 FB_SPKVOLL, 0x7F, 0, spkvol_scale), 621 SOC_DOUBLE_R_TLV("Master Playback Volume", R_DACVOLL, R_DACVOLR, 622 FB_DACVOLL, 0xFF, 0, dacvol_scale), 623 SOC_DOUBLE_R_TLV("PCM Capture Volume", R_ADCVOLL, R_ADCVOLR, 624 FB_ADCVOLL, 0xFF, 0, adcvol_scale), 625 SOC_DOUBLE_R_TLV("Master Capture Volume", R_INVOLL, R_INVOLR, 626 FB_INVOLL, 0x3F, 0, invol_scale), 627 628 /* INSEL */ 629 SOC_DOUBLE_R_TLV("Mic Boost Capture Volume", R_INSELL, R_INSELR, 630 FB_INSELL_MICBSTL, FV_INSELL_MICBSTL_30DB, 631 0, mic_boost_scale), 632 633 /* Input Channel Map */ 634 SOC_ENUM("Input Channel Map", ch_map_select_enum), 635 636 /* Coefficient Ram */ 637 COEFF_RAM_CTL("Cascade1L BiQuad1", BIQUAD_SIZE, 0x00), 638 COEFF_RAM_CTL("Cascade1L BiQuad2", BIQUAD_SIZE, 0x05), 639 COEFF_RAM_CTL("Cascade1L BiQuad3", BIQUAD_SIZE, 0x0a), 640 COEFF_RAM_CTL("Cascade1L BiQuad4", BIQUAD_SIZE, 0x0f), 641 COEFF_RAM_CTL("Cascade1L BiQuad5", BIQUAD_SIZE, 0x14), 642 COEFF_RAM_CTL("Cascade1L BiQuad6", BIQUAD_SIZE, 0x19), 643 644 COEFF_RAM_CTL("Cascade1R BiQuad1", BIQUAD_SIZE, 0x20), 645 COEFF_RAM_CTL("Cascade1R BiQuad2", BIQUAD_SIZE, 0x25), 646 COEFF_RAM_CTL("Cascade1R BiQuad3", BIQUAD_SIZE, 0x2a), 647 COEFF_RAM_CTL("Cascade1R BiQuad4", BIQUAD_SIZE, 0x2f), 648 COEFF_RAM_CTL("Cascade1R BiQuad5", BIQUAD_SIZE, 0x34), 649 COEFF_RAM_CTL("Cascade1R BiQuad6", BIQUAD_SIZE, 0x39), 650 651 COEFF_RAM_CTL("Cascade1L Prescale", COEFF_SIZE, 0x1f), 652 COEFF_RAM_CTL("Cascade1R Prescale", COEFF_SIZE, 0x3f), 653 654 COEFF_RAM_CTL("Cascade2L BiQuad1", BIQUAD_SIZE, 0x40), 655 COEFF_RAM_CTL("Cascade2L BiQuad2", BIQUAD_SIZE, 0x45), 656 COEFF_RAM_CTL("Cascade2L BiQuad3", BIQUAD_SIZE, 0x4a), 657 COEFF_RAM_CTL("Cascade2L BiQuad4", BIQUAD_SIZE, 0x4f), 658 COEFF_RAM_CTL("Cascade2L BiQuad5", BIQUAD_SIZE, 0x54), 659 COEFF_RAM_CTL("Cascade2L BiQuad6", BIQUAD_SIZE, 0x59), 660 661 COEFF_RAM_CTL("Cascade2R BiQuad1", BIQUAD_SIZE, 0x60), 662 COEFF_RAM_CTL("Cascade2R BiQuad2", BIQUAD_SIZE, 0x65), 663 COEFF_RAM_CTL("Cascade2R BiQuad3", BIQUAD_SIZE, 0x6a), 664 COEFF_RAM_CTL("Cascade2R BiQuad4", BIQUAD_SIZE, 0x6f), 665 COEFF_RAM_CTL("Cascade2R BiQuad5", BIQUAD_SIZE, 0x74), 666 COEFF_RAM_CTL("Cascade2R BiQuad6", BIQUAD_SIZE, 0x79), 667 668 COEFF_RAM_CTL("Cascade2L Prescale", COEFF_SIZE, 0x5f), 669 COEFF_RAM_CTL("Cascade2R Prescale", COEFF_SIZE, 0x7f), 670 671 COEFF_RAM_CTL("Bass Extraction BiQuad1", BIQUAD_SIZE, 0x80), 672 COEFF_RAM_CTL("Bass Extraction BiQuad2", BIQUAD_SIZE, 0x85), 673 674 COEFF_RAM_CTL("Bass Non Linear Function 1", COEFF_SIZE, 0x8a), 675 COEFF_RAM_CTL("Bass Non Linear Function 2", COEFF_SIZE, 0x8b), 676 677 COEFF_RAM_CTL("Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), 678 679 COEFF_RAM_CTL("Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), 680 681 COEFF_RAM_CTL("Bass Mix", COEFF_SIZE, 0x96), 682 683 COEFF_RAM_CTL("Treb Extraction BiQuad1", BIQUAD_SIZE, 0x97), 684 COEFF_RAM_CTL("Treb Extraction BiQuad2", BIQUAD_SIZE, 0x9c), 685 686 COEFF_RAM_CTL("Treb Non Linear Function 1", COEFF_SIZE, 0xa1), 687 COEFF_RAM_CTL("Treb Non Linear Function 2", COEFF_SIZE, 0xa2), 688 689 COEFF_RAM_CTL("Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), 690 691 COEFF_RAM_CTL("Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), 692 693 COEFF_RAM_CTL("Treb Mix", COEFF_SIZE, 0xad), 694 695 COEFF_RAM_CTL("3D", COEFF_SIZE, 0xae), 696 697 COEFF_RAM_CTL("3D Mix", COEFF_SIZE, 0xaf), 698 699 COEFF_RAM_CTL("MBC1 BiQuad1", BIQUAD_SIZE, 0xb0), 700 COEFF_RAM_CTL("MBC1 BiQuad2", BIQUAD_SIZE, 0xb5), 701 702 COEFF_RAM_CTL("MBC2 BiQuad1", BIQUAD_SIZE, 0xba), 703 COEFF_RAM_CTL("MBC2 BiQuad2", BIQUAD_SIZE, 0xbf), 704 705 COEFF_RAM_CTL("MBC3 BiQuad1", BIQUAD_SIZE, 0xc4), 706 COEFF_RAM_CTL("MBC3 BiQuad2", BIQUAD_SIZE, 0xc9), 707 708 /* EQ */ 709 SOC_SINGLE("EQ1 Switch", R_CONFIG1, FB_CONFIG1_EQ1_EN, 1, 0), 710 SOC_SINGLE("EQ2 Switch", R_CONFIG1, FB_CONFIG1_EQ2_EN, 1, 0), 711 SOC_ENUM("EQ1 Band Enable", eq1_band_enable_enum), 712 SOC_ENUM("EQ2 Band Enable", eq2_band_enable_enum), 713 714 /* CLE */ 715 SOC_ENUM("CLE Level Detect", 716 cle_level_detection_enum), 717 SOC_ENUM("CLE Level Detect Win", 718 cle_level_detection_window_enum), 719 SOC_SINGLE("Expander Switch", 720 R_CLECTL, FB_CLECTL_EXP_EN, 1, 0), 721 SOC_SINGLE("Limiter Switch", 722 R_CLECTL, FB_CLECTL_LIMIT_EN, 1, 0), 723 SOC_SINGLE("Comp Switch", 724 R_CLECTL, FB_CLECTL_COMP_EN, 1, 0), 725 SOC_SINGLE_TLV("CLE Make-Up Gain Playback Volume", 726 R_MUGAIN, FB_MUGAIN_CLEMUG, 0x1f, 0, mugain_scale), 727 SOC_SINGLE_TLV("Comp Thresh Playback Volume", 728 R_COMPTH, FB_COMPTH, 0xff, 0, compth_scale), 729 SOC_ENUM("Comp Ratio", compressor_ratio_enum), 730 SND_SOC_BYTES("Comp Atk Time", R_CATKTCL, 2), 731 732 /* Effects */ 733 SOC_SINGLE("3D Switch", R_FXCTL, FB_FXCTL_3DEN, 1, 0), 734 SOC_SINGLE("Treble Switch", R_FXCTL, FB_FXCTL_TEEN, 1, 0), 735 SOC_SINGLE("Treble Bypass Switch", R_FXCTL, FB_FXCTL_TNLFBYPASS, 1, 0), 736 SOC_SINGLE("Bass Switch", R_FXCTL, FB_FXCTL_BEEN, 1, 0), 737 SOC_SINGLE("Bass Bypass Switch", R_FXCTL, FB_FXCTL_BNLFBYPASS, 1, 0), 738 739 /* MBC */ 740 SOC_SINGLE("MBC Band1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0), 741 SOC_SINGLE("MBC Band2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0), 742 SOC_SINGLE("MBC Band3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0), 743 SOC_ENUM("MBC Band1 Level Detect", 744 mbc_level_detection_enums[0]), 745 SOC_ENUM("MBC Band2 Level Detect", 746 mbc_level_detection_enums[1]), 747 SOC_ENUM("MBC Band3 Level Detect", 748 mbc_level_detection_enums[2]), 749 SOC_ENUM("MBC Band1 Level Detect Win", 750 mbc_level_detection_window_enums[0]), 751 SOC_ENUM("MBC Band2 Level Detect Win", 752 mbc_level_detection_window_enums[1]), 753 SOC_ENUM("MBC Band3 Level Detect Win", 754 mbc_level_detection_window_enums[2]), 755 756 SOC_SINGLE("MBC1 Phase Invert Switch", 757 R_DACMBCMUG1, FB_DACMBCMUG1_PHASE, 1, 0), 758 SOC_SINGLE_TLV("DAC MBC1 Make-Up Gain Playback Volume", 759 R_DACMBCMUG1, FB_DACMBCMUG1_MUGAIN, 0x1f, 0, mugain_scale), 760 SOC_SINGLE_TLV("DAC MBC1 Comp Thresh Playback Volume", 761 R_DACMBCTHR1, FB_DACMBCTHR1_THRESH, 0xff, 0, compth_scale), 762 SOC_ENUM("DAC MBC1 Comp Ratio", 763 dac_mbc1_compressor_ratio_enum), 764 SND_SOC_BYTES("DAC MBC1 Comp Atk Time", R_DACMBCATK1L, 2), 765 SND_SOC_BYTES("DAC MBC1 Comp Rel Time Const", 766 R_DACMBCREL1L, 2), 767 768 SOC_SINGLE("MBC2 Phase Invert Switch", 769 R_DACMBCMUG2, FB_DACMBCMUG2_PHASE, 1, 0), 770 SOC_SINGLE_TLV("DAC MBC2 Make-Up Gain Playback Volume", 771 R_DACMBCMUG2, FB_DACMBCMUG2_MUGAIN, 0x1f, 0, mugain_scale), 772 SOC_SINGLE_TLV("DAC MBC2 Comp Thresh Playback Volume", 773 R_DACMBCTHR2, FB_DACMBCTHR2_THRESH, 0xff, 0, compth_scale), 774 SOC_ENUM("DAC MBC2 Comp Ratio", 775 dac_mbc2_compressor_ratio_enum), 776 SND_SOC_BYTES("DAC MBC2 Comp Atk Time", R_DACMBCATK2L, 2), 777 SND_SOC_BYTES("DAC MBC2 Comp Rel Time Const", 778 R_DACMBCREL2L, 2), 779 780 SOC_SINGLE("MBC3 Phase Invert Switch", 781 R_DACMBCMUG3, FB_DACMBCMUG3_PHASE, 1, 0), 782 SOC_SINGLE_TLV("DAC MBC3 Make-Up Gain Playback Volume", 783 R_DACMBCMUG3, FB_DACMBCMUG3_MUGAIN, 0x1f, 0, mugain_scale), 784 SOC_SINGLE_TLV("DAC MBC3 Comp Thresh Playback Volume", 785 R_DACMBCTHR3, FB_DACMBCTHR3_THRESH, 0xff, 0, compth_scale), 786 SOC_ENUM("DAC MBC3 Comp Ratio", 787 dac_mbc3_compressor_ratio_enum), 788 SND_SOC_BYTES("DAC MBC3 Comp Atk Time", R_DACMBCATK3L, 2), 789 SND_SOC_BYTES("DAC MBC3 Comp Rel Time Const", 790 R_DACMBCREL3L, 2), 791 }; 792 793 static int setup_sample_format(struct snd_soc_codec *codec, 794 snd_pcm_format_t format) 795 { 796 unsigned int width; 797 int ret; 798 799 switch (format) { 800 case SNDRV_PCM_FORMAT_S16_LE: 801 width = RV_AIC1_WL_16; 802 break; 803 case SNDRV_PCM_FORMAT_S20_3LE: 804 width = RV_AIC1_WL_20; 805 break; 806 case SNDRV_PCM_FORMAT_S24_LE: 807 width = RV_AIC1_WL_24; 808 break; 809 case SNDRV_PCM_FORMAT_S32_LE: 810 width = RV_AIC1_WL_32; 811 break; 812 default: 813 ret = -EINVAL; 814 dev_err(codec->dev, "Unsupported format width (%d)\n", ret); 815 return ret; 816 } 817 ret = snd_soc_update_bits(codec, R_AIC1, RM_AIC1_WL, width); 818 if (ret < 0) { 819 dev_err(codec->dev, "Failed to set sample width (%d)\n", ret); 820 return ret; 821 } 822 823 return 0; 824 } 825 826 static int setup_sample_rate(struct snd_soc_codec *codec, unsigned int rate) 827 { 828 struct tscs42xx *tscs42xx = snd_soc_codec_get_drvdata(codec); 829 unsigned int br, bm; 830 int ret; 831 832 switch (rate) { 833 case 8000: 834 br = RV_DACSR_DBR_32; 835 bm = RV_DACSR_DBM_PT25; 836 break; 837 case 16000: 838 br = RV_DACSR_DBR_32; 839 bm = RV_DACSR_DBM_PT5; 840 break; 841 case 24000: 842 br = RV_DACSR_DBR_48; 843 bm = RV_DACSR_DBM_PT5; 844 break; 845 case 32000: 846 br = RV_DACSR_DBR_32; 847 bm = RV_DACSR_DBM_1; 848 break; 849 case 48000: 850 br = RV_DACSR_DBR_48; 851 bm = RV_DACSR_DBM_1; 852 break; 853 case 96000: 854 br = RV_DACSR_DBR_48; 855 bm = RV_DACSR_DBM_2; 856 break; 857 case 11025: 858 br = RV_DACSR_DBR_44_1; 859 bm = RV_DACSR_DBM_PT25; 860 break; 861 case 22050: 862 br = RV_DACSR_DBR_44_1; 863 bm = RV_DACSR_DBM_PT5; 864 break; 865 case 44100: 866 br = RV_DACSR_DBR_44_1; 867 bm = RV_DACSR_DBM_1; 868 break; 869 case 88200: 870 br = RV_DACSR_DBR_44_1; 871 bm = RV_DACSR_DBM_2; 872 break; 873 default: 874 dev_err(codec->dev, "Unsupported sample rate %d\n", rate); 875 return -EINVAL; 876 } 877 878 /* DAC and ADC share bit and frame clock */ 879 ret = snd_soc_update_bits(codec, R_DACSR, RM_DACSR_DBR, br); 880 if (ret < 0) { 881 dev_err(codec->dev, "Failed to update register (%d)\n", ret); 882 return ret; 883 } 884 ret = snd_soc_update_bits(codec, R_DACSR, RM_DACSR_DBM, bm); 885 if (ret < 0) { 886 dev_err(codec->dev, "Failed to update register (%d)\n", ret); 887 return ret; 888 } 889 ret = snd_soc_update_bits(codec, R_ADCSR, RM_DACSR_DBR, br); 890 if (ret < 0) { 891 dev_err(codec->dev, "Failed to update register (%d)\n", ret); 892 return ret; 893 } 894 ret = snd_soc_update_bits(codec, R_ADCSR, RM_DACSR_DBM, bm); 895 if (ret < 0) { 896 dev_err(codec->dev, "Failed to update register (%d)\n", ret); 897 return ret; 898 } 899 900 mutex_lock(&tscs42xx->audio_params_lock); 901 902 tscs42xx->samplerate = rate; 903 904 mutex_unlock(&tscs42xx->audio_params_lock); 905 906 return 0; 907 } 908 909 struct reg_setting { 910 unsigned int addr; 911 unsigned int val; 912 unsigned int mask; 913 }; 914 915 #define PLL_REG_SETTINGS_COUNT 13 916 struct pll_ctl { 917 int input_freq; 918 struct reg_setting settings[PLL_REG_SETTINGS_COUNT]; 919 }; 920 921 #define PLL_CTL(f, rt, rd, r1b_l, r9, ra, rb, \ 922 rc, r12, r1b_h, re, rf, r10, r11) \ 923 { \ 924 .input_freq = f, \ 925 .settings = { \ 926 {R_TIMEBASE, rt, 0xFF}, \ 927 {R_PLLCTLD, rd, 0xFF}, \ 928 {R_PLLCTL1B, r1b_l, 0x0F}, \ 929 {R_PLLCTL9, r9, 0xFF}, \ 930 {R_PLLCTLA, ra, 0xFF}, \ 931 {R_PLLCTLB, rb, 0xFF}, \ 932 {R_PLLCTLC, rc, 0xFF}, \ 933 {R_PLLCTL12, r12, 0xFF}, \ 934 {R_PLLCTL1B, r1b_h, 0xF0}, \ 935 {R_PLLCTLE, re, 0xFF}, \ 936 {R_PLLCTLF, rf, 0xFF}, \ 937 {R_PLLCTL10, r10, 0xFF}, \ 938 {R_PLLCTL11, r11, 0xFF}, \ 939 }, \ 940 } 941 942 static const struct pll_ctl pll_ctls[] = { 943 PLL_CTL(1411200, 0x05, 944 0x39, 0x04, 0x07, 0x02, 0xC3, 0x04, 945 0x1B, 0x10, 0x03, 0x03, 0xD0, 0x02), 946 PLL_CTL(1536000, 0x05, 947 0x1A, 0x04, 0x02, 0x03, 0xE0, 0x01, 948 0x1A, 0x10, 0x02, 0x03, 0xB9, 0x01), 949 PLL_CTL(2822400, 0x0A, 950 0x23, 0x04, 0x07, 0x04, 0xC3, 0x04, 951 0x22, 0x10, 0x05, 0x03, 0x58, 0x02), 952 PLL_CTL(3072000, 0x0B, 953 0x22, 0x04, 0x07, 0x03, 0x48, 0x03, 954 0x1A, 0x10, 0x04, 0x03, 0xB9, 0x01), 955 PLL_CTL(5644800, 0x15, 956 0x23, 0x04, 0x0E, 0x04, 0xC3, 0x04, 957 0x1A, 0x10, 0x08, 0x03, 0xE0, 0x01), 958 PLL_CTL(6144000, 0x17, 959 0x1A, 0x04, 0x08, 0x03, 0xE0, 0x01, 960 0x1A, 0x10, 0x08, 0x03, 0xB9, 0x01), 961 PLL_CTL(12000000, 0x2E, 962 0x1B, 0x04, 0x19, 0x03, 0x00, 0x03, 963 0x2A, 0x10, 0x19, 0x05, 0x98, 0x04), 964 PLL_CTL(19200000, 0x4A, 965 0x13, 0x04, 0x14, 0x03, 0x80, 0x01, 966 0x1A, 0x10, 0x19, 0x03, 0xB9, 0x01), 967 PLL_CTL(22000000, 0x55, 968 0x2A, 0x04, 0x37, 0x05, 0x00, 0x06, 969 0x22, 0x10, 0x26, 0x03, 0x49, 0x02), 970 PLL_CTL(22579200, 0x57, 971 0x22, 0x04, 0x31, 0x03, 0x20, 0x03, 972 0x1A, 0x10, 0x1D, 0x03, 0xB3, 0x01), 973 PLL_CTL(24000000, 0x5D, 974 0x13, 0x04, 0x19, 0x03, 0x80, 0x01, 975 0x1B, 0x10, 0x19, 0x05, 0x4C, 0x02), 976 PLL_CTL(24576000, 0x5F, 977 0x13, 0x04, 0x1D, 0x03, 0xB3, 0x01, 978 0x22, 0x10, 0x40, 0x03, 0x72, 0x03), 979 PLL_CTL(27000000, 0x68, 980 0x22, 0x04, 0x4B, 0x03, 0x00, 0x04, 981 0x2A, 0x10, 0x7D, 0x03, 0x20, 0x06), 982 PLL_CTL(36000000, 0x8C, 983 0x1B, 0x04, 0x4B, 0x03, 0x00, 0x03, 984 0x2A, 0x10, 0x7D, 0x03, 0x98, 0x04), 985 PLL_CTL(25000000, 0x61, 986 0x1B, 0x04, 0x37, 0x03, 0x2B, 0x03, 987 0x1A, 0x10, 0x2A, 0x03, 0x39, 0x02), 988 PLL_CTL(26000000, 0x65, 989 0x23, 0x04, 0x41, 0x05, 0x00, 0x06, 990 0x1A, 0x10, 0x26, 0x03, 0xEF, 0x01), 991 PLL_CTL(12288000, 0x2F, 992 0x1A, 0x04, 0x12, 0x03, 0x1C, 0x02, 993 0x22, 0x10, 0x20, 0x03, 0x72, 0x03), 994 PLL_CTL(40000000, 0x9B, 995 0x22, 0x08, 0x7D, 0x03, 0x80, 0x04, 996 0x23, 0x10, 0x7D, 0x05, 0xE4, 0x06), 997 PLL_CTL(512000, 0x01, 998 0x22, 0x04, 0x01, 0x03, 0xD0, 0x02, 999 0x1B, 0x10, 0x01, 0x04, 0x72, 0x03), 1000 PLL_CTL(705600, 0x02, 1001 0x22, 0x04, 0x02, 0x03, 0x15, 0x04, 1002 0x22, 0x10, 0x01, 0x04, 0x80, 0x02), 1003 PLL_CTL(1024000, 0x03, 1004 0x22, 0x04, 0x02, 0x03, 0xD0, 0x02, 1005 0x1B, 0x10, 0x02, 0x04, 0x72, 0x03), 1006 PLL_CTL(2048000, 0x07, 1007 0x22, 0x04, 0x04, 0x03, 0xD0, 0x02, 1008 0x1B, 0x10, 0x04, 0x04, 0x72, 0x03), 1009 PLL_CTL(2400000, 0x08, 1010 0x22, 0x04, 0x05, 0x03, 0x00, 0x03, 1011 0x23, 0x10, 0x05, 0x05, 0x98, 0x04), 1012 }; 1013 1014 static const struct pll_ctl *get_pll_ctl(int input_freq) 1015 { 1016 int i; 1017 const struct pll_ctl *pll_ctl = NULL; 1018 1019 for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i) 1020 if (input_freq == pll_ctls[i].input_freq) { 1021 pll_ctl = &pll_ctls[i]; 1022 break; 1023 } 1024 1025 return pll_ctl; 1026 } 1027 1028 static int set_pll_ctl_from_input_freq(struct snd_soc_codec *codec, 1029 const int input_freq) 1030 { 1031 int ret; 1032 int i; 1033 const struct pll_ctl *pll_ctl; 1034 1035 pll_ctl = get_pll_ctl(input_freq); 1036 if (!pll_ctl) { 1037 ret = -EINVAL; 1038 dev_err(codec->dev, "No PLL input entry for %d (%d)\n", 1039 input_freq, ret); 1040 return ret; 1041 } 1042 1043 for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) { 1044 ret = snd_soc_update_bits(codec, 1045 pll_ctl->settings[i].addr, 1046 pll_ctl->settings[i].mask, 1047 pll_ctl->settings[i].val); 1048 if (ret < 0) { 1049 dev_err(codec->dev, "Failed to set pll ctl (%d)\n", 1050 ret); 1051 return ret; 1052 } 1053 } 1054 1055 return 0; 1056 } 1057 1058 static int tscs42xx_hw_params(struct snd_pcm_substream *substream, 1059 struct snd_pcm_hw_params *params, 1060 struct snd_soc_dai *codec_dai) 1061 { 1062 struct snd_soc_codec *codec = codec_dai->codec; 1063 int ret; 1064 1065 ret = setup_sample_format(codec, params_format(params)); 1066 if (ret < 0) { 1067 dev_err(codec->dev, "Failed to setup sample format (%d)\n", 1068 ret); 1069 return ret; 1070 } 1071 1072 ret = setup_sample_rate(codec, params_rate(params)); 1073 if (ret < 0) { 1074 dev_err(codec->dev, "Failed to setup sample rate (%d)\n", ret); 1075 return ret; 1076 } 1077 1078 return 0; 1079 } 1080 1081 static inline int dac_mute(struct snd_soc_codec *codec) 1082 { 1083 int ret; 1084 1085 ret = snd_soc_update_bits(codec, R_CNVRTR1, RM_CNVRTR1_DACMU, 1086 RV_CNVRTR1_DACMU_ENABLE); 1087 if (ret < 0) { 1088 dev_err(codec->dev, "Failed to mute DAC (%d)\n", 1089 ret); 1090 return ret; 1091 } 1092 1093 return 0; 1094 } 1095 1096 static inline int dac_unmute(struct snd_soc_codec *codec) 1097 { 1098 int ret; 1099 1100 ret = snd_soc_update_bits(codec, R_CNVRTR1, RM_CNVRTR1_DACMU, 1101 RV_CNVRTR1_DACMU_DISABLE); 1102 if (ret < 0) { 1103 dev_err(codec->dev, "Failed to unmute DAC (%d)\n", 1104 ret); 1105 return ret; 1106 } 1107 1108 return 0; 1109 } 1110 1111 static inline int adc_mute(struct snd_soc_codec *codec) 1112 { 1113 int ret; 1114 1115 ret = snd_soc_update_bits(codec, R_CNVRTR0, RM_CNVRTR0_ADCMU, 1116 RV_CNVRTR0_ADCMU_ENABLE); 1117 if (ret < 0) { 1118 dev_err(codec->dev, "Failed to mute ADC (%d)\n", 1119 ret); 1120 return ret; 1121 } 1122 1123 return 0; 1124 } 1125 1126 static inline int adc_unmute(struct snd_soc_codec *codec) 1127 { 1128 int ret; 1129 1130 ret = snd_soc_update_bits(codec, R_CNVRTR0, RM_CNVRTR0_ADCMU, 1131 RV_CNVRTR0_ADCMU_DISABLE); 1132 if (ret < 0) { 1133 dev_err(codec->dev, "Failed to unmute ADC (%d)\n", 1134 ret); 1135 return ret; 1136 } 1137 1138 return 0; 1139 } 1140 1141 static int tscs42xx_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 1142 { 1143 struct snd_soc_codec *codec = dai->codec; 1144 int ret; 1145 1146 if (mute) 1147 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1148 ret = dac_mute(codec); 1149 else 1150 ret = adc_mute(codec); 1151 else 1152 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1153 ret = dac_unmute(codec); 1154 else 1155 ret = adc_unmute(codec); 1156 1157 return ret; 1158 } 1159 1160 static int tscs42xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 1161 unsigned int fmt) 1162 { 1163 struct snd_soc_codec *codec = codec_dai->codec; 1164 int ret; 1165 1166 /* Slave mode not supported since it needs always-on frame clock */ 1167 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1168 case SND_SOC_DAIFMT_CBM_CFM: 1169 ret = snd_soc_update_bits(codec, R_AIC1, RM_AIC1_MS, 1170 RV_AIC1_MS_MASTER); 1171 if (ret < 0) { 1172 dev_err(codec->dev, 1173 "Failed to set codec DAI master (%d)\n", ret); 1174 return ret; 1175 } 1176 break; 1177 default: 1178 ret = -EINVAL; 1179 dev_err(codec->dev, "Unsupported format (%d)\n", ret); 1180 return ret; 1181 } 1182 1183 return 0; 1184 } 1185 1186 static int tscs42xx_set_dai_bclk_ratio(struct snd_soc_dai *codec_dai, 1187 unsigned int ratio) 1188 { 1189 struct snd_soc_codec *codec = codec_dai->codec; 1190 struct tscs42xx *tscs42xx = snd_soc_codec_get_drvdata(codec); 1191 unsigned int value; 1192 int ret = 0; 1193 1194 switch (ratio) { 1195 case 32: 1196 value = RV_DACSR_DBCM_32; 1197 break; 1198 case 40: 1199 value = RV_DACSR_DBCM_40; 1200 break; 1201 case 64: 1202 value = RV_DACSR_DBCM_64; 1203 break; 1204 default: 1205 dev_err(codec->dev, "Unsupported bclk ratio (%d)\n", ret); 1206 return -EINVAL; 1207 } 1208 1209 ret = snd_soc_update_bits(codec, R_DACSR, RM_DACSR_DBCM, value); 1210 if (ret < 0) { 1211 dev_err(codec->dev, "Failed to set DAC BCLK ratio (%d)\n", ret); 1212 return ret; 1213 } 1214 ret = snd_soc_update_bits(codec, R_ADCSR, RM_ADCSR_ABCM, value); 1215 if (ret < 0) { 1216 dev_err(codec->dev, "Failed to set ADC BCLK ratio (%d)\n", ret); 1217 return ret; 1218 } 1219 1220 mutex_lock(&tscs42xx->audio_params_lock); 1221 1222 tscs42xx->bclk_ratio = ratio; 1223 1224 mutex_unlock(&tscs42xx->audio_params_lock); 1225 1226 return 0; 1227 } 1228 1229 static int tscs42xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1230 int clk_id, unsigned int freq, int dir) 1231 { 1232 struct snd_soc_codec *codec = codec_dai->codec; 1233 int ret; 1234 1235 switch (clk_id) { 1236 case TSCS42XX_PLL_SRC_XTAL: 1237 case TSCS42XX_PLL_SRC_MCLK1: 1238 ret = snd_soc_write(codec, R_PLLREFSEL, 1239 RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 | 1240 RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1); 1241 if (ret < 0) { 1242 dev_err(codec->dev, 1243 "Failed to set pll reference input (%d)\n", 1244 ret); 1245 return ret; 1246 } 1247 break; 1248 case TSCS42XX_PLL_SRC_MCLK2: 1249 ret = snd_soc_write(codec, R_PLLREFSEL, 1250 RV_PLLREFSEL_PLL1_REF_SEL_MCLK2 | 1251 RV_PLLREFSEL_PLL2_REF_SEL_MCLK2); 1252 if (ret < 0) { 1253 dev_err(codec->dev, 1254 "Failed to set PLL reference (%d)\n", ret); 1255 return ret; 1256 } 1257 break; 1258 default: 1259 dev_err(codec->dev, "pll src is unsupported\n"); 1260 return -EINVAL; 1261 } 1262 1263 ret = set_pll_ctl_from_input_freq(codec, freq); 1264 if (ret < 0) { 1265 dev_err(codec->dev, 1266 "Failed to setup PLL input freq (%d)\n", ret); 1267 return ret; 1268 } 1269 1270 return 0; 1271 } 1272 1273 static const struct snd_soc_dai_ops tscs42xx_dai_ops = { 1274 .hw_params = tscs42xx_hw_params, 1275 .mute_stream = tscs42xx_mute_stream, 1276 .set_fmt = tscs42xx_set_dai_fmt, 1277 .set_bclk_ratio = tscs42xx_set_dai_bclk_ratio, 1278 .set_sysclk = tscs42xx_set_dai_sysclk, 1279 }; 1280 1281 static int part_is_valid(struct tscs42xx *tscs42xx) 1282 { 1283 int val; 1284 int ret; 1285 unsigned int reg; 1286 1287 ret = regmap_read(tscs42xx->regmap, R_DEVIDH, ®); 1288 if (ret < 0) 1289 return ret; 1290 1291 val = reg << 8; 1292 ret = regmap_read(tscs42xx->regmap, R_DEVIDL, ®); 1293 if (ret < 0) 1294 return ret; 1295 1296 val |= reg; 1297 1298 switch (val) { 1299 case 0x4A74: 1300 case 0x4A73: 1301 return true; 1302 default: 1303 return false; 1304 }; 1305 } 1306 1307 static struct snd_soc_codec_driver soc_codec_dev_tscs42xx = { 1308 .component_driver = { 1309 .dapm_widgets = tscs42xx_dapm_widgets, 1310 .num_dapm_widgets = ARRAY_SIZE(tscs42xx_dapm_widgets), 1311 .dapm_routes = tscs42xx_intercon, 1312 .num_dapm_routes = ARRAY_SIZE(tscs42xx_intercon), 1313 .controls = tscs42xx_snd_controls, 1314 .num_controls = ARRAY_SIZE(tscs42xx_snd_controls), 1315 }, 1316 }; 1317 1318 static inline void init_coeff_ram_cache(struct tscs42xx *tscs42xx) 1319 { 1320 const u8 norm_addrs[] = { 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, 0x1f, 1321 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45, 0x4a, 1322 0x4f, 0x54, 0x59, 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74, 0x79, 1323 0x7f, 0x80, 0x85, 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3, 0xa8, 1324 0xad, 0xaf, 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9, }; 1325 u8 *coeff_ram = tscs42xx->coeff_ram; 1326 int i; 1327 1328 for (i = 0; i < ARRAY_SIZE(norm_addrs); i++) 1329 coeff_ram[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; 1330 } 1331 1332 #define TSCS42XX_RATES SNDRV_PCM_RATE_8000_96000 1333 1334 #define TSCS42XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1335 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1336 1337 static struct snd_soc_dai_driver tscs42xx_dai = { 1338 .name = "tscs42xx-HiFi", 1339 .playback = { 1340 .stream_name = "HiFi Playback", 1341 .channels_min = 2, 1342 .channels_max = 2, 1343 .rates = TSCS42XX_RATES, 1344 .formats = TSCS42XX_FORMATS,}, 1345 .capture = { 1346 .stream_name = "HiFi Capture", 1347 .channels_min = 2, 1348 .channels_max = 2, 1349 .rates = TSCS42XX_RATES, 1350 .formats = TSCS42XX_FORMATS,}, 1351 .ops = &tscs42xx_dai_ops, 1352 .symmetric_rates = 1, 1353 .symmetric_channels = 1, 1354 .symmetric_samplebits = 1, 1355 }; 1356 1357 static const struct reg_sequence tscs42xx_patch[] = { 1358 { R_AIC2, RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED }, 1359 }; 1360 1361 static int tscs42xx_i2c_probe(struct i2c_client *i2c, 1362 const struct i2c_device_id *id) 1363 { 1364 struct tscs42xx *tscs42xx; 1365 int ret = 0; 1366 1367 tscs42xx = devm_kzalloc(&i2c->dev, sizeof(*tscs42xx), GFP_KERNEL); 1368 if (!tscs42xx) { 1369 ret = -ENOMEM; 1370 dev_err(&i2c->dev, 1371 "Failed to allocate memory for data (%d)\n", ret); 1372 return ret; 1373 } 1374 i2c_set_clientdata(i2c, tscs42xx); 1375 tscs42xx->dev = &i2c->dev; 1376 1377 tscs42xx->regmap = devm_regmap_init_i2c(i2c, &tscs42xx_regmap); 1378 if (IS_ERR(tscs42xx->regmap)) { 1379 ret = PTR_ERR(tscs42xx->regmap); 1380 dev_err(tscs42xx->dev, "Failed to allocate regmap (%d)\n", ret); 1381 return ret; 1382 } 1383 1384 init_coeff_ram_cache(tscs42xx); 1385 1386 ret = part_is_valid(tscs42xx); 1387 if (ret <= 0) { 1388 dev_err(tscs42xx->dev, "No valid part (%d)\n", ret); 1389 ret = -ENODEV; 1390 return ret; 1391 } 1392 1393 ret = regmap_write(tscs42xx->regmap, R_RESET, RV_RESET_ENABLE); 1394 if (ret < 0) { 1395 dev_err(tscs42xx->dev, "Failed to reset device (%d)\n", ret); 1396 return ret; 1397 } 1398 1399 ret = regmap_register_patch(tscs42xx->regmap, tscs42xx_patch, 1400 ARRAY_SIZE(tscs42xx_patch)); 1401 if (ret < 0) { 1402 dev_err(tscs42xx->dev, "Failed to apply patch (%d)\n", ret); 1403 return ret; 1404 } 1405 1406 mutex_init(&tscs42xx->audio_params_lock); 1407 mutex_init(&tscs42xx->coeff_ram_lock); 1408 mutex_init(&tscs42xx->pll_lock); 1409 1410 ret = snd_soc_register_codec(tscs42xx->dev, &soc_codec_dev_tscs42xx, 1411 &tscs42xx_dai, 1); 1412 if (ret) { 1413 dev_err(tscs42xx->dev, "Failed to register codec (%d)\n", ret); 1414 return ret; 1415 } 1416 1417 return 0; 1418 } 1419 1420 static int tscs42xx_i2c_remove(struct i2c_client *client) 1421 { 1422 snd_soc_unregister_codec(&client->dev); 1423 1424 return 0; 1425 } 1426 1427 static const struct i2c_device_id tscs42xx_i2c_id[] = { 1428 { "tscs42A1", 0 }, 1429 { "tscs42A2", 0 }, 1430 { } 1431 }; 1432 MODULE_DEVICE_TABLE(i2c, tscs42xx_i2c_id); 1433 1434 static const struct of_device_id tscs42xx_of_match[] = { 1435 { .compatible = "tempo,tscs42A1", }, 1436 { .compatible = "tempo,tscs42A2", }, 1437 { } 1438 }; 1439 MODULE_DEVICE_TABLE(of, tscs42xx_of_match); 1440 1441 static struct i2c_driver tscs42xx_i2c_driver = { 1442 .driver = { 1443 .name = "tscs42xx", 1444 .owner = THIS_MODULE, 1445 .of_match_table = tscs42xx_of_match, 1446 }, 1447 .probe = tscs42xx_i2c_probe, 1448 .remove = tscs42xx_i2c_remove, 1449 .id_table = tscs42xx_i2c_id, 1450 }; 1451 1452 module_i2c_driver(tscs42xx_i2c_driver); 1453 1454 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com"); 1455 MODULE_DESCRIPTION("ASoC TSCS42xx driver"); 1456 MODULE_LICENSE("GPL"); 1457