1 // SPDX-License-Identifier: GPL-2.0 2 // tscs42xx.c -- TSCS42xx ALSA SoC Audio driver 3 // Copyright 2017 Tempo Semiconductor, Inc. 4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com> 5 6 #include <linux/kernel.h> 7 #include <linux/device.h> 8 #include <linux/regmap.h> 9 #include <linux/i2c.h> 10 #include <linux/err.h> 11 #include <linux/string.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/mutex.h> 15 #include <sound/tlv.h> 16 #include <sound/pcm_params.h> 17 #include <sound/soc.h> 18 #include <sound/soc-dapm.h> 19 20 #include "tscs42xx.h" 21 22 #define COEFF_SIZE 3 23 #define BIQUAD_COEFF_COUNT 5 24 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT) 25 26 #define COEFF_RAM_MAX_ADDR 0xcd 27 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1) 28 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT) 29 30 struct tscs42xx { 31 32 int bclk_ratio; 33 int samplerate; 34 unsigned int blrcm; 35 struct mutex audio_params_lock; 36 37 u8 coeff_ram[COEFF_RAM_SIZE]; 38 bool coeff_ram_synced; 39 struct mutex coeff_ram_lock; 40 41 struct mutex pll_lock; 42 43 struct regmap *regmap; 44 45 struct device *dev; 46 }; 47 48 struct coeff_ram_ctl { 49 unsigned int addr; 50 struct soc_bytes_ext bytes_ext; 51 }; 52 53 static bool tscs42xx_volatile(struct device *dev, unsigned int reg) 54 { 55 switch (reg) { 56 case R_DACCRWRL: 57 case R_DACCRWRM: 58 case R_DACCRWRH: 59 case R_DACCRRDL: 60 case R_DACCRRDM: 61 case R_DACCRRDH: 62 case R_DACCRSTAT: 63 case R_DACCRADDR: 64 case R_PLLCTL0: 65 return true; 66 default: 67 return false; 68 }; 69 } 70 71 static bool tscs42xx_precious(struct device *dev, unsigned int reg) 72 { 73 switch (reg) { 74 case R_DACCRWRL: 75 case R_DACCRWRM: 76 case R_DACCRWRH: 77 case R_DACCRRDL: 78 case R_DACCRRDM: 79 case R_DACCRRDH: 80 return true; 81 default: 82 return false; 83 }; 84 } 85 86 static const struct regmap_config tscs42xx_regmap = { 87 .reg_bits = 8, 88 .val_bits = 8, 89 90 .volatile_reg = tscs42xx_volatile, 91 .precious_reg = tscs42xx_precious, 92 .max_register = R_DACMBCREL3H, 93 94 .cache_type = REGCACHE_RBTREE, 95 .can_multi_write = true, 96 }; 97 98 #define MAX_PLL_LOCK_20MS_WAITS 1 99 static bool plls_locked(struct snd_soc_component *component) 100 { 101 int ret; 102 int count = MAX_PLL_LOCK_20MS_WAITS; 103 104 do { 105 ret = snd_soc_component_read32(component, R_PLLCTL0); 106 if (ret < 0) { 107 dev_err(component->dev, 108 "Failed to read PLL lock status (%d)\n", ret); 109 return false; 110 } else if (ret > 0) { 111 return true; 112 } 113 msleep(20); 114 } while (count--); 115 116 return false; 117 } 118 119 static int sample_rate_to_pll_freq_out(int sample_rate) 120 { 121 switch (sample_rate) { 122 case 11025: 123 case 22050: 124 case 44100: 125 case 88200: 126 return 112896000; 127 case 8000: 128 case 16000: 129 case 32000: 130 case 48000: 131 case 96000: 132 return 122880000; 133 default: 134 return -EINVAL; 135 } 136 } 137 138 #define DACCRSTAT_MAX_TRYS 10 139 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram, 140 unsigned int addr, unsigned int coeff_cnt) 141 { 142 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 143 int cnt; 144 int trys; 145 int ret; 146 147 for (cnt = 0; cnt < coeff_cnt; cnt++, addr++) { 148 149 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) { 150 ret = snd_soc_component_read32(component, R_DACCRSTAT); 151 if (ret < 0) { 152 dev_err(component->dev, 153 "Failed to read stat (%d)\n", ret); 154 return ret; 155 } 156 if (!ret) 157 break; 158 } 159 160 if (trys == DACCRSTAT_MAX_TRYS) { 161 ret = -EIO; 162 dev_err(component->dev, 163 "dac coefficient write error (%d)\n", ret); 164 return ret; 165 } 166 167 ret = regmap_write(tscs42xx->regmap, R_DACCRADDR, addr); 168 if (ret < 0) { 169 dev_err(component->dev, 170 "Failed to write dac ram address (%d)\n", ret); 171 return ret; 172 } 173 174 ret = regmap_bulk_write(tscs42xx->regmap, R_DACCRWRL, 175 &coeff_ram[addr * COEFF_SIZE], 176 COEFF_SIZE); 177 if (ret < 0) { 178 dev_err(component->dev, 179 "Failed to write dac ram (%d)\n", ret); 180 return ret; 181 } 182 } 183 184 return 0; 185 } 186 187 static int power_up_audio_plls(struct snd_soc_component *component) 188 { 189 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 190 int freq_out; 191 int ret; 192 unsigned int mask; 193 unsigned int val; 194 195 freq_out = sample_rate_to_pll_freq_out(tscs42xx->samplerate); 196 switch (freq_out) { 197 case 122880000: /* 48k */ 198 mask = RM_PLLCTL1C_PDB_PLL1; 199 val = RV_PLLCTL1C_PDB_PLL1_ENABLE; 200 break; 201 case 112896000: /* 44.1k */ 202 mask = RM_PLLCTL1C_PDB_PLL2; 203 val = RV_PLLCTL1C_PDB_PLL2_ENABLE; 204 break; 205 default: 206 ret = -EINVAL; 207 dev_err(component->dev, "Unrecognized PLL output freq (%d)\n", ret); 208 return ret; 209 } 210 211 mutex_lock(&tscs42xx->pll_lock); 212 213 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, mask, val); 214 if (ret < 0) { 215 dev_err(component->dev, "Failed to turn PLL on (%d)\n", ret); 216 goto exit; 217 } 218 219 if (!plls_locked(component)) { 220 dev_err(component->dev, "Failed to lock plls\n"); 221 ret = -ENOMSG; 222 goto exit; 223 } 224 225 ret = 0; 226 exit: 227 mutex_unlock(&tscs42xx->pll_lock); 228 229 return ret; 230 } 231 232 static int power_down_audio_plls(struct snd_soc_component *component) 233 { 234 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 235 int ret; 236 237 mutex_lock(&tscs42xx->pll_lock); 238 239 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, 240 RM_PLLCTL1C_PDB_PLL1, 241 RV_PLLCTL1C_PDB_PLL1_DISABLE); 242 if (ret < 0) { 243 dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret); 244 goto exit; 245 } 246 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, 247 RM_PLLCTL1C_PDB_PLL2, 248 RV_PLLCTL1C_PDB_PLL2_DISABLE); 249 if (ret < 0) { 250 dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret); 251 goto exit; 252 } 253 254 ret = 0; 255 exit: 256 mutex_unlock(&tscs42xx->pll_lock); 257 258 return ret; 259 } 260 261 static int coeff_ram_get(struct snd_kcontrol *kcontrol, 262 struct snd_ctl_elem_value *ucontrol) 263 { 264 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 265 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 266 struct coeff_ram_ctl *ctl = 267 (struct coeff_ram_ctl *)kcontrol->private_value; 268 struct soc_bytes_ext *params = &ctl->bytes_ext; 269 270 mutex_lock(&tscs42xx->coeff_ram_lock); 271 272 memcpy(ucontrol->value.bytes.data, 273 &tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], params->max); 274 275 mutex_unlock(&tscs42xx->coeff_ram_lock); 276 277 return 0; 278 } 279 280 static int coeff_ram_put(struct snd_kcontrol *kcontrol, 281 struct snd_ctl_elem_value *ucontrol) 282 { 283 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 284 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 285 struct coeff_ram_ctl *ctl = 286 (struct coeff_ram_ctl *)kcontrol->private_value; 287 struct soc_bytes_ext *params = &ctl->bytes_ext; 288 unsigned int coeff_cnt = params->max / COEFF_SIZE; 289 int ret; 290 291 mutex_lock(&tscs42xx->coeff_ram_lock); 292 293 tscs42xx->coeff_ram_synced = false; 294 295 memcpy(&tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], 296 ucontrol->value.bytes.data, params->max); 297 298 mutex_lock(&tscs42xx->pll_lock); 299 300 if (plls_locked(component)) { 301 ret = write_coeff_ram(component, tscs42xx->coeff_ram, 302 ctl->addr, coeff_cnt); 303 if (ret < 0) { 304 dev_err(component->dev, 305 "Failed to flush coeff ram cache (%d)\n", ret); 306 goto exit; 307 } 308 tscs42xx->coeff_ram_synced = true; 309 } 310 311 ret = 0; 312 exit: 313 mutex_unlock(&tscs42xx->pll_lock); 314 315 mutex_unlock(&tscs42xx->coeff_ram_lock); 316 317 return ret; 318 } 319 320 /* Input L Capture Route */ 321 static char const * const input_select_text[] = { 322 "Line 1", "Line 2", "Line 3", "D2S" 323 }; 324 325 static const struct soc_enum left_input_select_enum = 326 SOC_ENUM_SINGLE(R_INSELL, FB_INSELL, ARRAY_SIZE(input_select_text), 327 input_select_text); 328 329 static const struct snd_kcontrol_new left_input_select = 330 SOC_DAPM_ENUM("LEFT_INPUT_SELECT_ENUM", left_input_select_enum); 331 332 /* Input R Capture Route */ 333 static const struct soc_enum right_input_select_enum = 334 SOC_ENUM_SINGLE(R_INSELR, FB_INSELR, ARRAY_SIZE(input_select_text), 335 input_select_text); 336 337 static const struct snd_kcontrol_new right_input_select = 338 SOC_DAPM_ENUM("RIGHT_INPUT_SELECT_ENUM", right_input_select_enum); 339 340 /* Input Channel Mapping */ 341 static char const * const ch_map_select_text[] = { 342 "Normal", "Left to Right", "Right to Left", "Swap" 343 }; 344 345 static const struct soc_enum ch_map_select_enum = 346 SOC_ENUM_SINGLE(R_AIC2, FB_AIC2_ADCDSEL, ARRAY_SIZE(ch_map_select_text), 347 ch_map_select_text); 348 349 static int dapm_vref_event(struct snd_soc_dapm_widget *w, 350 struct snd_kcontrol *kcontrol, int event) 351 { 352 msleep(20); 353 return 0; 354 } 355 356 static int dapm_micb_event(struct snd_soc_dapm_widget *w, 357 struct snd_kcontrol *kcontrol, int event) 358 { 359 msleep(20); 360 return 0; 361 } 362 363 static int pll_event(struct snd_soc_dapm_widget *w, 364 struct snd_kcontrol *kcontrol, int event) 365 { 366 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 367 int ret; 368 369 if (SND_SOC_DAPM_EVENT_ON(event)) 370 ret = power_up_audio_plls(component); 371 else 372 ret = power_down_audio_plls(component); 373 374 return ret; 375 } 376 377 static int dac_event(struct snd_soc_dapm_widget *w, 378 struct snd_kcontrol *kcontrol, int event) 379 { 380 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 381 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 382 int ret; 383 384 mutex_lock(&tscs42xx->coeff_ram_lock); 385 386 if (tscs42xx->coeff_ram_synced == false) { 387 ret = write_coeff_ram(component, tscs42xx->coeff_ram, 0x00, 388 COEFF_RAM_COEFF_COUNT); 389 if (ret < 0) 390 goto exit; 391 tscs42xx->coeff_ram_synced = true; 392 } 393 394 ret = 0; 395 exit: 396 mutex_unlock(&tscs42xx->coeff_ram_lock); 397 398 return ret; 399 } 400 401 static const struct snd_soc_dapm_widget tscs42xx_dapm_widgets[] = { 402 /* Vref */ 403 SND_SOC_DAPM_SUPPLY_S("Vref", 1, R_PWRM2, FB_PWRM2_VREF, 0, 404 dapm_vref_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 405 406 /* PLL */ 407 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, pll_event, 408 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 409 410 /* Headphone */ 411 SND_SOC_DAPM_DAC_E("DAC L", "HiFi Playback", R_PWRM2, FB_PWRM2_HPL, 0, 412 dac_event, SND_SOC_DAPM_POST_PMU), 413 SND_SOC_DAPM_DAC_E("DAC R", "HiFi Playback", R_PWRM2, FB_PWRM2_HPR, 0, 414 dac_event, SND_SOC_DAPM_POST_PMU), 415 SND_SOC_DAPM_OUTPUT("Headphone L"), 416 SND_SOC_DAPM_OUTPUT("Headphone R"), 417 418 /* Speaker */ 419 SND_SOC_DAPM_DAC_E("ClassD L", "HiFi Playback", 420 R_PWRM2, FB_PWRM2_SPKL, 0, 421 dac_event, SND_SOC_DAPM_POST_PMU), 422 SND_SOC_DAPM_DAC_E("ClassD R", "HiFi Playback", 423 R_PWRM2, FB_PWRM2_SPKR, 0, 424 dac_event, SND_SOC_DAPM_POST_PMU), 425 SND_SOC_DAPM_OUTPUT("Speaker L"), 426 SND_SOC_DAPM_OUTPUT("Speaker R"), 427 428 /* Capture */ 429 SND_SOC_DAPM_PGA("Analog In PGA L", R_PWRM1, FB_PWRM1_PGAL, 0, NULL, 0), 430 SND_SOC_DAPM_PGA("Analog In PGA R", R_PWRM1, FB_PWRM1_PGAR, 0, NULL, 0), 431 SND_SOC_DAPM_PGA("Analog Boost L", R_PWRM1, FB_PWRM1_BSTL, 0, NULL, 0), 432 SND_SOC_DAPM_PGA("Analog Boost R", R_PWRM1, FB_PWRM1_BSTR, 0, NULL, 0), 433 SND_SOC_DAPM_PGA("ADC Mute", R_CNVRTR0, FB_CNVRTR0_HPOR, true, NULL, 0), 434 SND_SOC_DAPM_ADC("ADC L", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCL, 0), 435 SND_SOC_DAPM_ADC("ADC R", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCR, 0), 436 437 /* Capture Input */ 438 SND_SOC_DAPM_MUX("Input L Capture Route", R_PWRM2, 439 FB_PWRM2_INSELL, 0, &left_input_select), 440 SND_SOC_DAPM_MUX("Input R Capture Route", R_PWRM2, 441 FB_PWRM2_INSELR, 0, &right_input_select), 442 443 /* Digital Mic */ 444 SND_SOC_DAPM_SUPPLY_S("Digital Mic Enable", 2, R_DMICCTL, 445 FB_DMICCTL_DMICEN, 0, NULL, 446 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 447 448 /* Analog Mic */ 449 SND_SOC_DAPM_SUPPLY_S("Mic Bias", 2, R_PWRM1, FB_PWRM1_MICB, 450 0, dapm_micb_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 451 452 /* Line In */ 453 SND_SOC_DAPM_INPUT("Line In 1 L"), 454 SND_SOC_DAPM_INPUT("Line In 1 R"), 455 SND_SOC_DAPM_INPUT("Line In 2 L"), 456 SND_SOC_DAPM_INPUT("Line In 2 R"), 457 SND_SOC_DAPM_INPUT("Line In 3 L"), 458 SND_SOC_DAPM_INPUT("Line In 3 R"), 459 }; 460 461 static const struct snd_soc_dapm_route tscs42xx_intercon[] = { 462 {"DAC L", NULL, "PLL"}, 463 {"DAC R", NULL, "PLL"}, 464 {"DAC L", NULL, "Vref"}, 465 {"DAC R", NULL, "Vref"}, 466 {"Headphone L", NULL, "DAC L"}, 467 {"Headphone R", NULL, "DAC R"}, 468 469 {"ClassD L", NULL, "PLL"}, 470 {"ClassD R", NULL, "PLL"}, 471 {"ClassD L", NULL, "Vref"}, 472 {"ClassD R", NULL, "Vref"}, 473 {"Speaker L", NULL, "ClassD L"}, 474 {"Speaker R", NULL, "ClassD R"}, 475 476 {"Input L Capture Route", NULL, "Vref"}, 477 {"Input R Capture Route", NULL, "Vref"}, 478 479 {"Mic Bias", NULL, "Vref"}, 480 481 {"Input L Capture Route", "Line 1", "Line In 1 L"}, 482 {"Input R Capture Route", "Line 1", "Line In 1 R"}, 483 {"Input L Capture Route", "Line 2", "Line In 2 L"}, 484 {"Input R Capture Route", "Line 2", "Line In 2 R"}, 485 {"Input L Capture Route", "Line 3", "Line In 3 L"}, 486 {"Input R Capture Route", "Line 3", "Line In 3 R"}, 487 488 {"Analog In PGA L", NULL, "Input L Capture Route"}, 489 {"Analog In PGA R", NULL, "Input R Capture Route"}, 490 {"Analog Boost L", NULL, "Analog In PGA L"}, 491 {"Analog Boost R", NULL, "Analog In PGA R"}, 492 {"ADC Mute", NULL, "Analog Boost L"}, 493 {"ADC Mute", NULL, "Analog Boost R"}, 494 {"ADC L", NULL, "PLL"}, 495 {"ADC R", NULL, "PLL"}, 496 {"ADC L", NULL, "ADC Mute"}, 497 {"ADC R", NULL, "ADC Mute"}, 498 }; 499 500 /************ 501 * CONTROLS * 502 ************/ 503 504 static char const * const eq_band_enable_text[] = { 505 "Prescale only", 506 "Band1", 507 "Band1:2", 508 "Band1:3", 509 "Band1:4", 510 "Band1:5", 511 "Band1:6", 512 }; 513 514 static char const * const level_detection_text[] = { 515 "Average", 516 "Peak", 517 }; 518 519 static char const * const level_detection_window_text[] = { 520 "512 Samples", 521 "64 Samples", 522 }; 523 524 static char const * const compressor_ratio_text[] = { 525 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1", 526 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1", 527 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1", 528 }; 529 530 static DECLARE_TLV_DB_SCALE(hpvol_scale, -8850, 75, 0); 531 static DECLARE_TLV_DB_SCALE(spkvol_scale, -7725, 75, 0); 532 static DECLARE_TLV_DB_SCALE(dacvol_scale, -9563, 38, 0); 533 static DECLARE_TLV_DB_SCALE(adcvol_scale, -7125, 38, 0); 534 static DECLARE_TLV_DB_SCALE(invol_scale, -1725, 75, 0); 535 static DECLARE_TLV_DB_SCALE(mic_boost_scale, 0, 1000, 0); 536 static DECLARE_TLV_DB_MINMAX(mugain_scale, 0, 4650); 537 static DECLARE_TLV_DB_MINMAX(compth_scale, -9562, 0); 538 539 static const struct soc_enum eq1_band_enable_enum = 540 SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ1_BE, 541 ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text); 542 543 static const struct soc_enum eq2_band_enable_enum = 544 SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ2_BE, 545 ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text); 546 547 static const struct soc_enum cle_level_detection_enum = 548 SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_LVL_MODE, 549 ARRAY_SIZE(level_detection_text), 550 level_detection_text); 551 552 static const struct soc_enum cle_level_detection_window_enum = 553 SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_WINDOWSEL, 554 ARRAY_SIZE(level_detection_window_text), 555 level_detection_window_text); 556 557 static const struct soc_enum mbc_level_detection_enums[] = { 558 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1, 559 ARRAY_SIZE(level_detection_text), 560 level_detection_text), 561 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2, 562 ARRAY_SIZE(level_detection_text), 563 level_detection_text), 564 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3, 565 ARRAY_SIZE(level_detection_text), 566 level_detection_text), 567 }; 568 569 static const struct soc_enum mbc_level_detection_window_enums[] = { 570 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1, 571 ARRAY_SIZE(level_detection_window_text), 572 level_detection_window_text), 573 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2, 574 ARRAY_SIZE(level_detection_window_text), 575 level_detection_window_text), 576 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3, 577 ARRAY_SIZE(level_detection_window_text), 578 level_detection_window_text), 579 }; 580 581 static const struct soc_enum compressor_ratio_enum = 582 SOC_ENUM_SINGLE(R_CMPRAT, FB_CMPRAT, 583 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 584 585 static const struct soc_enum dac_mbc1_compressor_ratio_enum = 586 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT1_RATIO, 587 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 588 589 static const struct soc_enum dac_mbc2_compressor_ratio_enum = 590 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT2_RATIO, 591 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 592 593 static const struct soc_enum dac_mbc3_compressor_ratio_enum = 594 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT3_RATIO, 595 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 596 597 static int bytes_info_ext(struct snd_kcontrol *kcontrol, 598 struct snd_ctl_elem_info *ucontrol) 599 { 600 struct coeff_ram_ctl *ctl = 601 (struct coeff_ram_ctl *)kcontrol->private_value; 602 struct soc_bytes_ext *params = &ctl->bytes_ext; 603 604 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 605 ucontrol->count = params->max; 606 607 return 0; 608 } 609 610 #define COEFF_RAM_CTL(xname, xcount, xaddr) \ 611 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 612 .info = bytes_info_ext, \ 613 .get = coeff_ram_get, .put = coeff_ram_put, \ 614 .private_value = (unsigned long)&(struct coeff_ram_ctl) { \ 615 .addr = xaddr, \ 616 .bytes_ext = {.max = xcount, }, \ 617 } \ 618 } 619 620 static const struct snd_kcontrol_new tscs42xx_snd_controls[] = { 621 /* Volumes */ 622 SOC_DOUBLE_R_TLV("Headphone Playback Volume", R_HPVOLL, R_HPVOLR, 623 FB_HPVOLL, 0x7F, 0, hpvol_scale), 624 SOC_DOUBLE_R_TLV("Speaker Playback Volume", R_SPKVOLL, R_SPKVOLR, 625 FB_SPKVOLL, 0x7F, 0, spkvol_scale), 626 SOC_DOUBLE_R_TLV("Master Playback Volume", R_DACVOLL, R_DACVOLR, 627 FB_DACVOLL, 0xFF, 0, dacvol_scale), 628 SOC_DOUBLE_R_TLV("PCM Capture Volume", R_ADCVOLL, R_ADCVOLR, 629 FB_ADCVOLL, 0xFF, 0, adcvol_scale), 630 SOC_DOUBLE_R_TLV("Master Capture Volume", R_INVOLL, R_INVOLR, 631 FB_INVOLL, 0x3F, 0, invol_scale), 632 633 /* INSEL */ 634 SOC_DOUBLE_R_TLV("Mic Boost Capture Volume", R_INSELL, R_INSELR, 635 FB_INSELL_MICBSTL, FV_INSELL_MICBSTL_30DB, 636 0, mic_boost_scale), 637 638 /* Input Channel Map */ 639 SOC_ENUM("Input Channel Map", ch_map_select_enum), 640 641 /* Coefficient Ram */ 642 COEFF_RAM_CTL("Cascade1L BiQuad1", BIQUAD_SIZE, 0x00), 643 COEFF_RAM_CTL("Cascade1L BiQuad2", BIQUAD_SIZE, 0x05), 644 COEFF_RAM_CTL("Cascade1L BiQuad3", BIQUAD_SIZE, 0x0a), 645 COEFF_RAM_CTL("Cascade1L BiQuad4", BIQUAD_SIZE, 0x0f), 646 COEFF_RAM_CTL("Cascade1L BiQuad5", BIQUAD_SIZE, 0x14), 647 COEFF_RAM_CTL("Cascade1L BiQuad6", BIQUAD_SIZE, 0x19), 648 649 COEFF_RAM_CTL("Cascade1R BiQuad1", BIQUAD_SIZE, 0x20), 650 COEFF_RAM_CTL("Cascade1R BiQuad2", BIQUAD_SIZE, 0x25), 651 COEFF_RAM_CTL("Cascade1R BiQuad3", BIQUAD_SIZE, 0x2a), 652 COEFF_RAM_CTL("Cascade1R BiQuad4", BIQUAD_SIZE, 0x2f), 653 COEFF_RAM_CTL("Cascade1R BiQuad5", BIQUAD_SIZE, 0x34), 654 COEFF_RAM_CTL("Cascade1R BiQuad6", BIQUAD_SIZE, 0x39), 655 656 COEFF_RAM_CTL("Cascade1L Prescale", COEFF_SIZE, 0x1f), 657 COEFF_RAM_CTL("Cascade1R Prescale", COEFF_SIZE, 0x3f), 658 659 COEFF_RAM_CTL("Cascade2L BiQuad1", BIQUAD_SIZE, 0x40), 660 COEFF_RAM_CTL("Cascade2L BiQuad2", BIQUAD_SIZE, 0x45), 661 COEFF_RAM_CTL("Cascade2L BiQuad3", BIQUAD_SIZE, 0x4a), 662 COEFF_RAM_CTL("Cascade2L BiQuad4", BIQUAD_SIZE, 0x4f), 663 COEFF_RAM_CTL("Cascade2L BiQuad5", BIQUAD_SIZE, 0x54), 664 COEFF_RAM_CTL("Cascade2L BiQuad6", BIQUAD_SIZE, 0x59), 665 666 COEFF_RAM_CTL("Cascade2R BiQuad1", BIQUAD_SIZE, 0x60), 667 COEFF_RAM_CTL("Cascade2R BiQuad2", BIQUAD_SIZE, 0x65), 668 COEFF_RAM_CTL("Cascade2R BiQuad3", BIQUAD_SIZE, 0x6a), 669 COEFF_RAM_CTL("Cascade2R BiQuad4", BIQUAD_SIZE, 0x6f), 670 COEFF_RAM_CTL("Cascade2R BiQuad5", BIQUAD_SIZE, 0x74), 671 COEFF_RAM_CTL("Cascade2R BiQuad6", BIQUAD_SIZE, 0x79), 672 673 COEFF_RAM_CTL("Cascade2L Prescale", COEFF_SIZE, 0x5f), 674 COEFF_RAM_CTL("Cascade2R Prescale", COEFF_SIZE, 0x7f), 675 676 COEFF_RAM_CTL("Bass Extraction BiQuad1", BIQUAD_SIZE, 0x80), 677 COEFF_RAM_CTL("Bass Extraction BiQuad2", BIQUAD_SIZE, 0x85), 678 679 COEFF_RAM_CTL("Bass Non Linear Function 1", COEFF_SIZE, 0x8a), 680 COEFF_RAM_CTL("Bass Non Linear Function 2", COEFF_SIZE, 0x8b), 681 682 COEFF_RAM_CTL("Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), 683 684 COEFF_RAM_CTL("Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), 685 686 COEFF_RAM_CTL("Bass Mix", COEFF_SIZE, 0x96), 687 688 COEFF_RAM_CTL("Treb Extraction BiQuad1", BIQUAD_SIZE, 0x97), 689 COEFF_RAM_CTL("Treb Extraction BiQuad2", BIQUAD_SIZE, 0x9c), 690 691 COEFF_RAM_CTL("Treb Non Linear Function 1", COEFF_SIZE, 0xa1), 692 COEFF_RAM_CTL("Treb Non Linear Function 2", COEFF_SIZE, 0xa2), 693 694 COEFF_RAM_CTL("Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), 695 696 COEFF_RAM_CTL("Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), 697 698 COEFF_RAM_CTL("Treb Mix", COEFF_SIZE, 0xad), 699 700 COEFF_RAM_CTL("3D", COEFF_SIZE, 0xae), 701 702 COEFF_RAM_CTL("3D Mix", COEFF_SIZE, 0xaf), 703 704 COEFF_RAM_CTL("MBC1 BiQuad1", BIQUAD_SIZE, 0xb0), 705 COEFF_RAM_CTL("MBC1 BiQuad2", BIQUAD_SIZE, 0xb5), 706 707 COEFF_RAM_CTL("MBC2 BiQuad1", BIQUAD_SIZE, 0xba), 708 COEFF_RAM_CTL("MBC2 BiQuad2", BIQUAD_SIZE, 0xbf), 709 710 COEFF_RAM_CTL("MBC3 BiQuad1", BIQUAD_SIZE, 0xc4), 711 COEFF_RAM_CTL("MBC3 BiQuad2", BIQUAD_SIZE, 0xc9), 712 713 /* EQ */ 714 SOC_SINGLE("EQ1 Switch", R_CONFIG1, FB_CONFIG1_EQ1_EN, 1, 0), 715 SOC_SINGLE("EQ2 Switch", R_CONFIG1, FB_CONFIG1_EQ2_EN, 1, 0), 716 SOC_ENUM("EQ1 Band Enable", eq1_band_enable_enum), 717 SOC_ENUM("EQ2 Band Enable", eq2_band_enable_enum), 718 719 /* CLE */ 720 SOC_ENUM("CLE Level Detect", 721 cle_level_detection_enum), 722 SOC_ENUM("CLE Level Detect Win", 723 cle_level_detection_window_enum), 724 SOC_SINGLE("Expander Switch", 725 R_CLECTL, FB_CLECTL_EXP_EN, 1, 0), 726 SOC_SINGLE("Limiter Switch", 727 R_CLECTL, FB_CLECTL_LIMIT_EN, 1, 0), 728 SOC_SINGLE("Comp Switch", 729 R_CLECTL, FB_CLECTL_COMP_EN, 1, 0), 730 SOC_SINGLE_TLV("CLE Make-Up Gain Playback Volume", 731 R_MUGAIN, FB_MUGAIN_CLEMUG, 0x1f, 0, mugain_scale), 732 SOC_SINGLE_TLV("Comp Thresh Playback Volume", 733 R_COMPTH, FB_COMPTH, 0xff, 0, compth_scale), 734 SOC_ENUM("Comp Ratio", compressor_ratio_enum), 735 SND_SOC_BYTES("Comp Atk Time", R_CATKTCL, 2), 736 737 /* Effects */ 738 SOC_SINGLE("3D Switch", R_FXCTL, FB_FXCTL_3DEN, 1, 0), 739 SOC_SINGLE("Treble Switch", R_FXCTL, FB_FXCTL_TEEN, 1, 0), 740 SOC_SINGLE("Treble Bypass Switch", R_FXCTL, FB_FXCTL_TNLFBYPASS, 1, 0), 741 SOC_SINGLE("Bass Switch", R_FXCTL, FB_FXCTL_BEEN, 1, 0), 742 SOC_SINGLE("Bass Bypass Switch", R_FXCTL, FB_FXCTL_BNLFBYPASS, 1, 0), 743 744 /* MBC */ 745 SOC_SINGLE("MBC Band1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0), 746 SOC_SINGLE("MBC Band2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0), 747 SOC_SINGLE("MBC Band3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0), 748 SOC_ENUM("MBC Band1 Level Detect", 749 mbc_level_detection_enums[0]), 750 SOC_ENUM("MBC Band2 Level Detect", 751 mbc_level_detection_enums[1]), 752 SOC_ENUM("MBC Band3 Level Detect", 753 mbc_level_detection_enums[2]), 754 SOC_ENUM("MBC Band1 Level Detect Win", 755 mbc_level_detection_window_enums[0]), 756 SOC_ENUM("MBC Band2 Level Detect Win", 757 mbc_level_detection_window_enums[1]), 758 SOC_ENUM("MBC Band3 Level Detect Win", 759 mbc_level_detection_window_enums[2]), 760 761 SOC_SINGLE("MBC1 Phase Invert Switch", 762 R_DACMBCMUG1, FB_DACMBCMUG1_PHASE, 1, 0), 763 SOC_SINGLE_TLV("DAC MBC1 Make-Up Gain Playback Volume", 764 R_DACMBCMUG1, FB_DACMBCMUG1_MUGAIN, 0x1f, 0, mugain_scale), 765 SOC_SINGLE_TLV("DAC MBC1 Comp Thresh Playback Volume", 766 R_DACMBCTHR1, FB_DACMBCTHR1_THRESH, 0xff, 0, compth_scale), 767 SOC_ENUM("DAC MBC1 Comp Ratio", 768 dac_mbc1_compressor_ratio_enum), 769 SND_SOC_BYTES("DAC MBC1 Comp Atk Time", R_DACMBCATK1L, 2), 770 SND_SOC_BYTES("DAC MBC1 Comp Rel Time Const", 771 R_DACMBCREL1L, 2), 772 773 SOC_SINGLE("MBC2 Phase Invert Switch", 774 R_DACMBCMUG2, FB_DACMBCMUG2_PHASE, 1, 0), 775 SOC_SINGLE_TLV("DAC MBC2 Make-Up Gain Playback Volume", 776 R_DACMBCMUG2, FB_DACMBCMUG2_MUGAIN, 0x1f, 0, mugain_scale), 777 SOC_SINGLE_TLV("DAC MBC2 Comp Thresh Playback Volume", 778 R_DACMBCTHR2, FB_DACMBCTHR2_THRESH, 0xff, 0, compth_scale), 779 SOC_ENUM("DAC MBC2 Comp Ratio", 780 dac_mbc2_compressor_ratio_enum), 781 SND_SOC_BYTES("DAC MBC2 Comp Atk Time", R_DACMBCATK2L, 2), 782 SND_SOC_BYTES("DAC MBC2 Comp Rel Time Const", 783 R_DACMBCREL2L, 2), 784 785 SOC_SINGLE("MBC3 Phase Invert Switch", 786 R_DACMBCMUG3, FB_DACMBCMUG3_PHASE, 1, 0), 787 SOC_SINGLE_TLV("DAC MBC3 Make-Up Gain Playback Volume", 788 R_DACMBCMUG3, FB_DACMBCMUG3_MUGAIN, 0x1f, 0, mugain_scale), 789 SOC_SINGLE_TLV("DAC MBC3 Comp Thresh Playback Volume", 790 R_DACMBCTHR3, FB_DACMBCTHR3_THRESH, 0xff, 0, compth_scale), 791 SOC_ENUM("DAC MBC3 Comp Ratio", 792 dac_mbc3_compressor_ratio_enum), 793 SND_SOC_BYTES("DAC MBC3 Comp Atk Time", R_DACMBCATK3L, 2), 794 SND_SOC_BYTES("DAC MBC3 Comp Rel Time Const", 795 R_DACMBCREL3L, 2), 796 }; 797 798 static int setup_sample_format(struct snd_soc_component *component, 799 snd_pcm_format_t format) 800 { 801 unsigned int width; 802 int ret; 803 804 switch (format) { 805 case SNDRV_PCM_FORMAT_S16_LE: 806 width = RV_AIC1_WL_16; 807 break; 808 case SNDRV_PCM_FORMAT_S20_3LE: 809 width = RV_AIC1_WL_20; 810 break; 811 case SNDRV_PCM_FORMAT_S24_LE: 812 width = RV_AIC1_WL_24; 813 break; 814 case SNDRV_PCM_FORMAT_S32_LE: 815 width = RV_AIC1_WL_32; 816 break; 817 default: 818 ret = -EINVAL; 819 dev_err(component->dev, "Unsupported format width (%d)\n", ret); 820 return ret; 821 } 822 ret = snd_soc_component_update_bits(component, R_AIC1, RM_AIC1_WL, width); 823 if (ret < 0) { 824 dev_err(component->dev, "Failed to set sample width (%d)\n", ret); 825 return ret; 826 } 827 828 return 0; 829 } 830 831 static int setup_sample_rate(struct snd_soc_component *component, unsigned int rate) 832 { 833 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 834 unsigned int br, bm; 835 int ret; 836 837 switch (rate) { 838 case 8000: 839 br = RV_DACSR_DBR_32; 840 bm = RV_DACSR_DBM_PT25; 841 break; 842 case 16000: 843 br = RV_DACSR_DBR_32; 844 bm = RV_DACSR_DBM_PT5; 845 break; 846 case 24000: 847 br = RV_DACSR_DBR_48; 848 bm = RV_DACSR_DBM_PT5; 849 break; 850 case 32000: 851 br = RV_DACSR_DBR_32; 852 bm = RV_DACSR_DBM_1; 853 break; 854 case 48000: 855 br = RV_DACSR_DBR_48; 856 bm = RV_DACSR_DBM_1; 857 break; 858 case 96000: 859 br = RV_DACSR_DBR_48; 860 bm = RV_DACSR_DBM_2; 861 break; 862 case 11025: 863 br = RV_DACSR_DBR_44_1; 864 bm = RV_DACSR_DBM_PT25; 865 break; 866 case 22050: 867 br = RV_DACSR_DBR_44_1; 868 bm = RV_DACSR_DBM_PT5; 869 break; 870 case 44100: 871 br = RV_DACSR_DBR_44_1; 872 bm = RV_DACSR_DBM_1; 873 break; 874 case 88200: 875 br = RV_DACSR_DBR_44_1; 876 bm = RV_DACSR_DBM_2; 877 break; 878 default: 879 dev_err(component->dev, "Unsupported sample rate %d\n", rate); 880 return -EINVAL; 881 } 882 883 /* DAC and ADC share bit and frame clock */ 884 ret = snd_soc_component_update_bits(component, R_DACSR, RM_DACSR_DBR, br); 885 if (ret < 0) { 886 dev_err(component->dev, "Failed to update register (%d)\n", ret); 887 return ret; 888 } 889 ret = snd_soc_component_update_bits(component, R_DACSR, RM_DACSR_DBM, bm); 890 if (ret < 0) { 891 dev_err(component->dev, "Failed to update register (%d)\n", ret); 892 return ret; 893 } 894 ret = snd_soc_component_update_bits(component, R_ADCSR, RM_DACSR_DBR, br); 895 if (ret < 0) { 896 dev_err(component->dev, "Failed to update register (%d)\n", ret); 897 return ret; 898 } 899 ret = snd_soc_component_update_bits(component, R_ADCSR, RM_DACSR_DBM, bm); 900 if (ret < 0) { 901 dev_err(component->dev, "Failed to update register (%d)\n", ret); 902 return ret; 903 } 904 905 mutex_lock(&tscs42xx->audio_params_lock); 906 907 tscs42xx->samplerate = rate; 908 909 mutex_unlock(&tscs42xx->audio_params_lock); 910 911 return 0; 912 } 913 914 struct reg_setting { 915 unsigned int addr; 916 unsigned int val; 917 unsigned int mask; 918 }; 919 920 #define PLL_REG_SETTINGS_COUNT 13 921 struct pll_ctl { 922 int input_freq; 923 struct reg_setting settings[PLL_REG_SETTINGS_COUNT]; 924 }; 925 926 #define PLL_CTL(f, rt, rd, r1b_l, r9, ra, rb, \ 927 rc, r12, r1b_h, re, rf, r10, r11) \ 928 { \ 929 .input_freq = f, \ 930 .settings = { \ 931 {R_TIMEBASE, rt, 0xFF}, \ 932 {R_PLLCTLD, rd, 0xFF}, \ 933 {R_PLLCTL1B, r1b_l, 0x0F}, \ 934 {R_PLLCTL9, r9, 0xFF}, \ 935 {R_PLLCTLA, ra, 0xFF}, \ 936 {R_PLLCTLB, rb, 0xFF}, \ 937 {R_PLLCTLC, rc, 0xFF}, \ 938 {R_PLLCTL12, r12, 0xFF}, \ 939 {R_PLLCTL1B, r1b_h, 0xF0}, \ 940 {R_PLLCTLE, re, 0xFF}, \ 941 {R_PLLCTLF, rf, 0xFF}, \ 942 {R_PLLCTL10, r10, 0xFF}, \ 943 {R_PLLCTL11, r11, 0xFF}, \ 944 }, \ 945 } 946 947 static const struct pll_ctl pll_ctls[] = { 948 PLL_CTL(1411200, 0x05, 949 0x39, 0x04, 0x07, 0x02, 0xC3, 0x04, 950 0x1B, 0x10, 0x03, 0x03, 0xD0, 0x02), 951 PLL_CTL(1536000, 0x05, 952 0x1A, 0x04, 0x02, 0x03, 0xE0, 0x01, 953 0x1A, 0x10, 0x02, 0x03, 0xB9, 0x01), 954 PLL_CTL(2822400, 0x0A, 955 0x23, 0x04, 0x07, 0x04, 0xC3, 0x04, 956 0x22, 0x10, 0x05, 0x03, 0x58, 0x02), 957 PLL_CTL(3072000, 0x0B, 958 0x22, 0x04, 0x07, 0x03, 0x48, 0x03, 959 0x1A, 0x10, 0x04, 0x03, 0xB9, 0x01), 960 PLL_CTL(5644800, 0x15, 961 0x23, 0x04, 0x0E, 0x04, 0xC3, 0x04, 962 0x1A, 0x10, 0x08, 0x03, 0xE0, 0x01), 963 PLL_CTL(6144000, 0x17, 964 0x1A, 0x04, 0x08, 0x03, 0xE0, 0x01, 965 0x1A, 0x10, 0x08, 0x03, 0xB9, 0x01), 966 PLL_CTL(12000000, 0x2E, 967 0x1B, 0x04, 0x19, 0x03, 0x00, 0x03, 968 0x2A, 0x10, 0x19, 0x05, 0x98, 0x04), 969 PLL_CTL(19200000, 0x4A, 970 0x13, 0x04, 0x14, 0x03, 0x80, 0x01, 971 0x1A, 0x10, 0x19, 0x03, 0xB9, 0x01), 972 PLL_CTL(22000000, 0x55, 973 0x2A, 0x04, 0x37, 0x05, 0x00, 0x06, 974 0x22, 0x10, 0x26, 0x03, 0x49, 0x02), 975 PLL_CTL(22579200, 0x57, 976 0x22, 0x04, 0x31, 0x03, 0x20, 0x03, 977 0x1A, 0x10, 0x1D, 0x03, 0xB3, 0x01), 978 PLL_CTL(24000000, 0x5D, 979 0x13, 0x04, 0x19, 0x03, 0x80, 0x01, 980 0x1B, 0x10, 0x19, 0x05, 0x4C, 0x02), 981 PLL_CTL(24576000, 0x5F, 982 0x13, 0x04, 0x1D, 0x03, 0xB3, 0x01, 983 0x22, 0x10, 0x40, 0x03, 0x72, 0x03), 984 PLL_CTL(27000000, 0x68, 985 0x22, 0x04, 0x4B, 0x03, 0x00, 0x04, 986 0x2A, 0x10, 0x7D, 0x03, 0x20, 0x06), 987 PLL_CTL(36000000, 0x8C, 988 0x1B, 0x04, 0x4B, 0x03, 0x00, 0x03, 989 0x2A, 0x10, 0x7D, 0x03, 0x98, 0x04), 990 PLL_CTL(25000000, 0x61, 991 0x1B, 0x04, 0x37, 0x03, 0x2B, 0x03, 992 0x1A, 0x10, 0x2A, 0x03, 0x39, 0x02), 993 PLL_CTL(26000000, 0x65, 994 0x23, 0x04, 0x41, 0x05, 0x00, 0x06, 995 0x1A, 0x10, 0x26, 0x03, 0xEF, 0x01), 996 PLL_CTL(12288000, 0x2F, 997 0x1A, 0x04, 0x12, 0x03, 0x1C, 0x02, 998 0x22, 0x10, 0x20, 0x03, 0x72, 0x03), 999 PLL_CTL(40000000, 0x9B, 1000 0x22, 0x08, 0x7D, 0x03, 0x80, 0x04, 1001 0x23, 0x10, 0x7D, 0x05, 0xE4, 0x06), 1002 PLL_CTL(512000, 0x01, 1003 0x22, 0x04, 0x01, 0x03, 0xD0, 0x02, 1004 0x1B, 0x10, 0x01, 0x04, 0x72, 0x03), 1005 PLL_CTL(705600, 0x02, 1006 0x22, 0x04, 0x02, 0x03, 0x15, 0x04, 1007 0x22, 0x10, 0x01, 0x04, 0x80, 0x02), 1008 PLL_CTL(1024000, 0x03, 1009 0x22, 0x04, 0x02, 0x03, 0xD0, 0x02, 1010 0x1B, 0x10, 0x02, 0x04, 0x72, 0x03), 1011 PLL_CTL(2048000, 0x07, 1012 0x22, 0x04, 0x04, 0x03, 0xD0, 0x02, 1013 0x1B, 0x10, 0x04, 0x04, 0x72, 0x03), 1014 PLL_CTL(2400000, 0x08, 1015 0x22, 0x04, 0x05, 0x03, 0x00, 0x03, 1016 0x23, 0x10, 0x05, 0x05, 0x98, 0x04), 1017 }; 1018 1019 static const struct pll_ctl *get_pll_ctl(int input_freq) 1020 { 1021 int i; 1022 const struct pll_ctl *pll_ctl = NULL; 1023 1024 for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i) 1025 if (input_freq == pll_ctls[i].input_freq) { 1026 pll_ctl = &pll_ctls[i]; 1027 break; 1028 } 1029 1030 return pll_ctl; 1031 } 1032 1033 static int set_pll_ctl_from_input_freq(struct snd_soc_component *component, 1034 const int input_freq) 1035 { 1036 int ret; 1037 int i; 1038 const struct pll_ctl *pll_ctl; 1039 1040 pll_ctl = get_pll_ctl(input_freq); 1041 if (!pll_ctl) { 1042 ret = -EINVAL; 1043 dev_err(component->dev, "No PLL input entry for %d (%d)\n", 1044 input_freq, ret); 1045 return ret; 1046 } 1047 1048 for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) { 1049 ret = snd_soc_component_update_bits(component, 1050 pll_ctl->settings[i].addr, 1051 pll_ctl->settings[i].mask, 1052 pll_ctl->settings[i].val); 1053 if (ret < 0) { 1054 dev_err(component->dev, "Failed to set pll ctl (%d)\n", 1055 ret); 1056 return ret; 1057 } 1058 } 1059 1060 return 0; 1061 } 1062 1063 static int tscs42xx_hw_params(struct snd_pcm_substream *substream, 1064 struct snd_pcm_hw_params *params, 1065 struct snd_soc_dai *codec_dai) 1066 { 1067 struct snd_soc_component *component = codec_dai->component; 1068 int ret; 1069 1070 ret = setup_sample_format(component, params_format(params)); 1071 if (ret < 0) { 1072 dev_err(component->dev, "Failed to setup sample format (%d)\n", 1073 ret); 1074 return ret; 1075 } 1076 1077 ret = setup_sample_rate(component, params_rate(params)); 1078 if (ret < 0) { 1079 dev_err(component->dev, "Failed to setup sample rate (%d)\n", ret); 1080 return ret; 1081 } 1082 1083 return 0; 1084 } 1085 1086 static inline int dac_mute(struct snd_soc_component *component) 1087 { 1088 int ret; 1089 1090 ret = snd_soc_component_update_bits(component, R_CNVRTR1, RM_CNVRTR1_DACMU, 1091 RV_CNVRTR1_DACMU_ENABLE); 1092 if (ret < 0) { 1093 dev_err(component->dev, "Failed to mute DAC (%d)\n", 1094 ret); 1095 return ret; 1096 } 1097 1098 return 0; 1099 } 1100 1101 static inline int dac_unmute(struct snd_soc_component *component) 1102 { 1103 int ret; 1104 1105 ret = snd_soc_component_update_bits(component, R_CNVRTR1, RM_CNVRTR1_DACMU, 1106 RV_CNVRTR1_DACMU_DISABLE); 1107 if (ret < 0) { 1108 dev_err(component->dev, "Failed to unmute DAC (%d)\n", 1109 ret); 1110 return ret; 1111 } 1112 1113 return 0; 1114 } 1115 1116 static inline int adc_mute(struct snd_soc_component *component) 1117 { 1118 int ret; 1119 1120 ret = snd_soc_component_update_bits(component, R_CNVRTR0, RM_CNVRTR0_ADCMU, 1121 RV_CNVRTR0_ADCMU_ENABLE); 1122 if (ret < 0) { 1123 dev_err(component->dev, "Failed to mute ADC (%d)\n", 1124 ret); 1125 return ret; 1126 } 1127 1128 return 0; 1129 } 1130 1131 static inline int adc_unmute(struct snd_soc_component *component) 1132 { 1133 int ret; 1134 1135 ret = snd_soc_component_update_bits(component, R_CNVRTR0, RM_CNVRTR0_ADCMU, 1136 RV_CNVRTR0_ADCMU_DISABLE); 1137 if (ret < 0) { 1138 dev_err(component->dev, "Failed to unmute ADC (%d)\n", 1139 ret); 1140 return ret; 1141 } 1142 1143 return 0; 1144 } 1145 1146 static int tscs42xx_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 1147 { 1148 struct snd_soc_component *component = dai->component; 1149 int ret; 1150 1151 if (mute) 1152 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1153 ret = dac_mute(component); 1154 else 1155 ret = adc_mute(component); 1156 else 1157 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1158 ret = dac_unmute(component); 1159 else 1160 ret = adc_unmute(component); 1161 1162 return ret; 1163 } 1164 1165 static int tscs42xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 1166 unsigned int fmt) 1167 { 1168 struct snd_soc_component *component = codec_dai->component; 1169 int ret; 1170 1171 /* Slave mode not supported since it needs always-on frame clock */ 1172 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1173 case SND_SOC_DAIFMT_CBM_CFM: 1174 ret = snd_soc_component_update_bits(component, R_AIC1, RM_AIC1_MS, 1175 RV_AIC1_MS_MASTER); 1176 if (ret < 0) { 1177 dev_err(component->dev, 1178 "Failed to set codec DAI master (%d)\n", ret); 1179 return ret; 1180 } 1181 break; 1182 default: 1183 ret = -EINVAL; 1184 dev_err(component->dev, "Unsupported format (%d)\n", ret); 1185 return ret; 1186 } 1187 1188 return 0; 1189 } 1190 1191 static int tscs42xx_set_dai_bclk_ratio(struct snd_soc_dai *codec_dai, 1192 unsigned int ratio) 1193 { 1194 struct snd_soc_component *component = codec_dai->component; 1195 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 1196 unsigned int value; 1197 int ret = 0; 1198 1199 switch (ratio) { 1200 case 32: 1201 value = RV_DACSR_DBCM_32; 1202 break; 1203 case 40: 1204 value = RV_DACSR_DBCM_40; 1205 break; 1206 case 64: 1207 value = RV_DACSR_DBCM_64; 1208 break; 1209 default: 1210 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret); 1211 return -EINVAL; 1212 } 1213 1214 ret = snd_soc_component_update_bits(component, R_DACSR, RM_DACSR_DBCM, value); 1215 if (ret < 0) { 1216 dev_err(component->dev, "Failed to set DAC BCLK ratio (%d)\n", ret); 1217 return ret; 1218 } 1219 ret = snd_soc_component_update_bits(component, R_ADCSR, RM_ADCSR_ABCM, value); 1220 if (ret < 0) { 1221 dev_err(component->dev, "Failed to set ADC BCLK ratio (%d)\n", ret); 1222 return ret; 1223 } 1224 1225 mutex_lock(&tscs42xx->audio_params_lock); 1226 1227 tscs42xx->bclk_ratio = ratio; 1228 1229 mutex_unlock(&tscs42xx->audio_params_lock); 1230 1231 return 0; 1232 } 1233 1234 static int tscs42xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1235 int clk_id, unsigned int freq, int dir) 1236 { 1237 struct snd_soc_component *component = codec_dai->component; 1238 int ret; 1239 1240 switch (clk_id) { 1241 case TSCS42XX_PLL_SRC_XTAL: 1242 case TSCS42XX_PLL_SRC_MCLK1: 1243 ret = snd_soc_component_write(component, R_PLLREFSEL, 1244 RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 | 1245 RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1); 1246 if (ret < 0) { 1247 dev_err(component->dev, 1248 "Failed to set pll reference input (%d)\n", 1249 ret); 1250 return ret; 1251 } 1252 break; 1253 case TSCS42XX_PLL_SRC_MCLK2: 1254 ret = snd_soc_component_write(component, R_PLLREFSEL, 1255 RV_PLLREFSEL_PLL1_REF_SEL_MCLK2 | 1256 RV_PLLREFSEL_PLL2_REF_SEL_MCLK2); 1257 if (ret < 0) { 1258 dev_err(component->dev, 1259 "Failed to set PLL reference (%d)\n", ret); 1260 return ret; 1261 } 1262 break; 1263 default: 1264 dev_err(component->dev, "pll src is unsupported\n"); 1265 return -EINVAL; 1266 } 1267 1268 ret = set_pll_ctl_from_input_freq(component, freq); 1269 if (ret < 0) { 1270 dev_err(component->dev, 1271 "Failed to setup PLL input freq (%d)\n", ret); 1272 return ret; 1273 } 1274 1275 return 0; 1276 } 1277 1278 static const struct snd_soc_dai_ops tscs42xx_dai_ops = { 1279 .hw_params = tscs42xx_hw_params, 1280 .mute_stream = tscs42xx_mute_stream, 1281 .set_fmt = tscs42xx_set_dai_fmt, 1282 .set_bclk_ratio = tscs42xx_set_dai_bclk_ratio, 1283 .set_sysclk = tscs42xx_set_dai_sysclk, 1284 }; 1285 1286 static int part_is_valid(struct tscs42xx *tscs42xx) 1287 { 1288 int val; 1289 int ret; 1290 unsigned int reg; 1291 1292 ret = regmap_read(tscs42xx->regmap, R_DEVIDH, ®); 1293 if (ret < 0) 1294 return ret; 1295 1296 val = reg << 8; 1297 ret = regmap_read(tscs42xx->regmap, R_DEVIDL, ®); 1298 if (ret < 0) 1299 return ret; 1300 1301 val |= reg; 1302 1303 switch (val) { 1304 case 0x4A74: 1305 case 0x4A73: 1306 return true; 1307 default: 1308 return false; 1309 }; 1310 } 1311 1312 static struct snd_soc_component_driver soc_codec_dev_tscs42xx = { 1313 .dapm_widgets = tscs42xx_dapm_widgets, 1314 .num_dapm_widgets = ARRAY_SIZE(tscs42xx_dapm_widgets), 1315 .dapm_routes = tscs42xx_intercon, 1316 .num_dapm_routes = ARRAY_SIZE(tscs42xx_intercon), 1317 .controls = tscs42xx_snd_controls, 1318 .num_controls = ARRAY_SIZE(tscs42xx_snd_controls), 1319 .idle_bias_on = 1, 1320 .use_pmdown_time = 1, 1321 .endianness = 1, 1322 .non_legacy_dai_naming = 1, 1323 }; 1324 1325 static inline void init_coeff_ram_cache(struct tscs42xx *tscs42xx) 1326 { 1327 static const u8 norm_addrs[] = { 1328 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, 0x1f, 0x20, 0x25, 0x2a, 1329 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45, 0x4a, 0x4f, 0x54, 0x59, 1330 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74, 0x79, 0x7f, 0x80, 0x85, 1331 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3, 0xa8, 0xad, 0xaf, 0xb0, 1332 0xb5, 0xba, 0xbf, 0xc4, 0xc9, 1333 }; 1334 u8 *coeff_ram = tscs42xx->coeff_ram; 1335 int i; 1336 1337 for (i = 0; i < ARRAY_SIZE(norm_addrs); i++) 1338 coeff_ram[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; 1339 } 1340 1341 #define TSCS42XX_RATES SNDRV_PCM_RATE_8000_96000 1342 1343 #define TSCS42XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1344 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1345 1346 static struct snd_soc_dai_driver tscs42xx_dai = { 1347 .name = "tscs42xx-HiFi", 1348 .playback = { 1349 .stream_name = "HiFi Playback", 1350 .channels_min = 2, 1351 .channels_max = 2, 1352 .rates = TSCS42XX_RATES, 1353 .formats = TSCS42XX_FORMATS,}, 1354 .capture = { 1355 .stream_name = "HiFi Capture", 1356 .channels_min = 2, 1357 .channels_max = 2, 1358 .rates = TSCS42XX_RATES, 1359 .formats = TSCS42XX_FORMATS,}, 1360 .ops = &tscs42xx_dai_ops, 1361 .symmetric_rates = 1, 1362 .symmetric_channels = 1, 1363 .symmetric_samplebits = 1, 1364 }; 1365 1366 static const struct reg_sequence tscs42xx_patch[] = { 1367 { R_AIC2, RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED }, 1368 }; 1369 1370 static int tscs42xx_i2c_probe(struct i2c_client *i2c, 1371 const struct i2c_device_id *id) 1372 { 1373 struct tscs42xx *tscs42xx; 1374 int ret = 0; 1375 1376 tscs42xx = devm_kzalloc(&i2c->dev, sizeof(*tscs42xx), GFP_KERNEL); 1377 if (!tscs42xx) { 1378 ret = -ENOMEM; 1379 dev_err(&i2c->dev, 1380 "Failed to allocate memory for data (%d)\n", ret); 1381 return ret; 1382 } 1383 i2c_set_clientdata(i2c, tscs42xx); 1384 tscs42xx->dev = &i2c->dev; 1385 1386 tscs42xx->regmap = devm_regmap_init_i2c(i2c, &tscs42xx_regmap); 1387 if (IS_ERR(tscs42xx->regmap)) { 1388 ret = PTR_ERR(tscs42xx->regmap); 1389 dev_err(tscs42xx->dev, "Failed to allocate regmap (%d)\n", ret); 1390 return ret; 1391 } 1392 1393 init_coeff_ram_cache(tscs42xx); 1394 1395 ret = part_is_valid(tscs42xx); 1396 if (ret <= 0) { 1397 dev_err(tscs42xx->dev, "No valid part (%d)\n", ret); 1398 ret = -ENODEV; 1399 return ret; 1400 } 1401 1402 ret = regmap_write(tscs42xx->regmap, R_RESET, RV_RESET_ENABLE); 1403 if (ret < 0) { 1404 dev_err(tscs42xx->dev, "Failed to reset device (%d)\n", ret); 1405 return ret; 1406 } 1407 1408 ret = regmap_register_patch(tscs42xx->regmap, tscs42xx_patch, 1409 ARRAY_SIZE(tscs42xx_patch)); 1410 if (ret < 0) { 1411 dev_err(tscs42xx->dev, "Failed to apply patch (%d)\n", ret); 1412 return ret; 1413 } 1414 1415 mutex_init(&tscs42xx->audio_params_lock); 1416 mutex_init(&tscs42xx->coeff_ram_lock); 1417 mutex_init(&tscs42xx->pll_lock); 1418 1419 ret = devm_snd_soc_register_component(tscs42xx->dev, &soc_codec_dev_tscs42xx, 1420 &tscs42xx_dai, 1); 1421 if (ret) { 1422 dev_err(tscs42xx->dev, "Failed to register codec (%d)\n", ret); 1423 return ret; 1424 } 1425 1426 return 0; 1427 } 1428 1429 static const struct i2c_device_id tscs42xx_i2c_id[] = { 1430 { "tscs42A1", 0 }, 1431 { "tscs42A2", 0 }, 1432 { } 1433 }; 1434 MODULE_DEVICE_TABLE(i2c, tscs42xx_i2c_id); 1435 1436 static const struct of_device_id tscs42xx_of_match[] = { 1437 { .compatible = "tempo,tscs42A1", }, 1438 { .compatible = "tempo,tscs42A2", }, 1439 { } 1440 }; 1441 MODULE_DEVICE_TABLE(of, tscs42xx_of_match); 1442 1443 static struct i2c_driver tscs42xx_i2c_driver = { 1444 .driver = { 1445 .name = "tscs42xx", 1446 .of_match_table = tscs42xx_of_match, 1447 }, 1448 .probe = tscs42xx_i2c_probe, 1449 .id_table = tscs42xx_i2c_id, 1450 }; 1451 1452 module_i2c_driver(tscs42xx_i2c_driver); 1453 1454 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com"); 1455 MODULE_DESCRIPTION("ASoC TSCS42xx driver"); 1456 MODULE_LICENSE("GPL"); 1457