1 /* 2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver 3 * 4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com> 5 * 6 * Copyright: (C) 2009 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 */ 23 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/init.h> 27 #include <linux/delay.h> 28 #include <linux/pm.h> 29 #include <linux/i2c.h> 30 #include <linux/platform_device.h> 31 #include <linux/interrupt.h> 32 #include <linux/gpio.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/slab.h> 35 #include <sound/core.h> 36 #include <sound/pcm.h> 37 #include <sound/pcm_params.h> 38 #include <sound/soc.h> 39 #include <sound/initval.h> 40 #include <sound/tlv.h> 41 42 #include <sound/tlv320dac33-plat.h> 43 #include "tlv320dac33.h" 44 45 /* 46 * The internal FIFO is 24576 bytes long 47 * It can be configured to hold 16bit or 24bit samples 48 * In 16bit configuration the FIFO can hold 6144 stereo samples 49 * In 24bit configuration the FIFO can hold 4096 stereo samples 50 */ 51 #define DAC33_FIFO_SIZE_16BIT 6144 52 #define DAC33_FIFO_SIZE_24BIT 4096 53 #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */ 54 55 #define BURST_BASEFREQ_HZ 49152000 56 57 #define SAMPLES_TO_US(rate, samples) \ 58 (1000000000 / ((rate * 1000) / samples)) 59 60 #define US_TO_SAMPLES(rate, us) \ 61 (rate / (1000000 / (us < 1000000 ? us : 1000000))) 62 63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \ 64 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate))) 65 66 static void dac33_calculate_times(struct snd_pcm_substream *substream); 67 static int dac33_prepare_chip(struct snd_pcm_substream *substream); 68 69 enum dac33_state { 70 DAC33_IDLE = 0, 71 DAC33_PREFILL, 72 DAC33_PLAYBACK, 73 DAC33_FLUSH, 74 }; 75 76 enum dac33_fifo_modes { 77 DAC33_FIFO_BYPASS = 0, 78 DAC33_FIFO_MODE1, 79 DAC33_FIFO_MODE7, 80 DAC33_FIFO_LAST_MODE, 81 }; 82 83 #define DAC33_NUM_SUPPLIES 3 84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = { 85 "AVDD", 86 "DVDD", 87 "IOVDD", 88 }; 89 90 struct tlv320dac33_priv { 91 struct mutex mutex; 92 struct workqueue_struct *dac33_wq; 93 struct work_struct work; 94 struct snd_soc_codec *codec; 95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES]; 96 struct snd_pcm_substream *substream; 97 int power_gpio; 98 int chip_power; 99 int irq; 100 unsigned int refclk; 101 102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ 103 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ 104 unsigned int fifo_size; /* Size of the FIFO in samples */ 105 unsigned int nsample; /* burst read amount from host */ 106 int mode1_latency; /* latency caused by the i2c writes in 107 * us */ 108 u8 burst_bclkdiv; /* BCLK divider value in burst mode */ 109 unsigned int burst_rate; /* Interface speed in Burst modes */ 110 111 int keep_bclk; /* Keep the BCLK continuously running 112 * in FIFO modes */ 113 spinlock_t lock; 114 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */ 115 unsigned long long t_stamp2; /* calculate the FIFO caused delay */ 116 117 unsigned int mode1_us_burst; /* Time to burst read n number of 118 * samples */ 119 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */ 120 121 unsigned int uthr; 122 123 enum dac33_state state; 124 enum snd_soc_control_type control_type; 125 void *control_data; 126 }; 127 128 static const u8 dac33_reg[DAC33_CACHEREGNUM] = { 129 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */ 130 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */ 131 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */ 132 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */ 133 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */ 134 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */ 135 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */ 136 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */ 137 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */ 138 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */ 139 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */ 140 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */ 141 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */ 142 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */ 143 0x00, 0x00, /* 0x38 - 0x39 */ 144 /* Registers 0x3a - 0x3f are reserved */ 145 0x00, 0x00, /* 0x3a - 0x3b */ 146 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */ 147 148 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */ 149 0x00, 0x80, /* 0x44 - 0x45 */ 150 /* Registers 0x46 - 0x47 are reserved */ 151 0x80, 0x80, /* 0x46 - 0x47 */ 152 153 0x80, 0x00, 0x00, /* 0x48 - 0x4a */ 154 /* Registers 0x4b - 0x7c are reserved */ 155 0x00, /* 0x4b */ 156 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */ 157 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */ 158 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */ 159 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */ 160 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */ 161 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */ 162 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */ 163 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */ 164 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */ 165 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */ 166 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */ 167 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */ 168 0x00, /* 0x7c */ 169 170 0xda, 0x33, 0x03, /* 0x7d - 0x7f */ 171 }; 172 173 /* Register read and write */ 174 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec, 175 unsigned reg) 176 { 177 u8 *cache = codec->reg_cache; 178 if (reg >= DAC33_CACHEREGNUM) 179 return 0; 180 181 return cache[reg]; 182 } 183 184 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec, 185 u8 reg, u8 value) 186 { 187 u8 *cache = codec->reg_cache; 188 if (reg >= DAC33_CACHEREGNUM) 189 return; 190 191 cache[reg] = value; 192 } 193 194 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg, 195 u8 *value) 196 { 197 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 198 int val, ret = 0; 199 200 *value = reg & 0xff; 201 202 /* If powered off, return the cached value */ 203 if (dac33->chip_power) { 204 val = i2c_smbus_read_byte_data(codec->control_data, value[0]); 205 if (val < 0) { 206 dev_err(codec->dev, "Read failed (%d)\n", val); 207 value[0] = dac33_read_reg_cache(codec, reg); 208 ret = val; 209 } else { 210 value[0] = val; 211 dac33_write_reg_cache(codec, reg, val); 212 } 213 } else { 214 value[0] = dac33_read_reg_cache(codec, reg); 215 } 216 217 return ret; 218 } 219 220 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg, 221 unsigned int value) 222 { 223 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 224 u8 data[2]; 225 int ret = 0; 226 227 /* 228 * data is 229 * D15..D8 dac33 register offset 230 * D7...D0 register data 231 */ 232 data[0] = reg & 0xff; 233 data[1] = value & 0xff; 234 235 dac33_write_reg_cache(codec, data[0], data[1]); 236 if (dac33->chip_power) { 237 ret = codec->hw_write(codec->control_data, data, 2); 238 if (ret != 2) 239 dev_err(codec->dev, "Write failed (%d)\n", ret); 240 else 241 ret = 0; 242 } 243 244 return ret; 245 } 246 247 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg, 248 unsigned int value) 249 { 250 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 251 int ret; 252 253 mutex_lock(&dac33->mutex); 254 ret = dac33_write(codec, reg, value); 255 mutex_unlock(&dac33->mutex); 256 257 return ret; 258 } 259 260 #define DAC33_I2C_ADDR_AUTOINC 0x80 261 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg, 262 unsigned int value) 263 { 264 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 265 u8 data[3]; 266 int ret = 0; 267 268 /* 269 * data is 270 * D23..D16 dac33 register offset 271 * D15..D8 register data MSB 272 * D7...D0 register data LSB 273 */ 274 data[0] = reg & 0xff; 275 data[1] = (value >> 8) & 0xff; 276 data[2] = value & 0xff; 277 278 dac33_write_reg_cache(codec, data[0], data[1]); 279 dac33_write_reg_cache(codec, data[0] + 1, data[2]); 280 281 if (dac33->chip_power) { 282 /* We need to set autoincrement mode for 16 bit writes */ 283 data[0] |= DAC33_I2C_ADDR_AUTOINC; 284 ret = codec->hw_write(codec->control_data, data, 3); 285 if (ret != 3) 286 dev_err(codec->dev, "Write failed (%d)\n", ret); 287 else 288 ret = 0; 289 } 290 291 return ret; 292 } 293 294 static void dac33_init_chip(struct snd_soc_codec *codec) 295 { 296 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 297 298 if (unlikely(!dac33->chip_power)) 299 return; 300 301 /* A : DAC sample rate Fsref/1.5 */ 302 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); 303 /* B : DAC src=normal, not muted */ 304 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT | 305 DAC33_DACSRCL_LEFT); 306 /* C : (defaults) */ 307 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00); 308 309 /* 73 : volume soft stepping control, 310 clock source = internal osc (?) */ 311 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); 312 313 /* Restore only selected registers (gains mostly) */ 314 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL, 315 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL)); 316 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL, 317 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL)); 318 319 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL, 320 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL)); 321 dac33_write(codec, DAC33_LINER_TO_RLO_VOL, 322 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL)); 323 324 dac33_write(codec, DAC33_OUT_AMP_CTRL, 325 dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL)); 326 327 } 328 329 static inline int dac33_read_id(struct snd_soc_codec *codec) 330 { 331 int i, ret = 0; 332 u8 reg; 333 334 for (i = 0; i < 3; i++) { 335 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, ®); 336 if (ret < 0) 337 break; 338 } 339 340 return ret; 341 } 342 343 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power) 344 { 345 u8 reg; 346 347 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); 348 if (power) 349 reg |= DAC33_PDNALLB; 350 else 351 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB | 352 DAC33_DACRPDNB | DAC33_DACLPDNB); 353 dac33_write(codec, DAC33_PWR_CTRL, reg); 354 } 355 356 static inline void dac33_disable_digital(struct snd_soc_codec *codec) 357 { 358 u8 reg; 359 360 /* Stop the DAI clock */ 361 reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 362 reg &= ~DAC33_BCLKON; 363 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg); 364 365 /* Power down the Oscillator, and DACs */ 366 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); 367 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB); 368 dac33_write(codec, DAC33_PWR_CTRL, reg); 369 } 370 371 static int dac33_hard_power(struct snd_soc_codec *codec, int power) 372 { 373 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 374 int ret = 0; 375 376 mutex_lock(&dac33->mutex); 377 378 /* Safety check */ 379 if (unlikely(power == dac33->chip_power)) { 380 dev_dbg(codec->dev, "Trying to set the same power state: %s\n", 381 power ? "ON" : "OFF"); 382 goto exit; 383 } 384 385 if (power) { 386 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies), 387 dac33->supplies); 388 if (ret != 0) { 389 dev_err(codec->dev, 390 "Failed to enable supplies: %d\n", ret); 391 goto exit; 392 } 393 394 if (dac33->power_gpio >= 0) 395 gpio_set_value(dac33->power_gpio, 1); 396 397 dac33->chip_power = 1; 398 } else { 399 dac33_soft_power(codec, 0); 400 if (dac33->power_gpio >= 0) 401 gpio_set_value(dac33->power_gpio, 0); 402 403 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), 404 dac33->supplies); 405 if (ret != 0) { 406 dev_err(codec->dev, 407 "Failed to disable supplies: %d\n", ret); 408 goto exit; 409 } 410 411 dac33->chip_power = 0; 412 } 413 414 exit: 415 mutex_unlock(&dac33->mutex); 416 return ret; 417 } 418 419 static int dac33_playback_event(struct snd_soc_dapm_widget *w, 420 struct snd_kcontrol *kcontrol, int event) 421 { 422 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec); 423 424 switch (event) { 425 case SND_SOC_DAPM_PRE_PMU: 426 if (likely(dac33->substream)) { 427 dac33_calculate_times(dac33->substream); 428 dac33_prepare_chip(dac33->substream); 429 } 430 break; 431 case SND_SOC_DAPM_POST_PMD: 432 dac33_disable_digital(w->codec); 433 break; 434 } 435 return 0; 436 } 437 438 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, 439 struct snd_ctl_elem_value *ucontrol) 440 { 441 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 442 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 443 444 ucontrol->value.integer.value[0] = dac33->fifo_mode; 445 446 return 0; 447 } 448 449 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol, 450 struct snd_ctl_elem_value *ucontrol) 451 { 452 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 453 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 454 int ret = 0; 455 456 if (dac33->fifo_mode == ucontrol->value.integer.value[0]) 457 return 0; 458 /* Do not allow changes while stream is running*/ 459 if (codec->active) 460 return -EPERM; 461 462 if (ucontrol->value.integer.value[0] < 0 || 463 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE) 464 ret = -EINVAL; 465 else 466 dac33->fifo_mode = ucontrol->value.integer.value[0]; 467 468 return ret; 469 } 470 471 /* Codec operation modes */ 472 static const char *dac33_fifo_mode_texts[] = { 473 "Bypass", "Mode 1", "Mode 7" 474 }; 475 476 static const struct soc_enum dac33_fifo_mode_enum = 477 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts), 478 dac33_fifo_mode_texts); 479 480 /* L/R Line Output Gain */ 481 static const char *lr_lineout_gain_texts[] = { 482 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB", 483 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB", 484 }; 485 486 static const struct soc_enum l_lineout_gain_enum = 487 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0, 488 ARRAY_SIZE(lr_lineout_gain_texts), 489 lr_lineout_gain_texts); 490 491 static const struct soc_enum r_lineout_gain_enum = 492 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0, 493 ARRAY_SIZE(lr_lineout_gain_texts), 494 lr_lineout_gain_texts); 495 496 /* 497 * DACL/R digital volume control: 498 * from 0 dB to -63.5 in 0.5 dB steps 499 * Need to be inverted later on: 500 * 0x00 == 0 dB 501 * 0x7f == -63.5 dB 502 */ 503 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0); 504 505 static const struct snd_kcontrol_new dac33_snd_controls[] = { 506 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume", 507 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 508 0, 0x7f, 1, dac_digivol_tlv), 509 SOC_DOUBLE_R("DAC Digital Playback Switch", 510 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1), 511 SOC_DOUBLE_R("Line to Line Out Volume", 512 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1), 513 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum), 514 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum), 515 }; 516 517 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = { 518 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum, 519 dac33_get_fifo_mode, dac33_set_fifo_mode), 520 }; 521 522 /* Analog bypass */ 523 static const struct snd_kcontrol_new dac33_dapm_abypassl_control = 524 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); 525 526 static const struct snd_kcontrol_new dac33_dapm_abypassr_control = 527 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1); 528 529 /* LOP L/R invert selection */ 530 static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"}; 531 532 static const struct soc_enum dac33_left_lom_enum = 533 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 3, 534 ARRAY_SIZE(dac33_lr_lom_texts), 535 dac33_lr_lom_texts); 536 537 static const struct snd_kcontrol_new dac33_dapm_left_lom_control = 538 SOC_DAPM_ENUM("Route", dac33_left_lom_enum); 539 540 static const struct soc_enum dac33_right_lom_enum = 541 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 2, 542 ARRAY_SIZE(dac33_lr_lom_texts), 543 dac33_lr_lom_texts); 544 545 static const struct snd_kcontrol_new dac33_dapm_right_lom_control = 546 SOC_DAPM_ENUM("Route", dac33_right_lom_enum); 547 548 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { 549 SND_SOC_DAPM_OUTPUT("LEFT_LO"), 550 SND_SOC_DAPM_OUTPUT("RIGHT_LO"), 551 552 SND_SOC_DAPM_INPUT("LINEL"), 553 SND_SOC_DAPM_INPUT("LINER"), 554 555 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), 556 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), 557 558 /* Analog bypass */ 559 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0, 560 &dac33_dapm_abypassl_control), 561 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, 562 &dac33_dapm_abypassr_control), 563 564 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0, 565 &dac33_dapm_left_lom_control), 566 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0, 567 &dac33_dapm_right_lom_control), 568 /* 569 * For DAPM path, when only the anlog bypass path is enabled, and the 570 * LOP inverted from the corresponding DAC side. 571 * This is needed, so we can attach the DAC power supply in this case. 572 */ 573 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 574 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 575 576 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier", 577 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), 578 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier", 579 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), 580 581 SND_SOC_DAPM_SUPPLY("Left DAC Power", 582 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0), 583 SND_SOC_DAPM_SUPPLY("Right DAC Power", 584 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0), 585 586 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event), 587 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event), 588 }; 589 590 static const struct snd_soc_dapm_route audio_map[] = { 591 /* Analog bypass */ 592 {"Analog Left Bypass", "Switch", "LINEL"}, 593 {"Analog Right Bypass", "Switch", "LINER"}, 594 595 {"Output Left Amplifier", NULL, "DACL"}, 596 {"Output Right Amplifier", NULL, "DACR"}, 597 598 {"Left Bypass PGA", NULL, "Analog Left Bypass"}, 599 {"Right Bypass PGA", NULL, "Analog Right Bypass"}, 600 601 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"}, 602 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"}, 603 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"}, 604 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"}, 605 606 {"Output Left Amplifier", NULL, "Left LOM Inverted From"}, 607 {"Output Right Amplifier", NULL, "Right LOM Inverted From"}, 608 609 {"DACL", NULL, "Left DAC Power"}, 610 {"DACR", NULL, "Right DAC Power"}, 611 612 {"Left Bypass PGA", NULL, "Left DAC Power"}, 613 {"Right Bypass PGA", NULL, "Right DAC Power"}, 614 615 /* output */ 616 {"LEFT_LO", NULL, "Output Left Amplifier"}, 617 {"RIGHT_LO", NULL, "Output Right Amplifier"}, 618 }; 619 620 static int dac33_add_widgets(struct snd_soc_codec *codec) 621 { 622 struct snd_soc_dapm_context *dapm = &codec->dapm; 623 624 snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets, 625 ARRAY_SIZE(dac33_dapm_widgets)); 626 /* set up audio path interconnects */ 627 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); 628 629 return 0; 630 } 631 632 static int dac33_set_bias_level(struct snd_soc_codec *codec, 633 enum snd_soc_bias_level level) 634 { 635 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 636 int ret; 637 638 switch (level) { 639 case SND_SOC_BIAS_ON: 640 if (!dac33->substream) 641 dac33_soft_power(codec, 1); 642 break; 643 case SND_SOC_BIAS_PREPARE: 644 break; 645 case SND_SOC_BIAS_STANDBY: 646 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 647 /* Coming from OFF, switch on the codec */ 648 ret = dac33_hard_power(codec, 1); 649 if (ret != 0) 650 return ret; 651 652 dac33_init_chip(codec); 653 } 654 break; 655 case SND_SOC_BIAS_OFF: 656 /* Do not power off, when the codec is already off */ 657 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) 658 return 0; 659 ret = dac33_hard_power(codec, 0); 660 if (ret != 0) 661 return ret; 662 break; 663 } 664 codec->dapm.bias_level = level; 665 666 return 0; 667 } 668 669 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33) 670 { 671 struct snd_soc_codec *codec = dac33->codec; 672 unsigned int delay; 673 674 switch (dac33->fifo_mode) { 675 case DAC33_FIFO_MODE1: 676 dac33_write16(codec, DAC33_NSAMPLE_MSB, 677 DAC33_THRREG(dac33->nsample)); 678 679 /* Take the timestamps */ 680 spin_lock_irq(&dac33->lock); 681 dac33->t_stamp2 = ktime_to_us(ktime_get()); 682 dac33->t_stamp1 = dac33->t_stamp2; 683 spin_unlock_irq(&dac33->lock); 684 685 dac33_write16(codec, DAC33_PREFILL_MSB, 686 DAC33_THRREG(dac33->alarm_threshold)); 687 /* Enable Alarm Threshold IRQ with a delay */ 688 delay = SAMPLES_TO_US(dac33->burst_rate, 689 dac33->alarm_threshold) + 1000; 690 usleep_range(delay, delay + 500); 691 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT); 692 break; 693 case DAC33_FIFO_MODE7: 694 /* Take the timestamp */ 695 spin_lock_irq(&dac33->lock); 696 dac33->t_stamp1 = ktime_to_us(ktime_get()); 697 /* Move back the timestamp with drain time */ 698 dac33->t_stamp1 -= dac33->mode7_us_to_lthr; 699 spin_unlock_irq(&dac33->lock); 700 701 dac33_write16(codec, DAC33_PREFILL_MSB, 702 DAC33_THRREG(DAC33_MODE7_MARGIN)); 703 704 /* Enable Upper Threshold IRQ */ 705 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT); 706 break; 707 default: 708 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 709 dac33->fifo_mode); 710 break; 711 } 712 } 713 714 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33) 715 { 716 struct snd_soc_codec *codec = dac33->codec; 717 718 switch (dac33->fifo_mode) { 719 case DAC33_FIFO_MODE1: 720 /* Take the timestamp */ 721 spin_lock_irq(&dac33->lock); 722 dac33->t_stamp2 = ktime_to_us(ktime_get()); 723 spin_unlock_irq(&dac33->lock); 724 725 dac33_write16(codec, DAC33_NSAMPLE_MSB, 726 DAC33_THRREG(dac33->nsample)); 727 break; 728 case DAC33_FIFO_MODE7: 729 /* At the moment we are not using interrupts in mode7 */ 730 break; 731 default: 732 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 733 dac33->fifo_mode); 734 break; 735 } 736 } 737 738 static void dac33_work(struct work_struct *work) 739 { 740 struct snd_soc_codec *codec; 741 struct tlv320dac33_priv *dac33; 742 u8 reg; 743 744 dac33 = container_of(work, struct tlv320dac33_priv, work); 745 codec = dac33->codec; 746 747 mutex_lock(&dac33->mutex); 748 switch (dac33->state) { 749 case DAC33_PREFILL: 750 dac33->state = DAC33_PLAYBACK; 751 dac33_prefill_handler(dac33); 752 break; 753 case DAC33_PLAYBACK: 754 dac33_playback_handler(dac33); 755 break; 756 case DAC33_IDLE: 757 break; 758 case DAC33_FLUSH: 759 dac33->state = DAC33_IDLE; 760 /* Mask all interrupts from dac33 */ 761 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0); 762 763 /* flush fifo */ 764 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); 765 reg |= DAC33_FIFOFLUSH; 766 dac33_write(codec, DAC33_FIFO_CTRL_A, reg); 767 break; 768 } 769 mutex_unlock(&dac33->mutex); 770 } 771 772 static irqreturn_t dac33_interrupt_handler(int irq, void *dev) 773 { 774 struct snd_soc_codec *codec = dev; 775 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 776 777 spin_lock(&dac33->lock); 778 dac33->t_stamp1 = ktime_to_us(ktime_get()); 779 spin_unlock(&dac33->lock); 780 781 /* Do not schedule the workqueue in Mode7 */ 782 if (dac33->fifo_mode != DAC33_FIFO_MODE7) 783 queue_work(dac33->dac33_wq, &dac33->work); 784 785 return IRQ_HANDLED; 786 } 787 788 static void dac33_oscwait(struct snd_soc_codec *codec) 789 { 790 int timeout = 60; 791 u8 reg; 792 793 do { 794 usleep_range(1000, 2000); 795 dac33_read(codec, DAC33_INT_OSC_STATUS, ®); 796 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--); 797 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) 798 dev_err(codec->dev, 799 "internal oscillator calibration failed\n"); 800 } 801 802 static int dac33_startup(struct snd_pcm_substream *substream, 803 struct snd_soc_dai *dai) 804 { 805 struct snd_soc_pcm_runtime *rtd = substream->private_data; 806 struct snd_soc_codec *codec = rtd->codec; 807 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 808 809 /* Stream started, save the substream pointer */ 810 dac33->substream = substream; 811 812 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24); 813 814 return 0; 815 } 816 817 static void dac33_shutdown(struct snd_pcm_substream *substream, 818 struct snd_soc_dai *dai) 819 { 820 struct snd_soc_pcm_runtime *rtd = substream->private_data; 821 struct snd_soc_codec *codec = rtd->codec; 822 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 823 824 dac33->substream = NULL; 825 } 826 827 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \ 828 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample) 829 static int dac33_hw_params(struct snd_pcm_substream *substream, 830 struct snd_pcm_hw_params *params, 831 struct snd_soc_dai *dai) 832 { 833 struct snd_soc_pcm_runtime *rtd = substream->private_data; 834 struct snd_soc_codec *codec = rtd->codec; 835 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 836 837 /* Check parameters for validity */ 838 switch (params_rate(params)) { 839 case 44100: 840 case 48000: 841 break; 842 default: 843 dev_err(codec->dev, "unsupported rate %d\n", 844 params_rate(params)); 845 return -EINVAL; 846 } 847 848 switch (params_format(params)) { 849 case SNDRV_PCM_FORMAT_S16_LE: 850 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT; 851 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32); 852 break; 853 case SNDRV_PCM_FORMAT_S32_LE: 854 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT; 855 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64); 856 break; 857 default: 858 dev_err(codec->dev, "unsupported format %d\n", 859 params_format(params)); 860 return -EINVAL; 861 } 862 863 return 0; 864 } 865 866 #define CALC_OSCSET(rate, refclk) ( \ 867 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000) 868 #define CALC_RATIOSET(rate, refclk) ( \ 869 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000) 870 871 /* 872 * tlv320dac33 is strict on the sequence of the register writes, if the register 873 * writes happens in different order, than dac33 might end up in unknown state. 874 * Use the known, working sequence of register writes to initialize the dac33. 875 */ 876 static int dac33_prepare_chip(struct snd_pcm_substream *substream) 877 { 878 struct snd_soc_pcm_runtime *rtd = substream->private_data; 879 struct snd_soc_codec *codec = rtd->codec; 880 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 881 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; 882 u8 aictrl_a, aictrl_b, fifoctrl_a; 883 884 switch (substream->runtime->rate) { 885 case 44100: 886 case 48000: 887 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk); 888 ratioset = CALC_RATIOSET(substream->runtime->rate, 889 dac33->refclk); 890 break; 891 default: 892 dev_err(codec->dev, "unsupported rate %d\n", 893 substream->runtime->rate); 894 return -EINVAL; 895 } 896 897 898 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); 899 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK); 900 /* Read FIFO control A, and clear FIFO flush bit */ 901 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); 902 fifoctrl_a &= ~DAC33_FIFOFLUSH; 903 904 fifoctrl_a &= ~DAC33_WIDTH; 905 switch (substream->runtime->format) { 906 case SNDRV_PCM_FORMAT_S16_LE: 907 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); 908 fifoctrl_a |= DAC33_WIDTH; 909 break; 910 case SNDRV_PCM_FORMAT_S32_LE: 911 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24); 912 break; 913 default: 914 dev_err(codec->dev, "unsupported format %d\n", 915 substream->runtime->format); 916 return -EINVAL; 917 } 918 919 mutex_lock(&dac33->mutex); 920 921 if (!dac33->chip_power) { 922 /* 923 * Chip is not powered yet. 924 * Do the init in the dac33_set_bias_level later. 925 */ 926 mutex_unlock(&dac33->mutex); 927 return 0; 928 } 929 930 dac33_soft_power(codec, 0); 931 dac33_soft_power(codec, 1); 932 933 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); 934 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp); 935 936 /* Write registers 0x08 and 0x09 (MSB, LSB) */ 937 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset); 938 939 /* calib time: 128 is a nice number ;) */ 940 dac33_write(codec, DAC33_CALIB_TIME, 128); 941 942 /* adjustment treshold & step */ 943 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) | 944 DAC33_ADJSTEP(1)); 945 946 /* div=4 / gain=1 / div */ 947 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4)); 948 949 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); 950 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB; 951 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl); 952 953 dac33_oscwait(codec); 954 955 if (dac33->fifo_mode) { 956 /* Generic for all FIFO modes */ 957 /* 50-51 : ASRC Control registers */ 958 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1)); 959 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */ 960 961 /* Write registers 0x34 and 0x35 (MSB, LSB) */ 962 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset); 963 964 /* Set interrupts to high active */ 965 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH); 966 } else { 967 /* FIFO bypass mode */ 968 /* 50-51 : ASRC Control registers */ 969 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP); 970 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */ 971 } 972 973 /* Interrupt behaviour configuration */ 974 switch (dac33->fifo_mode) { 975 case DAC33_FIFO_MODE1: 976 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B, 977 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); 978 break; 979 case DAC33_FIFO_MODE7: 980 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A, 981 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL)); 982 break; 983 default: 984 /* in FIFO bypass mode, the interrupts are not used */ 985 break; 986 } 987 988 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 989 990 switch (dac33->fifo_mode) { 991 case DAC33_FIFO_MODE1: 992 /* 993 * For mode1: 994 * Disable the FIFO bypass (Enable the use of FIFO) 995 * Select nSample mode 996 * BCLK is only running when data is needed by DAC33 997 */ 998 fifoctrl_a &= ~DAC33_FBYPAS; 999 fifoctrl_a &= ~DAC33_FAUTO; 1000 if (dac33->keep_bclk) 1001 aictrl_b |= DAC33_BCLKON; 1002 else 1003 aictrl_b &= ~DAC33_BCLKON; 1004 break; 1005 case DAC33_FIFO_MODE7: 1006 /* 1007 * For mode1: 1008 * Disable the FIFO bypass (Enable the use of FIFO) 1009 * Select Threshold mode 1010 * BCLK is only running when data is needed by DAC33 1011 */ 1012 fifoctrl_a &= ~DAC33_FBYPAS; 1013 fifoctrl_a |= DAC33_FAUTO; 1014 if (dac33->keep_bclk) 1015 aictrl_b |= DAC33_BCLKON; 1016 else 1017 aictrl_b &= ~DAC33_BCLKON; 1018 break; 1019 default: 1020 /* 1021 * For FIFO bypass mode: 1022 * Enable the FIFO bypass (Disable the FIFO use) 1023 * Set the BCLK as continous 1024 */ 1025 fifoctrl_a |= DAC33_FBYPAS; 1026 aictrl_b |= DAC33_BCLKON; 1027 break; 1028 } 1029 1030 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a); 1031 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 1032 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); 1033 1034 /* 1035 * BCLK divide ratio 1036 * 0: 1.5 1037 * 1: 1 1038 * 2: 2 1039 * ... 1040 * 254: 254 1041 * 255: 255 1042 */ 1043 if (dac33->fifo_mode) 1044 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 1045 dac33->burst_bclkdiv); 1046 else 1047 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) 1048 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32); 1049 else 1050 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16); 1051 1052 switch (dac33->fifo_mode) { 1053 case DAC33_FIFO_MODE1: 1054 dac33_write16(codec, DAC33_ATHR_MSB, 1055 DAC33_THRREG(dac33->alarm_threshold)); 1056 break; 1057 case DAC33_FIFO_MODE7: 1058 /* 1059 * Configure the threshold levels, and leave 10 sample space 1060 * at the bottom, and also at the top of the FIFO 1061 */ 1062 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr)); 1063 dac33_write16(codec, DAC33_LTHR_MSB, 1064 DAC33_THRREG(DAC33_MODE7_MARGIN)); 1065 break; 1066 default: 1067 break; 1068 } 1069 1070 mutex_unlock(&dac33->mutex); 1071 1072 return 0; 1073 } 1074 1075 static void dac33_calculate_times(struct snd_pcm_substream *substream) 1076 { 1077 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1078 struct snd_soc_codec *codec = rtd->codec; 1079 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1080 unsigned int period_size = substream->runtime->period_size; 1081 unsigned int rate = substream->runtime->rate; 1082 unsigned int nsample_limit; 1083 1084 /* In bypass mode we don't need to calculate */ 1085 if (!dac33->fifo_mode) 1086 return; 1087 1088 switch (dac33->fifo_mode) { 1089 case DAC33_FIFO_MODE1: 1090 /* Number of samples under i2c latency */ 1091 dac33->alarm_threshold = US_TO_SAMPLES(rate, 1092 dac33->mode1_latency); 1093 nsample_limit = dac33->fifo_size - dac33->alarm_threshold; 1094 1095 if (period_size <= dac33->alarm_threshold) 1096 /* 1097 * Configure nSamaple to number of periods, 1098 * which covers the latency requironment. 1099 */ 1100 dac33->nsample = period_size * 1101 ((dac33->alarm_threshold / period_size) + 1102 (dac33->alarm_threshold % period_size ? 1103 1 : 0)); 1104 else if (period_size > nsample_limit) 1105 dac33->nsample = nsample_limit; 1106 else 1107 dac33->nsample = period_size; 1108 1109 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, 1110 dac33->nsample); 1111 dac33->t_stamp1 = 0; 1112 dac33->t_stamp2 = 0; 1113 break; 1114 case DAC33_FIFO_MODE7: 1115 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate, 1116 dac33->burst_rate) + 9; 1117 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN)) 1118 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN; 1119 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10)) 1120 dac33->uthr = (DAC33_MODE7_MARGIN + 10); 1121 1122 dac33->mode7_us_to_lthr = 1123 SAMPLES_TO_US(substream->runtime->rate, 1124 dac33->uthr - DAC33_MODE7_MARGIN + 1); 1125 dac33->t_stamp1 = 0; 1126 break; 1127 default: 1128 break; 1129 } 1130 1131 } 1132 1133 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 1134 struct snd_soc_dai *dai) 1135 { 1136 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1137 struct snd_soc_codec *codec = rtd->codec; 1138 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1139 int ret = 0; 1140 1141 switch (cmd) { 1142 case SNDRV_PCM_TRIGGER_START: 1143 case SNDRV_PCM_TRIGGER_RESUME: 1144 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1145 if (dac33->fifo_mode) { 1146 dac33->state = DAC33_PREFILL; 1147 queue_work(dac33->dac33_wq, &dac33->work); 1148 } 1149 break; 1150 case SNDRV_PCM_TRIGGER_STOP: 1151 case SNDRV_PCM_TRIGGER_SUSPEND: 1152 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1153 if (dac33->fifo_mode) { 1154 dac33->state = DAC33_FLUSH; 1155 queue_work(dac33->dac33_wq, &dac33->work); 1156 } 1157 break; 1158 default: 1159 ret = -EINVAL; 1160 } 1161 1162 return ret; 1163 } 1164 1165 static snd_pcm_sframes_t dac33_dai_delay( 1166 struct snd_pcm_substream *substream, 1167 struct snd_soc_dai *dai) 1168 { 1169 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1170 struct snd_soc_codec *codec = rtd->codec; 1171 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1172 unsigned long long t0, t1, t_now; 1173 unsigned int time_delta, uthr; 1174 int samples_out, samples_in, samples; 1175 snd_pcm_sframes_t delay = 0; 1176 1177 switch (dac33->fifo_mode) { 1178 case DAC33_FIFO_BYPASS: 1179 break; 1180 case DAC33_FIFO_MODE1: 1181 spin_lock(&dac33->lock); 1182 t0 = dac33->t_stamp1; 1183 t1 = dac33->t_stamp2; 1184 spin_unlock(&dac33->lock); 1185 t_now = ktime_to_us(ktime_get()); 1186 1187 /* We have not started to fill the FIFO yet, delay is 0 */ 1188 if (!t1) 1189 goto out; 1190 1191 if (t0 > t1) { 1192 /* 1193 * Phase 1: 1194 * After Alarm threshold, and before nSample write 1195 */ 1196 time_delta = t_now - t0; 1197 samples_out = time_delta ? US_TO_SAMPLES( 1198 substream->runtime->rate, 1199 time_delta) : 0; 1200 1201 if (likely(dac33->alarm_threshold > samples_out)) 1202 delay = dac33->alarm_threshold - samples_out; 1203 else 1204 delay = 0; 1205 } else if ((t_now - t1) <= dac33->mode1_us_burst) { 1206 /* 1207 * Phase 2: 1208 * After nSample write (during burst operation) 1209 */ 1210 time_delta = t_now - t0; 1211 samples_out = time_delta ? US_TO_SAMPLES( 1212 substream->runtime->rate, 1213 time_delta) : 0; 1214 1215 time_delta = t_now - t1; 1216 samples_in = time_delta ? US_TO_SAMPLES( 1217 dac33->burst_rate, 1218 time_delta) : 0; 1219 1220 samples = dac33->alarm_threshold; 1221 samples += (samples_in - samples_out); 1222 1223 if (likely(samples > 0)) 1224 delay = samples; 1225 else 1226 delay = 0; 1227 } else { 1228 /* 1229 * Phase 3: 1230 * After burst operation, before next alarm threshold 1231 */ 1232 time_delta = t_now - t0; 1233 samples_out = time_delta ? US_TO_SAMPLES( 1234 substream->runtime->rate, 1235 time_delta) : 0; 1236 1237 samples_in = dac33->nsample; 1238 samples = dac33->alarm_threshold; 1239 samples += (samples_in - samples_out); 1240 1241 if (likely(samples > 0)) 1242 delay = samples > dac33->fifo_size ? 1243 dac33->fifo_size : samples; 1244 else 1245 delay = 0; 1246 } 1247 break; 1248 case DAC33_FIFO_MODE7: 1249 spin_lock(&dac33->lock); 1250 t0 = dac33->t_stamp1; 1251 uthr = dac33->uthr; 1252 spin_unlock(&dac33->lock); 1253 t_now = ktime_to_us(ktime_get()); 1254 1255 /* We have not started to fill the FIFO yet, delay is 0 */ 1256 if (!t0) 1257 goto out; 1258 1259 if (t_now <= t0) { 1260 /* 1261 * Either the timestamps are messed or equal. Report 1262 * maximum delay 1263 */ 1264 delay = uthr; 1265 goto out; 1266 } 1267 1268 time_delta = t_now - t0; 1269 if (time_delta <= dac33->mode7_us_to_lthr) { 1270 /* 1271 * Phase 1: 1272 * After burst (draining phase) 1273 */ 1274 samples_out = US_TO_SAMPLES( 1275 substream->runtime->rate, 1276 time_delta); 1277 1278 if (likely(uthr > samples_out)) 1279 delay = uthr - samples_out; 1280 else 1281 delay = 0; 1282 } else { 1283 /* 1284 * Phase 2: 1285 * During burst operation 1286 */ 1287 time_delta = time_delta - dac33->mode7_us_to_lthr; 1288 1289 samples_out = US_TO_SAMPLES( 1290 substream->runtime->rate, 1291 time_delta); 1292 samples_in = US_TO_SAMPLES( 1293 dac33->burst_rate, 1294 time_delta); 1295 delay = DAC33_MODE7_MARGIN + samples_in - samples_out; 1296 1297 if (unlikely(delay > uthr)) 1298 delay = uthr; 1299 } 1300 break; 1301 default: 1302 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 1303 dac33->fifo_mode); 1304 break; 1305 } 1306 out: 1307 return delay; 1308 } 1309 1310 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1311 int clk_id, unsigned int freq, int dir) 1312 { 1313 struct snd_soc_codec *codec = codec_dai->codec; 1314 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1315 u8 ioc_reg, asrcb_reg; 1316 1317 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); 1318 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B); 1319 switch (clk_id) { 1320 case TLV320DAC33_MCLK: 1321 ioc_reg |= DAC33_REFSEL; 1322 asrcb_reg |= DAC33_SRCREFSEL; 1323 break; 1324 case TLV320DAC33_SLEEPCLK: 1325 ioc_reg &= ~DAC33_REFSEL; 1326 asrcb_reg &= ~DAC33_SRCREFSEL; 1327 break; 1328 default: 1329 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id); 1330 break; 1331 } 1332 dac33->refclk = freq; 1333 1334 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg); 1335 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg); 1336 1337 return 0; 1338 } 1339 1340 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai, 1341 unsigned int fmt) 1342 { 1343 struct snd_soc_codec *codec = codec_dai->codec; 1344 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1345 u8 aictrl_a, aictrl_b; 1346 1347 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); 1348 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 1349 /* set master/slave audio interface */ 1350 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1351 case SND_SOC_DAIFMT_CBM_CFM: 1352 /* Codec Master */ 1353 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK); 1354 break; 1355 case SND_SOC_DAIFMT_CBS_CFS: 1356 /* Codec Slave */ 1357 if (dac33->fifo_mode) { 1358 dev_err(codec->dev, "FIFO mode requires master mode\n"); 1359 return -EINVAL; 1360 } else 1361 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK); 1362 break; 1363 default: 1364 return -EINVAL; 1365 } 1366 1367 aictrl_a &= ~DAC33_AFMT_MASK; 1368 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1369 case SND_SOC_DAIFMT_I2S: 1370 aictrl_a |= DAC33_AFMT_I2S; 1371 break; 1372 case SND_SOC_DAIFMT_DSP_A: 1373 aictrl_a |= DAC33_AFMT_DSP; 1374 aictrl_b &= ~DAC33_DATA_DELAY_MASK; 1375 aictrl_b |= DAC33_DATA_DELAY(0); 1376 break; 1377 case SND_SOC_DAIFMT_RIGHT_J: 1378 aictrl_a |= DAC33_AFMT_RIGHT_J; 1379 break; 1380 case SND_SOC_DAIFMT_LEFT_J: 1381 aictrl_a |= DAC33_AFMT_LEFT_J; 1382 break; 1383 default: 1384 dev_err(codec->dev, "Unsupported format (%u)\n", 1385 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1386 return -EINVAL; 1387 } 1388 1389 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 1390 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); 1391 1392 return 0; 1393 } 1394 1395 static int dac33_soc_probe(struct snd_soc_codec *codec) 1396 { 1397 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1398 int ret = 0; 1399 1400 codec->control_data = dac33->control_data; 1401 codec->hw_write = (hw_write_t) i2c_master_send; 1402 codec->dapm.idle_bias_off = 1; 1403 dac33->codec = codec; 1404 1405 /* Read the tlv320dac33 ID registers */ 1406 ret = dac33_hard_power(codec, 1); 1407 if (ret != 0) { 1408 dev_err(codec->dev, "Failed to power up codec: %d\n", ret); 1409 goto err_power; 1410 } 1411 ret = dac33_read_id(codec); 1412 dac33_hard_power(codec, 0); 1413 1414 if (ret < 0) { 1415 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret); 1416 ret = -ENODEV; 1417 goto err_power; 1418 } 1419 1420 /* Check if the IRQ number is valid and request it */ 1421 if (dac33->irq >= 0) { 1422 ret = request_irq(dac33->irq, dac33_interrupt_handler, 1423 IRQF_TRIGGER_RISING | IRQF_DISABLED, 1424 codec->name, codec); 1425 if (ret < 0) { 1426 dev_err(codec->dev, "Could not request IRQ%d (%d)\n", 1427 dac33->irq, ret); 1428 dac33->irq = -1; 1429 } 1430 if (dac33->irq != -1) { 1431 /* Setup work queue */ 1432 dac33->dac33_wq = 1433 create_singlethread_workqueue("tlv320dac33"); 1434 if (dac33->dac33_wq == NULL) { 1435 free_irq(dac33->irq, codec); 1436 return -ENOMEM; 1437 } 1438 1439 INIT_WORK(&dac33->work, dac33_work); 1440 } 1441 } 1442 1443 snd_soc_add_controls(codec, dac33_snd_controls, 1444 ARRAY_SIZE(dac33_snd_controls)); 1445 /* Only add the FIFO controls, if we have valid IRQ number */ 1446 if (dac33->irq >= 0) 1447 snd_soc_add_controls(codec, dac33_mode_snd_controls, 1448 ARRAY_SIZE(dac33_mode_snd_controls)); 1449 1450 dac33_add_widgets(codec); 1451 1452 err_power: 1453 return ret; 1454 } 1455 1456 static int dac33_soc_remove(struct snd_soc_codec *codec) 1457 { 1458 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1459 1460 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF); 1461 1462 if (dac33->irq >= 0) { 1463 free_irq(dac33->irq, dac33->codec); 1464 destroy_workqueue(dac33->dac33_wq); 1465 } 1466 return 0; 1467 } 1468 1469 static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state) 1470 { 1471 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF); 1472 1473 return 0; 1474 } 1475 1476 static int dac33_soc_resume(struct snd_soc_codec *codec) 1477 { 1478 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1479 1480 return 0; 1481 } 1482 1483 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = { 1484 .read = dac33_read_reg_cache, 1485 .write = dac33_write_locked, 1486 .set_bias_level = dac33_set_bias_level, 1487 .reg_cache_size = ARRAY_SIZE(dac33_reg), 1488 .reg_word_size = sizeof(u8), 1489 .reg_cache_default = dac33_reg, 1490 .probe = dac33_soc_probe, 1491 .remove = dac33_soc_remove, 1492 .suspend = dac33_soc_suspend, 1493 .resume = dac33_soc_resume, 1494 }; 1495 1496 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ 1497 SNDRV_PCM_RATE_48000) 1498 #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 1499 1500 static struct snd_soc_dai_ops dac33_dai_ops = { 1501 .startup = dac33_startup, 1502 .shutdown = dac33_shutdown, 1503 .hw_params = dac33_hw_params, 1504 .trigger = dac33_pcm_trigger, 1505 .delay = dac33_dai_delay, 1506 .set_sysclk = dac33_set_dai_sysclk, 1507 .set_fmt = dac33_set_dai_fmt, 1508 }; 1509 1510 static struct snd_soc_dai_driver dac33_dai = { 1511 .name = "tlv320dac33-hifi", 1512 .playback = { 1513 .stream_name = "Playback", 1514 .channels_min = 2, 1515 .channels_max = 2, 1516 .rates = DAC33_RATES, 1517 .formats = DAC33_FORMATS,}, 1518 .ops = &dac33_dai_ops, 1519 }; 1520 1521 static int __devinit dac33_i2c_probe(struct i2c_client *client, 1522 const struct i2c_device_id *id) 1523 { 1524 struct tlv320dac33_platform_data *pdata; 1525 struct tlv320dac33_priv *dac33; 1526 int ret, i; 1527 1528 if (client->dev.platform_data == NULL) { 1529 dev_err(&client->dev, "Platform data not set\n"); 1530 return -ENODEV; 1531 } 1532 pdata = client->dev.platform_data; 1533 1534 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL); 1535 if (dac33 == NULL) 1536 return -ENOMEM; 1537 1538 dac33->control_data = client; 1539 mutex_init(&dac33->mutex); 1540 spin_lock_init(&dac33->lock); 1541 1542 i2c_set_clientdata(client, dac33); 1543 1544 dac33->power_gpio = pdata->power_gpio; 1545 dac33->burst_bclkdiv = pdata->burst_bclkdiv; 1546 dac33->keep_bclk = pdata->keep_bclk; 1547 dac33->mode1_latency = pdata->mode1_latency; 1548 if (!dac33->mode1_latency) 1549 dac33->mode1_latency = 10000; /* 10ms */ 1550 dac33->irq = client->irq; 1551 /* Disable FIFO use by default */ 1552 dac33->fifo_mode = DAC33_FIFO_BYPASS; 1553 1554 /* Check if the reset GPIO number is valid and request it */ 1555 if (dac33->power_gpio >= 0) { 1556 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset"); 1557 if (ret < 0) { 1558 dev_err(&client->dev, 1559 "Failed to request reset GPIO (%d)\n", 1560 dac33->power_gpio); 1561 goto err_gpio; 1562 } 1563 gpio_direction_output(dac33->power_gpio, 0); 1564 } 1565 1566 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++) 1567 dac33->supplies[i].supply = dac33_supply_names[i]; 1568 1569 ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies), 1570 dac33->supplies); 1571 1572 if (ret != 0) { 1573 dev_err(&client->dev, "Failed to request supplies: %d\n", ret); 1574 goto err_get; 1575 } 1576 1577 ret = snd_soc_register_codec(&client->dev, 1578 &soc_codec_dev_tlv320dac33, &dac33_dai, 1); 1579 if (ret < 0) 1580 goto err_register; 1581 1582 return ret; 1583 err_register: 1584 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies); 1585 err_get: 1586 if (dac33->power_gpio >= 0) 1587 gpio_free(dac33->power_gpio); 1588 err_gpio: 1589 kfree(dac33); 1590 return ret; 1591 } 1592 1593 static int __devexit dac33_i2c_remove(struct i2c_client *client) 1594 { 1595 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client); 1596 1597 if (unlikely(dac33->chip_power)) 1598 dac33_hard_power(dac33->codec, 0); 1599 1600 if (dac33->power_gpio >= 0) 1601 gpio_free(dac33->power_gpio); 1602 1603 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies); 1604 1605 snd_soc_unregister_codec(&client->dev); 1606 kfree(dac33); 1607 1608 return 0; 1609 } 1610 1611 static const struct i2c_device_id tlv320dac33_i2c_id[] = { 1612 { 1613 .name = "tlv320dac33", 1614 .driver_data = 0, 1615 }, 1616 { }, 1617 }; 1618 1619 static struct i2c_driver tlv320dac33_i2c_driver = { 1620 .driver = { 1621 .name = "tlv320dac33-codec", 1622 .owner = THIS_MODULE, 1623 }, 1624 .probe = dac33_i2c_probe, 1625 .remove = __devexit_p(dac33_i2c_remove), 1626 .id_table = tlv320dac33_i2c_id, 1627 }; 1628 1629 static int __init dac33_module_init(void) 1630 { 1631 int r; 1632 r = i2c_add_driver(&tlv320dac33_i2c_driver); 1633 if (r < 0) { 1634 printk(KERN_ERR "DAC33: driver registration failed\n"); 1635 return r; 1636 } 1637 return 0; 1638 } 1639 module_init(dac33_module_init); 1640 1641 static void __exit dac33_module_exit(void) 1642 { 1643 i2c_del_driver(&tlv320dac33_i2c_driver); 1644 } 1645 module_exit(dac33_module_exit); 1646 1647 1648 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver"); 1649 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>"); 1650 MODULE_LICENSE("GPL"); 1651