1 /* 2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver 3 * 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 * 6 * Copyright: (C) 2009 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 */ 23 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/init.h> 27 #include <linux/delay.h> 28 #include <linux/pm.h> 29 #include <linux/i2c.h> 30 #include <linux/platform_device.h> 31 #include <linux/interrupt.h> 32 #include <linux/gpio.h> 33 #include <linux/regulator/consumer.h> 34 #include <linux/slab.h> 35 #include <sound/core.h> 36 #include <sound/pcm.h> 37 #include <sound/pcm_params.h> 38 #include <sound/soc.h> 39 #include <sound/initval.h> 40 #include <sound/tlv.h> 41 42 #include <sound/tlv320dac33-plat.h> 43 #include "tlv320dac33.h" 44 45 /* 46 * The internal FIFO is 24576 bytes long 47 * It can be configured to hold 16bit or 24bit samples 48 * In 16bit configuration the FIFO can hold 6144 stereo samples 49 * In 24bit configuration the FIFO can hold 4096 stereo samples 50 */ 51 #define DAC33_FIFO_SIZE_16BIT 6144 52 #define DAC33_FIFO_SIZE_24BIT 4096 53 #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */ 54 55 #define BURST_BASEFREQ_HZ 49152000 56 57 #define SAMPLES_TO_US(rate, samples) \ 58 (1000000000 / ((rate * 1000) / samples)) 59 60 #define US_TO_SAMPLES(rate, us) \ 61 (rate / (1000000 / (us < 1000000 ? us : 1000000))) 62 63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \ 64 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate))) 65 66 static void dac33_calculate_times(struct snd_pcm_substream *substream); 67 static int dac33_prepare_chip(struct snd_pcm_substream *substream); 68 69 enum dac33_state { 70 DAC33_IDLE = 0, 71 DAC33_PREFILL, 72 DAC33_PLAYBACK, 73 DAC33_FLUSH, 74 }; 75 76 enum dac33_fifo_modes { 77 DAC33_FIFO_BYPASS = 0, 78 DAC33_FIFO_MODE1, 79 DAC33_FIFO_MODE7, 80 DAC33_FIFO_LAST_MODE, 81 }; 82 83 #define DAC33_NUM_SUPPLIES 3 84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = { 85 "AVDD", 86 "DVDD", 87 "IOVDD", 88 }; 89 90 struct tlv320dac33_priv { 91 struct mutex mutex; 92 struct workqueue_struct *dac33_wq; 93 struct work_struct work; 94 struct snd_soc_codec *codec; 95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES]; 96 struct snd_pcm_substream *substream; 97 int power_gpio; 98 int chip_power; 99 int irq; 100 unsigned int refclk; 101 102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ 103 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ 104 unsigned int fifo_size; /* Size of the FIFO in samples */ 105 unsigned int nsample; /* burst read amount from host */ 106 int mode1_latency; /* latency caused by the i2c writes in 107 * us */ 108 u8 burst_bclkdiv; /* BCLK divider value in burst mode */ 109 unsigned int burst_rate; /* Interface speed in Burst modes */ 110 111 int keep_bclk; /* Keep the BCLK continuously running 112 * in FIFO modes */ 113 spinlock_t lock; 114 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */ 115 unsigned long long t_stamp2; /* calculate the FIFO caused delay */ 116 117 unsigned int mode1_us_burst; /* Time to burst read n number of 118 * samples */ 119 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */ 120 121 unsigned int uthr; 122 123 enum dac33_state state; 124 enum snd_soc_control_type control_type; 125 void *control_data; 126 }; 127 128 static const u8 dac33_reg[DAC33_CACHEREGNUM] = { 129 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */ 130 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */ 131 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */ 132 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */ 133 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */ 134 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */ 135 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */ 136 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */ 137 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */ 138 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */ 139 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */ 140 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */ 141 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */ 142 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */ 143 0x00, 0x00, /* 0x38 - 0x39 */ 144 /* Registers 0x3a - 0x3f are reserved */ 145 0x00, 0x00, /* 0x3a - 0x3b */ 146 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */ 147 148 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */ 149 0x00, 0x80, /* 0x44 - 0x45 */ 150 /* Registers 0x46 - 0x47 are reserved */ 151 0x80, 0x80, /* 0x46 - 0x47 */ 152 153 0x80, 0x00, 0x00, /* 0x48 - 0x4a */ 154 /* Registers 0x4b - 0x7c are reserved */ 155 0x00, /* 0x4b */ 156 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */ 157 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */ 158 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */ 159 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */ 160 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */ 161 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */ 162 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */ 163 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */ 164 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */ 165 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */ 166 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */ 167 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */ 168 0x00, /* 0x7c */ 169 170 0xda, 0x33, 0x03, /* 0x7d - 0x7f */ 171 }; 172 173 /* Register read and write */ 174 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec, 175 unsigned reg) 176 { 177 u8 *cache = codec->reg_cache; 178 if (reg >= DAC33_CACHEREGNUM) 179 return 0; 180 181 return cache[reg]; 182 } 183 184 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec, 185 u8 reg, u8 value) 186 { 187 u8 *cache = codec->reg_cache; 188 if (reg >= DAC33_CACHEREGNUM) 189 return; 190 191 cache[reg] = value; 192 } 193 194 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg, 195 u8 *value) 196 { 197 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 198 int val, ret = 0; 199 200 *value = reg & 0xff; 201 202 /* If powered off, return the cached value */ 203 if (dac33->chip_power) { 204 val = i2c_smbus_read_byte_data(codec->control_data, value[0]); 205 if (val < 0) { 206 dev_err(codec->dev, "Read failed (%d)\n", val); 207 value[0] = dac33_read_reg_cache(codec, reg); 208 ret = val; 209 } else { 210 value[0] = val; 211 dac33_write_reg_cache(codec, reg, val); 212 } 213 } else { 214 value[0] = dac33_read_reg_cache(codec, reg); 215 } 216 217 return ret; 218 } 219 220 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg, 221 unsigned int value) 222 { 223 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 224 u8 data[2]; 225 int ret = 0; 226 227 /* 228 * data is 229 * D15..D8 dac33 register offset 230 * D7...D0 register data 231 */ 232 data[0] = reg & 0xff; 233 data[1] = value & 0xff; 234 235 dac33_write_reg_cache(codec, data[0], data[1]); 236 if (dac33->chip_power) { 237 ret = codec->hw_write(codec->control_data, data, 2); 238 if (ret != 2) 239 dev_err(codec->dev, "Write failed (%d)\n", ret); 240 else 241 ret = 0; 242 } 243 244 return ret; 245 } 246 247 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg, 248 unsigned int value) 249 { 250 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 251 int ret; 252 253 mutex_lock(&dac33->mutex); 254 ret = dac33_write(codec, reg, value); 255 mutex_unlock(&dac33->mutex); 256 257 return ret; 258 } 259 260 #define DAC33_I2C_ADDR_AUTOINC 0x80 261 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg, 262 unsigned int value) 263 { 264 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 265 u8 data[3]; 266 int ret = 0; 267 268 /* 269 * data is 270 * D23..D16 dac33 register offset 271 * D15..D8 register data MSB 272 * D7...D0 register data LSB 273 */ 274 data[0] = reg & 0xff; 275 data[1] = (value >> 8) & 0xff; 276 data[2] = value & 0xff; 277 278 dac33_write_reg_cache(codec, data[0], data[1]); 279 dac33_write_reg_cache(codec, data[0] + 1, data[2]); 280 281 if (dac33->chip_power) { 282 /* We need to set autoincrement mode for 16 bit writes */ 283 data[0] |= DAC33_I2C_ADDR_AUTOINC; 284 ret = codec->hw_write(codec->control_data, data, 3); 285 if (ret != 3) 286 dev_err(codec->dev, "Write failed (%d)\n", ret); 287 else 288 ret = 0; 289 } 290 291 return ret; 292 } 293 294 static void dac33_init_chip(struct snd_soc_codec *codec) 295 { 296 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 297 298 if (unlikely(!dac33->chip_power)) 299 return; 300 301 /* A : DAC sample rate Fsref/1.5 */ 302 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); 303 /* B : DAC src=normal, not muted */ 304 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT | 305 DAC33_DACSRCL_LEFT); 306 /* C : (defaults) */ 307 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00); 308 309 /* 73 : volume soft stepping control, 310 clock source = internal osc (?) */ 311 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); 312 313 /* Restore only selected registers (gains mostly) */ 314 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL, 315 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL)); 316 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL, 317 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL)); 318 319 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL, 320 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL)); 321 dac33_write(codec, DAC33_LINER_TO_RLO_VOL, 322 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL)); 323 324 dac33_write(codec, DAC33_OUT_AMP_CTRL, 325 dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL)); 326 327 dac33_write(codec, DAC33_LDAC_PWR_CTRL, 328 dac33_read_reg_cache(codec, DAC33_LDAC_PWR_CTRL)); 329 dac33_write(codec, DAC33_RDAC_PWR_CTRL, 330 dac33_read_reg_cache(codec, DAC33_RDAC_PWR_CTRL)); 331 } 332 333 static inline int dac33_read_id(struct snd_soc_codec *codec) 334 { 335 int i, ret = 0; 336 u8 reg; 337 338 for (i = 0; i < 3; i++) { 339 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, ®); 340 if (ret < 0) 341 break; 342 } 343 344 return ret; 345 } 346 347 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power) 348 { 349 u8 reg; 350 351 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); 352 if (power) 353 reg |= DAC33_PDNALLB; 354 else 355 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB | 356 DAC33_DACRPDNB | DAC33_DACLPDNB); 357 dac33_write(codec, DAC33_PWR_CTRL, reg); 358 } 359 360 static inline void dac33_disable_digital(struct snd_soc_codec *codec) 361 { 362 u8 reg; 363 364 /* Stop the DAI clock */ 365 reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 366 reg &= ~DAC33_BCLKON; 367 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg); 368 369 /* Power down the Oscillator, and DACs */ 370 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); 371 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB); 372 dac33_write(codec, DAC33_PWR_CTRL, reg); 373 } 374 375 static int dac33_hard_power(struct snd_soc_codec *codec, int power) 376 { 377 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 378 int ret = 0; 379 380 mutex_lock(&dac33->mutex); 381 382 /* Safety check */ 383 if (unlikely(power == dac33->chip_power)) { 384 dev_dbg(codec->dev, "Trying to set the same power state: %s\n", 385 power ? "ON" : "OFF"); 386 goto exit; 387 } 388 389 if (power) { 390 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies), 391 dac33->supplies); 392 if (ret != 0) { 393 dev_err(codec->dev, 394 "Failed to enable supplies: %d\n", ret); 395 goto exit; 396 } 397 398 if (dac33->power_gpio >= 0) 399 gpio_set_value(dac33->power_gpio, 1); 400 401 dac33->chip_power = 1; 402 } else { 403 dac33_soft_power(codec, 0); 404 if (dac33->power_gpio >= 0) 405 gpio_set_value(dac33->power_gpio, 0); 406 407 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), 408 dac33->supplies); 409 if (ret != 0) { 410 dev_err(codec->dev, 411 "Failed to disable supplies: %d\n", ret); 412 goto exit; 413 } 414 415 dac33->chip_power = 0; 416 } 417 418 exit: 419 mutex_unlock(&dac33->mutex); 420 return ret; 421 } 422 423 static int dac33_playback_event(struct snd_soc_dapm_widget *w, 424 struct snd_kcontrol *kcontrol, int event) 425 { 426 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec); 427 428 switch (event) { 429 case SND_SOC_DAPM_PRE_PMU: 430 if (likely(dac33->substream)) { 431 dac33_calculate_times(dac33->substream); 432 dac33_prepare_chip(dac33->substream); 433 } 434 break; 435 case SND_SOC_DAPM_POST_PMD: 436 dac33_disable_digital(w->codec); 437 break; 438 } 439 return 0; 440 } 441 442 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, 443 struct snd_ctl_elem_value *ucontrol) 444 { 445 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 446 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 447 448 ucontrol->value.integer.value[0] = dac33->fifo_mode; 449 450 return 0; 451 } 452 453 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol, 454 struct snd_ctl_elem_value *ucontrol) 455 { 456 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 457 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 458 int ret = 0; 459 460 if (dac33->fifo_mode == ucontrol->value.integer.value[0]) 461 return 0; 462 /* Do not allow changes while stream is running*/ 463 if (codec->active) 464 return -EPERM; 465 466 if (ucontrol->value.integer.value[0] < 0 || 467 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE) 468 ret = -EINVAL; 469 else 470 dac33->fifo_mode = ucontrol->value.integer.value[0]; 471 472 return ret; 473 } 474 475 /* Codec operation modes */ 476 static const char *dac33_fifo_mode_texts[] = { 477 "Bypass", "Mode 1", "Mode 7" 478 }; 479 480 static const struct soc_enum dac33_fifo_mode_enum = 481 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts), 482 dac33_fifo_mode_texts); 483 484 /* L/R Line Output Gain */ 485 static const char *lr_lineout_gain_texts[] = { 486 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB", 487 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB", 488 }; 489 490 static const struct soc_enum l_lineout_gain_enum = 491 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0, 492 ARRAY_SIZE(lr_lineout_gain_texts), 493 lr_lineout_gain_texts); 494 495 static const struct soc_enum r_lineout_gain_enum = 496 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0, 497 ARRAY_SIZE(lr_lineout_gain_texts), 498 lr_lineout_gain_texts); 499 500 /* 501 * DACL/R digital volume control: 502 * from 0 dB to -63.5 in 0.5 dB steps 503 * Need to be inverted later on: 504 * 0x00 == 0 dB 505 * 0x7f == -63.5 dB 506 */ 507 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0); 508 509 static const struct snd_kcontrol_new dac33_snd_controls[] = { 510 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume", 511 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 512 0, 0x7f, 1, dac_digivol_tlv), 513 SOC_DOUBLE_R("DAC Digital Playback Switch", 514 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1), 515 SOC_DOUBLE_R("Line to Line Out Volume", 516 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1), 517 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum), 518 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum), 519 }; 520 521 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = { 522 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum, 523 dac33_get_fifo_mode, dac33_set_fifo_mode), 524 }; 525 526 /* Analog bypass */ 527 static const struct snd_kcontrol_new dac33_dapm_abypassl_control = 528 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); 529 530 static const struct snd_kcontrol_new dac33_dapm_abypassr_control = 531 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1); 532 533 /* LOP L/R invert selection */ 534 static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"}; 535 536 static const struct soc_enum dac33_left_lom_enum = 537 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 3, 538 ARRAY_SIZE(dac33_lr_lom_texts), 539 dac33_lr_lom_texts); 540 541 static const struct snd_kcontrol_new dac33_dapm_left_lom_control = 542 SOC_DAPM_ENUM("Route", dac33_left_lom_enum); 543 544 static const struct soc_enum dac33_right_lom_enum = 545 SOC_ENUM_SINGLE(DAC33_OUT_AMP_CTRL, 2, 546 ARRAY_SIZE(dac33_lr_lom_texts), 547 dac33_lr_lom_texts); 548 549 static const struct snd_kcontrol_new dac33_dapm_right_lom_control = 550 SOC_DAPM_ENUM("Route", dac33_right_lom_enum); 551 552 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { 553 SND_SOC_DAPM_OUTPUT("LEFT_LO"), 554 SND_SOC_DAPM_OUTPUT("RIGHT_LO"), 555 556 SND_SOC_DAPM_INPUT("LINEL"), 557 SND_SOC_DAPM_INPUT("LINER"), 558 559 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), 560 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), 561 562 /* Analog bypass */ 563 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0, 564 &dac33_dapm_abypassl_control), 565 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, 566 &dac33_dapm_abypassr_control), 567 568 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0, 569 &dac33_dapm_left_lom_control), 570 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0, 571 &dac33_dapm_right_lom_control), 572 /* 573 * For DAPM path, when only the anlog bypass path is enabled, and the 574 * LOP inverted from the corresponding DAC side. 575 * This is needed, so we can attach the DAC power supply in this case. 576 */ 577 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 578 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 579 580 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier", 581 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), 582 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier", 583 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), 584 585 SND_SOC_DAPM_SUPPLY("Left DAC Power", 586 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0), 587 SND_SOC_DAPM_SUPPLY("Right DAC Power", 588 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0), 589 590 SND_SOC_DAPM_SUPPLY("Codec Power", 591 DAC33_PWR_CTRL, 4, 0, NULL, 0), 592 593 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event), 594 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event), 595 }; 596 597 static const struct snd_soc_dapm_route audio_map[] = { 598 /* Analog bypass */ 599 {"Analog Left Bypass", "Switch", "LINEL"}, 600 {"Analog Right Bypass", "Switch", "LINER"}, 601 602 {"Output Left Amplifier", NULL, "DACL"}, 603 {"Output Right Amplifier", NULL, "DACR"}, 604 605 {"Left Bypass PGA", NULL, "Analog Left Bypass"}, 606 {"Right Bypass PGA", NULL, "Analog Right Bypass"}, 607 608 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"}, 609 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"}, 610 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"}, 611 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"}, 612 613 {"Output Left Amplifier", NULL, "Left LOM Inverted From"}, 614 {"Output Right Amplifier", NULL, "Right LOM Inverted From"}, 615 616 {"DACL", NULL, "Left DAC Power"}, 617 {"DACR", NULL, "Right DAC Power"}, 618 619 {"Left Bypass PGA", NULL, "Left DAC Power"}, 620 {"Right Bypass PGA", NULL, "Right DAC Power"}, 621 622 /* output */ 623 {"LEFT_LO", NULL, "Output Left Amplifier"}, 624 {"RIGHT_LO", NULL, "Output Right Amplifier"}, 625 626 {"LEFT_LO", NULL, "Codec Power"}, 627 {"RIGHT_LO", NULL, "Codec Power"}, 628 }; 629 630 static int dac33_add_widgets(struct snd_soc_codec *codec) 631 { 632 struct snd_soc_dapm_context *dapm = &codec->dapm; 633 634 snd_soc_dapm_new_controls(dapm, dac33_dapm_widgets, 635 ARRAY_SIZE(dac33_dapm_widgets)); 636 /* set up audio path interconnects */ 637 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); 638 639 return 0; 640 } 641 642 static int dac33_set_bias_level(struct snd_soc_codec *codec, 643 enum snd_soc_bias_level level) 644 { 645 int ret; 646 647 switch (level) { 648 case SND_SOC_BIAS_ON: 649 break; 650 case SND_SOC_BIAS_PREPARE: 651 break; 652 case SND_SOC_BIAS_STANDBY: 653 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 654 /* Coming from OFF, switch on the codec */ 655 ret = dac33_hard_power(codec, 1); 656 if (ret != 0) 657 return ret; 658 659 dac33_init_chip(codec); 660 } 661 break; 662 case SND_SOC_BIAS_OFF: 663 /* Do not power off, when the codec is already off */ 664 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) 665 return 0; 666 ret = dac33_hard_power(codec, 0); 667 if (ret != 0) 668 return ret; 669 break; 670 } 671 codec->dapm.bias_level = level; 672 673 return 0; 674 } 675 676 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33) 677 { 678 struct snd_soc_codec *codec = dac33->codec; 679 unsigned int delay; 680 unsigned long flags; 681 682 switch (dac33->fifo_mode) { 683 case DAC33_FIFO_MODE1: 684 dac33_write16(codec, DAC33_NSAMPLE_MSB, 685 DAC33_THRREG(dac33->nsample)); 686 687 /* Take the timestamps */ 688 spin_lock_irqsave(&dac33->lock, flags); 689 dac33->t_stamp2 = ktime_to_us(ktime_get()); 690 dac33->t_stamp1 = dac33->t_stamp2; 691 spin_unlock_irqrestore(&dac33->lock, flags); 692 693 dac33_write16(codec, DAC33_PREFILL_MSB, 694 DAC33_THRREG(dac33->alarm_threshold)); 695 /* Enable Alarm Threshold IRQ with a delay */ 696 delay = SAMPLES_TO_US(dac33->burst_rate, 697 dac33->alarm_threshold) + 1000; 698 usleep_range(delay, delay + 500); 699 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT); 700 break; 701 case DAC33_FIFO_MODE7: 702 /* Take the timestamp */ 703 spin_lock_irqsave(&dac33->lock, flags); 704 dac33->t_stamp1 = ktime_to_us(ktime_get()); 705 /* Move back the timestamp with drain time */ 706 dac33->t_stamp1 -= dac33->mode7_us_to_lthr; 707 spin_unlock_irqrestore(&dac33->lock, flags); 708 709 dac33_write16(codec, DAC33_PREFILL_MSB, 710 DAC33_THRREG(DAC33_MODE7_MARGIN)); 711 712 /* Enable Upper Threshold IRQ */ 713 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT); 714 break; 715 default: 716 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 717 dac33->fifo_mode); 718 break; 719 } 720 } 721 722 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33) 723 { 724 struct snd_soc_codec *codec = dac33->codec; 725 unsigned long flags; 726 727 switch (dac33->fifo_mode) { 728 case DAC33_FIFO_MODE1: 729 /* Take the timestamp */ 730 spin_lock_irqsave(&dac33->lock, flags); 731 dac33->t_stamp2 = ktime_to_us(ktime_get()); 732 spin_unlock_irqrestore(&dac33->lock, flags); 733 734 dac33_write16(codec, DAC33_NSAMPLE_MSB, 735 DAC33_THRREG(dac33->nsample)); 736 break; 737 case DAC33_FIFO_MODE7: 738 /* At the moment we are not using interrupts in mode7 */ 739 break; 740 default: 741 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 742 dac33->fifo_mode); 743 break; 744 } 745 } 746 747 static void dac33_work(struct work_struct *work) 748 { 749 struct snd_soc_codec *codec; 750 struct tlv320dac33_priv *dac33; 751 u8 reg; 752 753 dac33 = container_of(work, struct tlv320dac33_priv, work); 754 codec = dac33->codec; 755 756 mutex_lock(&dac33->mutex); 757 switch (dac33->state) { 758 case DAC33_PREFILL: 759 dac33->state = DAC33_PLAYBACK; 760 dac33_prefill_handler(dac33); 761 break; 762 case DAC33_PLAYBACK: 763 dac33_playback_handler(dac33); 764 break; 765 case DAC33_IDLE: 766 break; 767 case DAC33_FLUSH: 768 dac33->state = DAC33_IDLE; 769 /* Mask all interrupts from dac33 */ 770 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0); 771 772 /* flush fifo */ 773 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); 774 reg |= DAC33_FIFOFLUSH; 775 dac33_write(codec, DAC33_FIFO_CTRL_A, reg); 776 break; 777 } 778 mutex_unlock(&dac33->mutex); 779 } 780 781 static irqreturn_t dac33_interrupt_handler(int irq, void *dev) 782 { 783 struct snd_soc_codec *codec = dev; 784 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 785 unsigned long flags; 786 787 spin_lock_irqsave(&dac33->lock, flags); 788 dac33->t_stamp1 = ktime_to_us(ktime_get()); 789 spin_unlock_irqrestore(&dac33->lock, flags); 790 791 /* Do not schedule the workqueue in Mode7 */ 792 if (dac33->fifo_mode != DAC33_FIFO_MODE7) 793 queue_work(dac33->dac33_wq, &dac33->work); 794 795 return IRQ_HANDLED; 796 } 797 798 static void dac33_oscwait(struct snd_soc_codec *codec) 799 { 800 int timeout = 60; 801 u8 reg; 802 803 do { 804 usleep_range(1000, 2000); 805 dac33_read(codec, DAC33_INT_OSC_STATUS, ®); 806 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--); 807 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) 808 dev_err(codec->dev, 809 "internal oscillator calibration failed\n"); 810 } 811 812 static int dac33_startup(struct snd_pcm_substream *substream, 813 struct snd_soc_dai *dai) 814 { 815 struct snd_soc_pcm_runtime *rtd = substream->private_data; 816 struct snd_soc_codec *codec = rtd->codec; 817 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 818 819 /* Stream started, save the substream pointer */ 820 dac33->substream = substream; 821 822 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24); 823 824 return 0; 825 } 826 827 static void dac33_shutdown(struct snd_pcm_substream *substream, 828 struct snd_soc_dai *dai) 829 { 830 struct snd_soc_pcm_runtime *rtd = substream->private_data; 831 struct snd_soc_codec *codec = rtd->codec; 832 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 833 834 dac33->substream = NULL; 835 } 836 837 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \ 838 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample) 839 static int dac33_hw_params(struct snd_pcm_substream *substream, 840 struct snd_pcm_hw_params *params, 841 struct snd_soc_dai *dai) 842 { 843 struct snd_soc_pcm_runtime *rtd = substream->private_data; 844 struct snd_soc_codec *codec = rtd->codec; 845 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 846 847 /* Check parameters for validity */ 848 switch (params_rate(params)) { 849 case 44100: 850 case 48000: 851 break; 852 default: 853 dev_err(codec->dev, "unsupported rate %d\n", 854 params_rate(params)); 855 return -EINVAL; 856 } 857 858 switch (params_format(params)) { 859 case SNDRV_PCM_FORMAT_S16_LE: 860 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT; 861 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32); 862 break; 863 case SNDRV_PCM_FORMAT_S32_LE: 864 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT; 865 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64); 866 break; 867 default: 868 dev_err(codec->dev, "unsupported format %d\n", 869 params_format(params)); 870 return -EINVAL; 871 } 872 873 return 0; 874 } 875 876 #define CALC_OSCSET(rate, refclk) ( \ 877 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000) 878 #define CALC_RATIOSET(rate, refclk) ( \ 879 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000) 880 881 /* 882 * tlv320dac33 is strict on the sequence of the register writes, if the register 883 * writes happens in different order, than dac33 might end up in unknown state. 884 * Use the known, working sequence of register writes to initialize the dac33. 885 */ 886 static int dac33_prepare_chip(struct snd_pcm_substream *substream) 887 { 888 struct snd_soc_pcm_runtime *rtd = substream->private_data; 889 struct snd_soc_codec *codec = rtd->codec; 890 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 891 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; 892 u8 aictrl_a, aictrl_b, fifoctrl_a; 893 894 switch (substream->runtime->rate) { 895 case 44100: 896 case 48000: 897 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk); 898 ratioset = CALC_RATIOSET(substream->runtime->rate, 899 dac33->refclk); 900 break; 901 default: 902 dev_err(codec->dev, "unsupported rate %d\n", 903 substream->runtime->rate); 904 return -EINVAL; 905 } 906 907 908 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); 909 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK); 910 /* Read FIFO control A, and clear FIFO flush bit */ 911 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); 912 fifoctrl_a &= ~DAC33_FIFOFLUSH; 913 914 fifoctrl_a &= ~DAC33_WIDTH; 915 switch (substream->runtime->format) { 916 case SNDRV_PCM_FORMAT_S16_LE: 917 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); 918 fifoctrl_a |= DAC33_WIDTH; 919 break; 920 case SNDRV_PCM_FORMAT_S32_LE: 921 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24); 922 break; 923 default: 924 dev_err(codec->dev, "unsupported format %d\n", 925 substream->runtime->format); 926 return -EINVAL; 927 } 928 929 mutex_lock(&dac33->mutex); 930 931 if (!dac33->chip_power) { 932 /* 933 * Chip is not powered yet. 934 * Do the init in the dac33_set_bias_level later. 935 */ 936 mutex_unlock(&dac33->mutex); 937 return 0; 938 } 939 940 dac33_soft_power(codec, 0); 941 dac33_soft_power(codec, 1); 942 943 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); 944 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp); 945 946 /* Write registers 0x08 and 0x09 (MSB, LSB) */ 947 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset); 948 949 /* OSC calibration time */ 950 dac33_write(codec, DAC33_CALIB_TIME, 96); 951 952 /* adjustment treshold & step */ 953 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) | 954 DAC33_ADJSTEP(1)); 955 956 /* div=4 / gain=1 / div */ 957 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4)); 958 959 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); 960 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB; 961 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl); 962 963 dac33_oscwait(codec); 964 965 if (dac33->fifo_mode) { 966 /* Generic for all FIFO modes */ 967 /* 50-51 : ASRC Control registers */ 968 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1)); 969 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */ 970 971 /* Write registers 0x34 and 0x35 (MSB, LSB) */ 972 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset); 973 974 /* Set interrupts to high active */ 975 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH); 976 } else { 977 /* FIFO bypass mode */ 978 /* 50-51 : ASRC Control registers */ 979 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP); 980 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */ 981 } 982 983 /* Interrupt behaviour configuration */ 984 switch (dac33->fifo_mode) { 985 case DAC33_FIFO_MODE1: 986 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B, 987 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); 988 break; 989 case DAC33_FIFO_MODE7: 990 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A, 991 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL)); 992 break; 993 default: 994 /* in FIFO bypass mode, the interrupts are not used */ 995 break; 996 } 997 998 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 999 1000 switch (dac33->fifo_mode) { 1001 case DAC33_FIFO_MODE1: 1002 /* 1003 * For mode1: 1004 * Disable the FIFO bypass (Enable the use of FIFO) 1005 * Select nSample mode 1006 * BCLK is only running when data is needed by DAC33 1007 */ 1008 fifoctrl_a &= ~DAC33_FBYPAS; 1009 fifoctrl_a &= ~DAC33_FAUTO; 1010 if (dac33->keep_bclk) 1011 aictrl_b |= DAC33_BCLKON; 1012 else 1013 aictrl_b &= ~DAC33_BCLKON; 1014 break; 1015 case DAC33_FIFO_MODE7: 1016 /* 1017 * For mode1: 1018 * Disable the FIFO bypass (Enable the use of FIFO) 1019 * Select Threshold mode 1020 * BCLK is only running when data is needed by DAC33 1021 */ 1022 fifoctrl_a &= ~DAC33_FBYPAS; 1023 fifoctrl_a |= DAC33_FAUTO; 1024 if (dac33->keep_bclk) 1025 aictrl_b |= DAC33_BCLKON; 1026 else 1027 aictrl_b &= ~DAC33_BCLKON; 1028 break; 1029 default: 1030 /* 1031 * For FIFO bypass mode: 1032 * Enable the FIFO bypass (Disable the FIFO use) 1033 * Set the BCLK as continuous 1034 */ 1035 fifoctrl_a |= DAC33_FBYPAS; 1036 aictrl_b |= DAC33_BCLKON; 1037 break; 1038 } 1039 1040 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a); 1041 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 1042 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); 1043 1044 /* 1045 * BCLK divide ratio 1046 * 0: 1.5 1047 * 1: 1 1048 * 2: 2 1049 * ... 1050 * 254: 254 1051 * 255: 255 1052 */ 1053 if (dac33->fifo_mode) 1054 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 1055 dac33->burst_bclkdiv); 1056 else 1057 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) 1058 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32); 1059 else 1060 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16); 1061 1062 switch (dac33->fifo_mode) { 1063 case DAC33_FIFO_MODE1: 1064 dac33_write16(codec, DAC33_ATHR_MSB, 1065 DAC33_THRREG(dac33->alarm_threshold)); 1066 break; 1067 case DAC33_FIFO_MODE7: 1068 /* 1069 * Configure the threshold levels, and leave 10 sample space 1070 * at the bottom, and also at the top of the FIFO 1071 */ 1072 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr)); 1073 dac33_write16(codec, DAC33_LTHR_MSB, 1074 DAC33_THRREG(DAC33_MODE7_MARGIN)); 1075 break; 1076 default: 1077 break; 1078 } 1079 1080 mutex_unlock(&dac33->mutex); 1081 1082 return 0; 1083 } 1084 1085 static void dac33_calculate_times(struct snd_pcm_substream *substream) 1086 { 1087 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1088 struct snd_soc_codec *codec = rtd->codec; 1089 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1090 unsigned int period_size = substream->runtime->period_size; 1091 unsigned int rate = substream->runtime->rate; 1092 unsigned int nsample_limit; 1093 1094 /* In bypass mode we don't need to calculate */ 1095 if (!dac33->fifo_mode) 1096 return; 1097 1098 switch (dac33->fifo_mode) { 1099 case DAC33_FIFO_MODE1: 1100 /* Number of samples under i2c latency */ 1101 dac33->alarm_threshold = US_TO_SAMPLES(rate, 1102 dac33->mode1_latency); 1103 nsample_limit = dac33->fifo_size - dac33->alarm_threshold; 1104 1105 if (period_size <= dac33->alarm_threshold) 1106 /* 1107 * Configure nSamaple to number of periods, 1108 * which covers the latency requironment. 1109 */ 1110 dac33->nsample = period_size * 1111 ((dac33->alarm_threshold / period_size) + 1112 (dac33->alarm_threshold % period_size ? 1113 1 : 0)); 1114 else if (period_size > nsample_limit) 1115 dac33->nsample = nsample_limit; 1116 else 1117 dac33->nsample = period_size; 1118 1119 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, 1120 dac33->nsample); 1121 dac33->t_stamp1 = 0; 1122 dac33->t_stamp2 = 0; 1123 break; 1124 case DAC33_FIFO_MODE7: 1125 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate, 1126 dac33->burst_rate) + 9; 1127 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN)) 1128 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN; 1129 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10)) 1130 dac33->uthr = (DAC33_MODE7_MARGIN + 10); 1131 1132 dac33->mode7_us_to_lthr = 1133 SAMPLES_TO_US(substream->runtime->rate, 1134 dac33->uthr - DAC33_MODE7_MARGIN + 1); 1135 dac33->t_stamp1 = 0; 1136 break; 1137 default: 1138 break; 1139 } 1140 1141 } 1142 1143 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 1144 struct snd_soc_dai *dai) 1145 { 1146 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1147 struct snd_soc_codec *codec = rtd->codec; 1148 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1149 int ret = 0; 1150 1151 switch (cmd) { 1152 case SNDRV_PCM_TRIGGER_START: 1153 case SNDRV_PCM_TRIGGER_RESUME: 1154 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1155 if (dac33->fifo_mode) { 1156 dac33->state = DAC33_PREFILL; 1157 queue_work(dac33->dac33_wq, &dac33->work); 1158 } 1159 break; 1160 case SNDRV_PCM_TRIGGER_STOP: 1161 case SNDRV_PCM_TRIGGER_SUSPEND: 1162 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1163 if (dac33->fifo_mode) { 1164 dac33->state = DAC33_FLUSH; 1165 queue_work(dac33->dac33_wq, &dac33->work); 1166 } 1167 break; 1168 default: 1169 ret = -EINVAL; 1170 } 1171 1172 return ret; 1173 } 1174 1175 static snd_pcm_sframes_t dac33_dai_delay( 1176 struct snd_pcm_substream *substream, 1177 struct snd_soc_dai *dai) 1178 { 1179 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1180 struct snd_soc_codec *codec = rtd->codec; 1181 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1182 unsigned long long t0, t1, t_now; 1183 unsigned int time_delta, uthr; 1184 int samples_out, samples_in, samples; 1185 snd_pcm_sframes_t delay = 0; 1186 unsigned long flags; 1187 1188 switch (dac33->fifo_mode) { 1189 case DAC33_FIFO_BYPASS: 1190 break; 1191 case DAC33_FIFO_MODE1: 1192 spin_lock_irqsave(&dac33->lock, flags); 1193 t0 = dac33->t_stamp1; 1194 t1 = dac33->t_stamp2; 1195 spin_unlock_irqrestore(&dac33->lock, flags); 1196 t_now = ktime_to_us(ktime_get()); 1197 1198 /* We have not started to fill the FIFO yet, delay is 0 */ 1199 if (!t1) 1200 goto out; 1201 1202 if (t0 > t1) { 1203 /* 1204 * Phase 1: 1205 * After Alarm threshold, and before nSample write 1206 */ 1207 time_delta = t_now - t0; 1208 samples_out = time_delta ? US_TO_SAMPLES( 1209 substream->runtime->rate, 1210 time_delta) : 0; 1211 1212 if (likely(dac33->alarm_threshold > samples_out)) 1213 delay = dac33->alarm_threshold - samples_out; 1214 else 1215 delay = 0; 1216 } else if ((t_now - t1) <= dac33->mode1_us_burst) { 1217 /* 1218 * Phase 2: 1219 * After nSample write (during burst operation) 1220 */ 1221 time_delta = t_now - t0; 1222 samples_out = time_delta ? US_TO_SAMPLES( 1223 substream->runtime->rate, 1224 time_delta) : 0; 1225 1226 time_delta = t_now - t1; 1227 samples_in = time_delta ? US_TO_SAMPLES( 1228 dac33->burst_rate, 1229 time_delta) : 0; 1230 1231 samples = dac33->alarm_threshold; 1232 samples += (samples_in - samples_out); 1233 1234 if (likely(samples > 0)) 1235 delay = samples; 1236 else 1237 delay = 0; 1238 } else { 1239 /* 1240 * Phase 3: 1241 * After burst operation, before next alarm threshold 1242 */ 1243 time_delta = t_now - t0; 1244 samples_out = time_delta ? US_TO_SAMPLES( 1245 substream->runtime->rate, 1246 time_delta) : 0; 1247 1248 samples_in = dac33->nsample; 1249 samples = dac33->alarm_threshold; 1250 samples += (samples_in - samples_out); 1251 1252 if (likely(samples > 0)) 1253 delay = samples > dac33->fifo_size ? 1254 dac33->fifo_size : samples; 1255 else 1256 delay = 0; 1257 } 1258 break; 1259 case DAC33_FIFO_MODE7: 1260 spin_lock_irqsave(&dac33->lock, flags); 1261 t0 = dac33->t_stamp1; 1262 uthr = dac33->uthr; 1263 spin_unlock_irqrestore(&dac33->lock, flags); 1264 t_now = ktime_to_us(ktime_get()); 1265 1266 /* We have not started to fill the FIFO yet, delay is 0 */ 1267 if (!t0) 1268 goto out; 1269 1270 if (t_now <= t0) { 1271 /* 1272 * Either the timestamps are messed or equal. Report 1273 * maximum delay 1274 */ 1275 delay = uthr; 1276 goto out; 1277 } 1278 1279 time_delta = t_now - t0; 1280 if (time_delta <= dac33->mode7_us_to_lthr) { 1281 /* 1282 * Phase 1: 1283 * After burst (draining phase) 1284 */ 1285 samples_out = US_TO_SAMPLES( 1286 substream->runtime->rate, 1287 time_delta); 1288 1289 if (likely(uthr > samples_out)) 1290 delay = uthr - samples_out; 1291 else 1292 delay = 0; 1293 } else { 1294 /* 1295 * Phase 2: 1296 * During burst operation 1297 */ 1298 time_delta = time_delta - dac33->mode7_us_to_lthr; 1299 1300 samples_out = US_TO_SAMPLES( 1301 substream->runtime->rate, 1302 time_delta); 1303 samples_in = US_TO_SAMPLES( 1304 dac33->burst_rate, 1305 time_delta); 1306 delay = DAC33_MODE7_MARGIN + samples_in - samples_out; 1307 1308 if (unlikely(delay > uthr)) 1309 delay = uthr; 1310 } 1311 break; 1312 default: 1313 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 1314 dac33->fifo_mode); 1315 break; 1316 } 1317 out: 1318 return delay; 1319 } 1320 1321 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1322 int clk_id, unsigned int freq, int dir) 1323 { 1324 struct snd_soc_codec *codec = codec_dai->codec; 1325 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1326 u8 ioc_reg, asrcb_reg; 1327 1328 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); 1329 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B); 1330 switch (clk_id) { 1331 case TLV320DAC33_MCLK: 1332 ioc_reg |= DAC33_REFSEL; 1333 asrcb_reg |= DAC33_SRCREFSEL; 1334 break; 1335 case TLV320DAC33_SLEEPCLK: 1336 ioc_reg &= ~DAC33_REFSEL; 1337 asrcb_reg &= ~DAC33_SRCREFSEL; 1338 break; 1339 default: 1340 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id); 1341 break; 1342 } 1343 dac33->refclk = freq; 1344 1345 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg); 1346 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg); 1347 1348 return 0; 1349 } 1350 1351 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai, 1352 unsigned int fmt) 1353 { 1354 struct snd_soc_codec *codec = codec_dai->codec; 1355 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1356 u8 aictrl_a, aictrl_b; 1357 1358 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); 1359 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 1360 /* set master/slave audio interface */ 1361 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1362 case SND_SOC_DAIFMT_CBM_CFM: 1363 /* Codec Master */ 1364 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK); 1365 break; 1366 case SND_SOC_DAIFMT_CBS_CFS: 1367 /* Codec Slave */ 1368 if (dac33->fifo_mode) { 1369 dev_err(codec->dev, "FIFO mode requires master mode\n"); 1370 return -EINVAL; 1371 } else 1372 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK); 1373 break; 1374 default: 1375 return -EINVAL; 1376 } 1377 1378 aictrl_a &= ~DAC33_AFMT_MASK; 1379 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1380 case SND_SOC_DAIFMT_I2S: 1381 aictrl_a |= DAC33_AFMT_I2S; 1382 break; 1383 case SND_SOC_DAIFMT_DSP_A: 1384 aictrl_a |= DAC33_AFMT_DSP; 1385 aictrl_b &= ~DAC33_DATA_DELAY_MASK; 1386 aictrl_b |= DAC33_DATA_DELAY(0); 1387 break; 1388 case SND_SOC_DAIFMT_RIGHT_J: 1389 aictrl_a |= DAC33_AFMT_RIGHT_J; 1390 break; 1391 case SND_SOC_DAIFMT_LEFT_J: 1392 aictrl_a |= DAC33_AFMT_LEFT_J; 1393 break; 1394 default: 1395 dev_err(codec->dev, "Unsupported format (%u)\n", 1396 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1397 return -EINVAL; 1398 } 1399 1400 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 1401 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); 1402 1403 return 0; 1404 } 1405 1406 static int dac33_soc_probe(struct snd_soc_codec *codec) 1407 { 1408 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1409 int ret = 0; 1410 1411 codec->control_data = dac33->control_data; 1412 codec->hw_write = (hw_write_t) i2c_master_send; 1413 codec->dapm.idle_bias_off = 1; 1414 dac33->codec = codec; 1415 1416 /* Read the tlv320dac33 ID registers */ 1417 ret = dac33_hard_power(codec, 1); 1418 if (ret != 0) { 1419 dev_err(codec->dev, "Failed to power up codec: %d\n", ret); 1420 goto err_power; 1421 } 1422 ret = dac33_read_id(codec); 1423 dac33_hard_power(codec, 0); 1424 1425 if (ret < 0) { 1426 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret); 1427 ret = -ENODEV; 1428 goto err_power; 1429 } 1430 1431 /* Check if the IRQ number is valid and request it */ 1432 if (dac33->irq >= 0) { 1433 ret = request_irq(dac33->irq, dac33_interrupt_handler, 1434 IRQF_TRIGGER_RISING | IRQF_DISABLED, 1435 codec->name, codec); 1436 if (ret < 0) { 1437 dev_err(codec->dev, "Could not request IRQ%d (%d)\n", 1438 dac33->irq, ret); 1439 dac33->irq = -1; 1440 } 1441 if (dac33->irq != -1) { 1442 /* Setup work queue */ 1443 dac33->dac33_wq = 1444 create_singlethread_workqueue("tlv320dac33"); 1445 if (dac33->dac33_wq == NULL) { 1446 free_irq(dac33->irq, codec); 1447 return -ENOMEM; 1448 } 1449 1450 INIT_WORK(&dac33->work, dac33_work); 1451 } 1452 } 1453 1454 snd_soc_add_controls(codec, dac33_snd_controls, 1455 ARRAY_SIZE(dac33_snd_controls)); 1456 /* Only add the FIFO controls, if we have valid IRQ number */ 1457 if (dac33->irq >= 0) 1458 snd_soc_add_controls(codec, dac33_mode_snd_controls, 1459 ARRAY_SIZE(dac33_mode_snd_controls)); 1460 1461 dac33_add_widgets(codec); 1462 1463 err_power: 1464 return ret; 1465 } 1466 1467 static int dac33_soc_remove(struct snd_soc_codec *codec) 1468 { 1469 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1470 1471 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF); 1472 1473 if (dac33->irq >= 0) { 1474 free_irq(dac33->irq, dac33->codec); 1475 destroy_workqueue(dac33->dac33_wq); 1476 } 1477 return 0; 1478 } 1479 1480 static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state) 1481 { 1482 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF); 1483 1484 return 0; 1485 } 1486 1487 static int dac33_soc_resume(struct snd_soc_codec *codec) 1488 { 1489 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1490 1491 return 0; 1492 } 1493 1494 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = { 1495 .read = dac33_read_reg_cache, 1496 .write = dac33_write_locked, 1497 .set_bias_level = dac33_set_bias_level, 1498 .reg_cache_size = ARRAY_SIZE(dac33_reg), 1499 .reg_word_size = sizeof(u8), 1500 .reg_cache_default = dac33_reg, 1501 .probe = dac33_soc_probe, 1502 .remove = dac33_soc_remove, 1503 .suspend = dac33_soc_suspend, 1504 .resume = dac33_soc_resume, 1505 }; 1506 1507 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ 1508 SNDRV_PCM_RATE_48000) 1509 #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 1510 1511 static struct snd_soc_dai_ops dac33_dai_ops = { 1512 .startup = dac33_startup, 1513 .shutdown = dac33_shutdown, 1514 .hw_params = dac33_hw_params, 1515 .trigger = dac33_pcm_trigger, 1516 .delay = dac33_dai_delay, 1517 .set_sysclk = dac33_set_dai_sysclk, 1518 .set_fmt = dac33_set_dai_fmt, 1519 }; 1520 1521 static struct snd_soc_dai_driver dac33_dai = { 1522 .name = "tlv320dac33-hifi", 1523 .playback = { 1524 .stream_name = "Playback", 1525 .channels_min = 2, 1526 .channels_max = 2, 1527 .rates = DAC33_RATES, 1528 .formats = DAC33_FORMATS,}, 1529 .ops = &dac33_dai_ops, 1530 }; 1531 1532 static int __devinit dac33_i2c_probe(struct i2c_client *client, 1533 const struct i2c_device_id *id) 1534 { 1535 struct tlv320dac33_platform_data *pdata; 1536 struct tlv320dac33_priv *dac33; 1537 int ret, i; 1538 1539 if (client->dev.platform_data == NULL) { 1540 dev_err(&client->dev, "Platform data not set\n"); 1541 return -ENODEV; 1542 } 1543 pdata = client->dev.platform_data; 1544 1545 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL); 1546 if (dac33 == NULL) 1547 return -ENOMEM; 1548 1549 dac33->control_data = client; 1550 mutex_init(&dac33->mutex); 1551 spin_lock_init(&dac33->lock); 1552 1553 i2c_set_clientdata(client, dac33); 1554 1555 dac33->power_gpio = pdata->power_gpio; 1556 dac33->burst_bclkdiv = pdata->burst_bclkdiv; 1557 dac33->keep_bclk = pdata->keep_bclk; 1558 dac33->mode1_latency = pdata->mode1_latency; 1559 if (!dac33->mode1_latency) 1560 dac33->mode1_latency = 10000; /* 10ms */ 1561 dac33->irq = client->irq; 1562 /* Disable FIFO use by default */ 1563 dac33->fifo_mode = DAC33_FIFO_BYPASS; 1564 1565 /* Check if the reset GPIO number is valid and request it */ 1566 if (dac33->power_gpio >= 0) { 1567 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset"); 1568 if (ret < 0) { 1569 dev_err(&client->dev, 1570 "Failed to request reset GPIO (%d)\n", 1571 dac33->power_gpio); 1572 goto err_gpio; 1573 } 1574 gpio_direction_output(dac33->power_gpio, 0); 1575 } 1576 1577 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++) 1578 dac33->supplies[i].supply = dac33_supply_names[i]; 1579 1580 ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies), 1581 dac33->supplies); 1582 1583 if (ret != 0) { 1584 dev_err(&client->dev, "Failed to request supplies: %d\n", ret); 1585 goto err_get; 1586 } 1587 1588 ret = snd_soc_register_codec(&client->dev, 1589 &soc_codec_dev_tlv320dac33, &dac33_dai, 1); 1590 if (ret < 0) 1591 goto err_register; 1592 1593 return ret; 1594 err_register: 1595 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies); 1596 err_get: 1597 if (dac33->power_gpio >= 0) 1598 gpio_free(dac33->power_gpio); 1599 err_gpio: 1600 kfree(dac33); 1601 return ret; 1602 } 1603 1604 static int __devexit dac33_i2c_remove(struct i2c_client *client) 1605 { 1606 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client); 1607 1608 if (unlikely(dac33->chip_power)) 1609 dac33_hard_power(dac33->codec, 0); 1610 1611 if (dac33->power_gpio >= 0) 1612 gpio_free(dac33->power_gpio); 1613 1614 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies); 1615 1616 snd_soc_unregister_codec(&client->dev); 1617 kfree(dac33); 1618 1619 return 0; 1620 } 1621 1622 static const struct i2c_device_id tlv320dac33_i2c_id[] = { 1623 { 1624 .name = "tlv320dac33", 1625 .driver_data = 0, 1626 }, 1627 { }, 1628 }; 1629 MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id); 1630 1631 static struct i2c_driver tlv320dac33_i2c_driver = { 1632 .driver = { 1633 .name = "tlv320dac33-codec", 1634 .owner = THIS_MODULE, 1635 }, 1636 .probe = dac33_i2c_probe, 1637 .remove = __devexit_p(dac33_i2c_remove), 1638 .id_table = tlv320dac33_i2c_id, 1639 }; 1640 1641 static int __init dac33_module_init(void) 1642 { 1643 int r; 1644 r = i2c_add_driver(&tlv320dac33_i2c_driver); 1645 if (r < 0) { 1646 printk(KERN_ERR "DAC33: driver registration failed\n"); 1647 return r; 1648 } 1649 return 0; 1650 } 1651 module_init(dac33_module_init); 1652 1653 static void __exit dac33_module_exit(void) 1654 { 1655 i2c_del_driver(&tlv320dac33_i2c_driver); 1656 } 1657 module_exit(dac33_module_exit); 1658 1659 1660 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver"); 1661 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1662 MODULE_LICENSE("GPL"); 1663