1 /* 2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver 3 * 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 * 6 * Copyright: (C) 2009 Nokia Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 20 * 02110-1301 USA 21 * 22 */ 23 24 #include <linux/module.h> 25 #include <linux/moduleparam.h> 26 #include <linux/init.h> 27 #include <linux/delay.h> 28 #include <linux/pm.h> 29 #include <linux/i2c.h> 30 #include <linux/interrupt.h> 31 #include <linux/gpio.h> 32 #include <linux/regulator/consumer.h> 33 #include <linux/slab.h> 34 #include <sound/core.h> 35 #include <sound/pcm.h> 36 #include <sound/pcm_params.h> 37 #include <sound/soc.h> 38 #include <sound/initval.h> 39 #include <sound/tlv.h> 40 41 #include <sound/tlv320dac33-plat.h> 42 #include "tlv320dac33.h" 43 44 /* 45 * The internal FIFO is 24576 bytes long 46 * It can be configured to hold 16bit or 24bit samples 47 * In 16bit configuration the FIFO can hold 6144 stereo samples 48 * In 24bit configuration the FIFO can hold 4096 stereo samples 49 */ 50 #define DAC33_FIFO_SIZE_16BIT 6144 51 #define DAC33_FIFO_SIZE_24BIT 4096 52 #define DAC33_MODE7_MARGIN 10 /* Safety margin for FIFO in Mode7 */ 53 54 #define BURST_BASEFREQ_HZ 49152000 55 56 #define SAMPLES_TO_US(rate, samples) \ 57 (1000000000 / (((rate) * 1000) / (samples))) 58 59 #define US_TO_SAMPLES(rate, us) \ 60 ((rate) / (1000000 / ((us) < 1000000 ? (us) : 1000000))) 61 62 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \ 63 (((samples)*5000) / (((burstrate)*5000) / ((burstrate) - (playrate)))) 64 65 static void dac33_calculate_times(struct snd_pcm_substream *substream, 66 struct snd_soc_codec *codec); 67 static int dac33_prepare_chip(struct snd_pcm_substream *substream, 68 struct snd_soc_codec *codec); 69 70 enum dac33_state { 71 DAC33_IDLE = 0, 72 DAC33_PREFILL, 73 DAC33_PLAYBACK, 74 DAC33_FLUSH, 75 }; 76 77 enum dac33_fifo_modes { 78 DAC33_FIFO_BYPASS = 0, 79 DAC33_FIFO_MODE1, 80 DAC33_FIFO_MODE7, 81 DAC33_FIFO_LAST_MODE, 82 }; 83 84 #define DAC33_NUM_SUPPLIES 3 85 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = { 86 "AVDD", 87 "DVDD", 88 "IOVDD", 89 }; 90 91 struct tlv320dac33_priv { 92 struct mutex mutex; 93 struct work_struct work; 94 struct snd_soc_codec *codec; 95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES]; 96 struct snd_pcm_substream *substream; 97 int power_gpio; 98 int chip_power; 99 int irq; 100 unsigned int refclk; 101 102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */ 103 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */ 104 unsigned int fifo_size; /* Size of the FIFO in samples */ 105 unsigned int nsample; /* burst read amount from host */ 106 int mode1_latency; /* latency caused by the i2c writes in 107 * us */ 108 u8 burst_bclkdiv; /* BCLK divider value in burst mode */ 109 unsigned int burst_rate; /* Interface speed in Burst modes */ 110 111 int keep_bclk; /* Keep the BCLK continuously running 112 * in FIFO modes */ 113 spinlock_t lock; 114 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */ 115 unsigned long long t_stamp2; /* calculate the FIFO caused delay */ 116 117 unsigned int mode1_us_burst; /* Time to burst read n number of 118 * samples */ 119 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */ 120 121 unsigned int uthr; 122 123 enum dac33_state state; 124 void *control_data; 125 }; 126 127 static const u8 dac33_reg[DAC33_CACHEREGNUM] = { 128 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */ 129 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */ 130 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */ 131 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */ 132 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */ 133 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */ 134 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */ 135 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */ 136 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */ 137 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */ 138 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */ 139 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */ 140 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */ 141 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */ 142 0x00, 0x00, /* 0x38 - 0x39 */ 143 /* Registers 0x3a - 0x3f are reserved */ 144 0x00, 0x00, /* 0x3a - 0x3b */ 145 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */ 146 147 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */ 148 0x00, 0x80, /* 0x44 - 0x45 */ 149 /* Registers 0x46 - 0x47 are reserved */ 150 0x80, 0x80, /* 0x46 - 0x47 */ 151 152 0x80, 0x00, 0x00, /* 0x48 - 0x4a */ 153 /* Registers 0x4b - 0x7c are reserved */ 154 0x00, /* 0x4b */ 155 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */ 156 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */ 157 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */ 158 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */ 159 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */ 160 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */ 161 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */ 162 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */ 163 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */ 164 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */ 165 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */ 166 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */ 167 0x00, /* 0x7c */ 168 169 0xda, 0x33, 0x03, /* 0x7d - 0x7f */ 170 }; 171 172 /* Register read and write */ 173 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec, 174 unsigned reg) 175 { 176 u8 *cache = codec->reg_cache; 177 if (reg >= DAC33_CACHEREGNUM) 178 return 0; 179 180 return cache[reg]; 181 } 182 183 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec, 184 u8 reg, u8 value) 185 { 186 u8 *cache = codec->reg_cache; 187 if (reg >= DAC33_CACHEREGNUM) 188 return; 189 190 cache[reg] = value; 191 } 192 193 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg, 194 u8 *value) 195 { 196 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 197 int val, ret = 0; 198 199 *value = reg & 0xff; 200 201 /* If powered off, return the cached value */ 202 if (dac33->chip_power) { 203 val = i2c_smbus_read_byte_data(codec->control_data, value[0]); 204 if (val < 0) { 205 dev_err(codec->dev, "Read failed (%d)\n", val); 206 value[0] = dac33_read_reg_cache(codec, reg); 207 ret = val; 208 } else { 209 value[0] = val; 210 dac33_write_reg_cache(codec, reg, val); 211 } 212 } else { 213 value[0] = dac33_read_reg_cache(codec, reg); 214 } 215 216 return ret; 217 } 218 219 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg, 220 unsigned int value) 221 { 222 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 223 u8 data[2]; 224 int ret = 0; 225 226 /* 227 * data is 228 * D15..D8 dac33 register offset 229 * D7...D0 register data 230 */ 231 data[0] = reg & 0xff; 232 data[1] = value & 0xff; 233 234 dac33_write_reg_cache(codec, data[0], data[1]); 235 if (dac33->chip_power) { 236 ret = codec->hw_write(codec->control_data, data, 2); 237 if (ret != 2) 238 dev_err(codec->dev, "Write failed (%d)\n", ret); 239 else 240 ret = 0; 241 } 242 243 return ret; 244 } 245 246 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg, 247 unsigned int value) 248 { 249 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 250 int ret; 251 252 mutex_lock(&dac33->mutex); 253 ret = dac33_write(codec, reg, value); 254 mutex_unlock(&dac33->mutex); 255 256 return ret; 257 } 258 259 #define DAC33_I2C_ADDR_AUTOINC 0x80 260 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg, 261 unsigned int value) 262 { 263 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 264 u8 data[3]; 265 int ret = 0; 266 267 /* 268 * data is 269 * D23..D16 dac33 register offset 270 * D15..D8 register data MSB 271 * D7...D0 register data LSB 272 */ 273 data[0] = reg & 0xff; 274 data[1] = (value >> 8) & 0xff; 275 data[2] = value & 0xff; 276 277 dac33_write_reg_cache(codec, data[0], data[1]); 278 dac33_write_reg_cache(codec, data[0] + 1, data[2]); 279 280 if (dac33->chip_power) { 281 /* We need to set autoincrement mode for 16 bit writes */ 282 data[0] |= DAC33_I2C_ADDR_AUTOINC; 283 ret = codec->hw_write(codec->control_data, data, 3); 284 if (ret != 3) 285 dev_err(codec->dev, "Write failed (%d)\n", ret); 286 else 287 ret = 0; 288 } 289 290 return ret; 291 } 292 293 static void dac33_init_chip(struct snd_soc_codec *codec) 294 { 295 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 296 297 if (unlikely(!dac33->chip_power)) 298 return; 299 300 /* A : DAC sample rate Fsref/1.5 */ 301 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0)); 302 /* B : DAC src=normal, not muted */ 303 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT | 304 DAC33_DACSRCL_LEFT); 305 /* C : (defaults) */ 306 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00); 307 308 /* 73 : volume soft stepping control, 309 clock source = internal osc (?) */ 310 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN); 311 312 /* Restore only selected registers (gains mostly) */ 313 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL, 314 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL)); 315 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL, 316 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL)); 317 318 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL, 319 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL)); 320 dac33_write(codec, DAC33_LINER_TO_RLO_VOL, 321 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL)); 322 323 dac33_write(codec, DAC33_OUT_AMP_CTRL, 324 dac33_read_reg_cache(codec, DAC33_OUT_AMP_CTRL)); 325 326 dac33_write(codec, DAC33_LDAC_PWR_CTRL, 327 dac33_read_reg_cache(codec, DAC33_LDAC_PWR_CTRL)); 328 dac33_write(codec, DAC33_RDAC_PWR_CTRL, 329 dac33_read_reg_cache(codec, DAC33_RDAC_PWR_CTRL)); 330 } 331 332 static inline int dac33_read_id(struct snd_soc_codec *codec) 333 { 334 int i, ret = 0; 335 u8 reg; 336 337 for (i = 0; i < 3; i++) { 338 ret = dac33_read(codec, DAC33_DEVICE_ID_MSB + i, ®); 339 if (ret < 0) 340 break; 341 } 342 343 return ret; 344 } 345 346 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power) 347 { 348 u8 reg; 349 350 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); 351 if (power) 352 reg |= DAC33_PDNALLB; 353 else 354 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB | 355 DAC33_DACRPDNB | DAC33_DACLPDNB); 356 dac33_write(codec, DAC33_PWR_CTRL, reg); 357 } 358 359 static inline void dac33_disable_digital(struct snd_soc_codec *codec) 360 { 361 u8 reg; 362 363 /* Stop the DAI clock */ 364 reg = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 365 reg &= ~DAC33_BCLKON; 366 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, reg); 367 368 /* Power down the Oscillator, and DACs */ 369 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); 370 reg &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB); 371 dac33_write(codec, DAC33_PWR_CTRL, reg); 372 } 373 374 static int dac33_hard_power(struct snd_soc_codec *codec, int power) 375 { 376 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 377 int ret = 0; 378 379 mutex_lock(&dac33->mutex); 380 381 /* Safety check */ 382 if (unlikely(power == dac33->chip_power)) { 383 dev_dbg(codec->dev, "Trying to set the same power state: %s\n", 384 power ? "ON" : "OFF"); 385 goto exit; 386 } 387 388 if (power) { 389 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies), 390 dac33->supplies); 391 if (ret != 0) { 392 dev_err(codec->dev, 393 "Failed to enable supplies: %d\n", ret); 394 goto exit; 395 } 396 397 if (dac33->power_gpio >= 0) 398 gpio_set_value(dac33->power_gpio, 1); 399 400 dac33->chip_power = 1; 401 } else { 402 dac33_soft_power(codec, 0); 403 if (dac33->power_gpio >= 0) 404 gpio_set_value(dac33->power_gpio, 0); 405 406 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), 407 dac33->supplies); 408 if (ret != 0) { 409 dev_err(codec->dev, 410 "Failed to disable supplies: %d\n", ret); 411 goto exit; 412 } 413 414 dac33->chip_power = 0; 415 } 416 417 exit: 418 mutex_unlock(&dac33->mutex); 419 return ret; 420 } 421 422 static int dac33_playback_event(struct snd_soc_dapm_widget *w, 423 struct snd_kcontrol *kcontrol, int event) 424 { 425 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 426 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 427 428 switch (event) { 429 case SND_SOC_DAPM_PRE_PMU: 430 if (likely(dac33->substream)) { 431 dac33_calculate_times(dac33->substream, codec); 432 dac33_prepare_chip(dac33->substream, codec); 433 } 434 break; 435 case SND_SOC_DAPM_POST_PMD: 436 dac33_disable_digital(codec); 437 break; 438 } 439 return 0; 440 } 441 442 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol, 443 struct snd_ctl_elem_value *ucontrol) 444 { 445 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 446 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 447 448 ucontrol->value.enumerated.item[0] = dac33->fifo_mode; 449 450 return 0; 451 } 452 453 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol, 454 struct snd_ctl_elem_value *ucontrol) 455 { 456 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 457 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 458 int ret = 0; 459 460 if (dac33->fifo_mode == ucontrol->value.enumerated.item[0]) 461 return 0; 462 /* Do not allow changes while stream is running*/ 463 if (snd_soc_codec_is_active(codec)) 464 return -EPERM; 465 466 if (ucontrol->value.enumerated.item[0] >= DAC33_FIFO_LAST_MODE) 467 ret = -EINVAL; 468 else 469 dac33->fifo_mode = ucontrol->value.enumerated.item[0]; 470 471 return ret; 472 } 473 474 /* Codec operation modes */ 475 static const char *dac33_fifo_mode_texts[] = { 476 "Bypass", "Mode 1", "Mode 7" 477 }; 478 479 static SOC_ENUM_SINGLE_EXT_DECL(dac33_fifo_mode_enum, dac33_fifo_mode_texts); 480 481 /* L/R Line Output Gain */ 482 static const char *lr_lineout_gain_texts[] = { 483 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB", 484 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB", 485 }; 486 487 static SOC_ENUM_SINGLE_DECL(l_lineout_gain_enum, 488 DAC33_LDAC_PWR_CTRL, 0, 489 lr_lineout_gain_texts); 490 491 static SOC_ENUM_SINGLE_DECL(r_lineout_gain_enum, 492 DAC33_RDAC_PWR_CTRL, 0, 493 lr_lineout_gain_texts); 494 495 /* 496 * DACL/R digital volume control: 497 * from 0 dB to -63.5 in 0.5 dB steps 498 * Need to be inverted later on: 499 * 0x00 == 0 dB 500 * 0x7f == -63.5 dB 501 */ 502 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0); 503 504 static const struct snd_kcontrol_new dac33_snd_controls[] = { 505 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume", 506 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 507 0, 0x7f, 1, dac_digivol_tlv), 508 SOC_DOUBLE_R("DAC Digital Playback Switch", 509 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1), 510 SOC_DOUBLE_R("Line to Line Out Volume", 511 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1), 512 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum), 513 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum), 514 }; 515 516 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = { 517 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum, 518 dac33_get_fifo_mode, dac33_set_fifo_mode), 519 }; 520 521 /* Analog bypass */ 522 static const struct snd_kcontrol_new dac33_dapm_abypassl_control = 523 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1); 524 525 static const struct snd_kcontrol_new dac33_dapm_abypassr_control = 526 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1); 527 528 /* LOP L/R invert selection */ 529 static const char *dac33_lr_lom_texts[] = {"DAC", "LOP"}; 530 531 static SOC_ENUM_SINGLE_DECL(dac33_left_lom_enum, 532 DAC33_OUT_AMP_CTRL, 3, 533 dac33_lr_lom_texts); 534 535 static const struct snd_kcontrol_new dac33_dapm_left_lom_control = 536 SOC_DAPM_ENUM("Route", dac33_left_lom_enum); 537 538 static SOC_ENUM_SINGLE_DECL(dac33_right_lom_enum, 539 DAC33_OUT_AMP_CTRL, 2, 540 dac33_lr_lom_texts); 541 542 static const struct snd_kcontrol_new dac33_dapm_right_lom_control = 543 SOC_DAPM_ENUM("Route", dac33_right_lom_enum); 544 545 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = { 546 SND_SOC_DAPM_OUTPUT("LEFT_LO"), 547 SND_SOC_DAPM_OUTPUT("RIGHT_LO"), 548 549 SND_SOC_DAPM_INPUT("LINEL"), 550 SND_SOC_DAPM_INPUT("LINER"), 551 552 SND_SOC_DAPM_DAC("DACL", "Left Playback", SND_SOC_NOPM, 0, 0), 553 SND_SOC_DAPM_DAC("DACR", "Right Playback", SND_SOC_NOPM, 0, 0), 554 555 /* Analog bypass */ 556 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0, 557 &dac33_dapm_abypassl_control), 558 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0, 559 &dac33_dapm_abypassr_control), 560 561 SND_SOC_DAPM_MUX("Left LOM Inverted From", SND_SOC_NOPM, 0, 0, 562 &dac33_dapm_left_lom_control), 563 SND_SOC_DAPM_MUX("Right LOM Inverted From", SND_SOC_NOPM, 0, 0, 564 &dac33_dapm_right_lom_control), 565 /* 566 * For DAPM path, when only the anlog bypass path is enabled, and the 567 * LOP inverted from the corresponding DAC side. 568 * This is needed, so we can attach the DAC power supply in this case. 569 */ 570 SND_SOC_DAPM_PGA("Left Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 571 SND_SOC_DAPM_PGA("Right Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0), 572 573 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amplifier", 574 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0), 575 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amplifier", 576 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0), 577 578 SND_SOC_DAPM_SUPPLY("Left DAC Power", 579 DAC33_LDAC_PWR_CTRL, 2, 0, NULL, 0), 580 SND_SOC_DAPM_SUPPLY("Right DAC Power", 581 DAC33_RDAC_PWR_CTRL, 2, 0, NULL, 0), 582 583 SND_SOC_DAPM_SUPPLY("Codec Power", 584 DAC33_PWR_CTRL, 4, 0, NULL, 0), 585 586 SND_SOC_DAPM_PRE("Pre Playback", dac33_playback_event), 587 SND_SOC_DAPM_POST("Post Playback", dac33_playback_event), 588 }; 589 590 static const struct snd_soc_dapm_route audio_map[] = { 591 /* Analog bypass */ 592 {"Analog Left Bypass", "Switch", "LINEL"}, 593 {"Analog Right Bypass", "Switch", "LINER"}, 594 595 {"Output Left Amplifier", NULL, "DACL"}, 596 {"Output Right Amplifier", NULL, "DACR"}, 597 598 {"Left Bypass PGA", NULL, "Analog Left Bypass"}, 599 {"Right Bypass PGA", NULL, "Analog Right Bypass"}, 600 601 {"Left LOM Inverted From", "DAC", "Left Bypass PGA"}, 602 {"Right LOM Inverted From", "DAC", "Right Bypass PGA"}, 603 {"Left LOM Inverted From", "LOP", "Analog Left Bypass"}, 604 {"Right LOM Inverted From", "LOP", "Analog Right Bypass"}, 605 606 {"Output Left Amplifier", NULL, "Left LOM Inverted From"}, 607 {"Output Right Amplifier", NULL, "Right LOM Inverted From"}, 608 609 {"DACL", NULL, "Left DAC Power"}, 610 {"DACR", NULL, "Right DAC Power"}, 611 612 {"Left Bypass PGA", NULL, "Left DAC Power"}, 613 {"Right Bypass PGA", NULL, "Right DAC Power"}, 614 615 /* output */ 616 {"LEFT_LO", NULL, "Output Left Amplifier"}, 617 {"RIGHT_LO", NULL, "Output Right Amplifier"}, 618 619 {"LEFT_LO", NULL, "Codec Power"}, 620 {"RIGHT_LO", NULL, "Codec Power"}, 621 }; 622 623 static int dac33_set_bias_level(struct snd_soc_codec *codec, 624 enum snd_soc_bias_level level) 625 { 626 int ret; 627 628 switch (level) { 629 case SND_SOC_BIAS_ON: 630 break; 631 case SND_SOC_BIAS_PREPARE: 632 break; 633 case SND_SOC_BIAS_STANDBY: 634 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { 635 /* Coming from OFF, switch on the codec */ 636 ret = dac33_hard_power(codec, 1); 637 if (ret != 0) 638 return ret; 639 640 dac33_init_chip(codec); 641 } 642 break; 643 case SND_SOC_BIAS_OFF: 644 /* Do not power off, when the codec is already off */ 645 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) 646 return 0; 647 ret = dac33_hard_power(codec, 0); 648 if (ret != 0) 649 return ret; 650 break; 651 } 652 653 return 0; 654 } 655 656 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33) 657 { 658 struct snd_soc_codec *codec = dac33->codec; 659 unsigned int delay; 660 unsigned long flags; 661 662 switch (dac33->fifo_mode) { 663 case DAC33_FIFO_MODE1: 664 dac33_write16(codec, DAC33_NSAMPLE_MSB, 665 DAC33_THRREG(dac33->nsample)); 666 667 /* Take the timestamps */ 668 spin_lock_irqsave(&dac33->lock, flags); 669 dac33->t_stamp2 = ktime_to_us(ktime_get()); 670 dac33->t_stamp1 = dac33->t_stamp2; 671 spin_unlock_irqrestore(&dac33->lock, flags); 672 673 dac33_write16(codec, DAC33_PREFILL_MSB, 674 DAC33_THRREG(dac33->alarm_threshold)); 675 /* Enable Alarm Threshold IRQ with a delay */ 676 delay = SAMPLES_TO_US(dac33->burst_rate, 677 dac33->alarm_threshold) + 1000; 678 usleep_range(delay, delay + 500); 679 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT); 680 break; 681 case DAC33_FIFO_MODE7: 682 /* Take the timestamp */ 683 spin_lock_irqsave(&dac33->lock, flags); 684 dac33->t_stamp1 = ktime_to_us(ktime_get()); 685 /* Move back the timestamp with drain time */ 686 dac33->t_stamp1 -= dac33->mode7_us_to_lthr; 687 spin_unlock_irqrestore(&dac33->lock, flags); 688 689 dac33_write16(codec, DAC33_PREFILL_MSB, 690 DAC33_THRREG(DAC33_MODE7_MARGIN)); 691 692 /* Enable Upper Threshold IRQ */ 693 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT); 694 break; 695 default: 696 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 697 dac33->fifo_mode); 698 break; 699 } 700 } 701 702 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33) 703 { 704 struct snd_soc_codec *codec = dac33->codec; 705 unsigned long flags; 706 707 switch (dac33->fifo_mode) { 708 case DAC33_FIFO_MODE1: 709 /* Take the timestamp */ 710 spin_lock_irqsave(&dac33->lock, flags); 711 dac33->t_stamp2 = ktime_to_us(ktime_get()); 712 spin_unlock_irqrestore(&dac33->lock, flags); 713 714 dac33_write16(codec, DAC33_NSAMPLE_MSB, 715 DAC33_THRREG(dac33->nsample)); 716 break; 717 case DAC33_FIFO_MODE7: 718 /* At the moment we are not using interrupts in mode7 */ 719 break; 720 default: 721 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 722 dac33->fifo_mode); 723 break; 724 } 725 } 726 727 static void dac33_work(struct work_struct *work) 728 { 729 struct snd_soc_codec *codec; 730 struct tlv320dac33_priv *dac33; 731 u8 reg; 732 733 dac33 = container_of(work, struct tlv320dac33_priv, work); 734 codec = dac33->codec; 735 736 mutex_lock(&dac33->mutex); 737 switch (dac33->state) { 738 case DAC33_PREFILL: 739 dac33->state = DAC33_PLAYBACK; 740 dac33_prefill_handler(dac33); 741 break; 742 case DAC33_PLAYBACK: 743 dac33_playback_handler(dac33); 744 break; 745 case DAC33_IDLE: 746 break; 747 case DAC33_FLUSH: 748 dac33->state = DAC33_IDLE; 749 /* Mask all interrupts from dac33 */ 750 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0); 751 752 /* flush fifo */ 753 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); 754 reg |= DAC33_FIFOFLUSH; 755 dac33_write(codec, DAC33_FIFO_CTRL_A, reg); 756 break; 757 } 758 mutex_unlock(&dac33->mutex); 759 } 760 761 static irqreturn_t dac33_interrupt_handler(int irq, void *dev) 762 { 763 struct snd_soc_codec *codec = dev; 764 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 765 unsigned long flags; 766 767 spin_lock_irqsave(&dac33->lock, flags); 768 dac33->t_stamp1 = ktime_to_us(ktime_get()); 769 spin_unlock_irqrestore(&dac33->lock, flags); 770 771 /* Do not schedule the workqueue in Mode7 */ 772 if (dac33->fifo_mode != DAC33_FIFO_MODE7) 773 schedule_work(&dac33->work); 774 775 return IRQ_HANDLED; 776 } 777 778 static void dac33_oscwait(struct snd_soc_codec *codec) 779 { 780 int timeout = 60; 781 u8 reg; 782 783 do { 784 usleep_range(1000, 2000); 785 dac33_read(codec, DAC33_INT_OSC_STATUS, ®); 786 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--); 787 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) 788 dev_err(codec->dev, 789 "internal oscillator calibration failed\n"); 790 } 791 792 static int dac33_startup(struct snd_pcm_substream *substream, 793 struct snd_soc_dai *dai) 794 { 795 struct snd_soc_codec *codec = dai->codec; 796 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 797 798 /* Stream started, save the substream pointer */ 799 dac33->substream = substream; 800 801 return 0; 802 } 803 804 static void dac33_shutdown(struct snd_pcm_substream *substream, 805 struct snd_soc_dai *dai) 806 { 807 struct snd_soc_codec *codec = dai->codec; 808 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 809 810 dac33->substream = NULL; 811 } 812 813 #define CALC_BURST_RATE(bclkdiv, bclk_per_sample) \ 814 (BURST_BASEFREQ_HZ / bclkdiv / bclk_per_sample) 815 static int dac33_hw_params(struct snd_pcm_substream *substream, 816 struct snd_pcm_hw_params *params, 817 struct snd_soc_dai *dai) 818 { 819 struct snd_soc_codec *codec = dai->codec; 820 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 821 822 /* Check parameters for validity */ 823 switch (params_rate(params)) { 824 case 44100: 825 case 48000: 826 break; 827 default: 828 dev_err(codec->dev, "unsupported rate %d\n", 829 params_rate(params)); 830 return -EINVAL; 831 } 832 833 switch (params_width(params)) { 834 case 16: 835 dac33->fifo_size = DAC33_FIFO_SIZE_16BIT; 836 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 32); 837 break; 838 case 32: 839 dac33->fifo_size = DAC33_FIFO_SIZE_24BIT; 840 dac33->burst_rate = CALC_BURST_RATE(dac33->burst_bclkdiv, 64); 841 break; 842 default: 843 dev_err(codec->dev, "unsupported width %d\n", 844 params_width(params)); 845 return -EINVAL; 846 } 847 848 return 0; 849 } 850 851 #define CALC_OSCSET(rate, refclk) ( \ 852 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000) 853 #define CALC_RATIOSET(rate, refclk) ( \ 854 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000) 855 856 /* 857 * tlv320dac33 is strict on the sequence of the register writes, if the register 858 * writes happens in different order, than dac33 might end up in unknown state. 859 * Use the known, working sequence of register writes to initialize the dac33. 860 */ 861 static int dac33_prepare_chip(struct snd_pcm_substream *substream, 862 struct snd_soc_codec *codec) 863 { 864 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 865 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp; 866 u8 aictrl_a, aictrl_b, fifoctrl_a; 867 868 switch (substream->runtime->rate) { 869 case 44100: 870 case 48000: 871 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk); 872 ratioset = CALC_RATIOSET(substream->runtime->rate, 873 dac33->refclk); 874 break; 875 default: 876 dev_err(codec->dev, "unsupported rate %d\n", 877 substream->runtime->rate); 878 return -EINVAL; 879 } 880 881 882 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); 883 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK); 884 /* Read FIFO control A, and clear FIFO flush bit */ 885 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A); 886 fifoctrl_a &= ~DAC33_FIFOFLUSH; 887 888 fifoctrl_a &= ~DAC33_WIDTH; 889 switch (substream->runtime->format) { 890 case SNDRV_PCM_FORMAT_S16_LE: 891 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16); 892 fifoctrl_a |= DAC33_WIDTH; 893 break; 894 case SNDRV_PCM_FORMAT_S32_LE: 895 aictrl_a |= (DAC33_NCYCL_32 | DAC33_WLEN_24); 896 break; 897 default: 898 dev_err(codec->dev, "unsupported format %d\n", 899 substream->runtime->format); 900 return -EINVAL; 901 } 902 903 mutex_lock(&dac33->mutex); 904 905 if (!dac33->chip_power) { 906 /* 907 * Chip is not powered yet. 908 * Do the init in the dac33_set_bias_level later. 909 */ 910 mutex_unlock(&dac33->mutex); 911 return 0; 912 } 913 914 dac33_soft_power(codec, 0); 915 dac33_soft_power(codec, 1); 916 917 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); 918 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp); 919 920 /* Write registers 0x08 and 0x09 (MSB, LSB) */ 921 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset); 922 923 /* OSC calibration time */ 924 dac33_write(codec, DAC33_CALIB_TIME, 96); 925 926 /* adjustment treshold & step */ 927 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) | 928 DAC33_ADJSTEP(1)); 929 930 /* div=4 / gain=1 / div */ 931 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4)); 932 933 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL); 934 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB; 935 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl); 936 937 dac33_oscwait(codec); 938 939 if (dac33->fifo_mode) { 940 /* Generic for all FIFO modes */ 941 /* 50-51 : ASRC Control registers */ 942 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1)); 943 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */ 944 945 /* Write registers 0x34 and 0x35 (MSB, LSB) */ 946 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset); 947 948 /* Set interrupts to high active */ 949 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH); 950 } else { 951 /* FIFO bypass mode */ 952 /* 50-51 : ASRC Control registers */ 953 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP); 954 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */ 955 } 956 957 /* Interrupt behaviour configuration */ 958 switch (dac33->fifo_mode) { 959 case DAC33_FIFO_MODE1: 960 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B, 961 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL)); 962 break; 963 case DAC33_FIFO_MODE7: 964 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A, 965 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL)); 966 break; 967 default: 968 /* in FIFO bypass mode, the interrupts are not used */ 969 break; 970 } 971 972 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 973 974 switch (dac33->fifo_mode) { 975 case DAC33_FIFO_MODE1: 976 /* 977 * For mode1: 978 * Disable the FIFO bypass (Enable the use of FIFO) 979 * Select nSample mode 980 * BCLK is only running when data is needed by DAC33 981 */ 982 fifoctrl_a &= ~DAC33_FBYPAS; 983 fifoctrl_a &= ~DAC33_FAUTO; 984 if (dac33->keep_bclk) 985 aictrl_b |= DAC33_BCLKON; 986 else 987 aictrl_b &= ~DAC33_BCLKON; 988 break; 989 case DAC33_FIFO_MODE7: 990 /* 991 * For mode1: 992 * Disable the FIFO bypass (Enable the use of FIFO) 993 * Select Threshold mode 994 * BCLK is only running when data is needed by DAC33 995 */ 996 fifoctrl_a &= ~DAC33_FBYPAS; 997 fifoctrl_a |= DAC33_FAUTO; 998 if (dac33->keep_bclk) 999 aictrl_b |= DAC33_BCLKON; 1000 else 1001 aictrl_b &= ~DAC33_BCLKON; 1002 break; 1003 default: 1004 /* 1005 * For FIFO bypass mode: 1006 * Enable the FIFO bypass (Disable the FIFO use) 1007 * Set the BCLK as continuous 1008 */ 1009 fifoctrl_a |= DAC33_FBYPAS; 1010 aictrl_b |= DAC33_BCLKON; 1011 break; 1012 } 1013 1014 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a); 1015 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 1016 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); 1017 1018 /* 1019 * BCLK divide ratio 1020 * 0: 1.5 1021 * 1: 1 1022 * 2: 2 1023 * ... 1024 * 254: 254 1025 * 255: 255 1026 */ 1027 if (dac33->fifo_mode) 1028 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 1029 dac33->burst_bclkdiv); 1030 else 1031 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE) 1032 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32); 1033 else 1034 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 16); 1035 1036 switch (dac33->fifo_mode) { 1037 case DAC33_FIFO_MODE1: 1038 dac33_write16(codec, DAC33_ATHR_MSB, 1039 DAC33_THRREG(dac33->alarm_threshold)); 1040 break; 1041 case DAC33_FIFO_MODE7: 1042 /* 1043 * Configure the threshold levels, and leave 10 sample space 1044 * at the bottom, and also at the top of the FIFO 1045 */ 1046 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr)); 1047 dac33_write16(codec, DAC33_LTHR_MSB, 1048 DAC33_THRREG(DAC33_MODE7_MARGIN)); 1049 break; 1050 default: 1051 break; 1052 } 1053 1054 mutex_unlock(&dac33->mutex); 1055 1056 return 0; 1057 } 1058 1059 static void dac33_calculate_times(struct snd_pcm_substream *substream, 1060 struct snd_soc_codec *codec) 1061 { 1062 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1063 unsigned int period_size = substream->runtime->period_size; 1064 unsigned int rate = substream->runtime->rate; 1065 unsigned int nsample_limit; 1066 1067 /* In bypass mode we don't need to calculate */ 1068 if (!dac33->fifo_mode) 1069 return; 1070 1071 switch (dac33->fifo_mode) { 1072 case DAC33_FIFO_MODE1: 1073 /* Number of samples under i2c latency */ 1074 dac33->alarm_threshold = US_TO_SAMPLES(rate, 1075 dac33->mode1_latency); 1076 nsample_limit = dac33->fifo_size - dac33->alarm_threshold; 1077 1078 if (period_size <= dac33->alarm_threshold) 1079 /* 1080 * Configure nSamaple to number of periods, 1081 * which covers the latency requironment. 1082 */ 1083 dac33->nsample = period_size * 1084 ((dac33->alarm_threshold / period_size) + 1085 (dac33->alarm_threshold % period_size ? 1086 1 : 0)); 1087 else if (period_size > nsample_limit) 1088 dac33->nsample = nsample_limit; 1089 else 1090 dac33->nsample = period_size; 1091 1092 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate, 1093 dac33->nsample); 1094 dac33->t_stamp1 = 0; 1095 dac33->t_stamp2 = 0; 1096 break; 1097 case DAC33_FIFO_MODE7: 1098 dac33->uthr = UTHR_FROM_PERIOD_SIZE(period_size, rate, 1099 dac33->burst_rate) + 9; 1100 if (dac33->uthr > (dac33->fifo_size - DAC33_MODE7_MARGIN)) 1101 dac33->uthr = dac33->fifo_size - DAC33_MODE7_MARGIN; 1102 if (dac33->uthr < (DAC33_MODE7_MARGIN + 10)) 1103 dac33->uthr = (DAC33_MODE7_MARGIN + 10); 1104 1105 dac33->mode7_us_to_lthr = 1106 SAMPLES_TO_US(substream->runtime->rate, 1107 dac33->uthr - DAC33_MODE7_MARGIN + 1); 1108 dac33->t_stamp1 = 0; 1109 break; 1110 default: 1111 break; 1112 } 1113 1114 } 1115 1116 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd, 1117 struct snd_soc_dai *dai) 1118 { 1119 struct snd_soc_codec *codec = dai->codec; 1120 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1121 int ret = 0; 1122 1123 switch (cmd) { 1124 case SNDRV_PCM_TRIGGER_START: 1125 case SNDRV_PCM_TRIGGER_RESUME: 1126 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1127 if (dac33->fifo_mode) { 1128 dac33->state = DAC33_PREFILL; 1129 schedule_work(&dac33->work); 1130 } 1131 break; 1132 case SNDRV_PCM_TRIGGER_STOP: 1133 case SNDRV_PCM_TRIGGER_SUSPEND: 1134 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1135 if (dac33->fifo_mode) { 1136 dac33->state = DAC33_FLUSH; 1137 schedule_work(&dac33->work); 1138 } 1139 break; 1140 default: 1141 ret = -EINVAL; 1142 } 1143 1144 return ret; 1145 } 1146 1147 static snd_pcm_sframes_t dac33_dai_delay( 1148 struct snd_pcm_substream *substream, 1149 struct snd_soc_dai *dai) 1150 { 1151 struct snd_soc_codec *codec = dai->codec; 1152 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1153 unsigned long long t0, t1, t_now; 1154 unsigned int time_delta, uthr; 1155 int samples_out, samples_in, samples; 1156 snd_pcm_sframes_t delay = 0; 1157 unsigned long flags; 1158 1159 switch (dac33->fifo_mode) { 1160 case DAC33_FIFO_BYPASS: 1161 break; 1162 case DAC33_FIFO_MODE1: 1163 spin_lock_irqsave(&dac33->lock, flags); 1164 t0 = dac33->t_stamp1; 1165 t1 = dac33->t_stamp2; 1166 spin_unlock_irqrestore(&dac33->lock, flags); 1167 t_now = ktime_to_us(ktime_get()); 1168 1169 /* We have not started to fill the FIFO yet, delay is 0 */ 1170 if (!t1) 1171 goto out; 1172 1173 if (t0 > t1) { 1174 /* 1175 * Phase 1: 1176 * After Alarm threshold, and before nSample write 1177 */ 1178 time_delta = t_now - t0; 1179 samples_out = time_delta ? US_TO_SAMPLES( 1180 substream->runtime->rate, 1181 time_delta) : 0; 1182 1183 if (likely(dac33->alarm_threshold > samples_out)) 1184 delay = dac33->alarm_threshold - samples_out; 1185 else 1186 delay = 0; 1187 } else if ((t_now - t1) <= dac33->mode1_us_burst) { 1188 /* 1189 * Phase 2: 1190 * After nSample write (during burst operation) 1191 */ 1192 time_delta = t_now - t0; 1193 samples_out = time_delta ? US_TO_SAMPLES( 1194 substream->runtime->rate, 1195 time_delta) : 0; 1196 1197 time_delta = t_now - t1; 1198 samples_in = time_delta ? US_TO_SAMPLES( 1199 dac33->burst_rate, 1200 time_delta) : 0; 1201 1202 samples = dac33->alarm_threshold; 1203 samples += (samples_in - samples_out); 1204 1205 if (likely(samples > 0)) 1206 delay = samples; 1207 else 1208 delay = 0; 1209 } else { 1210 /* 1211 * Phase 3: 1212 * After burst operation, before next alarm threshold 1213 */ 1214 time_delta = t_now - t0; 1215 samples_out = time_delta ? US_TO_SAMPLES( 1216 substream->runtime->rate, 1217 time_delta) : 0; 1218 1219 samples_in = dac33->nsample; 1220 samples = dac33->alarm_threshold; 1221 samples += (samples_in - samples_out); 1222 1223 if (likely(samples > 0)) 1224 delay = samples > dac33->fifo_size ? 1225 dac33->fifo_size : samples; 1226 else 1227 delay = 0; 1228 } 1229 break; 1230 case DAC33_FIFO_MODE7: 1231 spin_lock_irqsave(&dac33->lock, flags); 1232 t0 = dac33->t_stamp1; 1233 uthr = dac33->uthr; 1234 spin_unlock_irqrestore(&dac33->lock, flags); 1235 t_now = ktime_to_us(ktime_get()); 1236 1237 /* We have not started to fill the FIFO yet, delay is 0 */ 1238 if (!t0) 1239 goto out; 1240 1241 if (t_now <= t0) { 1242 /* 1243 * Either the timestamps are messed or equal. Report 1244 * maximum delay 1245 */ 1246 delay = uthr; 1247 goto out; 1248 } 1249 1250 time_delta = t_now - t0; 1251 if (time_delta <= dac33->mode7_us_to_lthr) { 1252 /* 1253 * Phase 1: 1254 * After burst (draining phase) 1255 */ 1256 samples_out = US_TO_SAMPLES( 1257 substream->runtime->rate, 1258 time_delta); 1259 1260 if (likely(uthr > samples_out)) 1261 delay = uthr - samples_out; 1262 else 1263 delay = 0; 1264 } else { 1265 /* 1266 * Phase 2: 1267 * During burst operation 1268 */ 1269 time_delta = time_delta - dac33->mode7_us_to_lthr; 1270 1271 samples_out = US_TO_SAMPLES( 1272 substream->runtime->rate, 1273 time_delta); 1274 samples_in = US_TO_SAMPLES( 1275 dac33->burst_rate, 1276 time_delta); 1277 delay = DAC33_MODE7_MARGIN + samples_in - samples_out; 1278 1279 if (unlikely(delay > uthr)) 1280 delay = uthr; 1281 } 1282 break; 1283 default: 1284 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n", 1285 dac33->fifo_mode); 1286 break; 1287 } 1288 out: 1289 return delay; 1290 } 1291 1292 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1293 int clk_id, unsigned int freq, int dir) 1294 { 1295 struct snd_soc_codec *codec = codec_dai->codec; 1296 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1297 u8 ioc_reg, asrcb_reg; 1298 1299 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL); 1300 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B); 1301 switch (clk_id) { 1302 case TLV320DAC33_MCLK: 1303 ioc_reg |= DAC33_REFSEL; 1304 asrcb_reg |= DAC33_SRCREFSEL; 1305 break; 1306 case TLV320DAC33_SLEEPCLK: 1307 ioc_reg &= ~DAC33_REFSEL; 1308 asrcb_reg &= ~DAC33_SRCREFSEL; 1309 break; 1310 default: 1311 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id); 1312 break; 1313 } 1314 dac33->refclk = freq; 1315 1316 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg); 1317 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg); 1318 1319 return 0; 1320 } 1321 1322 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai, 1323 unsigned int fmt) 1324 { 1325 struct snd_soc_codec *codec = codec_dai->codec; 1326 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1327 u8 aictrl_a, aictrl_b; 1328 1329 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A); 1330 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B); 1331 /* set master/slave audio interface */ 1332 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1333 case SND_SOC_DAIFMT_CBM_CFM: 1334 /* Codec Master */ 1335 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK); 1336 break; 1337 case SND_SOC_DAIFMT_CBS_CFS: 1338 /* Codec Slave */ 1339 if (dac33->fifo_mode) { 1340 dev_err(codec->dev, "FIFO mode requires master mode\n"); 1341 return -EINVAL; 1342 } else 1343 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK); 1344 break; 1345 default: 1346 return -EINVAL; 1347 } 1348 1349 aictrl_a &= ~DAC33_AFMT_MASK; 1350 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1351 case SND_SOC_DAIFMT_I2S: 1352 aictrl_a |= DAC33_AFMT_I2S; 1353 break; 1354 case SND_SOC_DAIFMT_DSP_A: 1355 aictrl_a |= DAC33_AFMT_DSP; 1356 aictrl_b &= ~DAC33_DATA_DELAY_MASK; 1357 aictrl_b |= DAC33_DATA_DELAY(0); 1358 break; 1359 case SND_SOC_DAIFMT_RIGHT_J: 1360 aictrl_a |= DAC33_AFMT_RIGHT_J; 1361 break; 1362 case SND_SOC_DAIFMT_LEFT_J: 1363 aictrl_a |= DAC33_AFMT_LEFT_J; 1364 break; 1365 default: 1366 dev_err(codec->dev, "Unsupported format (%u)\n", 1367 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1368 return -EINVAL; 1369 } 1370 1371 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a); 1372 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b); 1373 1374 return 0; 1375 } 1376 1377 static int dac33_soc_probe(struct snd_soc_codec *codec) 1378 { 1379 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1380 int ret = 0; 1381 1382 codec->control_data = dac33->control_data; 1383 codec->hw_write = (hw_write_t) i2c_master_send; 1384 dac33->codec = codec; 1385 1386 /* Read the tlv320dac33 ID registers */ 1387 ret = dac33_hard_power(codec, 1); 1388 if (ret != 0) { 1389 dev_err(codec->dev, "Failed to power up codec: %d\n", ret); 1390 goto err_power; 1391 } 1392 ret = dac33_read_id(codec); 1393 dac33_hard_power(codec, 0); 1394 1395 if (ret < 0) { 1396 dev_err(codec->dev, "Failed to read chip ID: %d\n", ret); 1397 ret = -ENODEV; 1398 goto err_power; 1399 } 1400 1401 /* Check if the IRQ number is valid and request it */ 1402 if (dac33->irq >= 0) { 1403 ret = request_irq(dac33->irq, dac33_interrupt_handler, 1404 IRQF_TRIGGER_RISING, 1405 codec->component.name, codec); 1406 if (ret < 0) { 1407 dev_err(codec->dev, "Could not request IRQ%d (%d)\n", 1408 dac33->irq, ret); 1409 dac33->irq = -1; 1410 } 1411 if (dac33->irq != -1) { 1412 INIT_WORK(&dac33->work, dac33_work); 1413 } 1414 } 1415 1416 /* Only add the FIFO controls, if we have valid IRQ number */ 1417 if (dac33->irq >= 0) 1418 snd_soc_add_codec_controls(codec, dac33_mode_snd_controls, 1419 ARRAY_SIZE(dac33_mode_snd_controls)); 1420 1421 err_power: 1422 return ret; 1423 } 1424 1425 static int dac33_soc_remove(struct snd_soc_codec *codec) 1426 { 1427 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec); 1428 1429 if (dac33->irq >= 0) { 1430 free_irq(dac33->irq, dac33->codec); 1431 flush_work(&dac33->work); 1432 } 1433 return 0; 1434 } 1435 1436 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = { 1437 .read = dac33_read_reg_cache, 1438 .write = dac33_write_locked, 1439 .set_bias_level = dac33_set_bias_level, 1440 .idle_bias_off = true, 1441 .reg_cache_size = ARRAY_SIZE(dac33_reg), 1442 .reg_word_size = sizeof(u8), 1443 .reg_cache_default = dac33_reg, 1444 .probe = dac33_soc_probe, 1445 .remove = dac33_soc_remove, 1446 1447 .component_driver = { 1448 .controls = dac33_snd_controls, 1449 .num_controls = ARRAY_SIZE(dac33_snd_controls), 1450 .dapm_widgets = dac33_dapm_widgets, 1451 .num_dapm_widgets = ARRAY_SIZE(dac33_dapm_widgets), 1452 .dapm_routes = audio_map, 1453 .num_dapm_routes = ARRAY_SIZE(audio_map), 1454 }, 1455 }; 1456 1457 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \ 1458 SNDRV_PCM_RATE_48000) 1459 #define DAC33_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 1460 1461 static const struct snd_soc_dai_ops dac33_dai_ops = { 1462 .startup = dac33_startup, 1463 .shutdown = dac33_shutdown, 1464 .hw_params = dac33_hw_params, 1465 .trigger = dac33_pcm_trigger, 1466 .delay = dac33_dai_delay, 1467 .set_sysclk = dac33_set_dai_sysclk, 1468 .set_fmt = dac33_set_dai_fmt, 1469 }; 1470 1471 static struct snd_soc_dai_driver dac33_dai = { 1472 .name = "tlv320dac33-hifi", 1473 .playback = { 1474 .stream_name = "Playback", 1475 .channels_min = 2, 1476 .channels_max = 2, 1477 .rates = DAC33_RATES, 1478 .formats = DAC33_FORMATS, 1479 .sig_bits = 24, 1480 }, 1481 .ops = &dac33_dai_ops, 1482 }; 1483 1484 static int dac33_i2c_probe(struct i2c_client *client, 1485 const struct i2c_device_id *id) 1486 { 1487 struct tlv320dac33_platform_data *pdata; 1488 struct tlv320dac33_priv *dac33; 1489 int ret, i; 1490 1491 if (client->dev.platform_data == NULL) { 1492 dev_err(&client->dev, "Platform data not set\n"); 1493 return -ENODEV; 1494 } 1495 pdata = client->dev.platform_data; 1496 1497 dac33 = devm_kzalloc(&client->dev, sizeof(struct tlv320dac33_priv), 1498 GFP_KERNEL); 1499 if (dac33 == NULL) 1500 return -ENOMEM; 1501 1502 dac33->control_data = client; 1503 mutex_init(&dac33->mutex); 1504 spin_lock_init(&dac33->lock); 1505 1506 i2c_set_clientdata(client, dac33); 1507 1508 dac33->power_gpio = pdata->power_gpio; 1509 dac33->burst_bclkdiv = pdata->burst_bclkdiv; 1510 dac33->keep_bclk = pdata->keep_bclk; 1511 dac33->mode1_latency = pdata->mode1_latency; 1512 if (!dac33->mode1_latency) 1513 dac33->mode1_latency = 10000; /* 10ms */ 1514 dac33->irq = client->irq; 1515 /* Disable FIFO use by default */ 1516 dac33->fifo_mode = DAC33_FIFO_BYPASS; 1517 1518 /* Check if the reset GPIO number is valid and request it */ 1519 if (dac33->power_gpio >= 0) { 1520 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset"); 1521 if (ret < 0) { 1522 dev_err(&client->dev, 1523 "Failed to request reset GPIO (%d)\n", 1524 dac33->power_gpio); 1525 goto err_gpio; 1526 } 1527 gpio_direction_output(dac33->power_gpio, 0); 1528 } 1529 1530 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++) 1531 dac33->supplies[i].supply = dac33_supply_names[i]; 1532 1533 ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies), 1534 dac33->supplies); 1535 1536 if (ret != 0) { 1537 dev_err(&client->dev, "Failed to request supplies: %d\n", ret); 1538 goto err_get; 1539 } 1540 1541 ret = snd_soc_register_codec(&client->dev, 1542 &soc_codec_dev_tlv320dac33, &dac33_dai, 1); 1543 if (ret < 0) 1544 goto err_get; 1545 1546 return ret; 1547 err_get: 1548 if (dac33->power_gpio >= 0) 1549 gpio_free(dac33->power_gpio); 1550 err_gpio: 1551 return ret; 1552 } 1553 1554 static int dac33_i2c_remove(struct i2c_client *client) 1555 { 1556 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client); 1557 1558 if (unlikely(dac33->chip_power)) 1559 dac33_hard_power(dac33->codec, 0); 1560 1561 if (dac33->power_gpio >= 0) 1562 gpio_free(dac33->power_gpio); 1563 1564 snd_soc_unregister_codec(&client->dev); 1565 return 0; 1566 } 1567 1568 static const struct i2c_device_id tlv320dac33_i2c_id[] = { 1569 { 1570 .name = "tlv320dac33", 1571 .driver_data = 0, 1572 }, 1573 { }, 1574 }; 1575 MODULE_DEVICE_TABLE(i2c, tlv320dac33_i2c_id); 1576 1577 static struct i2c_driver tlv320dac33_i2c_driver = { 1578 .driver = { 1579 .name = "tlv320dac33-codec", 1580 }, 1581 .probe = dac33_i2c_probe, 1582 .remove = dac33_i2c_remove, 1583 .id_table = tlv320dac33_i2c_id, 1584 }; 1585 1586 module_i2c_driver(tlv320dac33_i2c_driver); 1587 1588 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver"); 1589 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1590 MODULE_LICENSE("GPL"); 1591