1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * ALSA SoC TLV320AIC3X codec driver 4 * 5 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 6 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 7 */ 8 9 #ifndef _AIC3X_H 10 #define _AIC3X_H 11 12 /* AIC3X register space */ 13 #define AIC3X_CACHEREGNUM 110 14 15 /* Page select register */ 16 #define AIC3X_PAGE_SELECT 0 17 /* Software reset register */ 18 #define AIC3X_RESET 1 19 /* Codec Sample rate select register */ 20 #define AIC3X_SAMPLE_RATE_SEL_REG 2 21 /* PLL progrramming register A */ 22 #define AIC3X_PLL_PROGA_REG 3 23 /* PLL progrramming register B */ 24 #define AIC3X_PLL_PROGB_REG 4 25 /* PLL progrramming register C */ 26 #define AIC3X_PLL_PROGC_REG 5 27 /* PLL progrramming register D */ 28 #define AIC3X_PLL_PROGD_REG 6 29 /* Codec datapath setup register */ 30 #define AIC3X_CODEC_DATAPATH_REG 7 31 /* Audio serial data interface control register A */ 32 #define AIC3X_ASD_INTF_CTRLA 8 33 /* Audio serial data interface control register B */ 34 #define AIC3X_ASD_INTF_CTRLB 9 35 /* Audio serial data interface control register C */ 36 #define AIC3X_ASD_INTF_CTRLC 10 37 /* Audio overflow status and PLL R value programming register */ 38 #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11 39 /* Audio codec digital filter control register */ 40 #define AIC3X_CODEC_DFILT_CTRL 12 41 /* Headset/button press detection register */ 42 #define AIC3X_HEADSET_DETECT_CTRL_A 13 43 #define AIC3X_HEADSET_DETECT_CTRL_B 14 44 /* ADC PGA Gain control registers */ 45 #define LADC_VOL 15 46 #define RADC_VOL 16 47 /* MIC3 control registers */ 48 #define MIC3LR_2_LADC_CTRL 17 49 #define MIC3LR_2_RADC_CTRL 18 50 /* Line1 Input control registers */ 51 #define LINE1L_2_LADC_CTRL 19 52 #define LINE1R_2_LADC_CTRL 21 53 #define LINE1R_2_RADC_CTRL 22 54 #define LINE1L_2_RADC_CTRL 24 55 /* Line2 Input control registers */ 56 #define LINE2L_2_LADC_CTRL 20 57 #define LINE2R_2_RADC_CTRL 23 58 /* MICBIAS Control Register */ 59 #define MICBIAS_CTRL 25 60 61 /* AGC Control Registers A, B, C */ 62 #define LAGC_CTRL_A 26 63 #define LAGC_CTRL_B 27 64 #define LAGC_CTRL_C 28 65 #define RAGC_CTRL_A 29 66 #define RAGC_CTRL_B 30 67 #define RAGC_CTRL_C 31 68 69 /* DAC Power and Left High Power Output control registers */ 70 #define DAC_PWR 37 71 #define HPLCOM_CFG 37 72 /* Right High Power Output control registers */ 73 #define HPRCOM_CFG 38 74 /* High Power Output Stage Control Register */ 75 #define HPOUT_SC 40 76 /* DAC Output Switching control registers */ 77 #define DAC_LINE_MUX 41 78 /* High Power Output Driver Pop Reduction registers */ 79 #define HPOUT_POP_REDUCTION 42 80 /* DAC Digital control registers */ 81 #define LDAC_VOL 43 82 #define RDAC_VOL 44 83 /* Left High Power Output control registers */ 84 #define LINE2L_2_HPLOUT_VOL 45 85 #define PGAL_2_HPLOUT_VOL 46 86 #define DACL1_2_HPLOUT_VOL 47 87 #define LINE2R_2_HPLOUT_VOL 48 88 #define PGAR_2_HPLOUT_VOL 49 89 #define DACR1_2_HPLOUT_VOL 50 90 #define HPLOUT_CTRL 51 91 /* Left High Power COM control registers */ 92 #define LINE2L_2_HPLCOM_VOL 52 93 #define PGAL_2_HPLCOM_VOL 53 94 #define DACL1_2_HPLCOM_VOL 54 95 #define LINE2R_2_HPLCOM_VOL 55 96 #define PGAR_2_HPLCOM_VOL 56 97 #define DACR1_2_HPLCOM_VOL 57 98 #define HPLCOM_CTRL 58 99 /* Right High Power Output control registers */ 100 #define LINE2L_2_HPROUT_VOL 59 101 #define PGAL_2_HPROUT_VOL 60 102 #define DACL1_2_HPROUT_VOL 61 103 #define LINE2R_2_HPROUT_VOL 62 104 #define PGAR_2_HPROUT_VOL 63 105 #define DACR1_2_HPROUT_VOL 64 106 #define HPROUT_CTRL 65 107 /* Right High Power COM control registers */ 108 #define LINE2L_2_HPRCOM_VOL 66 109 #define PGAL_2_HPRCOM_VOL 67 110 #define DACL1_2_HPRCOM_VOL 68 111 #define LINE2R_2_HPRCOM_VOL 69 112 #define PGAR_2_HPRCOM_VOL 70 113 #define DACR1_2_HPRCOM_VOL 71 114 #define HPRCOM_CTRL 72 115 /* Mono Line Output Plus/Minus control registers */ 116 #define LINE2L_2_MONOLOPM_VOL 73 117 #define PGAL_2_MONOLOPM_VOL 74 118 #define DACL1_2_MONOLOPM_VOL 75 119 #define LINE2R_2_MONOLOPM_VOL 76 120 #define PGAR_2_MONOLOPM_VOL 77 121 #define DACR1_2_MONOLOPM_VOL 78 122 #define MONOLOPM_CTRL 79 123 /* Class-D speaker driver on tlv320aic3007 */ 124 #define CLASSD_CTRL 73 125 /* Left Line Output Plus/Minus control registers */ 126 #define LINE2L_2_LLOPM_VOL 80 127 #define PGAL_2_LLOPM_VOL 81 128 #define DACL1_2_LLOPM_VOL 82 129 #define LINE2R_2_LLOPM_VOL 83 130 #define PGAR_2_LLOPM_VOL 84 131 #define DACR1_2_LLOPM_VOL 85 132 #define LLOPM_CTRL 86 133 /* Right Line Output Plus/Minus control registers */ 134 #define LINE2L_2_RLOPM_VOL 87 135 #define PGAL_2_RLOPM_VOL 88 136 #define DACL1_2_RLOPM_VOL 89 137 #define LINE2R_2_RLOPM_VOL 90 138 #define PGAR_2_RLOPM_VOL 91 139 #define DACR1_2_RLOPM_VOL 92 140 #define RLOPM_CTRL 93 141 /* GPIO/IRQ registers */ 142 #define AIC3X_STICKY_IRQ_FLAGS_REG 96 143 #define AIC3X_RT_IRQ_FLAGS_REG 97 144 #define AIC3X_GPIO1_REG 98 145 #define AIC3X_GPIO2_REG 99 146 #define AIC3X_GPIOA_REG 100 147 #define AIC3X_GPIOB_REG 101 148 /* Clock generation control register */ 149 #define AIC3X_CLKGEN_CTRL_REG 102 150 /* New AGC registers */ 151 #define LAGCN_ATTACK 103 152 #define LAGCN_DECAY 104 153 #define RAGCN_ATTACK 105 154 #define RAGCN_DECAY 106 155 /* New Programmable ADC Digital Path and I2C Bus Condition Register */ 156 #define NEW_ADC_DIGITALPATH 107 157 /* Passive Analog Signal Bypass Selection During Powerdown Register */ 158 #define PASSIVE_BYPASS 108 159 /* DAC Quiescent Current Adjustment Register */ 160 #define DAC_ICC_ADJ 109 161 162 /* Page select register bits */ 163 #define PAGE0_SELECT 0 164 #define PAGE1_SELECT 1 165 166 /* Audio serial data interface control register A bits */ 167 #define BIT_CLK_MASTER 0x80 168 #define WORD_CLK_MASTER 0x40 169 #define DOUT_TRISTATE 0x20 170 171 /* Codec Datapath setup register 7 */ 172 #define FSREF_44100 (1 << 7) 173 #define FSREF_48000 (0 << 7) 174 #define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) 175 #define LDAC2LCH (0x1 << 3) 176 #define RDAC2RCH (0x1 << 1) 177 #define LDAC2RCH (0x2 << 3) 178 #define RDAC2LCH (0x2 << 1) 179 #define LDAC2MONOMIX (0x3 << 3) 180 #define RDAC2MONOMIX (0x3 << 1) 181 182 /* PLL registers bitfields */ 183 #define PLLP_SHIFT 0 184 #define PLLP_MASK 7 185 #define PLLQ_SHIFT 3 186 #define PLLR_SHIFT 0 187 #define PLLJ_SHIFT 2 188 #define PLLD_MSB_SHIFT 0 189 #define PLLD_LSB_SHIFT 2 190 191 /* Clock generation register bits */ 192 #define CODEC_CLKIN_PLLDIV 0 193 #define CODEC_CLKIN_CLKDIV 1 194 #define PLL_CLKIN_SHIFT 4 195 #define MCLK_SOURCE 0x0 196 #define PLL_CLKDIV_SHIFT 0 197 #define PLLCLK_IN_MASK 0x30 198 #define PLLCLK_IN_SHIFT 4 199 #define CLKDIV_IN_MASK 0xc0 200 #define CLKDIV_IN_SHIFT 6 201 /* clock in source */ 202 #define CLKIN_MCLK 0 203 #define CLKIN_GPIO2 1 204 #define CLKIN_BCLK 2 205 206 /* Software reset register bits */ 207 #define SOFT_RESET 0x80 208 209 /* PLL progrramming register A bits */ 210 #define PLL_ENABLE 0x80 211 212 /* Route bits */ 213 #define ROUTE_ON 0x80 214 215 /* Mute bits */ 216 #define UNMUTE 0x08 217 #define MUTE_ON 0x80 218 219 /* Power bits */ 220 #define LADC_PWR_ON 0x04 221 #define RADC_PWR_ON 0x04 222 #define LDAC_PWR_ON 0x80 223 #define RDAC_PWR_ON 0x40 224 #define HPLOUT_PWR_ON 0x01 225 #define HPROUT_PWR_ON 0x01 226 #define HPLCOM_PWR_ON 0x01 227 #define HPRCOM_PWR_ON 0x01 228 #define MONOLOPM_PWR_ON 0x01 229 #define LLOPM_PWR_ON 0x01 230 #define RLOPM_PWR_ON 0x01 231 232 #define INVERT_VOL(val) (0x7f - val) 233 234 /* Default output volume (inverted) */ 235 #define DEFAULT_VOL INVERT_VOL(0x50) 236 /* Default input volume */ 237 #define DEFAULT_GAIN 0x20 238 239 /* MICBIAS Control Register */ 240 #define MICBIAS_LEVEL_SHIFT (6) 241 #define MICBIAS_LEVEL_MASK (3 << 6) 242 243 /* HPOUT_SC */ 244 #define HPOUT_SC_OCMV_MASK (3 << 6) 245 #define HPOUT_SC_OCMV_SHIFT (6) 246 #define HPOUT_SC_OCMV_1_35V 0 247 #define HPOUT_SC_OCMV_1_5V 1 248 #define HPOUT_SC_OCMV_1_65V 2 249 #define HPOUT_SC_OCMV_1_8V 3 250 251 /* headset detection / button API */ 252 253 /* The AIC3x supports detection of stereo headsets (GND + left + right signal) 254 * and cellular headsets (GND + speaker output + microphone input). 255 * It is recommended to enable MIC bias for this function to work properly. 256 * For more information, please refer to the datasheet. */ 257 enum { 258 AIC3X_HEADSET_DETECT_OFF = 0, 259 AIC3X_HEADSET_DETECT_STEREO = 1, 260 AIC3X_HEADSET_DETECT_CELLULAR = 2, 261 AIC3X_HEADSET_DETECT_BOTH = 3 262 }; 263 264 enum { 265 AIC3X_HEADSET_DEBOUNCE_16MS = 0, 266 AIC3X_HEADSET_DEBOUNCE_32MS = 1, 267 AIC3X_HEADSET_DEBOUNCE_64MS = 2, 268 AIC3X_HEADSET_DEBOUNCE_128MS = 3, 269 AIC3X_HEADSET_DEBOUNCE_256MS = 4, 270 AIC3X_HEADSET_DEBOUNCE_512MS = 5 271 }; 272 273 enum { 274 AIC3X_BUTTON_DEBOUNCE_0MS = 0, 275 AIC3X_BUTTON_DEBOUNCE_8MS = 1, 276 AIC3X_BUTTON_DEBOUNCE_16MS = 2, 277 AIC3X_BUTTON_DEBOUNCE_32MS = 3 278 }; 279 280 #define AIC3X_HEADSET_DETECT_ENABLED 0x80 281 #define AIC3X_HEADSET_DETECT_SHIFT 5 282 #define AIC3X_HEADSET_DETECT_MASK 3 283 #define AIC3X_HEADSET_DEBOUNCE_SHIFT 2 284 #define AIC3X_HEADSET_DEBOUNCE_MASK 7 285 #define AIC3X_BUTTON_DEBOUNCE_SHIFT 0 286 #define AIC3X_BUTTON_DEBOUNCE_MASK 3 287 288 #endif /* _AIC3X_H */ 289