1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * ALSA SoC TLV320AIC3X codec driver 4 * 5 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 6 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 7 */ 8 9 #ifndef _AIC3X_H 10 #define _AIC3X_H 11 12 struct device; 13 struct regmap_config; 14 15 extern const struct regmap_config aic3x_regmap; 16 int aic3x_probe(struct device *dev, struct regmap *regmap, kernel_ulong_t driver_data); 17 int aic3x_remove(struct device *dev); 18 19 #define AIC3X_MODEL_3X 0 20 #define AIC3X_MODEL_33 1 21 #define AIC3X_MODEL_3007 2 22 #define AIC3X_MODEL_3104 3 23 24 /* AIC3X register space */ 25 #define AIC3X_CACHEREGNUM 110 26 27 /* Page select register */ 28 #define AIC3X_PAGE_SELECT 0 29 /* Software reset register */ 30 #define AIC3X_RESET 1 31 /* Codec Sample rate select register */ 32 #define AIC3X_SAMPLE_RATE_SEL_REG 2 33 /* PLL progrramming register A */ 34 #define AIC3X_PLL_PROGA_REG 3 35 /* PLL progrramming register B */ 36 #define AIC3X_PLL_PROGB_REG 4 37 /* PLL progrramming register C */ 38 #define AIC3X_PLL_PROGC_REG 5 39 /* PLL progrramming register D */ 40 #define AIC3X_PLL_PROGD_REG 6 41 /* Codec datapath setup register */ 42 #define AIC3X_CODEC_DATAPATH_REG 7 43 /* Audio serial data interface control register A */ 44 #define AIC3X_ASD_INTF_CTRLA 8 45 /* Audio serial data interface control register B */ 46 #define AIC3X_ASD_INTF_CTRLB 9 47 /* Audio serial data interface control register C */ 48 #define AIC3X_ASD_INTF_CTRLC 10 49 /* Audio overflow status and PLL R value programming register */ 50 #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11 51 /* Audio codec digital filter control register */ 52 #define AIC3X_CODEC_DFILT_CTRL 12 53 /* Headset/button press detection register */ 54 #define AIC3X_HEADSET_DETECT_CTRL_A 13 55 #define AIC3X_HEADSET_DETECT_CTRL_B 14 56 /* ADC PGA Gain control registers */ 57 #define LADC_VOL 15 58 #define RADC_VOL 16 59 /* MIC3 control registers */ 60 #define MIC3LR_2_LADC_CTRL 17 61 #define MIC3LR_2_RADC_CTRL 18 62 /* Line1 Input control registers */ 63 #define LINE1L_2_LADC_CTRL 19 64 #define LINE1R_2_LADC_CTRL 21 65 #define LINE1R_2_RADC_CTRL 22 66 #define LINE1L_2_RADC_CTRL 24 67 /* Line2 Input control registers */ 68 #define LINE2L_2_LADC_CTRL 20 69 #define LINE2R_2_RADC_CTRL 23 70 /* MICBIAS Control Register */ 71 #define MICBIAS_CTRL 25 72 73 /* AGC Control Registers A, B, C */ 74 #define LAGC_CTRL_A 26 75 #define LAGC_CTRL_B 27 76 #define LAGC_CTRL_C 28 77 #define RAGC_CTRL_A 29 78 #define RAGC_CTRL_B 30 79 #define RAGC_CTRL_C 31 80 81 /* DAC Power and Left High Power Output control registers */ 82 #define DAC_PWR 37 83 #define HPLCOM_CFG 37 84 /* Right High Power Output control registers */ 85 #define HPRCOM_CFG 38 86 /* High Power Output Stage Control Register */ 87 #define HPOUT_SC 40 88 /* DAC Output Switching control registers */ 89 #define DAC_LINE_MUX 41 90 /* High Power Output Driver Pop Reduction registers */ 91 #define HPOUT_POP_REDUCTION 42 92 /* DAC Digital control registers */ 93 #define LDAC_VOL 43 94 #define RDAC_VOL 44 95 /* Left High Power Output control registers */ 96 #define LINE2L_2_HPLOUT_VOL 45 97 #define PGAL_2_HPLOUT_VOL 46 98 #define DACL1_2_HPLOUT_VOL 47 99 #define LINE2R_2_HPLOUT_VOL 48 100 #define PGAR_2_HPLOUT_VOL 49 101 #define DACR1_2_HPLOUT_VOL 50 102 #define HPLOUT_CTRL 51 103 /* Left High Power COM control registers */ 104 #define LINE2L_2_HPLCOM_VOL 52 105 #define PGAL_2_HPLCOM_VOL 53 106 #define DACL1_2_HPLCOM_VOL 54 107 #define LINE2R_2_HPLCOM_VOL 55 108 #define PGAR_2_HPLCOM_VOL 56 109 #define DACR1_2_HPLCOM_VOL 57 110 #define HPLCOM_CTRL 58 111 /* Right High Power Output control registers */ 112 #define LINE2L_2_HPROUT_VOL 59 113 #define PGAL_2_HPROUT_VOL 60 114 #define DACL1_2_HPROUT_VOL 61 115 #define LINE2R_2_HPROUT_VOL 62 116 #define PGAR_2_HPROUT_VOL 63 117 #define DACR1_2_HPROUT_VOL 64 118 #define HPROUT_CTRL 65 119 /* Right High Power COM control registers */ 120 #define LINE2L_2_HPRCOM_VOL 66 121 #define PGAL_2_HPRCOM_VOL 67 122 #define DACL1_2_HPRCOM_VOL 68 123 #define LINE2R_2_HPRCOM_VOL 69 124 #define PGAR_2_HPRCOM_VOL 70 125 #define DACR1_2_HPRCOM_VOL 71 126 #define HPRCOM_CTRL 72 127 /* Mono Line Output Plus/Minus control registers */ 128 #define LINE2L_2_MONOLOPM_VOL 73 129 #define PGAL_2_MONOLOPM_VOL 74 130 #define DACL1_2_MONOLOPM_VOL 75 131 #define LINE2R_2_MONOLOPM_VOL 76 132 #define PGAR_2_MONOLOPM_VOL 77 133 #define DACR1_2_MONOLOPM_VOL 78 134 #define MONOLOPM_CTRL 79 135 /* Class-D speaker driver on tlv320aic3007 */ 136 #define CLASSD_CTRL 73 137 /* Left Line Output Plus/Minus control registers */ 138 #define LINE2L_2_LLOPM_VOL 80 139 #define PGAL_2_LLOPM_VOL 81 140 #define DACL1_2_LLOPM_VOL 82 141 #define LINE2R_2_LLOPM_VOL 83 142 #define PGAR_2_LLOPM_VOL 84 143 #define DACR1_2_LLOPM_VOL 85 144 #define LLOPM_CTRL 86 145 /* Right Line Output Plus/Minus control registers */ 146 #define LINE2L_2_RLOPM_VOL 87 147 #define PGAL_2_RLOPM_VOL 88 148 #define DACL1_2_RLOPM_VOL 89 149 #define LINE2R_2_RLOPM_VOL 90 150 #define PGAR_2_RLOPM_VOL 91 151 #define DACR1_2_RLOPM_VOL 92 152 #define RLOPM_CTRL 93 153 /* GPIO/IRQ registers */ 154 #define AIC3X_STICKY_IRQ_FLAGS_REG 96 155 #define AIC3X_RT_IRQ_FLAGS_REG 97 156 #define AIC3X_GPIO1_REG 98 157 #define AIC3X_GPIO2_REG 99 158 #define AIC3X_GPIOA_REG 100 159 #define AIC3X_GPIOB_REG 101 160 /* Clock generation control register */ 161 #define AIC3X_CLKGEN_CTRL_REG 102 162 /* New AGC registers */ 163 #define LAGCN_ATTACK 103 164 #define LAGCN_DECAY 104 165 #define RAGCN_ATTACK 105 166 #define RAGCN_DECAY 106 167 /* New Programmable ADC Digital Path and I2C Bus Condition Register */ 168 #define NEW_ADC_DIGITALPATH 107 169 /* Passive Analog Signal Bypass Selection During Powerdown Register */ 170 #define PASSIVE_BYPASS 108 171 /* DAC Quiescent Current Adjustment Register */ 172 #define DAC_ICC_ADJ 109 173 174 /* Page select register bits */ 175 #define PAGE0_SELECT 0 176 #define PAGE1_SELECT 1 177 178 /* Audio serial data interface control register A bits */ 179 #define BIT_CLK_MASTER 0x80 180 #define WORD_CLK_MASTER 0x40 181 #define DOUT_TRISTATE 0x20 182 183 /* Codec Datapath setup register 7 */ 184 #define FSREF_44100 (1 << 7) 185 #define FSREF_48000 (0 << 7) 186 #define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) 187 #define LDAC2LCH (0x1 << 3) 188 #define RDAC2RCH (0x1 << 1) 189 #define LDAC2RCH (0x2 << 3) 190 #define RDAC2LCH (0x2 << 1) 191 #define LDAC2MONOMIX (0x3 << 3) 192 #define RDAC2MONOMIX (0x3 << 1) 193 194 /* PLL registers bitfields */ 195 #define PLLP_SHIFT 0 196 #define PLLP_MASK 7 197 #define PLLQ_SHIFT 3 198 #define PLLR_SHIFT 0 199 #define PLLJ_SHIFT 2 200 #define PLLD_MSB_SHIFT 0 201 #define PLLD_LSB_SHIFT 2 202 203 /* Clock generation register bits */ 204 #define CODEC_CLKIN_PLLDIV 0 205 #define CODEC_CLKIN_CLKDIV 1 206 #define PLL_CLKIN_SHIFT 4 207 #define MCLK_SOURCE 0x0 208 #define PLL_CLKDIV_SHIFT 0 209 #define PLLCLK_IN_MASK 0x30 210 #define PLLCLK_IN_SHIFT 4 211 #define CLKDIV_IN_MASK 0xc0 212 #define CLKDIV_IN_SHIFT 6 213 /* clock in source */ 214 #define CLKIN_MCLK 0 215 #define CLKIN_GPIO2 1 216 #define CLKIN_BCLK 2 217 218 /* Software reset register bits */ 219 #define SOFT_RESET 0x80 220 221 /* PLL progrramming register A bits */ 222 #define PLL_ENABLE 0x80 223 224 /* Route bits */ 225 #define ROUTE_ON 0x80 226 227 /* Mute bits */ 228 #define UNMUTE 0x08 229 #define MUTE_ON 0x80 230 231 /* Power bits */ 232 #define LADC_PWR_ON 0x04 233 #define RADC_PWR_ON 0x04 234 #define LDAC_PWR_ON 0x80 235 #define RDAC_PWR_ON 0x40 236 #define HPLOUT_PWR_ON 0x01 237 #define HPROUT_PWR_ON 0x01 238 #define HPLCOM_PWR_ON 0x01 239 #define HPRCOM_PWR_ON 0x01 240 #define MONOLOPM_PWR_ON 0x01 241 #define LLOPM_PWR_ON 0x01 242 #define RLOPM_PWR_ON 0x01 243 244 #define INVERT_VOL(val) (0x7f - val) 245 246 /* Default output volume (inverted) */ 247 #define DEFAULT_VOL INVERT_VOL(0x50) 248 /* Default input volume */ 249 #define DEFAULT_GAIN 0x20 250 251 /* MICBIAS Control Register */ 252 #define MICBIAS_LEVEL_SHIFT (6) 253 #define MICBIAS_LEVEL_MASK (3 << 6) 254 255 /* HPOUT_SC */ 256 #define HPOUT_SC_OCMV_MASK (3 << 6) 257 #define HPOUT_SC_OCMV_SHIFT (6) 258 #define HPOUT_SC_OCMV_1_35V 0 259 #define HPOUT_SC_OCMV_1_5V 1 260 #define HPOUT_SC_OCMV_1_65V 2 261 #define HPOUT_SC_OCMV_1_8V 3 262 263 /* headset detection / button API */ 264 265 /* The AIC3x supports detection of stereo headsets (GND + left + right signal) 266 * and cellular headsets (GND + speaker output + microphone input). 267 * It is recommended to enable MIC bias for this function to work properly. 268 * For more information, please refer to the datasheet. */ 269 enum { 270 AIC3X_HEADSET_DETECT_OFF = 0, 271 AIC3X_HEADSET_DETECT_STEREO = 1, 272 AIC3X_HEADSET_DETECT_CELLULAR = 2, 273 AIC3X_HEADSET_DETECT_BOTH = 3 274 }; 275 276 enum { 277 AIC3X_HEADSET_DEBOUNCE_16MS = 0, 278 AIC3X_HEADSET_DEBOUNCE_32MS = 1, 279 AIC3X_HEADSET_DEBOUNCE_64MS = 2, 280 AIC3X_HEADSET_DEBOUNCE_128MS = 3, 281 AIC3X_HEADSET_DEBOUNCE_256MS = 4, 282 AIC3X_HEADSET_DEBOUNCE_512MS = 5 283 }; 284 285 enum { 286 AIC3X_BUTTON_DEBOUNCE_0MS = 0, 287 AIC3X_BUTTON_DEBOUNCE_8MS = 1, 288 AIC3X_BUTTON_DEBOUNCE_16MS = 2, 289 AIC3X_BUTTON_DEBOUNCE_32MS = 3 290 }; 291 292 #define AIC3X_HEADSET_DETECT_ENABLED 0x80 293 #define AIC3X_HEADSET_DETECT_SHIFT 5 294 #define AIC3X_HEADSET_DETECT_MASK 3 295 #define AIC3X_HEADSET_DEBOUNCE_SHIFT 2 296 #define AIC3X_HEADSET_DEBOUNCE_MASK 7 297 #define AIC3X_BUTTON_DEBOUNCE_SHIFT 0 298 #define AIC3X_BUTTON_DEBOUNCE_MASK 3 299 300 #endif /* _AIC3X_H */ 301