1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * ALSA SoC TLV320AIC3X codec driver 4 * 5 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 6 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 7 */ 8 9 #ifndef _AIC3X_H 10 #define _AIC3X_H 11 12 #define AIC3X_MODEL_3X 0 13 #define AIC3X_MODEL_33 1 14 #define AIC3X_MODEL_3007 2 15 #define AIC3X_MODEL_3104 3 16 17 /* AIC3X register space */ 18 #define AIC3X_CACHEREGNUM 110 19 20 /* Page select register */ 21 #define AIC3X_PAGE_SELECT 0 22 /* Software reset register */ 23 #define AIC3X_RESET 1 24 /* Codec Sample rate select register */ 25 #define AIC3X_SAMPLE_RATE_SEL_REG 2 26 /* PLL progrramming register A */ 27 #define AIC3X_PLL_PROGA_REG 3 28 /* PLL progrramming register B */ 29 #define AIC3X_PLL_PROGB_REG 4 30 /* PLL progrramming register C */ 31 #define AIC3X_PLL_PROGC_REG 5 32 /* PLL progrramming register D */ 33 #define AIC3X_PLL_PROGD_REG 6 34 /* Codec datapath setup register */ 35 #define AIC3X_CODEC_DATAPATH_REG 7 36 /* Audio serial data interface control register A */ 37 #define AIC3X_ASD_INTF_CTRLA 8 38 /* Audio serial data interface control register B */ 39 #define AIC3X_ASD_INTF_CTRLB 9 40 /* Audio serial data interface control register C */ 41 #define AIC3X_ASD_INTF_CTRLC 10 42 /* Audio overflow status and PLL R value programming register */ 43 #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11 44 /* Audio codec digital filter control register */ 45 #define AIC3X_CODEC_DFILT_CTRL 12 46 /* Headset/button press detection register */ 47 #define AIC3X_HEADSET_DETECT_CTRL_A 13 48 #define AIC3X_HEADSET_DETECT_CTRL_B 14 49 /* ADC PGA Gain control registers */ 50 #define LADC_VOL 15 51 #define RADC_VOL 16 52 /* MIC3 control registers */ 53 #define MIC3LR_2_LADC_CTRL 17 54 #define MIC3LR_2_RADC_CTRL 18 55 /* Line1 Input control registers */ 56 #define LINE1L_2_LADC_CTRL 19 57 #define LINE1R_2_LADC_CTRL 21 58 #define LINE1R_2_RADC_CTRL 22 59 #define LINE1L_2_RADC_CTRL 24 60 /* Line2 Input control registers */ 61 #define LINE2L_2_LADC_CTRL 20 62 #define LINE2R_2_RADC_CTRL 23 63 /* MICBIAS Control Register */ 64 #define MICBIAS_CTRL 25 65 66 /* AGC Control Registers A, B, C */ 67 #define LAGC_CTRL_A 26 68 #define LAGC_CTRL_B 27 69 #define LAGC_CTRL_C 28 70 #define RAGC_CTRL_A 29 71 #define RAGC_CTRL_B 30 72 #define RAGC_CTRL_C 31 73 74 /* DAC Power and Left High Power Output control registers */ 75 #define DAC_PWR 37 76 #define HPLCOM_CFG 37 77 /* Right High Power Output control registers */ 78 #define HPRCOM_CFG 38 79 /* High Power Output Stage Control Register */ 80 #define HPOUT_SC 40 81 /* DAC Output Switching control registers */ 82 #define DAC_LINE_MUX 41 83 /* High Power Output Driver Pop Reduction registers */ 84 #define HPOUT_POP_REDUCTION 42 85 /* DAC Digital control registers */ 86 #define LDAC_VOL 43 87 #define RDAC_VOL 44 88 /* Left High Power Output control registers */ 89 #define LINE2L_2_HPLOUT_VOL 45 90 #define PGAL_2_HPLOUT_VOL 46 91 #define DACL1_2_HPLOUT_VOL 47 92 #define LINE2R_2_HPLOUT_VOL 48 93 #define PGAR_2_HPLOUT_VOL 49 94 #define DACR1_2_HPLOUT_VOL 50 95 #define HPLOUT_CTRL 51 96 /* Left High Power COM control registers */ 97 #define LINE2L_2_HPLCOM_VOL 52 98 #define PGAL_2_HPLCOM_VOL 53 99 #define DACL1_2_HPLCOM_VOL 54 100 #define LINE2R_2_HPLCOM_VOL 55 101 #define PGAR_2_HPLCOM_VOL 56 102 #define DACR1_2_HPLCOM_VOL 57 103 #define HPLCOM_CTRL 58 104 /* Right High Power Output control registers */ 105 #define LINE2L_2_HPROUT_VOL 59 106 #define PGAL_2_HPROUT_VOL 60 107 #define DACL1_2_HPROUT_VOL 61 108 #define LINE2R_2_HPROUT_VOL 62 109 #define PGAR_2_HPROUT_VOL 63 110 #define DACR1_2_HPROUT_VOL 64 111 #define HPROUT_CTRL 65 112 /* Right High Power COM control registers */ 113 #define LINE2L_2_HPRCOM_VOL 66 114 #define PGAL_2_HPRCOM_VOL 67 115 #define DACL1_2_HPRCOM_VOL 68 116 #define LINE2R_2_HPRCOM_VOL 69 117 #define PGAR_2_HPRCOM_VOL 70 118 #define DACR1_2_HPRCOM_VOL 71 119 #define HPRCOM_CTRL 72 120 /* Mono Line Output Plus/Minus control registers */ 121 #define LINE2L_2_MONOLOPM_VOL 73 122 #define PGAL_2_MONOLOPM_VOL 74 123 #define DACL1_2_MONOLOPM_VOL 75 124 #define LINE2R_2_MONOLOPM_VOL 76 125 #define PGAR_2_MONOLOPM_VOL 77 126 #define DACR1_2_MONOLOPM_VOL 78 127 #define MONOLOPM_CTRL 79 128 /* Class-D speaker driver on tlv320aic3007 */ 129 #define CLASSD_CTRL 73 130 /* Left Line Output Plus/Minus control registers */ 131 #define LINE2L_2_LLOPM_VOL 80 132 #define PGAL_2_LLOPM_VOL 81 133 #define DACL1_2_LLOPM_VOL 82 134 #define LINE2R_2_LLOPM_VOL 83 135 #define PGAR_2_LLOPM_VOL 84 136 #define DACR1_2_LLOPM_VOL 85 137 #define LLOPM_CTRL 86 138 /* Right Line Output Plus/Minus control registers */ 139 #define LINE2L_2_RLOPM_VOL 87 140 #define PGAL_2_RLOPM_VOL 88 141 #define DACL1_2_RLOPM_VOL 89 142 #define LINE2R_2_RLOPM_VOL 90 143 #define PGAR_2_RLOPM_VOL 91 144 #define DACR1_2_RLOPM_VOL 92 145 #define RLOPM_CTRL 93 146 /* GPIO/IRQ registers */ 147 #define AIC3X_STICKY_IRQ_FLAGS_REG 96 148 #define AIC3X_RT_IRQ_FLAGS_REG 97 149 #define AIC3X_GPIO1_REG 98 150 #define AIC3X_GPIO2_REG 99 151 #define AIC3X_GPIOA_REG 100 152 #define AIC3X_GPIOB_REG 101 153 /* Clock generation control register */ 154 #define AIC3X_CLKGEN_CTRL_REG 102 155 /* New AGC registers */ 156 #define LAGCN_ATTACK 103 157 #define LAGCN_DECAY 104 158 #define RAGCN_ATTACK 105 159 #define RAGCN_DECAY 106 160 /* New Programmable ADC Digital Path and I2C Bus Condition Register */ 161 #define NEW_ADC_DIGITALPATH 107 162 /* Passive Analog Signal Bypass Selection During Powerdown Register */ 163 #define PASSIVE_BYPASS 108 164 /* DAC Quiescent Current Adjustment Register */ 165 #define DAC_ICC_ADJ 109 166 167 /* Page select register bits */ 168 #define PAGE0_SELECT 0 169 #define PAGE1_SELECT 1 170 171 /* Audio serial data interface control register A bits */ 172 #define BIT_CLK_MASTER 0x80 173 #define WORD_CLK_MASTER 0x40 174 #define DOUT_TRISTATE 0x20 175 176 /* Codec Datapath setup register 7 */ 177 #define FSREF_44100 (1 << 7) 178 #define FSREF_48000 (0 << 7) 179 #define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) 180 #define LDAC2LCH (0x1 << 3) 181 #define RDAC2RCH (0x1 << 1) 182 #define LDAC2RCH (0x2 << 3) 183 #define RDAC2LCH (0x2 << 1) 184 #define LDAC2MONOMIX (0x3 << 3) 185 #define RDAC2MONOMIX (0x3 << 1) 186 187 /* PLL registers bitfields */ 188 #define PLLP_SHIFT 0 189 #define PLLP_MASK 7 190 #define PLLQ_SHIFT 3 191 #define PLLR_SHIFT 0 192 #define PLLJ_SHIFT 2 193 #define PLLD_MSB_SHIFT 0 194 #define PLLD_LSB_SHIFT 2 195 196 /* Clock generation register bits */ 197 #define CODEC_CLKIN_PLLDIV 0 198 #define CODEC_CLKIN_CLKDIV 1 199 #define PLL_CLKIN_SHIFT 4 200 #define MCLK_SOURCE 0x0 201 #define PLL_CLKDIV_SHIFT 0 202 #define PLLCLK_IN_MASK 0x30 203 #define PLLCLK_IN_SHIFT 4 204 #define CLKDIV_IN_MASK 0xc0 205 #define CLKDIV_IN_SHIFT 6 206 /* clock in source */ 207 #define CLKIN_MCLK 0 208 #define CLKIN_GPIO2 1 209 #define CLKIN_BCLK 2 210 211 /* Software reset register bits */ 212 #define SOFT_RESET 0x80 213 214 /* PLL progrramming register A bits */ 215 #define PLL_ENABLE 0x80 216 217 /* Route bits */ 218 #define ROUTE_ON 0x80 219 220 /* Mute bits */ 221 #define UNMUTE 0x08 222 #define MUTE_ON 0x80 223 224 /* Power bits */ 225 #define LADC_PWR_ON 0x04 226 #define RADC_PWR_ON 0x04 227 #define LDAC_PWR_ON 0x80 228 #define RDAC_PWR_ON 0x40 229 #define HPLOUT_PWR_ON 0x01 230 #define HPROUT_PWR_ON 0x01 231 #define HPLCOM_PWR_ON 0x01 232 #define HPRCOM_PWR_ON 0x01 233 #define MONOLOPM_PWR_ON 0x01 234 #define LLOPM_PWR_ON 0x01 235 #define RLOPM_PWR_ON 0x01 236 237 #define INVERT_VOL(val) (0x7f - val) 238 239 /* Default output volume (inverted) */ 240 #define DEFAULT_VOL INVERT_VOL(0x50) 241 /* Default input volume */ 242 #define DEFAULT_GAIN 0x20 243 244 /* MICBIAS Control Register */ 245 #define MICBIAS_LEVEL_SHIFT (6) 246 #define MICBIAS_LEVEL_MASK (3 << 6) 247 248 /* HPOUT_SC */ 249 #define HPOUT_SC_OCMV_MASK (3 << 6) 250 #define HPOUT_SC_OCMV_SHIFT (6) 251 #define HPOUT_SC_OCMV_1_35V 0 252 #define HPOUT_SC_OCMV_1_5V 1 253 #define HPOUT_SC_OCMV_1_65V 2 254 #define HPOUT_SC_OCMV_1_8V 3 255 256 /* headset detection / button API */ 257 258 /* The AIC3x supports detection of stereo headsets (GND + left + right signal) 259 * and cellular headsets (GND + speaker output + microphone input). 260 * It is recommended to enable MIC bias for this function to work properly. 261 * For more information, please refer to the datasheet. */ 262 enum { 263 AIC3X_HEADSET_DETECT_OFF = 0, 264 AIC3X_HEADSET_DETECT_STEREO = 1, 265 AIC3X_HEADSET_DETECT_CELLULAR = 2, 266 AIC3X_HEADSET_DETECT_BOTH = 3 267 }; 268 269 enum { 270 AIC3X_HEADSET_DEBOUNCE_16MS = 0, 271 AIC3X_HEADSET_DEBOUNCE_32MS = 1, 272 AIC3X_HEADSET_DEBOUNCE_64MS = 2, 273 AIC3X_HEADSET_DEBOUNCE_128MS = 3, 274 AIC3X_HEADSET_DEBOUNCE_256MS = 4, 275 AIC3X_HEADSET_DEBOUNCE_512MS = 5 276 }; 277 278 enum { 279 AIC3X_BUTTON_DEBOUNCE_0MS = 0, 280 AIC3X_BUTTON_DEBOUNCE_8MS = 1, 281 AIC3X_BUTTON_DEBOUNCE_16MS = 2, 282 AIC3X_BUTTON_DEBOUNCE_32MS = 3 283 }; 284 285 #define AIC3X_HEADSET_DETECT_ENABLED 0x80 286 #define AIC3X_HEADSET_DETECT_SHIFT 5 287 #define AIC3X_HEADSET_DETECT_MASK 3 288 #define AIC3X_HEADSET_DEBOUNCE_SHIFT 2 289 #define AIC3X_HEADSET_DEBOUNCE_MASK 7 290 #define AIC3X_BUTTON_DEBOUNCE_SHIFT 0 291 #define AIC3X_BUTTON_DEBOUNCE_MASK 3 292 293 #endif /* _AIC3X_H */ 294