144d0a879SVladimir Barinov /* 244d0a879SVladimir Barinov * ALSA SoC TLV320AIC3X codec driver 344d0a879SVladimir Barinov * 4d6b52039SVladimir Barinov * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 544d0a879SVladimir Barinov * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 644d0a879SVladimir Barinov * 744d0a879SVladimir Barinov * This program is free software; you can redistribute it and/or modify 844d0a879SVladimir Barinov * it under the terms of the GNU General Public License version 2 as 944d0a879SVladimir Barinov * published by the Free Software Foundation. 1044d0a879SVladimir Barinov */ 1144d0a879SVladimir Barinov 1244d0a879SVladimir Barinov #ifndef _AIC3X_H 1344d0a879SVladimir Barinov #define _AIC3X_H 1444d0a879SVladimir Barinov 1544d0a879SVladimir Barinov /* AIC3X register space */ 1644d0a879SVladimir Barinov #define AIC3X_CACHEREGNUM 103 1744d0a879SVladimir Barinov 1844d0a879SVladimir Barinov /* Page select register */ 1944d0a879SVladimir Barinov #define AIC3X_PAGE_SELECT 0 2044d0a879SVladimir Barinov /* Software reset register */ 2144d0a879SVladimir Barinov #define AIC3X_RESET 1 2244d0a879SVladimir Barinov /* Codec Sample rate select register */ 2344d0a879SVladimir Barinov #define AIC3X_SAMPLE_RATE_SEL_REG 2 2444d0a879SVladimir Barinov /* PLL progrramming register A */ 2544d0a879SVladimir Barinov #define AIC3X_PLL_PROGA_REG 3 2644d0a879SVladimir Barinov /* PLL progrramming register B */ 2744d0a879SVladimir Barinov #define AIC3X_PLL_PROGB_REG 4 2844d0a879SVladimir Barinov /* PLL progrramming register C */ 2944d0a879SVladimir Barinov #define AIC3X_PLL_PROGC_REG 5 3044d0a879SVladimir Barinov /* PLL progrramming register D */ 3144d0a879SVladimir Barinov #define AIC3X_PLL_PROGD_REG 6 3244d0a879SVladimir Barinov /* Codec datapath setup register */ 3344d0a879SVladimir Barinov #define AIC3X_CODEC_DATAPATH_REG 7 3444d0a879SVladimir Barinov /* Audio serial data interface control register A */ 3544d0a879SVladimir Barinov #define AIC3X_ASD_INTF_CTRLA 8 3644d0a879SVladimir Barinov /* Audio serial data interface control register B */ 3744d0a879SVladimir Barinov #define AIC3X_ASD_INTF_CTRLB 9 3844d0a879SVladimir Barinov /* Audio overflow status and PLL R value programming register */ 3944d0a879SVladimir Barinov #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11 404d20f70aSJarkko Nikula /* Audio codec digital filter control register */ 414d20f70aSJarkko Nikula #define AIC3X_CODEC_DFILT_CTRL 12 4244d0a879SVladimir Barinov 4344d0a879SVladimir Barinov /* ADC PGA Gain control registers */ 4444d0a879SVladimir Barinov #define LADC_VOL 15 4544d0a879SVladimir Barinov #define RADC_VOL 16 4644d0a879SVladimir Barinov /* MIC3 control registers */ 4744d0a879SVladimir Barinov #define MIC3LR_2_LADC_CTRL 17 4844d0a879SVladimir Barinov #define MIC3LR_2_RADC_CTRL 18 4944d0a879SVladimir Barinov /* Line1 Input control registers */ 5044d0a879SVladimir Barinov #define LINE1L_2_LADC_CTRL 19 5154f01916SDaniel Mack #define LINE1R_2_LADC_CTRL 21 5244d0a879SVladimir Barinov #define LINE1R_2_RADC_CTRL 22 5354f01916SDaniel Mack #define LINE1L_2_RADC_CTRL 24 5444d0a879SVladimir Barinov /* Line2 Input control registers */ 5544d0a879SVladimir Barinov #define LINE2L_2_LADC_CTRL 20 5644d0a879SVladimir Barinov #define LINE2R_2_RADC_CTRL 23 5744d0a879SVladimir Barinov /* MICBIAS Control Register */ 5844d0a879SVladimir Barinov #define MICBIAS_CTRL 25 5944d0a879SVladimir Barinov 6044d0a879SVladimir Barinov /* AGC Control Registers A, B, C */ 6144d0a879SVladimir Barinov #define LAGC_CTRL_A 26 6244d0a879SVladimir Barinov #define LAGC_CTRL_B 27 6344d0a879SVladimir Barinov #define LAGC_CTRL_C 28 6444d0a879SVladimir Barinov #define RAGC_CTRL_A 29 6544d0a879SVladimir Barinov #define RAGC_CTRL_B 30 6644d0a879SVladimir Barinov #define RAGC_CTRL_C 31 6744d0a879SVladimir Barinov 6844d0a879SVladimir Barinov /* DAC Power and Left High Power Output control registers */ 6944d0a879SVladimir Barinov #define DAC_PWR 37 7044d0a879SVladimir Barinov #define HPLCOM_CFG 37 7144d0a879SVladimir Barinov /* Right High Power Output control registers */ 7244d0a879SVladimir Barinov #define HPRCOM_CFG 38 7344d0a879SVladimir Barinov /* DAC Output Switching control registers */ 7444d0a879SVladimir Barinov #define DAC_LINE_MUX 41 7544d0a879SVladimir Barinov /* High Power Output Driver Pop Reduction registers */ 7644d0a879SVladimir Barinov #define HPOUT_POP_REDUCTION 42 7744d0a879SVladimir Barinov /* DAC Digital control registers */ 7844d0a879SVladimir Barinov #define LDAC_VOL 43 7944d0a879SVladimir Barinov #define RDAC_VOL 44 8044d0a879SVladimir Barinov /* High Power Output control registers */ 8144d0a879SVladimir Barinov #define LINE2L_2_HPLOUT_VOL 45 8244d0a879SVladimir Barinov #define LINE2R_2_HPROUT_VOL 62 8344d0a879SVladimir Barinov #define PGAL_2_HPLOUT_VOL 46 8454f01916SDaniel Mack #define PGAL_2_HPROUT_VOL 60 8554f01916SDaniel Mack #define PGAR_2_HPLOUT_VOL 49 8644d0a879SVladimir Barinov #define PGAR_2_HPROUT_VOL 63 8744d0a879SVladimir Barinov #define DACL1_2_HPLOUT_VOL 47 8844d0a879SVladimir Barinov #define DACR1_2_HPROUT_VOL 64 8944d0a879SVladimir Barinov #define HPLOUT_CTRL 51 9044d0a879SVladimir Barinov #define HPROUT_CTRL 65 9144d0a879SVladimir Barinov /* High Power COM control registers */ 9244d0a879SVladimir Barinov #define LINE2L_2_HPLCOM_VOL 52 9344d0a879SVladimir Barinov #define LINE2R_2_HPRCOM_VOL 69 9444d0a879SVladimir Barinov #define PGAL_2_HPLCOM_VOL 53 9554f01916SDaniel Mack #define PGAR_2_HPLCOM_VOL 56 9654f01916SDaniel Mack #define PGAL_2_HPRCOM_VOL 67 9744d0a879SVladimir Barinov #define PGAR_2_HPRCOM_VOL 70 9844d0a879SVladimir Barinov #define DACL1_2_HPLCOM_VOL 54 9944d0a879SVladimir Barinov #define DACR1_2_HPRCOM_VOL 71 10044d0a879SVladimir Barinov #define HPLCOM_CTRL 58 10144d0a879SVladimir Barinov #define HPRCOM_CTRL 72 10244d0a879SVladimir Barinov /* Mono Line Output Plus/Minus control registers */ 10344d0a879SVladimir Barinov #define LINE2L_2_MONOLOPM_VOL 73 10444d0a879SVladimir Barinov #define LINE2R_2_MONOLOPM_VOL 76 10544d0a879SVladimir Barinov #define PGAL_2_MONOLOPM_VOL 74 10644d0a879SVladimir Barinov #define PGAR_2_MONOLOPM_VOL 77 10744d0a879SVladimir Barinov #define DACL1_2_MONOLOPM_VOL 75 10844d0a879SVladimir Barinov #define DACR1_2_MONOLOPM_VOL 78 10944d0a879SVladimir Barinov #define MONOLOPM_CTRL 79 11044d0a879SVladimir Barinov /* Line Output Plus/Minus control registers */ 11144d0a879SVladimir Barinov #define LINE2L_2_LLOPM_VOL 80 11254f01916SDaniel Mack #define LINE2L_2_RLOPM_VOL 87 11354f01916SDaniel Mack #define LINE2R_2_LLOPM_VOL 83 11444d0a879SVladimir Barinov #define LINE2R_2_RLOPM_VOL 90 11544d0a879SVladimir Barinov #define PGAL_2_LLOPM_VOL 81 11654f01916SDaniel Mack #define PGAL_2_RLOPM_VOL 88 11754f01916SDaniel Mack #define PGAR_2_LLOPM_VOL 84 11844d0a879SVladimir Barinov #define PGAR_2_RLOPM_VOL 91 11944d0a879SVladimir Barinov #define DACL1_2_LLOPM_VOL 82 12054f01916SDaniel Mack #define DACL1_2_RLOPM_VOL 89 12144d0a879SVladimir Barinov #define DACR1_2_RLOPM_VOL 92 12254f01916SDaniel Mack #define DACR1_2_LLOPM_VOL 85 12344d0a879SVladimir Barinov #define LLOPM_CTRL 86 12444d0a879SVladimir Barinov #define RLOPM_CTRL 93 12554e7e616SDaniel Mack /* GPIO/IRQ registers */ 12654e7e616SDaniel Mack #define AIC3X_STICKY_IRQ_FLAGS_REG 96 12754e7e616SDaniel Mack #define AIC3X_RT_IRQ_FLAGS_REG 97 12854e7e616SDaniel Mack #define AIC3X_GPIO1_REG 98 12954e7e616SDaniel Mack #define AIC3X_GPIO2_REG 99 13054e7e616SDaniel Mack #define AIC3X_GPIOA_REG 100 1314f9c16ccSDaniel Mack #define AIC3X_GPIOB_REG 101 13254e7e616SDaniel Mack /* Clock generation control register */ 13344d0a879SVladimir Barinov #define AIC3X_CLKGEN_CTRL_REG 102 13444d0a879SVladimir Barinov 13544d0a879SVladimir Barinov /* Page select register bits */ 13644d0a879SVladimir Barinov #define PAGE0_SELECT 0 13744d0a879SVladimir Barinov #define PAGE1_SELECT 1 13844d0a879SVladimir Barinov 13944d0a879SVladimir Barinov /* Audio serial data interface control register A bits */ 14044d0a879SVladimir Barinov #define BIT_CLK_MASTER 0x80 14144d0a879SVladimir Barinov #define WORD_CLK_MASTER 0x40 14244d0a879SVladimir Barinov 14344d0a879SVladimir Barinov /* Codec Datapath setup register 7 */ 14444d0a879SVladimir Barinov #define FSREF_44100 (1 << 7) 14544d0a879SVladimir Barinov #define FSREF_48000 (0 << 7) 14644d0a879SVladimir Barinov #define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) 14744d0a879SVladimir Barinov #define LDAC2LCH (0x1 << 3) 14844d0a879SVladimir Barinov #define RDAC2RCH (0x1 << 1) 14944d0a879SVladimir Barinov 15044d0a879SVladimir Barinov /* PLL registers bitfields */ 15144d0a879SVladimir Barinov #define PLLP_SHIFT 0 1524f9c16ccSDaniel Mack #define PLLQ_SHIFT 3 15344d0a879SVladimir Barinov #define PLLR_SHIFT 0 15444d0a879SVladimir Barinov #define PLLJ_SHIFT 2 15544d0a879SVladimir Barinov #define PLLD_MSB_SHIFT 0 15644d0a879SVladimir Barinov #define PLLD_LSB_SHIFT 2 15744d0a879SVladimir Barinov 15844d0a879SVladimir Barinov /* Clock generation register bits */ 1594f9c16ccSDaniel Mack #define CODEC_CLKIN_PLLDIV 0 1604f9c16ccSDaniel Mack #define CODEC_CLKIN_CLKDIV 1 16144d0a879SVladimir Barinov #define PLL_CLKIN_SHIFT 4 16244d0a879SVladimir Barinov #define MCLK_SOURCE 0x0 16344d0a879SVladimir Barinov #define PLL_CLKDIV_SHIFT 0 16444d0a879SVladimir Barinov 16544d0a879SVladimir Barinov /* Software reset register bits */ 16644d0a879SVladimir Barinov #define SOFT_RESET 0x80 16744d0a879SVladimir Barinov 16844d0a879SVladimir Barinov /* PLL progrramming register A bits */ 16944d0a879SVladimir Barinov #define PLL_ENABLE 0x80 17044d0a879SVladimir Barinov 17144d0a879SVladimir Barinov /* Route bits */ 17244d0a879SVladimir Barinov #define ROUTE_ON 0x80 17344d0a879SVladimir Barinov 17444d0a879SVladimir Barinov /* Mute bits */ 17544d0a879SVladimir Barinov #define UNMUTE 0x08 17644d0a879SVladimir Barinov #define MUTE_ON 0x80 17744d0a879SVladimir Barinov 17844d0a879SVladimir Barinov /* Power bits */ 17944d0a879SVladimir Barinov #define LADC_PWR_ON 0x04 18044d0a879SVladimir Barinov #define RADC_PWR_ON 0x04 18144d0a879SVladimir Barinov #define LDAC_PWR_ON 0x80 18244d0a879SVladimir Barinov #define RDAC_PWR_ON 0x40 18344d0a879SVladimir Barinov #define HPLOUT_PWR_ON 0x01 18444d0a879SVladimir Barinov #define HPROUT_PWR_ON 0x01 18544d0a879SVladimir Barinov #define HPLCOM_PWR_ON 0x01 18644d0a879SVladimir Barinov #define HPRCOM_PWR_ON 0x01 18744d0a879SVladimir Barinov #define MONOLOPM_PWR_ON 0x01 18844d0a879SVladimir Barinov #define LLOPM_PWR_ON 0x01 18944d0a879SVladimir Barinov #define RLOPM_PWR_ON 0x01 19044d0a879SVladimir Barinov 19144d0a879SVladimir Barinov #define INVERT_VOL(val) (0x7f - val) 19244d0a879SVladimir Barinov 19344d0a879SVladimir Barinov /* Default output volume (inverted) */ 19444d0a879SVladimir Barinov #define DEFAULT_VOL INVERT_VOL(0x50) 19544d0a879SVladimir Barinov /* Default input volume */ 19644d0a879SVladimir Barinov #define DEFAULT_GAIN 0x20 19744d0a879SVladimir Barinov 19854e7e616SDaniel Mack /* GPIO API */ 19954e7e616SDaniel Mack enum { 20054e7e616SDaniel Mack AIC3X_GPIO1_FUNC_DISABLED = 0, 20154e7e616SDaniel Mack AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC = 1, 20254e7e616SDaniel Mack AIC3X_GPIO1_FUNC_CLOCK_MUX = 2, 20354e7e616SDaniel Mack AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 = 3, 20454e7e616SDaniel Mack AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 = 4, 20554e7e616SDaniel Mack AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 = 5, 20654e7e616SDaniel Mack AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ = 6, 20754e7e616SDaniel Mack AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ = 7, 20854e7e616SDaniel Mack AIC3X_GPIO1_FUNC_INPUT = 8, 20954e7e616SDaniel Mack AIC3X_GPIO1_FUNC_OUTPUT = 9, 21054e7e616SDaniel Mack AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK = 10, 21154e7e616SDaniel Mack AIC3X_GPIO1_FUNC_AUDIO_WORDCLK = 11, 21254e7e616SDaniel Mack AIC3X_GPIO1_FUNC_BUTTON_IRQ = 12, 21354e7e616SDaniel Mack AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ = 13, 21454e7e616SDaniel Mack AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 14, 21554e7e616SDaniel Mack AIC3X_GPIO1_FUNC_ALL_IRQ = 16 21654e7e616SDaniel Mack }; 21754e7e616SDaniel Mack 21854e7e616SDaniel Mack enum { 21954e7e616SDaniel Mack AIC3X_GPIO2_FUNC_DISABLED = 0, 22054e7e616SDaniel Mack AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ = 2, 22154e7e616SDaniel Mack AIC3X_GPIO2_FUNC_INPUT = 3, 22254e7e616SDaniel Mack AIC3X_GPIO2_FUNC_OUTPUT = 4, 22354e7e616SDaniel Mack AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT = 5, 22454e7e616SDaniel Mack AIC3X_GPIO2_FUNC_AUDIO_BITCLK = 8, 22554e7e616SDaniel Mack AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9, 22654e7e616SDaniel Mack AIC3X_GPIO2_FUNC_ALL_IRQ = 10, 22754e7e616SDaniel Mack AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11, 22854e7e616SDaniel Mack AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12, 22954e7e616SDaniel Mack AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ = 13, 23054e7e616SDaniel Mack AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ = 14, 23154e7e616SDaniel Mack AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ = 15 23254e7e616SDaniel Mack }; 23354e7e616SDaniel Mack 23454e7e616SDaniel Mack void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state); 23554e7e616SDaniel Mack int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio); 23654e7e616SDaniel Mack int aic3x_headset_detected(struct snd_soc_codec *codec); 23754e7e616SDaniel Mack 23844d0a879SVladimir Barinov struct aic3x_setup_data { 239ba8ed121SJean Delvare int i2c_bus; 24044d0a879SVladimir Barinov unsigned short i2c_address; 24154e7e616SDaniel Mack unsigned int gpio_func[2]; 24244d0a879SVladimir Barinov }; 24344d0a879SVladimir Barinov 244e550e17fSLiam Girdwood extern struct snd_soc_dai aic3x_dai; 24544d0a879SVladimir Barinov extern struct snd_soc_codec_device soc_codec_dev_aic3x; 24644d0a879SVladimir Barinov 24744d0a879SVladimir Barinov #endif /* _AIC3X_H */ 248