144d0a879SVladimir Barinov /* 244d0a879SVladimir Barinov * ALSA SoC TLV320AIC3X codec driver 344d0a879SVladimir Barinov * 444d0a879SVladimir Barinov * Author: Vladimir Barinov, <vbarinov@ru.mvista.com> 544d0a879SVladimir Barinov * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 644d0a879SVladimir Barinov * 744d0a879SVladimir Barinov * This program is free software; you can redistribute it and/or modify 844d0a879SVladimir Barinov * it under the terms of the GNU General Public License version 2 as 944d0a879SVladimir Barinov * published by the Free Software Foundation. 1044d0a879SVladimir Barinov */ 1144d0a879SVladimir Barinov 1244d0a879SVladimir Barinov #ifndef _AIC3X_H 1344d0a879SVladimir Barinov #define _AIC3X_H 1444d0a879SVladimir Barinov 1544d0a879SVladimir Barinov /* AIC3X register space */ 1644d0a879SVladimir Barinov #define AIC3X_CACHEREGNUM 103 1744d0a879SVladimir Barinov 1844d0a879SVladimir Barinov /* Page select register */ 1944d0a879SVladimir Barinov #define AIC3X_PAGE_SELECT 0 2044d0a879SVladimir Barinov /* Software reset register */ 2144d0a879SVladimir Barinov #define AIC3X_RESET 1 2244d0a879SVladimir Barinov /* Codec Sample rate select register */ 2344d0a879SVladimir Barinov #define AIC3X_SAMPLE_RATE_SEL_REG 2 2444d0a879SVladimir Barinov /* PLL progrramming register A */ 2544d0a879SVladimir Barinov #define AIC3X_PLL_PROGA_REG 3 2644d0a879SVladimir Barinov /* PLL progrramming register B */ 2744d0a879SVladimir Barinov #define AIC3X_PLL_PROGB_REG 4 2844d0a879SVladimir Barinov /* PLL progrramming register C */ 2944d0a879SVladimir Barinov #define AIC3X_PLL_PROGC_REG 5 3044d0a879SVladimir Barinov /* PLL progrramming register D */ 3144d0a879SVladimir Barinov #define AIC3X_PLL_PROGD_REG 6 3244d0a879SVladimir Barinov /* Codec datapath setup register */ 3344d0a879SVladimir Barinov #define AIC3X_CODEC_DATAPATH_REG 7 3444d0a879SVladimir Barinov /* Audio serial data interface control register A */ 3544d0a879SVladimir Barinov #define AIC3X_ASD_INTF_CTRLA 8 3644d0a879SVladimir Barinov /* Audio serial data interface control register B */ 3744d0a879SVladimir Barinov #define AIC3X_ASD_INTF_CTRLB 9 3844d0a879SVladimir Barinov /* Audio overflow status and PLL R value programming register */ 3944d0a879SVladimir Barinov #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11 4044d0a879SVladimir Barinov 4144d0a879SVladimir Barinov /* ADC PGA Gain control registers */ 4244d0a879SVladimir Barinov #define LADC_VOL 15 4344d0a879SVladimir Barinov #define RADC_VOL 16 4444d0a879SVladimir Barinov /* MIC3 control registers */ 4544d0a879SVladimir Barinov #define MIC3LR_2_LADC_CTRL 17 4644d0a879SVladimir Barinov #define MIC3LR_2_RADC_CTRL 18 4744d0a879SVladimir Barinov /* Line1 Input control registers */ 4844d0a879SVladimir Barinov #define LINE1L_2_LADC_CTRL 19 4944d0a879SVladimir Barinov #define LINE1R_2_RADC_CTRL 22 5044d0a879SVladimir Barinov /* Line2 Input control registers */ 5144d0a879SVladimir Barinov #define LINE2L_2_LADC_CTRL 20 5244d0a879SVladimir Barinov #define LINE2R_2_RADC_CTRL 23 5344d0a879SVladimir Barinov /* MICBIAS Control Register */ 5444d0a879SVladimir Barinov #define MICBIAS_CTRL 25 5544d0a879SVladimir Barinov 5644d0a879SVladimir Barinov /* AGC Control Registers A, B, C */ 5744d0a879SVladimir Barinov #define LAGC_CTRL_A 26 5844d0a879SVladimir Barinov #define LAGC_CTRL_B 27 5944d0a879SVladimir Barinov #define LAGC_CTRL_C 28 6044d0a879SVladimir Barinov #define RAGC_CTRL_A 29 6144d0a879SVladimir Barinov #define RAGC_CTRL_B 30 6244d0a879SVladimir Barinov #define RAGC_CTRL_C 31 6344d0a879SVladimir Barinov 6444d0a879SVladimir Barinov /* DAC Power and Left High Power Output control registers */ 6544d0a879SVladimir Barinov #define DAC_PWR 37 6644d0a879SVladimir Barinov #define HPLCOM_CFG 37 6744d0a879SVladimir Barinov /* Right High Power Output control registers */ 6844d0a879SVladimir Barinov #define HPRCOM_CFG 38 6944d0a879SVladimir Barinov /* DAC Output Switching control registers */ 7044d0a879SVladimir Barinov #define DAC_LINE_MUX 41 7144d0a879SVladimir Barinov /* High Power Output Driver Pop Reduction registers */ 7244d0a879SVladimir Barinov #define HPOUT_POP_REDUCTION 42 7344d0a879SVladimir Barinov /* DAC Digital control registers */ 7444d0a879SVladimir Barinov #define LDAC_VOL 43 7544d0a879SVladimir Barinov #define RDAC_VOL 44 7644d0a879SVladimir Barinov /* High Power Output control registers */ 7744d0a879SVladimir Barinov #define LINE2L_2_HPLOUT_VOL 45 7844d0a879SVladimir Barinov #define LINE2R_2_HPROUT_VOL 62 7944d0a879SVladimir Barinov #define PGAL_2_HPLOUT_VOL 46 8044d0a879SVladimir Barinov #define PGAR_2_HPROUT_VOL 63 8144d0a879SVladimir Barinov #define DACL1_2_HPLOUT_VOL 47 8244d0a879SVladimir Barinov #define DACR1_2_HPROUT_VOL 64 8344d0a879SVladimir Barinov #define HPLOUT_CTRL 51 8444d0a879SVladimir Barinov #define HPROUT_CTRL 65 8544d0a879SVladimir Barinov /* High Power COM control registers */ 8644d0a879SVladimir Barinov #define LINE2L_2_HPLCOM_VOL 52 8744d0a879SVladimir Barinov #define LINE2R_2_HPRCOM_VOL 69 8844d0a879SVladimir Barinov #define PGAL_2_HPLCOM_VOL 53 8944d0a879SVladimir Barinov #define PGAR_2_HPRCOM_VOL 70 9044d0a879SVladimir Barinov #define DACL1_2_HPLCOM_VOL 54 9144d0a879SVladimir Barinov #define DACR1_2_HPRCOM_VOL 71 9244d0a879SVladimir Barinov #define HPLCOM_CTRL 58 9344d0a879SVladimir Barinov #define HPRCOM_CTRL 72 9444d0a879SVladimir Barinov /* Mono Line Output Plus/Minus control registers */ 9544d0a879SVladimir Barinov #define LINE2L_2_MONOLOPM_VOL 73 9644d0a879SVladimir Barinov #define LINE2R_2_MONOLOPM_VOL 76 9744d0a879SVladimir Barinov #define PGAL_2_MONOLOPM_VOL 74 9844d0a879SVladimir Barinov #define PGAR_2_MONOLOPM_VOL 77 9944d0a879SVladimir Barinov #define DACL1_2_MONOLOPM_VOL 75 10044d0a879SVladimir Barinov #define DACR1_2_MONOLOPM_VOL 78 10144d0a879SVladimir Barinov #define MONOLOPM_CTRL 79 10244d0a879SVladimir Barinov /* Line Output Plus/Minus control registers */ 10344d0a879SVladimir Barinov #define LINE2L_2_LLOPM_VOL 80 10444d0a879SVladimir Barinov #define LINE2R_2_RLOPM_VOL 90 10544d0a879SVladimir Barinov #define PGAL_2_LLOPM_VOL 81 10644d0a879SVladimir Barinov #define PGAR_2_RLOPM_VOL 91 10744d0a879SVladimir Barinov #define DACL1_2_LLOPM_VOL 82 10844d0a879SVladimir Barinov #define DACR1_2_RLOPM_VOL 92 10944d0a879SVladimir Barinov #define LLOPM_CTRL 86 11044d0a879SVladimir Barinov #define RLOPM_CTRL 93 11144d0a879SVladimir Barinov /* Clock generation control register */ 1124f9c16ccSDaniel Mack #define AIC3X_GPIOB_REG 101 11344d0a879SVladimir Barinov #define AIC3X_CLKGEN_CTRL_REG 102 11444d0a879SVladimir Barinov 11544d0a879SVladimir Barinov /* Page select register bits */ 11644d0a879SVladimir Barinov #define PAGE0_SELECT 0 11744d0a879SVladimir Barinov #define PAGE1_SELECT 1 11844d0a879SVladimir Barinov 11944d0a879SVladimir Barinov /* Audio serial data interface control register A bits */ 12044d0a879SVladimir Barinov #define BIT_CLK_MASTER 0x80 12144d0a879SVladimir Barinov #define WORD_CLK_MASTER 0x40 12244d0a879SVladimir Barinov 12344d0a879SVladimir Barinov /* Codec Datapath setup register 7 */ 12444d0a879SVladimir Barinov #define FSREF_44100 (1 << 7) 12544d0a879SVladimir Barinov #define FSREF_48000 (0 << 7) 12644d0a879SVladimir Barinov #define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) 12744d0a879SVladimir Barinov #define LDAC2LCH (0x1 << 3) 12844d0a879SVladimir Barinov #define RDAC2RCH (0x1 << 1) 12944d0a879SVladimir Barinov 13044d0a879SVladimir Barinov /* PLL registers bitfields */ 13144d0a879SVladimir Barinov #define PLLP_SHIFT 0 1324f9c16ccSDaniel Mack #define PLLQ_SHIFT 3 13344d0a879SVladimir Barinov #define PLLR_SHIFT 0 13444d0a879SVladimir Barinov #define PLLJ_SHIFT 2 13544d0a879SVladimir Barinov #define PLLD_MSB_SHIFT 0 13644d0a879SVladimir Barinov #define PLLD_LSB_SHIFT 2 13744d0a879SVladimir Barinov 13844d0a879SVladimir Barinov /* Clock generation register bits */ 1394f9c16ccSDaniel Mack #define CODEC_CLKIN_PLLDIV 0 1404f9c16ccSDaniel Mack #define CODEC_CLKIN_CLKDIV 1 14144d0a879SVladimir Barinov #define PLL_CLKIN_SHIFT 4 14244d0a879SVladimir Barinov #define MCLK_SOURCE 0x0 14344d0a879SVladimir Barinov #define PLL_CLKDIV_SHIFT 0 14444d0a879SVladimir Barinov 14544d0a879SVladimir Barinov /* Software reset register bits */ 14644d0a879SVladimir Barinov #define SOFT_RESET 0x80 14744d0a879SVladimir Barinov 14844d0a879SVladimir Barinov /* PLL progrramming register A bits */ 14944d0a879SVladimir Barinov #define PLL_ENABLE 0x80 15044d0a879SVladimir Barinov 15144d0a879SVladimir Barinov /* Route bits */ 15244d0a879SVladimir Barinov #define ROUTE_ON 0x80 15344d0a879SVladimir Barinov 15444d0a879SVladimir Barinov /* Mute bits */ 15544d0a879SVladimir Barinov #define UNMUTE 0x08 15644d0a879SVladimir Barinov #define MUTE_ON 0x80 15744d0a879SVladimir Barinov 15844d0a879SVladimir Barinov /* Power bits */ 15944d0a879SVladimir Barinov #define LADC_PWR_ON 0x04 16044d0a879SVladimir Barinov #define RADC_PWR_ON 0x04 16144d0a879SVladimir Barinov #define LDAC_PWR_ON 0x80 16244d0a879SVladimir Barinov #define RDAC_PWR_ON 0x40 16344d0a879SVladimir Barinov #define HPLOUT_PWR_ON 0x01 16444d0a879SVladimir Barinov #define HPROUT_PWR_ON 0x01 16544d0a879SVladimir Barinov #define HPLCOM_PWR_ON 0x01 16644d0a879SVladimir Barinov #define HPRCOM_PWR_ON 0x01 16744d0a879SVladimir Barinov #define MONOLOPM_PWR_ON 0x01 16844d0a879SVladimir Barinov #define LLOPM_PWR_ON 0x01 16944d0a879SVladimir Barinov #define RLOPM_PWR_ON 0x01 17044d0a879SVladimir Barinov 17144d0a879SVladimir Barinov #define INVERT_VOL(val) (0x7f - val) 17244d0a879SVladimir Barinov 17344d0a879SVladimir Barinov /* Default output volume (inverted) */ 17444d0a879SVladimir Barinov #define DEFAULT_VOL INVERT_VOL(0x50) 17544d0a879SVladimir Barinov /* Default input volume */ 17644d0a879SVladimir Barinov #define DEFAULT_GAIN 0x20 17744d0a879SVladimir Barinov 17844d0a879SVladimir Barinov struct aic3x_setup_data { 17944d0a879SVladimir Barinov unsigned short i2c_address; 18044d0a879SVladimir Barinov }; 18144d0a879SVladimir Barinov 18244d0a879SVladimir Barinov extern struct snd_soc_codec_dai aic3x_dai; 18344d0a879SVladimir Barinov extern struct snd_soc_codec_device soc_codec_dev_aic3x; 18444d0a879SVladimir Barinov 18544d0a879SVladimir Barinov #endif /* _AIC3X_H */ 186