1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 244d0a879SVladimir Barinov /* 344d0a879SVladimir Barinov * ALSA SoC TLV320AIC3X codec driver 444d0a879SVladimir Barinov * 5d6b52039SVladimir Barinov * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 644d0a879SVladimir Barinov * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 744d0a879SVladimir Barinov */ 844d0a879SVladimir Barinov 944d0a879SVladimir Barinov #ifndef _AIC3X_H 1044d0a879SVladimir Barinov #define _AIC3X_H 1144d0a879SVladimir Barinov 12a96d2ba2SJiri Prchal struct device; 13a96d2ba2SJiri Prchal struct regmap_config; 14a96d2ba2SJiri Prchal 15a96d2ba2SJiri Prchal extern const struct regmap_config aic3x_regmap; 16a96d2ba2SJiri Prchal int aic3x_probe(struct device *dev, struct regmap *regmap, kernel_ulong_t driver_data); 172a798513SUwe Kleine-König void aic3x_remove(struct device *dev); 18a96d2ba2SJiri Prchal 1973a48088SJiri Prchal #define AIC3X_MODEL_3X 0 2073a48088SJiri Prchal #define AIC3X_MODEL_33 1 2173a48088SJiri Prchal #define AIC3X_MODEL_3007 2 2273a48088SJiri Prchal #define AIC3X_MODEL_3104 3 23a0bc855fSJiri Prchal #define AIC3X_MODEL_3106 4 2473a48088SJiri Prchal 2544d0a879SVladimir Barinov /* AIC3X register space */ 26784a897eSJiri Prchal #define AIC3X_CACHEREGNUM 110 2744d0a879SVladimir Barinov 2844d0a879SVladimir Barinov /* Page select register */ 2944d0a879SVladimir Barinov #define AIC3X_PAGE_SELECT 0 3044d0a879SVladimir Barinov /* Software reset register */ 3144d0a879SVladimir Barinov #define AIC3X_RESET 1 3244d0a879SVladimir Barinov /* Codec Sample rate select register */ 3344d0a879SVladimir Barinov #define AIC3X_SAMPLE_RATE_SEL_REG 2 3444d0a879SVladimir Barinov /* PLL progrramming register A */ 3544d0a879SVladimir Barinov #define AIC3X_PLL_PROGA_REG 3 3644d0a879SVladimir Barinov /* PLL progrramming register B */ 3744d0a879SVladimir Barinov #define AIC3X_PLL_PROGB_REG 4 3844d0a879SVladimir Barinov /* PLL progrramming register C */ 3944d0a879SVladimir Barinov #define AIC3X_PLL_PROGC_REG 5 4044d0a879SVladimir Barinov /* PLL progrramming register D */ 4144d0a879SVladimir Barinov #define AIC3X_PLL_PROGD_REG 6 4244d0a879SVladimir Barinov /* Codec datapath setup register */ 4344d0a879SVladimir Barinov #define AIC3X_CODEC_DATAPATH_REG 7 4444d0a879SVladimir Barinov /* Audio serial data interface control register A */ 4544d0a879SVladimir Barinov #define AIC3X_ASD_INTF_CTRLA 8 4644d0a879SVladimir Barinov /* Audio serial data interface control register B */ 4744d0a879SVladimir Barinov #define AIC3X_ASD_INTF_CTRLB 9 48a24f4f68STroy Kisky /* Audio serial data interface control register C */ 49a24f4f68STroy Kisky #define AIC3X_ASD_INTF_CTRLC 10 5044d0a879SVladimir Barinov /* Audio overflow status and PLL R value programming register */ 5144d0a879SVladimir Barinov #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11 524d20f70aSJarkko Nikula /* Audio codec digital filter control register */ 534d20f70aSJarkko Nikula #define AIC3X_CODEC_DFILT_CTRL 12 546f2a974bSDaniel Mack /* Headset/button press detection register */ 556f2a974bSDaniel Mack #define AIC3X_HEADSET_DETECT_CTRL_A 13 566f2a974bSDaniel Mack #define AIC3X_HEADSET_DETECT_CTRL_B 14 5744d0a879SVladimir Barinov /* ADC PGA Gain control registers */ 5844d0a879SVladimir Barinov #define LADC_VOL 15 5944d0a879SVladimir Barinov #define RADC_VOL 16 6044d0a879SVladimir Barinov /* MIC3 control registers */ 6144d0a879SVladimir Barinov #define MIC3LR_2_LADC_CTRL 17 6244d0a879SVladimir Barinov #define MIC3LR_2_RADC_CTRL 18 6344d0a879SVladimir Barinov /* Line1 Input control registers */ 6444d0a879SVladimir Barinov #define LINE1L_2_LADC_CTRL 19 6554f01916SDaniel Mack #define LINE1R_2_LADC_CTRL 21 6644d0a879SVladimir Barinov #define LINE1R_2_RADC_CTRL 22 6754f01916SDaniel Mack #define LINE1L_2_RADC_CTRL 24 6844d0a879SVladimir Barinov /* Line2 Input control registers */ 6944d0a879SVladimir Barinov #define LINE2L_2_LADC_CTRL 20 7044d0a879SVladimir Barinov #define LINE2R_2_RADC_CTRL 23 7144d0a879SVladimir Barinov /* MICBIAS Control Register */ 7244d0a879SVladimir Barinov #define MICBIAS_CTRL 25 7344d0a879SVladimir Barinov 7444d0a879SVladimir Barinov /* AGC Control Registers A, B, C */ 7544d0a879SVladimir Barinov #define LAGC_CTRL_A 26 7644d0a879SVladimir Barinov #define LAGC_CTRL_B 27 7744d0a879SVladimir Barinov #define LAGC_CTRL_C 28 7844d0a879SVladimir Barinov #define RAGC_CTRL_A 29 7944d0a879SVladimir Barinov #define RAGC_CTRL_B 30 8044d0a879SVladimir Barinov #define RAGC_CTRL_C 31 8144d0a879SVladimir Barinov 8244d0a879SVladimir Barinov /* DAC Power and Left High Power Output control registers */ 8344d0a879SVladimir Barinov #define DAC_PWR 37 8444d0a879SVladimir Barinov #define HPLCOM_CFG 37 8544d0a879SVladimir Barinov /* Right High Power Output control registers */ 8644d0a879SVladimir Barinov #define HPRCOM_CFG 38 87784a897eSJiri Prchal /* High Power Output Stage Control Register */ 88784a897eSJiri Prchal #define HPOUT_SC 40 8944d0a879SVladimir Barinov /* DAC Output Switching control registers */ 9044d0a879SVladimir Barinov #define DAC_LINE_MUX 41 9144d0a879SVladimir Barinov /* High Power Output Driver Pop Reduction registers */ 9244d0a879SVladimir Barinov #define HPOUT_POP_REDUCTION 42 9344d0a879SVladimir Barinov /* DAC Digital control registers */ 9444d0a879SVladimir Barinov #define LDAC_VOL 43 9544d0a879SVladimir Barinov #define RDAC_VOL 44 96b2eaac20SJarkko Nikula /* Left High Power Output control registers */ 9744d0a879SVladimir Barinov #define LINE2L_2_HPLOUT_VOL 45 9844d0a879SVladimir Barinov #define PGAL_2_HPLOUT_VOL 46 9944d0a879SVladimir Barinov #define DACL1_2_HPLOUT_VOL 47 100c3b79e05SJarkko Nikula #define LINE2R_2_HPLOUT_VOL 48 101b2eaac20SJarkko Nikula #define PGAR_2_HPLOUT_VOL 49 102c3b79e05SJarkko Nikula #define DACR1_2_HPLOUT_VOL 50 10344d0a879SVladimir Barinov #define HPLOUT_CTRL 51 104b2eaac20SJarkko Nikula /* Left High Power COM control registers */ 10544d0a879SVladimir Barinov #define LINE2L_2_HPLCOM_VOL 52 10644d0a879SVladimir Barinov #define PGAL_2_HPLCOM_VOL 53 10744d0a879SVladimir Barinov #define DACL1_2_HPLCOM_VOL 54 108c3b79e05SJarkko Nikula #define LINE2R_2_HPLCOM_VOL 55 109b2eaac20SJarkko Nikula #define PGAR_2_HPLCOM_VOL 56 110c3b79e05SJarkko Nikula #define DACR1_2_HPLCOM_VOL 57 11144d0a879SVladimir Barinov #define HPLCOM_CTRL 58 112b2eaac20SJarkko Nikula /* Right High Power Output control registers */ 113c3b79e05SJarkko Nikula #define LINE2L_2_HPROUT_VOL 59 114b2eaac20SJarkko Nikula #define PGAL_2_HPROUT_VOL 60 115c3b79e05SJarkko Nikula #define DACL1_2_HPROUT_VOL 61 116b2eaac20SJarkko Nikula #define LINE2R_2_HPROUT_VOL 62 117b2eaac20SJarkko Nikula #define PGAR_2_HPROUT_VOL 63 118b2eaac20SJarkko Nikula #define DACR1_2_HPROUT_VOL 64 119b2eaac20SJarkko Nikula #define HPROUT_CTRL 65 120b2eaac20SJarkko Nikula /* Right High Power COM control registers */ 121c3b79e05SJarkko Nikula #define LINE2L_2_HPRCOM_VOL 66 122b2eaac20SJarkko Nikula #define PGAL_2_HPRCOM_VOL 67 123c3b79e05SJarkko Nikula #define DACL1_2_HPRCOM_VOL 68 124b2eaac20SJarkko Nikula #define LINE2R_2_HPRCOM_VOL 69 125b2eaac20SJarkko Nikula #define PGAR_2_HPRCOM_VOL 70 126b2eaac20SJarkko Nikula #define DACR1_2_HPRCOM_VOL 71 12744d0a879SVladimir Barinov #define HPRCOM_CTRL 72 12844d0a879SVladimir Barinov /* Mono Line Output Plus/Minus control registers */ 12944d0a879SVladimir Barinov #define LINE2L_2_MONOLOPM_VOL 73 13044d0a879SVladimir Barinov #define PGAL_2_MONOLOPM_VOL 74 13144d0a879SVladimir Barinov #define DACL1_2_MONOLOPM_VOL 75 132b2eaac20SJarkko Nikula #define LINE2R_2_MONOLOPM_VOL 76 133b2eaac20SJarkko Nikula #define PGAR_2_MONOLOPM_VOL 77 13444d0a879SVladimir Barinov #define DACR1_2_MONOLOPM_VOL 78 13544d0a879SVladimir Barinov #define MONOLOPM_CTRL 79 1366184f105SRandolph Chung /* Class-D speaker driver on tlv320aic3007 */ 1376184f105SRandolph Chung #define CLASSD_CTRL 73 138b2eaac20SJarkko Nikula /* Left Line Output Plus/Minus control registers */ 13944d0a879SVladimir Barinov #define LINE2L_2_LLOPM_VOL 80 14044d0a879SVladimir Barinov #define PGAL_2_LLOPM_VOL 81 14144d0a879SVladimir Barinov #define DACL1_2_LLOPM_VOL 82 142b2eaac20SJarkko Nikula #define LINE2R_2_LLOPM_VOL 83 143b2eaac20SJarkko Nikula #define PGAR_2_LLOPM_VOL 84 14454f01916SDaniel Mack #define DACR1_2_LLOPM_VOL 85 14544d0a879SVladimir Barinov #define LLOPM_CTRL 86 146b2eaac20SJarkko Nikula /* Right Line Output Plus/Minus control registers */ 147b2eaac20SJarkko Nikula #define LINE2L_2_RLOPM_VOL 87 148b2eaac20SJarkko Nikula #define PGAL_2_RLOPM_VOL 88 149b2eaac20SJarkko Nikula #define DACL1_2_RLOPM_VOL 89 150b2eaac20SJarkko Nikula #define LINE2R_2_RLOPM_VOL 90 151b2eaac20SJarkko Nikula #define PGAR_2_RLOPM_VOL 91 152b2eaac20SJarkko Nikula #define DACR1_2_RLOPM_VOL 92 15344d0a879SVladimir Barinov #define RLOPM_CTRL 93 15454e7e616SDaniel Mack /* GPIO/IRQ registers */ 15554e7e616SDaniel Mack #define AIC3X_STICKY_IRQ_FLAGS_REG 96 15654e7e616SDaniel Mack #define AIC3X_RT_IRQ_FLAGS_REG 97 15754e7e616SDaniel Mack #define AIC3X_GPIO1_REG 98 15854e7e616SDaniel Mack #define AIC3X_GPIO2_REG 99 15954e7e616SDaniel Mack #define AIC3X_GPIOA_REG 100 1604f9c16ccSDaniel Mack #define AIC3X_GPIOB_REG 101 16154e7e616SDaniel Mack /* Clock generation control register */ 16244d0a879SVladimir Barinov #define AIC3X_CLKGEN_CTRL_REG 102 163784a897eSJiri Prchal /* New AGC registers */ 164784a897eSJiri Prchal #define LAGCN_ATTACK 103 165784a897eSJiri Prchal #define LAGCN_DECAY 104 166784a897eSJiri Prchal #define RAGCN_ATTACK 105 167784a897eSJiri Prchal #define RAGCN_DECAY 106 168784a897eSJiri Prchal /* New Programmable ADC Digital Path and I2C Bus Condition Register */ 169784a897eSJiri Prchal #define NEW_ADC_DIGITALPATH 107 170784a897eSJiri Prchal /* Passive Analog Signal Bypass Selection During Powerdown Register */ 171784a897eSJiri Prchal #define PASSIVE_BYPASS 108 172784a897eSJiri Prchal /* DAC Quiescent Current Adjustment Register */ 173784a897eSJiri Prchal #define DAC_ICC_ADJ 109 17444d0a879SVladimir Barinov 17544d0a879SVladimir Barinov /* Page select register bits */ 17644d0a879SVladimir Barinov #define PAGE0_SELECT 0 17744d0a879SVladimir Barinov #define PAGE1_SELECT 1 17844d0a879SVladimir Barinov 17944d0a879SVladimir Barinov /* Audio serial data interface control register A bits */ 18044d0a879SVladimir Barinov #define BIT_CLK_MASTER 0x80 18144d0a879SVladimir Barinov #define WORD_CLK_MASTER 0x40 18236849409SPeter Ujfalusi #define DOUT_TRISTATE 0x20 18344d0a879SVladimir Barinov 18444d0a879SVladimir Barinov /* Codec Datapath setup register 7 */ 18544d0a879SVladimir Barinov #define FSREF_44100 (1 << 7) 18644d0a879SVladimir Barinov #define FSREF_48000 (0 << 7) 18744d0a879SVladimir Barinov #define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) 18844d0a879SVladimir Barinov #define LDAC2LCH (0x1 << 3) 18944d0a879SVladimir Barinov #define RDAC2RCH (0x1 << 1) 190784a897eSJiri Prchal #define LDAC2RCH (0x2 << 3) 191784a897eSJiri Prchal #define RDAC2LCH (0x2 << 1) 192784a897eSJiri Prchal #define LDAC2MONOMIX (0x3 << 3) 193784a897eSJiri Prchal #define RDAC2MONOMIX (0x3 << 1) 19444d0a879SVladimir Barinov 19544d0a879SVladimir Barinov /* PLL registers bitfields */ 19644d0a879SVladimir Barinov #define PLLP_SHIFT 0 197c9fe573aSHebbar, Gururaja #define PLLP_MASK 7 1984f9c16ccSDaniel Mack #define PLLQ_SHIFT 3 19944d0a879SVladimir Barinov #define PLLR_SHIFT 0 20044d0a879SVladimir Barinov #define PLLJ_SHIFT 2 20144d0a879SVladimir Barinov #define PLLD_MSB_SHIFT 0 20244d0a879SVladimir Barinov #define PLLD_LSB_SHIFT 2 20344d0a879SVladimir Barinov 20444d0a879SVladimir Barinov /* Clock generation register bits */ 2054f9c16ccSDaniel Mack #define CODEC_CLKIN_PLLDIV 0 2064f9c16ccSDaniel Mack #define CODEC_CLKIN_CLKDIV 1 20744d0a879SVladimir Barinov #define PLL_CLKIN_SHIFT 4 20844d0a879SVladimir Barinov #define MCLK_SOURCE 0x0 20944d0a879SVladimir Barinov #define PLL_CLKDIV_SHIFT 0 210a1f34af0SJiri Prchal #define PLLCLK_IN_MASK 0x30 211a1f34af0SJiri Prchal #define PLLCLK_IN_SHIFT 4 212a1f34af0SJiri Prchal #define CLKDIV_IN_MASK 0xc0 213a1f34af0SJiri Prchal #define CLKDIV_IN_SHIFT 6 214a1f34af0SJiri Prchal /* clock in source */ 215a1f34af0SJiri Prchal #define CLKIN_MCLK 0 216a1f34af0SJiri Prchal #define CLKIN_GPIO2 1 217a1f34af0SJiri Prchal #define CLKIN_BCLK 2 21844d0a879SVladimir Barinov 21944d0a879SVladimir Barinov /* Software reset register bits */ 22044d0a879SVladimir Barinov #define SOFT_RESET 0x80 22144d0a879SVladimir Barinov 22244d0a879SVladimir Barinov /* PLL progrramming register A bits */ 22344d0a879SVladimir Barinov #define PLL_ENABLE 0x80 22444d0a879SVladimir Barinov 22544d0a879SVladimir Barinov /* Route bits */ 22644d0a879SVladimir Barinov #define ROUTE_ON 0x80 22744d0a879SVladimir Barinov 22844d0a879SVladimir Barinov /* Mute bits */ 22944d0a879SVladimir Barinov #define UNMUTE 0x08 23044d0a879SVladimir Barinov #define MUTE_ON 0x80 23144d0a879SVladimir Barinov 23244d0a879SVladimir Barinov /* Power bits */ 23344d0a879SVladimir Barinov #define LADC_PWR_ON 0x04 23444d0a879SVladimir Barinov #define RADC_PWR_ON 0x04 23544d0a879SVladimir Barinov #define LDAC_PWR_ON 0x80 23644d0a879SVladimir Barinov #define RDAC_PWR_ON 0x40 23744d0a879SVladimir Barinov #define HPLOUT_PWR_ON 0x01 23844d0a879SVladimir Barinov #define HPROUT_PWR_ON 0x01 23944d0a879SVladimir Barinov #define HPLCOM_PWR_ON 0x01 24044d0a879SVladimir Barinov #define HPRCOM_PWR_ON 0x01 24144d0a879SVladimir Barinov #define MONOLOPM_PWR_ON 0x01 24244d0a879SVladimir Barinov #define LLOPM_PWR_ON 0x01 24344d0a879SVladimir Barinov #define RLOPM_PWR_ON 0x01 24444d0a879SVladimir Barinov 24544d0a879SVladimir Barinov #define INVERT_VOL(val) (0x7f - val) 24644d0a879SVladimir Barinov 24744d0a879SVladimir Barinov /* Default output volume (inverted) */ 24844d0a879SVladimir Barinov #define DEFAULT_VOL INVERT_VOL(0x50) 24944d0a879SVladimir Barinov /* Default input volume */ 25044d0a879SVladimir Barinov #define DEFAULT_GAIN 0x20 25144d0a879SVladimir Barinov 252e2e8bfdfSHebbar Gururaja /* MICBIAS Control Register */ 253e2e8bfdfSHebbar Gururaja #define MICBIAS_LEVEL_SHIFT (6) 254e2e8bfdfSHebbar Gururaja #define MICBIAS_LEVEL_MASK (3 << 6) 255e2e8bfdfSHebbar Gururaja 25619b0fa11SPeter Ujfalusi /* HPOUT_SC */ 25719b0fa11SPeter Ujfalusi #define HPOUT_SC_OCMV_MASK (3 << 6) 25819b0fa11SPeter Ujfalusi #define HPOUT_SC_OCMV_SHIFT (6) 25919b0fa11SPeter Ujfalusi #define HPOUT_SC_OCMV_1_35V 0 26019b0fa11SPeter Ujfalusi #define HPOUT_SC_OCMV_1_5V 1 26119b0fa11SPeter Ujfalusi #define HPOUT_SC_OCMV_1_65V 2 26219b0fa11SPeter Ujfalusi #define HPOUT_SC_OCMV_1_8V 3 26319b0fa11SPeter Ujfalusi 2646f2a974bSDaniel Mack /* headset detection / button API */ 2656f2a974bSDaniel Mack 2666f2a974bSDaniel Mack /* The AIC3x supports detection of stereo headsets (GND + left + right signal) 2676f2a974bSDaniel Mack * and cellular headsets (GND + speaker output + microphone input). 2686f2a974bSDaniel Mack * It is recommended to enable MIC bias for this function to work properly. 2696f2a974bSDaniel Mack * For more information, please refer to the datasheet. */ 2706f2a974bSDaniel Mack enum { 2716f2a974bSDaniel Mack AIC3X_HEADSET_DETECT_OFF = 0, 2726f2a974bSDaniel Mack AIC3X_HEADSET_DETECT_STEREO = 1, 2736f2a974bSDaniel Mack AIC3X_HEADSET_DETECT_CELLULAR = 2, 2746f2a974bSDaniel Mack AIC3X_HEADSET_DETECT_BOTH = 3 2756f2a974bSDaniel Mack }; 2766f2a974bSDaniel Mack 2776f2a974bSDaniel Mack enum { 2786f2a974bSDaniel Mack AIC3X_HEADSET_DEBOUNCE_16MS = 0, 2796f2a974bSDaniel Mack AIC3X_HEADSET_DEBOUNCE_32MS = 1, 2806f2a974bSDaniel Mack AIC3X_HEADSET_DEBOUNCE_64MS = 2, 2816f2a974bSDaniel Mack AIC3X_HEADSET_DEBOUNCE_128MS = 3, 2826f2a974bSDaniel Mack AIC3X_HEADSET_DEBOUNCE_256MS = 4, 2836f2a974bSDaniel Mack AIC3X_HEADSET_DEBOUNCE_512MS = 5 2846f2a974bSDaniel Mack }; 2856f2a974bSDaniel Mack 2866f2a974bSDaniel Mack enum { 2876f2a974bSDaniel Mack AIC3X_BUTTON_DEBOUNCE_0MS = 0, 2886f2a974bSDaniel Mack AIC3X_BUTTON_DEBOUNCE_8MS = 1, 2896f2a974bSDaniel Mack AIC3X_BUTTON_DEBOUNCE_16MS = 2, 2906f2a974bSDaniel Mack AIC3X_BUTTON_DEBOUNCE_32MS = 3 2916f2a974bSDaniel Mack }; 2926f2a974bSDaniel Mack 2936f2a974bSDaniel Mack #define AIC3X_HEADSET_DETECT_ENABLED 0x80 2946f2a974bSDaniel Mack #define AIC3X_HEADSET_DETECT_SHIFT 5 2956f2a974bSDaniel Mack #define AIC3X_HEADSET_DETECT_MASK 3 2966f2a974bSDaniel Mack #define AIC3X_HEADSET_DEBOUNCE_SHIFT 2 2976f2a974bSDaniel Mack #define AIC3X_HEADSET_DEBOUNCE_MASK 7 2986f2a974bSDaniel Mack #define AIC3X_BUTTON_DEBOUNCE_SHIFT 0 2996f2a974bSDaniel Mack #define AIC3X_BUTTON_DEBOUNCE_MASK 3 3006f2a974bSDaniel Mack 301*426c7bf4SDmitry Torokhov /* GPIO API */ 302*426c7bf4SDmitry Torokhov enum { 303*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_DISABLED = 0, 304*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC = 1, 305*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_CLOCK_MUX = 2, 306*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 = 3, 307*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 = 4, 308*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 = 5, 309*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ = 6, 310*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ = 7, 311*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_INPUT = 8, 312*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_OUTPUT = 9, 313*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK = 10, 314*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_AUDIO_WORDCLK = 11, 315*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_BUTTON_IRQ = 12, 316*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ = 13, 317*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 14, 318*426c7bf4SDmitry Torokhov AIC3X_GPIO1_FUNC_ALL_IRQ = 16 319*426c7bf4SDmitry Torokhov }; 320*426c7bf4SDmitry Torokhov 321*426c7bf4SDmitry Torokhov enum { 322*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_DISABLED = 0, 323*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ = 2, 324*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_INPUT = 3, 325*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_OUTPUT = 4, 326*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT = 5, 327*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_AUDIO_BITCLK = 8, 328*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9, 329*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_ALL_IRQ = 10, 330*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11, 331*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12, 332*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ = 13, 333*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ = 14, 334*426c7bf4SDmitry Torokhov AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ = 15 335*426c7bf4SDmitry Torokhov }; 336*426c7bf4SDmitry Torokhov 337*426c7bf4SDmitry Torokhov enum aic3x_micbias_voltage { 338*426c7bf4SDmitry Torokhov AIC3X_MICBIAS_OFF = 0, 339*426c7bf4SDmitry Torokhov AIC3X_MICBIAS_2_0V = 1, 340*426c7bf4SDmitry Torokhov AIC3X_MICBIAS_2_5V = 2, 341*426c7bf4SDmitry Torokhov AIC3X_MICBIAS_AVDDV = 3, 342*426c7bf4SDmitry Torokhov }; 343*426c7bf4SDmitry Torokhov 34444d0a879SVladimir Barinov #endif /* _AIC3X_H */ 345