144d0a879SVladimir Barinov /* 244d0a879SVladimir Barinov * ALSA SoC TLV320AIC3X codec driver 344d0a879SVladimir Barinov * 4d6b52039SVladimir Barinov * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 544d0a879SVladimir Barinov * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 644d0a879SVladimir Barinov * 744d0a879SVladimir Barinov * This program is free software; you can redistribute it and/or modify 844d0a879SVladimir Barinov * it under the terms of the GNU General Public License version 2 as 944d0a879SVladimir Barinov * published by the Free Software Foundation. 1044d0a879SVladimir Barinov */ 1144d0a879SVladimir Barinov 1244d0a879SVladimir Barinov #ifndef _AIC3X_H 1344d0a879SVladimir Barinov #define _AIC3X_H 1444d0a879SVladimir Barinov 1544d0a879SVladimir Barinov /* AIC3X register space */ 16784a897eSJiri Prchal #define AIC3X_CACHEREGNUM 110 1744d0a879SVladimir Barinov 1844d0a879SVladimir Barinov /* Page select register */ 1944d0a879SVladimir Barinov #define AIC3X_PAGE_SELECT 0 2044d0a879SVladimir Barinov /* Software reset register */ 2144d0a879SVladimir Barinov #define AIC3X_RESET 1 2244d0a879SVladimir Barinov /* Codec Sample rate select register */ 2344d0a879SVladimir Barinov #define AIC3X_SAMPLE_RATE_SEL_REG 2 2444d0a879SVladimir Barinov /* PLL progrramming register A */ 2544d0a879SVladimir Barinov #define AIC3X_PLL_PROGA_REG 3 2644d0a879SVladimir Barinov /* PLL progrramming register B */ 2744d0a879SVladimir Barinov #define AIC3X_PLL_PROGB_REG 4 2844d0a879SVladimir Barinov /* PLL progrramming register C */ 2944d0a879SVladimir Barinov #define AIC3X_PLL_PROGC_REG 5 3044d0a879SVladimir Barinov /* PLL progrramming register D */ 3144d0a879SVladimir Barinov #define AIC3X_PLL_PROGD_REG 6 3244d0a879SVladimir Barinov /* Codec datapath setup register */ 3344d0a879SVladimir Barinov #define AIC3X_CODEC_DATAPATH_REG 7 3444d0a879SVladimir Barinov /* Audio serial data interface control register A */ 3544d0a879SVladimir Barinov #define AIC3X_ASD_INTF_CTRLA 8 3644d0a879SVladimir Barinov /* Audio serial data interface control register B */ 3744d0a879SVladimir Barinov #define AIC3X_ASD_INTF_CTRLB 9 38a24f4f68STroy Kisky /* Audio serial data interface control register C */ 39a24f4f68STroy Kisky #define AIC3X_ASD_INTF_CTRLC 10 4044d0a879SVladimir Barinov /* Audio overflow status and PLL R value programming register */ 4144d0a879SVladimir Barinov #define AIC3X_OVRF_STATUS_AND_PLLR_REG 11 424d20f70aSJarkko Nikula /* Audio codec digital filter control register */ 434d20f70aSJarkko Nikula #define AIC3X_CODEC_DFILT_CTRL 12 446f2a974bSDaniel Mack /* Headset/button press detection register */ 456f2a974bSDaniel Mack #define AIC3X_HEADSET_DETECT_CTRL_A 13 466f2a974bSDaniel Mack #define AIC3X_HEADSET_DETECT_CTRL_B 14 4744d0a879SVladimir Barinov /* ADC PGA Gain control registers */ 4844d0a879SVladimir Barinov #define LADC_VOL 15 4944d0a879SVladimir Barinov #define RADC_VOL 16 5044d0a879SVladimir Barinov /* MIC3 control registers */ 5144d0a879SVladimir Barinov #define MIC3LR_2_LADC_CTRL 17 5244d0a879SVladimir Barinov #define MIC3LR_2_RADC_CTRL 18 5344d0a879SVladimir Barinov /* Line1 Input control registers */ 5444d0a879SVladimir Barinov #define LINE1L_2_LADC_CTRL 19 5554f01916SDaniel Mack #define LINE1R_2_LADC_CTRL 21 5644d0a879SVladimir Barinov #define LINE1R_2_RADC_CTRL 22 5754f01916SDaniel Mack #define LINE1L_2_RADC_CTRL 24 5844d0a879SVladimir Barinov /* Line2 Input control registers */ 5944d0a879SVladimir Barinov #define LINE2L_2_LADC_CTRL 20 6044d0a879SVladimir Barinov #define LINE2R_2_RADC_CTRL 23 6144d0a879SVladimir Barinov /* MICBIAS Control Register */ 6244d0a879SVladimir Barinov #define MICBIAS_CTRL 25 6344d0a879SVladimir Barinov 6444d0a879SVladimir Barinov /* AGC Control Registers A, B, C */ 6544d0a879SVladimir Barinov #define LAGC_CTRL_A 26 6644d0a879SVladimir Barinov #define LAGC_CTRL_B 27 6744d0a879SVladimir Barinov #define LAGC_CTRL_C 28 6844d0a879SVladimir Barinov #define RAGC_CTRL_A 29 6944d0a879SVladimir Barinov #define RAGC_CTRL_B 30 7044d0a879SVladimir Barinov #define RAGC_CTRL_C 31 7144d0a879SVladimir Barinov 7244d0a879SVladimir Barinov /* DAC Power and Left High Power Output control registers */ 7344d0a879SVladimir Barinov #define DAC_PWR 37 7444d0a879SVladimir Barinov #define HPLCOM_CFG 37 7544d0a879SVladimir Barinov /* Right High Power Output control registers */ 7644d0a879SVladimir Barinov #define HPRCOM_CFG 38 77784a897eSJiri Prchal /* High Power Output Stage Control Register */ 78784a897eSJiri Prchal #define HPOUT_SC 40 7944d0a879SVladimir Barinov /* DAC Output Switching control registers */ 8044d0a879SVladimir Barinov #define DAC_LINE_MUX 41 8144d0a879SVladimir Barinov /* High Power Output Driver Pop Reduction registers */ 8244d0a879SVladimir Barinov #define HPOUT_POP_REDUCTION 42 8344d0a879SVladimir Barinov /* DAC Digital control registers */ 8444d0a879SVladimir Barinov #define LDAC_VOL 43 8544d0a879SVladimir Barinov #define RDAC_VOL 44 86b2eaac20SJarkko Nikula /* Left High Power Output control registers */ 8744d0a879SVladimir Barinov #define LINE2L_2_HPLOUT_VOL 45 8844d0a879SVladimir Barinov #define PGAL_2_HPLOUT_VOL 46 8944d0a879SVladimir Barinov #define DACL1_2_HPLOUT_VOL 47 90c3b79e05SJarkko Nikula #define LINE2R_2_HPLOUT_VOL 48 91b2eaac20SJarkko Nikula #define PGAR_2_HPLOUT_VOL 49 92c3b79e05SJarkko Nikula #define DACR1_2_HPLOUT_VOL 50 9344d0a879SVladimir Barinov #define HPLOUT_CTRL 51 94b2eaac20SJarkko Nikula /* Left High Power COM control registers */ 9544d0a879SVladimir Barinov #define LINE2L_2_HPLCOM_VOL 52 9644d0a879SVladimir Barinov #define PGAL_2_HPLCOM_VOL 53 9744d0a879SVladimir Barinov #define DACL1_2_HPLCOM_VOL 54 98c3b79e05SJarkko Nikula #define LINE2R_2_HPLCOM_VOL 55 99b2eaac20SJarkko Nikula #define PGAR_2_HPLCOM_VOL 56 100c3b79e05SJarkko Nikula #define DACR1_2_HPLCOM_VOL 57 10144d0a879SVladimir Barinov #define HPLCOM_CTRL 58 102b2eaac20SJarkko Nikula /* Right High Power Output control registers */ 103c3b79e05SJarkko Nikula #define LINE2L_2_HPROUT_VOL 59 104b2eaac20SJarkko Nikula #define PGAL_2_HPROUT_VOL 60 105c3b79e05SJarkko Nikula #define DACL1_2_HPROUT_VOL 61 106b2eaac20SJarkko Nikula #define LINE2R_2_HPROUT_VOL 62 107b2eaac20SJarkko Nikula #define PGAR_2_HPROUT_VOL 63 108b2eaac20SJarkko Nikula #define DACR1_2_HPROUT_VOL 64 109b2eaac20SJarkko Nikula #define HPROUT_CTRL 65 110b2eaac20SJarkko Nikula /* Right High Power COM control registers */ 111c3b79e05SJarkko Nikula #define LINE2L_2_HPRCOM_VOL 66 112b2eaac20SJarkko Nikula #define PGAL_2_HPRCOM_VOL 67 113c3b79e05SJarkko Nikula #define DACL1_2_HPRCOM_VOL 68 114b2eaac20SJarkko Nikula #define LINE2R_2_HPRCOM_VOL 69 115b2eaac20SJarkko Nikula #define PGAR_2_HPRCOM_VOL 70 116b2eaac20SJarkko Nikula #define DACR1_2_HPRCOM_VOL 71 11744d0a879SVladimir Barinov #define HPRCOM_CTRL 72 11844d0a879SVladimir Barinov /* Mono Line Output Plus/Minus control registers */ 11944d0a879SVladimir Barinov #define LINE2L_2_MONOLOPM_VOL 73 12044d0a879SVladimir Barinov #define PGAL_2_MONOLOPM_VOL 74 12144d0a879SVladimir Barinov #define DACL1_2_MONOLOPM_VOL 75 122b2eaac20SJarkko Nikula #define LINE2R_2_MONOLOPM_VOL 76 123b2eaac20SJarkko Nikula #define PGAR_2_MONOLOPM_VOL 77 12444d0a879SVladimir Barinov #define DACR1_2_MONOLOPM_VOL 78 12544d0a879SVladimir Barinov #define MONOLOPM_CTRL 79 1266184f105SRandolph Chung /* Class-D speaker driver on tlv320aic3007 */ 1276184f105SRandolph Chung #define CLASSD_CTRL 73 128b2eaac20SJarkko Nikula /* Left Line Output Plus/Minus control registers */ 12944d0a879SVladimir Barinov #define LINE2L_2_LLOPM_VOL 80 13044d0a879SVladimir Barinov #define PGAL_2_LLOPM_VOL 81 13144d0a879SVladimir Barinov #define DACL1_2_LLOPM_VOL 82 132b2eaac20SJarkko Nikula #define LINE2R_2_LLOPM_VOL 83 133b2eaac20SJarkko Nikula #define PGAR_2_LLOPM_VOL 84 13454f01916SDaniel Mack #define DACR1_2_LLOPM_VOL 85 13544d0a879SVladimir Barinov #define LLOPM_CTRL 86 136b2eaac20SJarkko Nikula /* Right Line Output Plus/Minus control registers */ 137b2eaac20SJarkko Nikula #define LINE2L_2_RLOPM_VOL 87 138b2eaac20SJarkko Nikula #define PGAL_2_RLOPM_VOL 88 139b2eaac20SJarkko Nikula #define DACL1_2_RLOPM_VOL 89 140b2eaac20SJarkko Nikula #define LINE2R_2_RLOPM_VOL 90 141b2eaac20SJarkko Nikula #define PGAR_2_RLOPM_VOL 91 142b2eaac20SJarkko Nikula #define DACR1_2_RLOPM_VOL 92 14344d0a879SVladimir Barinov #define RLOPM_CTRL 93 14454e7e616SDaniel Mack /* GPIO/IRQ registers */ 14554e7e616SDaniel Mack #define AIC3X_STICKY_IRQ_FLAGS_REG 96 14654e7e616SDaniel Mack #define AIC3X_RT_IRQ_FLAGS_REG 97 14754e7e616SDaniel Mack #define AIC3X_GPIO1_REG 98 14854e7e616SDaniel Mack #define AIC3X_GPIO2_REG 99 14954e7e616SDaniel Mack #define AIC3X_GPIOA_REG 100 1504f9c16ccSDaniel Mack #define AIC3X_GPIOB_REG 101 15154e7e616SDaniel Mack /* Clock generation control register */ 15244d0a879SVladimir Barinov #define AIC3X_CLKGEN_CTRL_REG 102 153784a897eSJiri Prchal /* New AGC registers */ 154784a897eSJiri Prchal #define LAGCN_ATTACK 103 155784a897eSJiri Prchal #define LAGCN_DECAY 104 156784a897eSJiri Prchal #define RAGCN_ATTACK 105 157784a897eSJiri Prchal #define RAGCN_DECAY 106 158784a897eSJiri Prchal /* New Programmable ADC Digital Path and I2C Bus Condition Register */ 159784a897eSJiri Prchal #define NEW_ADC_DIGITALPATH 107 160784a897eSJiri Prchal /* Passive Analog Signal Bypass Selection During Powerdown Register */ 161784a897eSJiri Prchal #define PASSIVE_BYPASS 108 162784a897eSJiri Prchal /* DAC Quiescent Current Adjustment Register */ 163784a897eSJiri Prchal #define DAC_ICC_ADJ 109 16444d0a879SVladimir Barinov 16544d0a879SVladimir Barinov /* Page select register bits */ 16644d0a879SVladimir Barinov #define PAGE0_SELECT 0 16744d0a879SVladimir Barinov #define PAGE1_SELECT 1 16844d0a879SVladimir Barinov 16944d0a879SVladimir Barinov /* Audio serial data interface control register A bits */ 17044d0a879SVladimir Barinov #define BIT_CLK_MASTER 0x80 17144d0a879SVladimir Barinov #define WORD_CLK_MASTER 0x40 17236849409SPeter Ujfalusi #define DOUT_TRISTATE 0x20 17344d0a879SVladimir Barinov 17444d0a879SVladimir Barinov /* Codec Datapath setup register 7 */ 17544d0a879SVladimir Barinov #define FSREF_44100 (1 << 7) 17644d0a879SVladimir Barinov #define FSREF_48000 (0 << 7) 17744d0a879SVladimir Barinov #define DUAL_RATE_MODE ((1 << 5) | (1 << 6)) 17844d0a879SVladimir Barinov #define LDAC2LCH (0x1 << 3) 17944d0a879SVladimir Barinov #define RDAC2RCH (0x1 << 1) 180784a897eSJiri Prchal #define LDAC2RCH (0x2 << 3) 181784a897eSJiri Prchal #define RDAC2LCH (0x2 << 1) 182784a897eSJiri Prchal #define LDAC2MONOMIX (0x3 << 3) 183784a897eSJiri Prchal #define RDAC2MONOMIX (0x3 << 1) 18444d0a879SVladimir Barinov 18544d0a879SVladimir Barinov /* PLL registers bitfields */ 18644d0a879SVladimir Barinov #define PLLP_SHIFT 0 187c9fe573aSHebbar, Gururaja #define PLLP_MASK 7 1884f9c16ccSDaniel Mack #define PLLQ_SHIFT 3 18944d0a879SVladimir Barinov #define PLLR_SHIFT 0 19044d0a879SVladimir Barinov #define PLLJ_SHIFT 2 19144d0a879SVladimir Barinov #define PLLD_MSB_SHIFT 0 19244d0a879SVladimir Barinov #define PLLD_LSB_SHIFT 2 19344d0a879SVladimir Barinov 19444d0a879SVladimir Barinov /* Clock generation register bits */ 1954f9c16ccSDaniel Mack #define CODEC_CLKIN_PLLDIV 0 1964f9c16ccSDaniel Mack #define CODEC_CLKIN_CLKDIV 1 19744d0a879SVladimir Barinov #define PLL_CLKIN_SHIFT 4 19844d0a879SVladimir Barinov #define MCLK_SOURCE 0x0 19944d0a879SVladimir Barinov #define PLL_CLKDIV_SHIFT 0 200a1f34af0SJiri Prchal #define PLLCLK_IN_MASK 0x30 201a1f34af0SJiri Prchal #define PLLCLK_IN_SHIFT 4 202a1f34af0SJiri Prchal #define CLKDIV_IN_MASK 0xc0 203a1f34af0SJiri Prchal #define CLKDIV_IN_SHIFT 6 204a1f34af0SJiri Prchal /* clock in source */ 205a1f34af0SJiri Prchal #define CLKIN_MCLK 0 206a1f34af0SJiri Prchal #define CLKIN_GPIO2 1 207a1f34af0SJiri Prchal #define CLKIN_BCLK 2 20844d0a879SVladimir Barinov 20944d0a879SVladimir Barinov /* Software reset register bits */ 21044d0a879SVladimir Barinov #define SOFT_RESET 0x80 21144d0a879SVladimir Barinov 21244d0a879SVladimir Barinov /* PLL progrramming register A bits */ 21344d0a879SVladimir Barinov #define PLL_ENABLE 0x80 21444d0a879SVladimir Barinov 21544d0a879SVladimir Barinov /* Route bits */ 21644d0a879SVladimir Barinov #define ROUTE_ON 0x80 21744d0a879SVladimir Barinov 21844d0a879SVladimir Barinov /* Mute bits */ 21944d0a879SVladimir Barinov #define UNMUTE 0x08 22044d0a879SVladimir Barinov #define MUTE_ON 0x80 22144d0a879SVladimir Barinov 22244d0a879SVladimir Barinov /* Power bits */ 22344d0a879SVladimir Barinov #define LADC_PWR_ON 0x04 22444d0a879SVladimir Barinov #define RADC_PWR_ON 0x04 22544d0a879SVladimir Barinov #define LDAC_PWR_ON 0x80 22644d0a879SVladimir Barinov #define RDAC_PWR_ON 0x40 22744d0a879SVladimir Barinov #define HPLOUT_PWR_ON 0x01 22844d0a879SVladimir Barinov #define HPROUT_PWR_ON 0x01 22944d0a879SVladimir Barinov #define HPLCOM_PWR_ON 0x01 23044d0a879SVladimir Barinov #define HPRCOM_PWR_ON 0x01 23144d0a879SVladimir Barinov #define MONOLOPM_PWR_ON 0x01 23244d0a879SVladimir Barinov #define LLOPM_PWR_ON 0x01 23344d0a879SVladimir Barinov #define RLOPM_PWR_ON 0x01 23444d0a879SVladimir Barinov 23544d0a879SVladimir Barinov #define INVERT_VOL(val) (0x7f - val) 23644d0a879SVladimir Barinov 23744d0a879SVladimir Barinov /* Default output volume (inverted) */ 23844d0a879SVladimir Barinov #define DEFAULT_VOL INVERT_VOL(0x50) 23944d0a879SVladimir Barinov /* Default input volume */ 24044d0a879SVladimir Barinov #define DEFAULT_GAIN 0x20 24144d0a879SVladimir Barinov 242e2e8bfdfSHebbar Gururaja /* MICBIAS Control Register */ 243e2e8bfdfSHebbar Gururaja #define MICBIAS_LEVEL_SHIFT (6) 244e2e8bfdfSHebbar Gururaja #define MICBIAS_LEVEL_MASK (3 << 6) 245e2e8bfdfSHebbar Gururaja 2466f2a974bSDaniel Mack /* headset detection / button API */ 2476f2a974bSDaniel Mack 2486f2a974bSDaniel Mack /* The AIC3x supports detection of stereo headsets (GND + left + right signal) 2496f2a974bSDaniel Mack * and cellular headsets (GND + speaker output + microphone input). 2506f2a974bSDaniel Mack * It is recommended to enable MIC bias for this function to work properly. 2516f2a974bSDaniel Mack * For more information, please refer to the datasheet. */ 2526f2a974bSDaniel Mack enum { 2536f2a974bSDaniel Mack AIC3X_HEADSET_DETECT_OFF = 0, 2546f2a974bSDaniel Mack AIC3X_HEADSET_DETECT_STEREO = 1, 2556f2a974bSDaniel Mack AIC3X_HEADSET_DETECT_CELLULAR = 2, 2566f2a974bSDaniel Mack AIC3X_HEADSET_DETECT_BOTH = 3 2576f2a974bSDaniel Mack }; 2586f2a974bSDaniel Mack 2596f2a974bSDaniel Mack enum { 2606f2a974bSDaniel Mack AIC3X_HEADSET_DEBOUNCE_16MS = 0, 2616f2a974bSDaniel Mack AIC3X_HEADSET_DEBOUNCE_32MS = 1, 2626f2a974bSDaniel Mack AIC3X_HEADSET_DEBOUNCE_64MS = 2, 2636f2a974bSDaniel Mack AIC3X_HEADSET_DEBOUNCE_128MS = 3, 2646f2a974bSDaniel Mack AIC3X_HEADSET_DEBOUNCE_256MS = 4, 2656f2a974bSDaniel Mack AIC3X_HEADSET_DEBOUNCE_512MS = 5 2666f2a974bSDaniel Mack }; 2676f2a974bSDaniel Mack 2686f2a974bSDaniel Mack enum { 2696f2a974bSDaniel Mack AIC3X_BUTTON_DEBOUNCE_0MS = 0, 2706f2a974bSDaniel Mack AIC3X_BUTTON_DEBOUNCE_8MS = 1, 2716f2a974bSDaniel Mack AIC3X_BUTTON_DEBOUNCE_16MS = 2, 2726f2a974bSDaniel Mack AIC3X_BUTTON_DEBOUNCE_32MS = 3 2736f2a974bSDaniel Mack }; 2746f2a974bSDaniel Mack 2756f2a974bSDaniel Mack #define AIC3X_HEADSET_DETECT_ENABLED 0x80 2766f2a974bSDaniel Mack #define AIC3X_HEADSET_DETECT_SHIFT 5 2776f2a974bSDaniel Mack #define AIC3X_HEADSET_DETECT_MASK 3 2786f2a974bSDaniel Mack #define AIC3X_HEADSET_DEBOUNCE_SHIFT 2 2796f2a974bSDaniel Mack #define AIC3X_HEADSET_DEBOUNCE_MASK 7 2806f2a974bSDaniel Mack #define AIC3X_BUTTON_DEBOUNCE_SHIFT 0 2816f2a974bSDaniel Mack #define AIC3X_BUTTON_DEBOUNCE_MASK 3 2826f2a974bSDaniel Mack 28344d0a879SVladimir Barinov #endif /* _AIC3X_H */ 284