1 /* 2 * ALSA SoC TLV320AIC3X codec driver 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Notes: 14 * The AIC3X is a driver for a low power stereo audio 15 * codecs aic31, aic32, aic33, aic3007. 16 * 17 * It supports full aic33 codec functionality. 18 * The compatibility with aic32, aic31 and aic3007 is as follows: 19 * aic32/aic3007 | aic31 20 * --------------------------------------- 21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A 22 * | IN1L -> LINE1L 23 * | IN1R -> LINE1R 24 * | IN2L -> LINE2L 25 * | IN2R -> LINE2R 26 * | MIC3L/R -> N/A 27 * truncated internal functionality in 28 * accordance with documentation 29 * --------------------------------------- 30 * 31 * Hence the machine layer should disable unsupported inputs/outputs by 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/init.h> 38 #include <linux/delay.h> 39 #include <linux/pm.h> 40 #include <linux/i2c.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/of_gpio.h> 44 #include <linux/slab.h> 45 #include <sound/core.h> 46 #include <sound/pcm.h> 47 #include <sound/pcm_params.h> 48 #include <sound/soc.h> 49 #include <sound/initval.h> 50 #include <sound/tlv.h> 51 #include <sound/tlv320aic3x.h> 52 53 #include "tlv320aic3x.h" 54 55 #define AIC3X_NUM_SUPPLIES 4 56 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { 57 "IOVDD", /* I/O Voltage */ 58 "DVDD", /* Digital Core Voltage */ 59 "AVDD", /* Analog DAC Voltage */ 60 "DRVDD", /* ADC Analog and Output Driver Voltage */ 61 }; 62 63 static LIST_HEAD(reset_list); 64 65 struct aic3x_priv; 66 67 struct aic3x_disable_nb { 68 struct notifier_block nb; 69 struct aic3x_priv *aic3x; 70 }; 71 72 /* codec private data */ 73 struct aic3x_priv { 74 struct snd_soc_codec *codec; 75 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; 76 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES]; 77 enum snd_soc_control_type control_type; 78 struct aic3x_setup_data *setup; 79 unsigned int sysclk; 80 struct list_head list; 81 int master; 82 int gpio_reset; 83 int power; 84 #define AIC3X_MODEL_3X 0 85 #define AIC3X_MODEL_33 1 86 #define AIC3X_MODEL_3007 2 87 u16 model; 88 89 /* Selects the micbias voltage */ 90 enum aic3x_micbias_voltage micbias_vg; 91 }; 92 93 /* 94 * AIC3X register cache 95 * We can't read the AIC3X register space when we are 96 * using 2 wire for device control, so we cache them instead. 97 * There is no point in caching the reset register 98 */ 99 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { 100 0x00, 0x00, 0x00, 0x10, /* 0 */ 101 0x04, 0x00, 0x00, 0x00, /* 4 */ 102 0x00, 0x00, 0x00, 0x01, /* 8 */ 103 0x00, 0x00, 0x00, 0x80, /* 12 */ 104 0x80, 0xff, 0xff, 0x78, /* 16 */ 105 0x78, 0x78, 0x78, 0x78, /* 20 */ 106 0x78, 0x00, 0x00, 0xfe, /* 24 */ 107 0x00, 0x00, 0xfe, 0x00, /* 28 */ 108 0x18, 0x18, 0x00, 0x00, /* 32 */ 109 0x00, 0x00, 0x00, 0x00, /* 36 */ 110 0x00, 0x00, 0x00, 0x80, /* 40 */ 111 0x80, 0x00, 0x00, 0x00, /* 44 */ 112 0x00, 0x00, 0x00, 0x04, /* 48 */ 113 0x00, 0x00, 0x00, 0x00, /* 52 */ 114 0x00, 0x00, 0x04, 0x00, /* 56 */ 115 0x00, 0x00, 0x00, 0x00, /* 60 */ 116 0x00, 0x04, 0x00, 0x00, /* 64 */ 117 0x00, 0x00, 0x00, 0x00, /* 68 */ 118 0x04, 0x00, 0x00, 0x00, /* 72 */ 119 0x00, 0x00, 0x00, 0x00, /* 76 */ 120 0x00, 0x00, 0x00, 0x00, /* 80 */ 121 0x00, 0x00, 0x00, 0x00, /* 84 */ 122 0x00, 0x00, 0x00, 0x00, /* 88 */ 123 0x00, 0x00, 0x00, 0x00, /* 92 */ 124 0x00, 0x00, 0x00, 0x00, /* 96 */ 125 0x00, 0x00, 0x02, 0x00, /* 100 */ 126 0x00, 0x00, 0x00, 0x00, /* 104 */ 127 0x00, 0x00, /* 108 */ 128 }; 129 130 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ 131 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \ 132 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x) 133 134 /* 135 * All input lines are connected when !0xf and disconnected with 0xf bit field, 136 * so we have to use specific dapm_put call for input mixer 137 */ 138 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, 139 struct snd_ctl_elem_value *ucontrol) 140 { 141 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); 142 struct soc_mixer_control *mc = 143 (struct soc_mixer_control *)kcontrol->private_value; 144 unsigned int reg = mc->reg; 145 unsigned int shift = mc->shift; 146 int max = mc->max; 147 unsigned int mask = (1 << fls(max)) - 1; 148 unsigned int invert = mc->invert; 149 unsigned short val; 150 struct snd_soc_dapm_update update; 151 int connect, change; 152 153 val = (ucontrol->value.integer.value[0] & mask); 154 155 mask = 0xf; 156 if (val) 157 val = mask; 158 159 connect = !!val; 160 161 if (invert) 162 val = mask - val; 163 164 mask <<= shift; 165 val <<= shift; 166 167 change = snd_soc_test_bits(codec, val, mask, reg); 168 if (change) { 169 update.kcontrol = kcontrol; 170 update.reg = reg; 171 update.mask = mask; 172 update.val = val; 173 174 snd_soc_dapm_mixer_update_power(&codec->dapm, kcontrol, connect, 175 &update); 176 } 177 178 return change; 179 } 180 181 /* 182 * mic bias power on/off share the same register bits with 183 * output voltage of mic bias. when power on mic bias, we 184 * need reclaim it to voltage value. 185 * 0x0 = Powered off 186 * 0x1 = MICBIAS output is powered to 2.0V, 187 * 0x2 = MICBIAS output is powered to 2.5V 188 * 0x3 = MICBIAS output is connected to AVDD 189 */ 190 static int mic_bias_event(struct snd_soc_dapm_widget *w, 191 struct snd_kcontrol *kcontrol, int event) 192 { 193 struct snd_soc_codec *codec = w->codec; 194 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 195 196 switch (event) { 197 case SND_SOC_DAPM_POST_PMU: 198 /* change mic bias voltage to user defined */ 199 snd_soc_update_bits(codec, MICBIAS_CTRL, 200 MICBIAS_LEVEL_MASK, 201 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT); 202 break; 203 204 case SND_SOC_DAPM_PRE_PMD: 205 snd_soc_update_bits(codec, MICBIAS_CTRL, 206 MICBIAS_LEVEL_MASK, 0); 207 break; 208 } 209 return 0; 210 } 211 212 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; 213 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; 214 static const char *aic3x_left_hpcom_mux[] = 215 { "differential of HPLOUT", "constant VCM", "single-ended" }; 216 static const char *aic3x_right_hpcom_mux[] = 217 { "differential of HPROUT", "constant VCM", "single-ended", 218 "differential of HPLCOM", "external feedback" }; 219 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; 220 static const char *aic3x_adc_hpf[] = 221 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; 222 223 #define LDAC_ENUM 0 224 #define RDAC_ENUM 1 225 #define LHPCOM_ENUM 2 226 #define RHPCOM_ENUM 3 227 #define LINE1L_2_L_ENUM 4 228 #define LINE1L_2_R_ENUM 5 229 #define LINE1R_2_L_ENUM 6 230 #define LINE1R_2_R_ENUM 7 231 #define LINE2L_ENUM 8 232 #define LINE2R_ENUM 9 233 #define ADC_HPF_ENUM 10 234 235 static const struct soc_enum aic3x_enum[] = { 236 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), 237 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), 238 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), 239 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), 240 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 241 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 242 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 243 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 244 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 245 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 246 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf), 247 }; 248 249 static const char *aic3x_agc_level[] = 250 { "-5.5dB", "-8dB", "-10dB", "-12dB", "-14dB", "-17dB", "-20dB", "-24dB" }; 251 static const struct soc_enum aic3x_agc_level_enum[] = { 252 SOC_ENUM_SINGLE(LAGC_CTRL_A, 4, 8, aic3x_agc_level), 253 SOC_ENUM_SINGLE(RAGC_CTRL_A, 4, 8, aic3x_agc_level), 254 }; 255 256 static const char *aic3x_agc_attack[] = { "8ms", "11ms", "16ms", "20ms" }; 257 static const struct soc_enum aic3x_agc_attack_enum[] = { 258 SOC_ENUM_SINGLE(LAGC_CTRL_A, 2, 4, aic3x_agc_attack), 259 SOC_ENUM_SINGLE(RAGC_CTRL_A, 2, 4, aic3x_agc_attack), 260 }; 261 262 static const char *aic3x_agc_decay[] = { "100ms", "200ms", "400ms", "500ms" }; 263 static const struct soc_enum aic3x_agc_decay_enum[] = { 264 SOC_ENUM_SINGLE(LAGC_CTRL_A, 0, 4, aic3x_agc_decay), 265 SOC_ENUM_SINGLE(RAGC_CTRL_A, 0, 4, aic3x_agc_decay), 266 }; 267 268 /* 269 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps 270 */ 271 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); 272 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ 273 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); 274 /* 275 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. 276 * Step size is approximately 0.5 dB over most of the scale but increasing 277 * near the very low levels. 278 * Define dB scale so that it is mostly correct for range about -55 to 0 dB 279 * but having increasing dB difference below that (and where it doesn't count 280 * so much). This setting shows -50 dB (actual is -50.3 dB) for register 281 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. 282 */ 283 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); 284 285 static const struct snd_kcontrol_new aic3x_snd_controls[] = { 286 /* Output */ 287 SOC_DOUBLE_R_TLV("PCM Playback Volume", 288 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 289 290 /* 291 * Output controls that map to output mixer switches. Note these are 292 * only for swapped L-to-R and R-to-L routes. See below stereo controls 293 * for direct L-to-L and R-to-R routes. 294 */ 295 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", 296 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 297 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", 298 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 299 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", 300 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 301 302 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", 303 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 304 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", 305 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 306 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", 307 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 308 309 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", 310 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 311 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", 312 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 313 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", 314 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 315 316 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", 317 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 318 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", 319 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 320 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", 321 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 322 323 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", 324 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 325 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", 326 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 327 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", 328 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 329 330 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", 331 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 332 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", 333 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 334 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", 335 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 336 337 /* Stereo output controls for direct L-to-L and R-to-R routes */ 338 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", 339 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, 340 0, 118, 1, output_stage_tlv), 341 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", 342 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, 343 0, 118, 1, output_stage_tlv), 344 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 345 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 346 0, 118, 1, output_stage_tlv), 347 348 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", 349 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 350 0, 118, 1, output_stage_tlv), 351 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", 352 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 353 0, 118, 1, output_stage_tlv), 354 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 355 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 356 0, 118, 1, output_stage_tlv), 357 358 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", 359 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 360 0, 118, 1, output_stage_tlv), 361 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", 362 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 363 0, 118, 1, output_stage_tlv), 364 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 365 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 366 0, 118, 1, output_stage_tlv), 367 368 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", 369 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 370 0, 118, 1, output_stage_tlv), 371 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", 372 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, 373 0, 118, 1, output_stage_tlv), 374 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 375 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 376 0, 118, 1, output_stage_tlv), 377 378 /* Output pin mute controls */ 379 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, 380 0x01, 0), 381 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 382 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 383 0x01, 0), 384 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 385 0x01, 0), 386 387 /* 388 * Note: enable Automatic input Gain Controller with care. It can 389 * adjust PGA to max value when ADC is on and will never go back. 390 */ 391 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), 392 SOC_ENUM("Left AGC Target level", aic3x_agc_level_enum[0]), 393 SOC_ENUM("Right AGC Target level", aic3x_agc_level_enum[1]), 394 SOC_ENUM("Left AGC Attack time", aic3x_agc_attack_enum[0]), 395 SOC_ENUM("Right AGC Attack time", aic3x_agc_attack_enum[1]), 396 SOC_ENUM("Left AGC Decay time", aic3x_agc_decay_enum[0]), 397 SOC_ENUM("Right AGC Decay time", aic3x_agc_decay_enum[1]), 398 399 /* De-emphasis */ 400 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0), 401 402 /* Input */ 403 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 404 0, 119, 0, adc_tlv), 405 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), 406 407 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]), 408 }; 409 410 /* 411 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps 412 */ 413 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0); 414 415 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl = 416 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv); 417 418 /* Left DAC Mux */ 419 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = 420 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); 421 422 /* Right DAC Mux */ 423 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = 424 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); 425 426 /* Left HPCOM Mux */ 427 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = 428 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); 429 430 /* Right HPCOM Mux */ 431 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = 432 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); 433 434 /* Left Line Mixer */ 435 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { 436 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), 437 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), 438 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), 439 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), 440 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), 441 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), 442 }; 443 444 /* Right Line Mixer */ 445 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { 446 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), 447 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), 448 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), 449 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), 450 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), 451 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), 452 }; 453 454 /* Mono Mixer */ 455 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { 456 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), 457 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), 458 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), 459 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), 460 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), 461 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), 462 }; 463 464 /* Left HP Mixer */ 465 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { 466 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), 467 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), 468 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), 469 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), 470 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), 471 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), 472 }; 473 474 /* Right HP Mixer */ 475 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { 476 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), 477 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), 478 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), 479 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), 480 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), 481 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), 482 }; 483 484 /* Left HPCOM Mixer */ 485 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { 486 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), 487 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), 488 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), 489 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), 490 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), 491 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), 492 }; 493 494 /* Right HPCOM Mixer */ 495 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { 496 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), 497 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), 498 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), 499 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), 500 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), 501 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), 502 }; 503 504 /* Left PGA Mixer */ 505 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { 506 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 507 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 508 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), 509 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 510 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 511 }; 512 513 /* Right PGA Mixer */ 514 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { 515 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 516 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 517 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), 518 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 519 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 520 }; 521 522 /* Left Line1 Mux */ 523 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls = 524 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]); 525 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls = 526 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]); 527 528 /* Right Line1 Mux */ 529 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls = 530 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]); 531 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls = 532 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]); 533 534 /* Left Line2 Mux */ 535 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = 536 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); 537 538 /* Right Line2 Mux */ 539 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = 540 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); 541 542 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { 543 /* Left DAC to Left Outputs */ 544 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), 545 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, 546 &aic3x_left_dac_mux_controls), 547 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, 548 &aic3x_left_hpcom_mux_controls), 549 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), 550 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), 551 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), 552 553 /* Right DAC to Right Outputs */ 554 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), 555 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, 556 &aic3x_right_dac_mux_controls), 557 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, 558 &aic3x_right_hpcom_mux_controls), 559 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), 560 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), 561 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), 562 563 /* Mono Output */ 564 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), 565 566 /* Inputs to Left ADC */ 567 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), 568 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 569 &aic3x_left_pga_mixer_controls[0], 570 ARRAY_SIZE(aic3x_left_pga_mixer_controls)), 571 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, 572 &aic3x_left_line1l_mux_controls), 573 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, 574 &aic3x_left_line1r_mux_controls), 575 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, 576 &aic3x_left_line2_mux_controls), 577 578 /* Inputs to Right ADC */ 579 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 580 LINE1R_2_RADC_CTRL, 2, 0), 581 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 582 &aic3x_right_pga_mixer_controls[0], 583 ARRAY_SIZE(aic3x_right_pga_mixer_controls)), 584 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, 585 &aic3x_right_line1l_mux_controls), 586 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, 587 &aic3x_right_line1r_mux_controls), 588 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, 589 &aic3x_right_line2_mux_controls), 590 591 /* 592 * Not a real mic bias widget but similar function. This is for dynamic 593 * control of GPIO1 digital mic modulator clock output function when 594 * using digital mic. 595 */ 596 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", 597 AIC3X_GPIO1_REG, 4, 0xf, 598 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, 599 AIC3X_GPIO1_FUNC_DISABLED), 600 601 /* 602 * Also similar function like mic bias. Selects digital mic with 603 * configurable oversampling rate instead of ADC converter. 604 */ 605 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", 606 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), 607 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", 608 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), 609 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", 610 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 611 612 /* Mic Bias */ 613 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0, 614 mic_bias_event, 615 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 616 617 /* Output mixers */ 618 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 619 &aic3x_left_line_mixer_controls[0], 620 ARRAY_SIZE(aic3x_left_line_mixer_controls)), 621 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 622 &aic3x_right_line_mixer_controls[0], 623 ARRAY_SIZE(aic3x_right_line_mixer_controls)), 624 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, 625 &aic3x_mono_mixer_controls[0], 626 ARRAY_SIZE(aic3x_mono_mixer_controls)), 627 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 628 &aic3x_left_hp_mixer_controls[0], 629 ARRAY_SIZE(aic3x_left_hp_mixer_controls)), 630 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 631 &aic3x_right_hp_mixer_controls[0], 632 ARRAY_SIZE(aic3x_right_hp_mixer_controls)), 633 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 634 &aic3x_left_hpcom_mixer_controls[0], 635 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), 636 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 637 &aic3x_right_hpcom_mixer_controls[0], 638 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), 639 640 SND_SOC_DAPM_OUTPUT("LLOUT"), 641 SND_SOC_DAPM_OUTPUT("RLOUT"), 642 SND_SOC_DAPM_OUTPUT("MONO_LOUT"), 643 SND_SOC_DAPM_OUTPUT("HPLOUT"), 644 SND_SOC_DAPM_OUTPUT("HPROUT"), 645 SND_SOC_DAPM_OUTPUT("HPLCOM"), 646 SND_SOC_DAPM_OUTPUT("HPRCOM"), 647 648 SND_SOC_DAPM_INPUT("MIC3L"), 649 SND_SOC_DAPM_INPUT("MIC3R"), 650 SND_SOC_DAPM_INPUT("LINE1L"), 651 SND_SOC_DAPM_INPUT("LINE1R"), 652 SND_SOC_DAPM_INPUT("LINE2L"), 653 SND_SOC_DAPM_INPUT("LINE2R"), 654 655 /* 656 * Virtual output pin to detection block inside codec. This can be 657 * used to keep codec bias on if gpio or detection features are needed. 658 * Force pin on or construct a path with an input jack and mic bias 659 * widgets. 660 */ 661 SND_SOC_DAPM_OUTPUT("Detection"), 662 }; 663 664 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { 665 /* Class-D outputs */ 666 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0), 667 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0), 668 669 SND_SOC_DAPM_OUTPUT("SPOP"), 670 SND_SOC_DAPM_OUTPUT("SPOM"), 671 }; 672 673 static const struct snd_soc_dapm_route intercon[] = { 674 /* Left Input */ 675 {"Left Line1L Mux", "single-ended", "LINE1L"}, 676 {"Left Line1L Mux", "differential", "LINE1L"}, 677 {"Left Line1R Mux", "single-ended", "LINE1R"}, 678 {"Left Line1R Mux", "differential", "LINE1R"}, 679 680 {"Left Line2L Mux", "single-ended", "LINE2L"}, 681 {"Left Line2L Mux", "differential", "LINE2L"}, 682 683 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, 684 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, 685 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, 686 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, 687 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, 688 689 {"Left ADC", NULL, "Left PGA Mixer"}, 690 {"Left ADC", NULL, "GPIO1 dmic modclk"}, 691 692 /* Right Input */ 693 {"Right Line1R Mux", "single-ended", "LINE1R"}, 694 {"Right Line1R Mux", "differential", "LINE1R"}, 695 {"Right Line1L Mux", "single-ended", "LINE1L"}, 696 {"Right Line1L Mux", "differential", "LINE1L"}, 697 698 {"Right Line2R Mux", "single-ended", "LINE2R"}, 699 {"Right Line2R Mux", "differential", "LINE2R"}, 700 701 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, 702 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, 703 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, 704 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, 705 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, 706 707 {"Right ADC", NULL, "Right PGA Mixer"}, 708 {"Right ADC", NULL, "GPIO1 dmic modclk"}, 709 710 /* 711 * Logical path between digital mic enable and GPIO1 modulator clock 712 * output function 713 */ 714 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, 715 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, 716 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, 717 718 /* Left DAC Output */ 719 {"Left DAC Mux", "DAC_L1", "Left DAC"}, 720 {"Left DAC Mux", "DAC_L2", "Left DAC"}, 721 {"Left DAC Mux", "DAC_L3", "Left DAC"}, 722 723 /* Right DAC Output */ 724 {"Right DAC Mux", "DAC_R1", "Right DAC"}, 725 {"Right DAC Mux", "DAC_R2", "Right DAC"}, 726 {"Right DAC Mux", "DAC_R3", "Right DAC"}, 727 728 /* Left Line Output */ 729 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 730 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 731 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 732 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 733 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 734 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 735 736 {"Left Line Out", NULL, "Left Line Mixer"}, 737 {"Left Line Out", NULL, "Left DAC Mux"}, 738 {"LLOUT", NULL, "Left Line Out"}, 739 740 /* Right Line Output */ 741 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 742 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 743 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 744 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 745 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 746 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 747 748 {"Right Line Out", NULL, "Right Line Mixer"}, 749 {"Right Line Out", NULL, "Right DAC Mux"}, 750 {"RLOUT", NULL, "Right Line Out"}, 751 752 /* Mono Output */ 753 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 754 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 755 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, 756 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 757 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 758 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, 759 760 {"Mono Out", NULL, "Mono Mixer"}, 761 {"MONO_LOUT", NULL, "Mono Out"}, 762 763 /* Left HP Output */ 764 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 765 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 766 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 767 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 768 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 769 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 770 771 {"Left HP Out", NULL, "Left HP Mixer"}, 772 {"Left HP Out", NULL, "Left DAC Mux"}, 773 {"HPLOUT", NULL, "Left HP Out"}, 774 775 /* Right HP Output */ 776 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 777 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 778 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 779 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 780 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 781 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 782 783 {"Right HP Out", NULL, "Right HP Mixer"}, 784 {"Right HP Out", NULL, "Right DAC Mux"}, 785 {"HPROUT", NULL, "Right HP Out"}, 786 787 /* Left HPCOM Output */ 788 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 789 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 790 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 791 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 792 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 793 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 794 795 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, 796 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, 797 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, 798 {"Left HP Com", NULL, "Left HPCOM Mux"}, 799 {"HPLCOM", NULL, "Left HP Com"}, 800 801 /* Right HPCOM Output */ 802 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 803 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 804 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 805 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 806 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 807 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 808 809 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, 810 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, 811 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, 812 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, 813 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, 814 {"Right HP Com", NULL, "Right HPCOM Mux"}, 815 {"HPRCOM", NULL, "Right HP Com"}, 816 }; 817 818 static const struct snd_soc_dapm_route intercon_3007[] = { 819 /* Class-D outputs */ 820 {"Left Class-D Out", NULL, "Left Line Out"}, 821 {"Right Class-D Out", NULL, "Left Line Out"}, 822 {"SPOP", NULL, "Left Class-D Out"}, 823 {"SPOM", NULL, "Right Class-D Out"}, 824 }; 825 826 static int aic3x_add_widgets(struct snd_soc_codec *codec) 827 { 828 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 829 struct snd_soc_dapm_context *dapm = &codec->dapm; 830 831 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets, 832 ARRAY_SIZE(aic3x_dapm_widgets)); 833 834 /* set up audio path interconnects */ 835 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 836 837 if (aic3x->model == AIC3X_MODEL_3007) { 838 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, 839 ARRAY_SIZE(aic3007_dapm_widgets)); 840 snd_soc_dapm_add_routes(dapm, intercon_3007, 841 ARRAY_SIZE(intercon_3007)); 842 } 843 844 return 0; 845 } 846 847 static int aic3x_hw_params(struct snd_pcm_substream *substream, 848 struct snd_pcm_hw_params *params, 849 struct snd_soc_dai *dai) 850 { 851 struct snd_soc_codec *codec = dai->codec; 852 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 853 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 854 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 855 u16 d, pll_d = 1; 856 int clk; 857 858 /* select data word length */ 859 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); 860 switch (params_format(params)) { 861 case SNDRV_PCM_FORMAT_S16_LE: 862 break; 863 case SNDRV_PCM_FORMAT_S20_3LE: 864 data |= (0x01 << 4); 865 break; 866 case SNDRV_PCM_FORMAT_S24_LE: 867 data |= (0x02 << 4); 868 break; 869 case SNDRV_PCM_FORMAT_S32_LE: 870 data |= (0x03 << 4); 871 break; 872 } 873 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data); 874 875 /* Fsref can be 44100 or 48000 */ 876 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; 877 878 /* Try to find a value for Q which allows us to bypass the PLL and 879 * generate CODEC_CLK directly. */ 880 for (pll_q = 2; pll_q < 18; pll_q++) 881 if (aic3x->sysclk / (128 * pll_q) == fsref) { 882 bypass_pll = 1; 883 break; 884 } 885 886 if (bypass_pll) { 887 pll_q &= 0xf; 888 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 889 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 890 /* disable PLL if it is bypassed */ 891 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); 892 893 } else { 894 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 895 /* enable PLL when it is used */ 896 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 897 PLL_ENABLE, PLL_ENABLE); 898 } 899 900 /* Route Left DAC to left channel input and 901 * right DAC to right channel input */ 902 data = (LDAC2LCH | RDAC2RCH); 903 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; 904 if (params_rate(params) >= 64000) 905 data |= DUAL_RATE_MODE; 906 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data); 907 908 /* codec sample rate select */ 909 data = (fsref * 20) / params_rate(params); 910 if (params_rate(params) < 64000) 911 data /= 2; 912 data /= 5; 913 data -= 2; 914 data |= (data << 4); 915 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); 916 917 if (bypass_pll) 918 return 0; 919 920 /* Use PLL, compute appropriate setup for j, d, r and p, the closest 921 * one wins the game. Try with d==0 first, next with d!=0. 922 * Constraints for j are according to the datasheet. 923 * The sysclk is divided by 1000 to prevent integer overflows. 924 */ 925 926 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); 927 928 for (r = 1; r <= 16; r++) 929 for (p = 1; p <= 8; p++) { 930 for (j = 4; j <= 55; j++) { 931 /* This is actually 1000*((j+(d/10000))*r)/p 932 * The term had to be converted to get 933 * rid of the division by 10000; d = 0 here 934 */ 935 int tmp_clk = (1000 * j * r) / p; 936 937 /* Check whether this values get closer than 938 * the best ones we had before 939 */ 940 if (abs(codec_clk - tmp_clk) < 941 abs(codec_clk - last_clk)) { 942 pll_j = j; pll_d = 0; 943 pll_r = r; pll_p = p; 944 last_clk = tmp_clk; 945 } 946 947 /* Early exit for exact matches */ 948 if (tmp_clk == codec_clk) 949 goto found; 950 } 951 } 952 953 /* try with d != 0 */ 954 for (p = 1; p <= 8; p++) { 955 j = codec_clk * p / 1000; 956 957 if (j < 4 || j > 11) 958 continue; 959 960 /* do not use codec_clk here since we'd loose precision */ 961 d = ((2048 * p * fsref) - j * aic3x->sysclk) 962 * 100 / (aic3x->sysclk/100); 963 964 clk = (10000 * j + d) / (10 * p); 965 966 /* check whether this values get closer than the best 967 * ones we had before */ 968 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { 969 pll_j = j; pll_d = d; pll_r = 1; pll_p = p; 970 last_clk = clk; 971 } 972 973 /* Early exit for exact matches */ 974 if (clk == codec_clk) 975 goto found; 976 } 977 978 if (last_clk == 0) { 979 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); 980 return -EINVAL; 981 } 982 983 found: 984 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p); 985 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, 986 pll_r << PLLR_SHIFT); 987 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); 988 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, 989 (pll_d >> 6) << PLLD_MSB_SHIFT); 990 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, 991 (pll_d & 0x3F) << PLLD_LSB_SHIFT); 992 993 return 0; 994 } 995 996 static int aic3x_mute(struct snd_soc_dai *dai, int mute) 997 { 998 struct snd_soc_codec *codec = dai->codec; 999 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON; 1000 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON; 1001 1002 if (mute) { 1003 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); 1004 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); 1005 } else { 1006 snd_soc_write(codec, LDAC_VOL, ldac_reg); 1007 snd_soc_write(codec, RDAC_VOL, rdac_reg); 1008 } 1009 1010 return 0; 1011 } 1012 1013 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1014 int clk_id, unsigned int freq, int dir) 1015 { 1016 struct snd_soc_codec *codec = codec_dai->codec; 1017 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1018 1019 /* set clock on MCLK or GPIO2 or BCLK */ 1020 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, 1021 clk_id << PLLCLK_IN_SHIFT); 1022 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, 1023 clk_id << CLKDIV_IN_SHIFT); 1024 1025 aic3x->sysclk = freq; 1026 return 0; 1027 } 1028 1029 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, 1030 unsigned int fmt) 1031 { 1032 struct snd_soc_codec *codec = codec_dai->codec; 1033 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1034 u8 iface_areg, iface_breg; 1035 int delay = 0; 1036 1037 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; 1038 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; 1039 1040 /* set master/slave audio interface */ 1041 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1042 case SND_SOC_DAIFMT_CBM_CFM: 1043 aic3x->master = 1; 1044 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; 1045 break; 1046 case SND_SOC_DAIFMT_CBS_CFS: 1047 aic3x->master = 0; 1048 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER); 1049 break; 1050 default: 1051 return -EINVAL; 1052 } 1053 1054 /* 1055 * match both interface format and signal polarities since they 1056 * are fixed 1057 */ 1058 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | 1059 SND_SOC_DAIFMT_INV_MASK)) { 1060 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): 1061 break; 1062 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): 1063 delay = 1; 1064 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): 1065 iface_breg |= (0x01 << 6); 1066 break; 1067 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): 1068 iface_breg |= (0x02 << 6); 1069 break; 1070 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): 1071 iface_breg |= (0x03 << 6); 1072 break; 1073 default: 1074 return -EINVAL; 1075 } 1076 1077 /* set iface */ 1078 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); 1079 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); 1080 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay); 1081 1082 return 0; 1083 } 1084 1085 static int aic3x_init_3007(struct snd_soc_codec *codec) 1086 { 1087 u8 tmp1, tmp2, *cache = codec->reg_cache; 1088 1089 /* 1090 * There is no need to cache writes to undocumented page 0xD but 1091 * respective page 0 register cache entries must be preserved 1092 */ 1093 tmp1 = cache[0xD]; 1094 tmp2 = cache[0x8]; 1095 /* Class-D speaker driver init; datasheet p. 46 */ 1096 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D); 1097 snd_soc_write(codec, 0xD, 0x0D); 1098 snd_soc_write(codec, 0x8, 0x5C); 1099 snd_soc_write(codec, 0x8, 0x5D); 1100 snd_soc_write(codec, 0x8, 0x5C); 1101 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00); 1102 cache[0xD] = tmp1; 1103 cache[0x8] = tmp2; 1104 1105 return 0; 1106 } 1107 1108 static int aic3x_regulator_event(struct notifier_block *nb, 1109 unsigned long event, void *data) 1110 { 1111 struct aic3x_disable_nb *disable_nb = 1112 container_of(nb, struct aic3x_disable_nb, nb); 1113 struct aic3x_priv *aic3x = disable_nb->aic3x; 1114 1115 if (event & REGULATOR_EVENT_DISABLE) { 1116 /* 1117 * Put codec to reset and require cache sync as at least one 1118 * of the supplies was disabled 1119 */ 1120 if (gpio_is_valid(aic3x->gpio_reset)) 1121 gpio_set_value(aic3x->gpio_reset, 0); 1122 aic3x->codec->cache_sync = 1; 1123 } 1124 1125 return 0; 1126 } 1127 1128 static int aic3x_set_power(struct snd_soc_codec *codec, int power) 1129 { 1130 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1131 int i, ret; 1132 u8 *cache = codec->reg_cache; 1133 1134 if (power) { 1135 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), 1136 aic3x->supplies); 1137 if (ret) 1138 goto out; 1139 aic3x->power = 1; 1140 /* 1141 * Reset release and cache sync is necessary only if some 1142 * supply was off or if there were cached writes 1143 */ 1144 if (!codec->cache_sync) 1145 goto out; 1146 1147 if (gpio_is_valid(aic3x->gpio_reset)) { 1148 udelay(1); 1149 gpio_set_value(aic3x->gpio_reset, 1); 1150 } 1151 1152 /* Sync reg_cache with the hardware */ 1153 codec->cache_only = 0; 1154 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++) 1155 snd_soc_write(codec, i, cache[i]); 1156 if (aic3x->model == AIC3X_MODEL_3007) 1157 aic3x_init_3007(codec); 1158 codec->cache_sync = 0; 1159 } else { 1160 /* 1161 * Do soft reset to this codec instance in order to clear 1162 * possible VDD leakage currents in case the supply regulators 1163 * remain on 1164 */ 1165 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1166 codec->cache_sync = 1; 1167 aic3x->power = 0; 1168 /* HW writes are needless when bias is off */ 1169 codec->cache_only = 1; 1170 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), 1171 aic3x->supplies); 1172 } 1173 out: 1174 return ret; 1175 } 1176 1177 static int aic3x_set_bias_level(struct snd_soc_codec *codec, 1178 enum snd_soc_bias_level level) 1179 { 1180 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1181 1182 switch (level) { 1183 case SND_SOC_BIAS_ON: 1184 break; 1185 case SND_SOC_BIAS_PREPARE: 1186 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY && 1187 aic3x->master) { 1188 /* enable pll */ 1189 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1190 PLL_ENABLE, PLL_ENABLE); 1191 } 1192 break; 1193 case SND_SOC_BIAS_STANDBY: 1194 if (!aic3x->power) 1195 aic3x_set_power(codec, 1); 1196 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE && 1197 aic3x->master) { 1198 /* disable pll */ 1199 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1200 PLL_ENABLE, 0); 1201 } 1202 break; 1203 case SND_SOC_BIAS_OFF: 1204 if (aic3x->power) 1205 aic3x_set_power(codec, 0); 1206 break; 1207 } 1208 codec->dapm.bias_level = level; 1209 1210 return 0; 1211 } 1212 1213 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1214 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1215 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1216 1217 static const struct snd_soc_dai_ops aic3x_dai_ops = { 1218 .hw_params = aic3x_hw_params, 1219 .digital_mute = aic3x_mute, 1220 .set_sysclk = aic3x_set_dai_sysclk, 1221 .set_fmt = aic3x_set_dai_fmt, 1222 }; 1223 1224 static struct snd_soc_dai_driver aic3x_dai = { 1225 .name = "tlv320aic3x-hifi", 1226 .playback = { 1227 .stream_name = "Playback", 1228 .channels_min = 2, 1229 .channels_max = 2, 1230 .rates = AIC3X_RATES, 1231 .formats = AIC3X_FORMATS,}, 1232 .capture = { 1233 .stream_name = "Capture", 1234 .channels_min = 2, 1235 .channels_max = 2, 1236 .rates = AIC3X_RATES, 1237 .formats = AIC3X_FORMATS,}, 1238 .ops = &aic3x_dai_ops, 1239 .symmetric_rates = 1, 1240 }; 1241 1242 static int aic3x_suspend(struct snd_soc_codec *codec) 1243 { 1244 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1245 1246 return 0; 1247 } 1248 1249 static int aic3x_resume(struct snd_soc_codec *codec) 1250 { 1251 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1252 1253 return 0; 1254 } 1255 1256 /* 1257 * initialise the AIC3X driver 1258 * register the mixer and dsp interfaces with the kernel 1259 */ 1260 static int aic3x_init(struct snd_soc_codec *codec) 1261 { 1262 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1263 1264 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); 1265 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1266 1267 /* DAC default volume and mute */ 1268 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); 1269 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); 1270 1271 /* DAC to HP default volume and route to Output mixer */ 1272 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); 1273 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); 1274 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1275 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1276 /* DAC to Line Out default volume and route to Output mixer */ 1277 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1278 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1279 /* DAC to Mono Line Out default volume and route to Output mixer */ 1280 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1281 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1282 1283 /* unmute all outputs */ 1284 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE); 1285 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE); 1286 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE); 1287 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE); 1288 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE); 1289 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE); 1290 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE); 1291 1292 /* ADC default volume and unmute */ 1293 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN); 1294 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN); 1295 /* By default route Line1 to ADC PGA mixer */ 1296 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0); 1297 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0); 1298 1299 /* PGA to HP Bypass default volume, disconnect from Output Mixer */ 1300 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); 1301 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); 1302 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); 1303 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); 1304 /* PGA to Line Out default volume, disconnect from Output Mixer */ 1305 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); 1306 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); 1307 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ 1308 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); 1309 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); 1310 1311 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ 1312 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); 1313 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); 1314 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); 1315 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); 1316 /* Line2 Line Out default volume, disconnect from Output Mixer */ 1317 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); 1318 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); 1319 /* Line2 to Mono Out default volume, disconnect from Output Mixer */ 1320 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); 1321 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); 1322 1323 if (aic3x->model == AIC3X_MODEL_3007) { 1324 aic3x_init_3007(codec); 1325 snd_soc_write(codec, CLASSD_CTRL, 0); 1326 } 1327 1328 return 0; 1329 } 1330 1331 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x) 1332 { 1333 struct aic3x_priv *a; 1334 1335 list_for_each_entry(a, &reset_list, list) { 1336 if (gpio_is_valid(aic3x->gpio_reset) && 1337 aic3x->gpio_reset == a->gpio_reset) 1338 return true; 1339 } 1340 1341 return false; 1342 } 1343 1344 static int aic3x_probe(struct snd_soc_codec *codec) 1345 { 1346 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1347 int ret, i; 1348 1349 INIT_LIST_HEAD(&aic3x->list); 1350 aic3x->codec = codec; 1351 1352 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type); 1353 if (ret != 0) { 1354 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1355 return ret; 1356 } 1357 1358 if (gpio_is_valid(aic3x->gpio_reset) && 1359 !aic3x_is_shared_reset(aic3x)) { 1360 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); 1361 if (ret != 0) 1362 goto err_gpio; 1363 gpio_direction_output(aic3x->gpio_reset, 0); 1364 } 1365 1366 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1367 aic3x->supplies[i].supply = aic3x_supply_names[i]; 1368 1369 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies), 1370 aic3x->supplies); 1371 if (ret != 0) { 1372 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 1373 goto err_get; 1374 } 1375 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) { 1376 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; 1377 aic3x->disable_nb[i].aic3x = aic3x; 1378 ret = regulator_register_notifier(aic3x->supplies[i].consumer, 1379 &aic3x->disable_nb[i].nb); 1380 if (ret) { 1381 dev_err(codec->dev, 1382 "Failed to request regulator notifier: %d\n", 1383 ret); 1384 goto err_notif; 1385 } 1386 } 1387 1388 codec->cache_only = 1; 1389 aic3x_init(codec); 1390 1391 if (aic3x->setup) { 1392 /* setup GPIO functions */ 1393 snd_soc_write(codec, AIC3X_GPIO1_REG, 1394 (aic3x->setup->gpio_func[0] & 0xf) << 4); 1395 snd_soc_write(codec, AIC3X_GPIO2_REG, 1396 (aic3x->setup->gpio_func[1] & 0xf) << 4); 1397 } 1398 1399 snd_soc_add_codec_controls(codec, aic3x_snd_controls, 1400 ARRAY_SIZE(aic3x_snd_controls)); 1401 if (aic3x->model == AIC3X_MODEL_3007) 1402 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1); 1403 1404 /* set mic bias voltage */ 1405 switch (aic3x->micbias_vg) { 1406 case AIC3X_MICBIAS_2_0V: 1407 case AIC3X_MICBIAS_2_5V: 1408 case AIC3X_MICBIAS_AVDDV: 1409 snd_soc_update_bits(codec, MICBIAS_CTRL, 1410 MICBIAS_LEVEL_MASK, 1411 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT); 1412 break; 1413 case AIC3X_MICBIAS_OFF: 1414 /* 1415 * noting to do. target won't enter here. This is just to avoid 1416 * compile time warning "warning: enumeration value 1417 * 'AIC3X_MICBIAS_OFF' not handled in switch" 1418 */ 1419 break; 1420 } 1421 1422 aic3x_add_widgets(codec); 1423 list_add(&aic3x->list, &reset_list); 1424 1425 return 0; 1426 1427 err_notif: 1428 while (i--) 1429 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1430 &aic3x->disable_nb[i].nb); 1431 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1432 err_get: 1433 if (gpio_is_valid(aic3x->gpio_reset) && 1434 !aic3x_is_shared_reset(aic3x)) 1435 gpio_free(aic3x->gpio_reset); 1436 err_gpio: 1437 return ret; 1438 } 1439 1440 static int aic3x_remove(struct snd_soc_codec *codec) 1441 { 1442 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1443 int i; 1444 1445 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1446 list_del(&aic3x->list); 1447 if (gpio_is_valid(aic3x->gpio_reset) && 1448 !aic3x_is_shared_reset(aic3x)) { 1449 gpio_set_value(aic3x->gpio_reset, 0); 1450 gpio_free(aic3x->gpio_reset); 1451 } 1452 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1453 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1454 &aic3x->disable_nb[i].nb); 1455 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1456 1457 return 0; 1458 } 1459 1460 static struct snd_soc_codec_driver soc_codec_dev_aic3x = { 1461 .set_bias_level = aic3x_set_bias_level, 1462 .idle_bias_off = true, 1463 .reg_cache_size = ARRAY_SIZE(aic3x_reg), 1464 .reg_word_size = sizeof(u8), 1465 .reg_cache_default = aic3x_reg, 1466 .probe = aic3x_probe, 1467 .remove = aic3x_remove, 1468 .suspend = aic3x_suspend, 1469 .resume = aic3x_resume, 1470 }; 1471 1472 /* 1473 * AIC3X 2 wire address can be up to 4 devices with device addresses 1474 * 0x18, 0x19, 0x1A, 0x1B 1475 */ 1476 1477 static const struct i2c_device_id aic3x_i2c_id[] = { 1478 { "tlv320aic3x", AIC3X_MODEL_3X }, 1479 { "tlv320aic33", AIC3X_MODEL_33 }, 1480 { "tlv320aic3007", AIC3X_MODEL_3007 }, 1481 { "tlv320aic3106", AIC3X_MODEL_3X }, 1482 { } 1483 }; 1484 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); 1485 1486 /* 1487 * If the i2c layer weren't so broken, we could pass this kind of data 1488 * around 1489 */ 1490 static int aic3x_i2c_probe(struct i2c_client *i2c, 1491 const struct i2c_device_id *id) 1492 { 1493 struct aic3x_pdata *pdata = i2c->dev.platform_data; 1494 struct aic3x_priv *aic3x; 1495 struct aic3x_setup_data *ai3x_setup; 1496 struct device_node *np = i2c->dev.of_node; 1497 int ret; 1498 u32 value; 1499 1500 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL); 1501 if (aic3x == NULL) { 1502 dev_err(&i2c->dev, "failed to create private data\n"); 1503 return -ENOMEM; 1504 } 1505 1506 aic3x->control_type = SND_SOC_I2C; 1507 1508 i2c_set_clientdata(i2c, aic3x); 1509 if (pdata) { 1510 aic3x->gpio_reset = pdata->gpio_reset; 1511 aic3x->setup = pdata->setup; 1512 aic3x->micbias_vg = pdata->micbias_vg; 1513 } else if (np) { 1514 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup), 1515 GFP_KERNEL); 1516 if (ai3x_setup == NULL) { 1517 dev_err(&i2c->dev, "failed to create private data\n"); 1518 return -ENOMEM; 1519 } 1520 1521 ret = of_get_named_gpio(np, "gpio-reset", 0); 1522 if (ret >= 0) 1523 aic3x->gpio_reset = ret; 1524 else 1525 aic3x->gpio_reset = -1; 1526 1527 if (of_property_read_u32_array(np, "ai3x-gpio-func", 1528 ai3x_setup->gpio_func, 2) >= 0) { 1529 aic3x->setup = ai3x_setup; 1530 } 1531 1532 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) { 1533 switch (value) { 1534 case 1 : 1535 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V; 1536 break; 1537 case 2 : 1538 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V; 1539 break; 1540 case 3 : 1541 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV; 1542 break; 1543 default : 1544 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; 1545 dev_err(&i2c->dev, "Unsuitable MicBias voltage " 1546 "found in DT\n"); 1547 } 1548 } else { 1549 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; 1550 } 1551 1552 } else { 1553 aic3x->gpio_reset = -1; 1554 } 1555 1556 aic3x->model = id->driver_data; 1557 1558 ret = snd_soc_register_codec(&i2c->dev, 1559 &soc_codec_dev_aic3x, &aic3x_dai, 1); 1560 return ret; 1561 } 1562 1563 static int aic3x_i2c_remove(struct i2c_client *client) 1564 { 1565 snd_soc_unregister_codec(&client->dev); 1566 return 0; 1567 } 1568 1569 #if defined(CONFIG_OF) 1570 static const struct of_device_id tlv320aic3x_of_match[] = { 1571 { .compatible = "ti,tlv320aic3x", }, 1572 { .compatible = "ti,tlv320aic33" }, 1573 { .compatible = "ti,tlv320aic3007" }, 1574 { .compatible = "ti,tlv320aic3106" }, 1575 {}, 1576 }; 1577 MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match); 1578 #endif 1579 1580 /* machine i2c codec control layer */ 1581 static struct i2c_driver aic3x_i2c_driver = { 1582 .driver = { 1583 .name = "tlv320aic3x-codec", 1584 .owner = THIS_MODULE, 1585 .of_match_table = of_match_ptr(tlv320aic3x_of_match), 1586 }, 1587 .probe = aic3x_i2c_probe, 1588 .remove = aic3x_i2c_remove, 1589 .id_table = aic3x_i2c_id, 1590 }; 1591 1592 module_i2c_driver(aic3x_i2c_driver); 1593 1594 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); 1595 MODULE_AUTHOR("Vladimir Barinov"); 1596 MODULE_LICENSE("GPL"); 1597