1 /* 2 * ALSA SoC TLV320AIC3X codec driver 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Notes: 14 * The AIC3X is a driver for a low power stereo audio 15 * codecs aic31, aic32, aic33. 16 * 17 * It supports full aic33 codec functionality. 18 * The compatibility with aic32, aic31 is as follows: 19 * aic32 | aic31 20 * --------------------------------------- 21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A 22 * | IN1L -> LINE1L 23 * | IN1R -> LINE1R 24 * | IN2L -> LINE2L 25 * | IN2R -> LINE2R 26 * | MIC3L/R -> N/A 27 * truncated internal functionality in 28 * accordance with documentation 29 * --------------------------------------- 30 * 31 * Hence the machine layer should disable unsupported inputs/outputs by 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/init.h> 38 #include <linux/delay.h> 39 #include <linux/pm.h> 40 #include <linux/i2c.h> 41 #include <linux/platform_device.h> 42 #include <sound/core.h> 43 #include <sound/pcm.h> 44 #include <sound/pcm_params.h> 45 #include <sound/soc.h> 46 #include <sound/soc-dapm.h> 47 #include <sound/initval.h> 48 #include <sound/tlv.h> 49 50 #include "tlv320aic3x.h" 51 52 #define AIC3X_VERSION "0.2" 53 54 /* codec private data */ 55 struct aic3x_priv { 56 struct snd_soc_codec codec; 57 unsigned int sysclk; 58 int master; 59 }; 60 61 /* 62 * AIC3X register cache 63 * We can't read the AIC3X register space when we are 64 * using 2 wire for device control, so we cache them instead. 65 * There is no point in caching the reset register 66 */ 67 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { 68 0x00, 0x00, 0x00, 0x10, /* 0 */ 69 0x04, 0x00, 0x00, 0x00, /* 4 */ 70 0x00, 0x00, 0x00, 0x01, /* 8 */ 71 0x00, 0x00, 0x00, 0x80, /* 12 */ 72 0x80, 0xff, 0xff, 0x78, /* 16 */ 73 0x78, 0x78, 0x78, 0x78, /* 20 */ 74 0x78, 0x00, 0x00, 0xfe, /* 24 */ 75 0x00, 0x00, 0xfe, 0x00, /* 28 */ 76 0x18, 0x18, 0x00, 0x00, /* 32 */ 77 0x00, 0x00, 0x00, 0x00, /* 36 */ 78 0x00, 0x00, 0x00, 0x80, /* 40 */ 79 0x80, 0x00, 0x00, 0x00, /* 44 */ 80 0x00, 0x00, 0x00, 0x04, /* 48 */ 81 0x00, 0x00, 0x00, 0x00, /* 52 */ 82 0x00, 0x00, 0x04, 0x00, /* 56 */ 83 0x00, 0x00, 0x00, 0x00, /* 60 */ 84 0x00, 0x04, 0x00, 0x00, /* 64 */ 85 0x00, 0x00, 0x00, 0x00, /* 68 */ 86 0x04, 0x00, 0x00, 0x00, /* 72 */ 87 0x00, 0x00, 0x00, 0x00, /* 76 */ 88 0x00, 0x00, 0x00, 0x00, /* 80 */ 89 0x00, 0x00, 0x00, 0x00, /* 84 */ 90 0x00, 0x00, 0x00, 0x00, /* 88 */ 91 0x00, 0x00, 0x00, 0x00, /* 92 */ 92 0x00, 0x00, 0x00, 0x00, /* 96 */ 93 0x00, 0x00, 0x02, /* 100 */ 94 }; 95 96 /* 97 * read aic3x register cache 98 */ 99 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec, 100 unsigned int reg) 101 { 102 u8 *cache = codec->reg_cache; 103 if (reg >= AIC3X_CACHEREGNUM) 104 return -1; 105 return cache[reg]; 106 } 107 108 /* 109 * write aic3x register cache 110 */ 111 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec, 112 u8 reg, u8 value) 113 { 114 u8 *cache = codec->reg_cache; 115 if (reg >= AIC3X_CACHEREGNUM) 116 return; 117 cache[reg] = value; 118 } 119 120 /* 121 * write to the aic3x register space 122 */ 123 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg, 124 unsigned int value) 125 { 126 u8 data[2]; 127 128 /* data is 129 * D15..D8 aic3x register offset 130 * D7...D0 register data 131 */ 132 data[0] = reg & 0xff; 133 data[1] = value & 0xff; 134 135 aic3x_write_reg_cache(codec, data[0], data[1]); 136 if (codec->hw_write(codec->control_data, data, 2) == 2) 137 return 0; 138 else 139 return -EIO; 140 } 141 142 /* 143 * read from the aic3x register space 144 */ 145 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg, 146 u8 *value) 147 { 148 *value = reg & 0xff; 149 150 value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]); 151 152 aic3x_write_reg_cache(codec, reg, *value); 153 return 0; 154 } 155 156 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ 157 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 158 .info = snd_soc_info_volsw, \ 159 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \ 160 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) } 161 162 /* 163 * All input lines are connected when !0xf and disconnected with 0xf bit field, 164 * so we have to use specific dapm_put call for input mixer 165 */ 166 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, 167 struct snd_ctl_elem_value *ucontrol) 168 { 169 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); 170 struct soc_mixer_control *mc = 171 (struct soc_mixer_control *)kcontrol->private_value; 172 unsigned int reg = mc->reg; 173 unsigned int shift = mc->shift; 174 int max = mc->max; 175 unsigned int mask = (1 << fls(max)) - 1; 176 unsigned int invert = mc->invert; 177 unsigned short val, val_mask; 178 int ret; 179 struct snd_soc_dapm_path *path; 180 int found = 0; 181 182 val = (ucontrol->value.integer.value[0] & mask); 183 184 mask = 0xf; 185 if (val) 186 val = mask; 187 188 if (invert) 189 val = mask - val; 190 val_mask = mask << shift; 191 val = val << shift; 192 193 mutex_lock(&widget->codec->mutex); 194 195 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { 196 /* find dapm widget path assoc with kcontrol */ 197 list_for_each_entry(path, &widget->codec->dapm_paths, list) { 198 if (path->kcontrol != kcontrol) 199 continue; 200 201 /* found, now check type */ 202 found = 1; 203 if (val) 204 /* new connection */ 205 path->connect = invert ? 0 : 1; 206 else 207 /* old connection must be powered down */ 208 path->connect = invert ? 1 : 0; 209 break; 210 } 211 212 if (found) 213 snd_soc_dapm_sync(widget->codec); 214 } 215 216 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); 217 218 mutex_unlock(&widget->codec->mutex); 219 return ret; 220 } 221 222 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; 223 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; 224 static const char *aic3x_left_hpcom_mux[] = 225 { "differential of HPLOUT", "constant VCM", "single-ended" }; 226 static const char *aic3x_right_hpcom_mux[] = 227 { "differential of HPROUT", "constant VCM", "single-ended", 228 "differential of HPLCOM", "external feedback" }; 229 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; 230 static const char *aic3x_adc_hpf[] = 231 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; 232 233 #define LDAC_ENUM 0 234 #define RDAC_ENUM 1 235 #define LHPCOM_ENUM 2 236 #define RHPCOM_ENUM 3 237 #define LINE1L_ENUM 4 238 #define LINE1R_ENUM 5 239 #define LINE2L_ENUM 6 240 #define LINE2R_ENUM 7 241 #define ADC_HPF_ENUM 8 242 243 static const struct soc_enum aic3x_enum[] = { 244 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), 245 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), 246 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), 247 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), 248 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 249 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 250 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 251 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 252 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf), 253 }; 254 255 /* 256 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps 257 */ 258 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); 259 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ 260 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); 261 /* 262 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. 263 * Step size is approximately 0.5 dB over most of the scale but increasing 264 * near the very low levels. 265 * Define dB scale so that it is mostly correct for range about -55 to 0 dB 266 * but having increasing dB difference below that (and where it doesn't count 267 * so much). This setting shows -50 dB (actual is -50.3 dB) for register 268 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. 269 */ 270 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); 271 272 static const struct snd_kcontrol_new aic3x_snd_controls[] = { 273 /* Output */ 274 SOC_DOUBLE_R_TLV("PCM Playback Volume", 275 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 276 277 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 278 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 279 0, 118, 1, output_stage_tlv), 280 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0), 281 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0), 282 SOC_DOUBLE_R_TLV("LineL DAC Playback Volume", 283 DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL, 284 0, 118, 1, output_stage_tlv), 285 SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume", 286 PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 287 SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume", 288 PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 289 SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume", 290 LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL, 291 0, 118, 1, output_stage_tlv), 292 SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume", 293 LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL, 294 0, 118, 1, output_stage_tlv), 295 296 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 297 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 298 0, 118, 1, output_stage_tlv), 299 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 300 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume", 301 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 302 0, 118, 1, output_stage_tlv), 303 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume", 304 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 305 0, 118, 1, output_stage_tlv), 306 307 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 308 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 309 0, 118, 1, output_stage_tlv), 310 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 311 0x01, 0), 312 SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume", 313 PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 314 0, 118, 1, output_stage_tlv), 315 SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume", 316 PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 317 SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume", 318 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 319 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume", 320 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 321 0, 118, 1, output_stage_tlv), 322 323 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 324 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 325 0, 118, 1, output_stage_tlv), 326 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 327 0x01, 0), 328 SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume", 329 PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 330 SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume", 331 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 332 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume", 333 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 334 0, 118, 1, output_stage_tlv), 335 336 /* 337 * Note: enable Automatic input Gain Controller with care. It can 338 * adjust PGA to max value when ADC is on and will never go back. 339 */ 340 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), 341 342 /* Input */ 343 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 344 0, 119, 0, adc_tlv), 345 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), 346 347 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]), 348 }; 349 350 /* Left DAC Mux */ 351 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = 352 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); 353 354 /* Right DAC Mux */ 355 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = 356 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); 357 358 /* Left HPCOM Mux */ 359 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = 360 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); 361 362 /* Right HPCOM Mux */ 363 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = 364 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); 365 366 /* Left DAC_L1 Mixer */ 367 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = { 368 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), 369 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), 370 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), 371 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), 372 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), 373 }; 374 375 /* Right DAC_R1 Mixer */ 376 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = { 377 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), 378 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), 379 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), 380 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), 381 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), 382 }; 383 384 /* Left PGA Mixer */ 385 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { 386 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 387 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 388 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), 389 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 390 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 391 }; 392 393 /* Right PGA Mixer */ 394 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { 395 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 396 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 397 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), 398 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 399 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 400 }; 401 402 /* Left Line1 Mux */ 403 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls = 404 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]); 405 406 /* Right Line1 Mux */ 407 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls = 408 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]); 409 410 /* Left Line2 Mux */ 411 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = 412 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); 413 414 /* Right Line2 Mux */ 415 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = 416 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); 417 418 /* Left PGA Bypass Mixer */ 419 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = { 420 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), 421 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), 422 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), 423 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), 424 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), 425 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), 426 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), 427 }; 428 429 /* Right PGA Bypass Mixer */ 430 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = { 431 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), 432 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), 433 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), 434 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), 435 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), 436 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), 437 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), 438 }; 439 440 /* Left Line2 Bypass Mixer */ 441 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = { 442 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), 443 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), 444 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), 445 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), 446 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), 447 }; 448 449 /* Right Line2 Bypass Mixer */ 450 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = { 451 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), 452 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), 453 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), 454 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), 455 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), 456 }; 457 458 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { 459 /* Left DAC to Left Outputs */ 460 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), 461 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, 462 &aic3x_left_dac_mux_controls), 463 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0, 464 &aic3x_left_dac_mixer_controls[0], 465 ARRAY_SIZE(aic3x_left_dac_mixer_controls)), 466 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, 467 &aic3x_left_hpcom_mux_controls), 468 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), 469 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), 470 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), 471 472 /* Right DAC to Right Outputs */ 473 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), 474 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, 475 &aic3x_right_dac_mux_controls), 476 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0, 477 &aic3x_right_dac_mixer_controls[0], 478 ARRAY_SIZE(aic3x_right_dac_mixer_controls)), 479 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, 480 &aic3x_right_hpcom_mux_controls), 481 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), 482 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), 483 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), 484 485 /* Mono Output */ 486 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), 487 488 /* Inputs to Left ADC */ 489 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), 490 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 491 &aic3x_left_pga_mixer_controls[0], 492 ARRAY_SIZE(aic3x_left_pga_mixer_controls)), 493 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, 494 &aic3x_left_line1_mux_controls), 495 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, 496 &aic3x_left_line1_mux_controls), 497 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, 498 &aic3x_left_line2_mux_controls), 499 500 /* Inputs to Right ADC */ 501 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 502 LINE1R_2_RADC_CTRL, 2, 0), 503 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 504 &aic3x_right_pga_mixer_controls[0], 505 ARRAY_SIZE(aic3x_right_pga_mixer_controls)), 506 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, 507 &aic3x_right_line1_mux_controls), 508 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, 509 &aic3x_right_line1_mux_controls), 510 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, 511 &aic3x_right_line2_mux_controls), 512 513 /* 514 * Not a real mic bias widget but similar function. This is for dynamic 515 * control of GPIO1 digital mic modulator clock output function when 516 * using digital mic. 517 */ 518 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", 519 AIC3X_GPIO1_REG, 4, 0xf, 520 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, 521 AIC3X_GPIO1_FUNC_DISABLED), 522 523 /* 524 * Also similar function like mic bias. Selects digital mic with 525 * configurable oversampling rate instead of ADC converter. 526 */ 527 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", 528 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), 529 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", 530 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), 531 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", 532 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 533 534 /* Mic Bias */ 535 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V", 536 MICBIAS_CTRL, 6, 3, 1, 0), 537 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V", 538 MICBIAS_CTRL, 6, 3, 2, 0), 539 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD", 540 MICBIAS_CTRL, 6, 3, 3, 0), 541 542 /* Left PGA to Left Output bypass */ 543 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, 544 &aic3x_left_pga_bp_mixer_controls[0], 545 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)), 546 547 /* Right PGA to Right Output bypass */ 548 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0, 549 &aic3x_right_pga_bp_mixer_controls[0], 550 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)), 551 552 /* Left Line2 to Left Output bypass */ 553 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, 554 &aic3x_left_line2_bp_mixer_controls[0], 555 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)), 556 557 /* Right Line2 to Right Output bypass */ 558 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0, 559 &aic3x_right_line2_bp_mixer_controls[0], 560 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)), 561 562 SND_SOC_DAPM_OUTPUT("LLOUT"), 563 SND_SOC_DAPM_OUTPUT("RLOUT"), 564 SND_SOC_DAPM_OUTPUT("MONO_LOUT"), 565 SND_SOC_DAPM_OUTPUT("HPLOUT"), 566 SND_SOC_DAPM_OUTPUT("HPROUT"), 567 SND_SOC_DAPM_OUTPUT("HPLCOM"), 568 SND_SOC_DAPM_OUTPUT("HPRCOM"), 569 570 SND_SOC_DAPM_INPUT("MIC3L"), 571 SND_SOC_DAPM_INPUT("MIC3R"), 572 SND_SOC_DAPM_INPUT("LINE1L"), 573 SND_SOC_DAPM_INPUT("LINE1R"), 574 SND_SOC_DAPM_INPUT("LINE2L"), 575 SND_SOC_DAPM_INPUT("LINE2R"), 576 }; 577 578 static const struct snd_soc_dapm_route intercon[] = { 579 /* Left Output */ 580 {"Left DAC Mux", "DAC_L1", "Left DAC"}, 581 {"Left DAC Mux", "DAC_L2", "Left DAC"}, 582 {"Left DAC Mux", "DAC_L3", "Left DAC"}, 583 584 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"}, 585 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"}, 586 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"}, 587 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"}, 588 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"}, 589 {"Left Line Out", NULL, "Left DAC Mux"}, 590 {"Left HP Out", NULL, "Left DAC Mux"}, 591 592 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"}, 593 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"}, 594 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"}, 595 596 {"Left Line Out", NULL, "Left DAC_L1 Mixer"}, 597 {"Mono Out", NULL, "Left DAC_L1 Mixer"}, 598 {"Left HP Out", NULL, "Left DAC_L1 Mixer"}, 599 {"Left HP Com", NULL, "Left HPCOM Mux"}, 600 601 {"LLOUT", NULL, "Left Line Out"}, 602 {"LLOUT", NULL, "Left Line Out"}, 603 {"HPLOUT", NULL, "Left HP Out"}, 604 {"HPLCOM", NULL, "Left HP Com"}, 605 606 /* Right Output */ 607 {"Right DAC Mux", "DAC_R1", "Right DAC"}, 608 {"Right DAC Mux", "DAC_R2", "Right DAC"}, 609 {"Right DAC Mux", "DAC_R3", "Right DAC"}, 610 611 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"}, 612 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"}, 613 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"}, 614 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"}, 615 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"}, 616 {"Right Line Out", NULL, "Right DAC Mux"}, 617 {"Right HP Out", NULL, "Right DAC Mux"}, 618 619 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"}, 620 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"}, 621 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"}, 622 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"}, 623 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"}, 624 625 {"Right Line Out", NULL, "Right DAC_R1 Mixer"}, 626 {"Mono Out", NULL, "Right DAC_R1 Mixer"}, 627 {"Right HP Out", NULL, "Right DAC_R1 Mixer"}, 628 {"Right HP Com", NULL, "Right HPCOM Mux"}, 629 630 {"RLOUT", NULL, "Right Line Out"}, 631 {"RLOUT", NULL, "Right Line Out"}, 632 {"HPROUT", NULL, "Right HP Out"}, 633 {"HPRCOM", NULL, "Right HP Com"}, 634 635 /* Mono Output */ 636 {"MONO_LOUT", NULL, "Mono Out"}, 637 {"MONO_LOUT", NULL, "Mono Out"}, 638 639 /* Left Input */ 640 {"Left Line1L Mux", "single-ended", "LINE1L"}, 641 {"Left Line1L Mux", "differential", "LINE1L"}, 642 643 {"Left Line2L Mux", "single-ended", "LINE2L"}, 644 {"Left Line2L Mux", "differential", "LINE2L"}, 645 646 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, 647 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, 648 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, 649 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, 650 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, 651 652 {"Left ADC", NULL, "Left PGA Mixer"}, 653 {"Left ADC", NULL, "GPIO1 dmic modclk"}, 654 655 /* Right Input */ 656 {"Right Line1R Mux", "single-ended", "LINE1R"}, 657 {"Right Line1R Mux", "differential", "LINE1R"}, 658 659 {"Right Line2R Mux", "single-ended", "LINE2R"}, 660 {"Right Line2R Mux", "differential", "LINE2R"}, 661 662 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, 663 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, 664 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, 665 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, 666 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, 667 668 {"Right ADC", NULL, "Right PGA Mixer"}, 669 {"Right ADC", NULL, "GPIO1 dmic modclk"}, 670 671 /* Left PGA Bypass */ 672 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"}, 673 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"}, 674 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"}, 675 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"}, 676 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"}, 677 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"}, 678 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"}, 679 680 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"}, 681 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"}, 682 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"}, 683 684 {"Left Line Out", NULL, "Left PGA Bypass Mixer"}, 685 {"Mono Out", NULL, "Left PGA Bypass Mixer"}, 686 {"Left HP Out", NULL, "Left PGA Bypass Mixer"}, 687 688 /* Right PGA Bypass */ 689 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"}, 690 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"}, 691 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"}, 692 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"}, 693 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"}, 694 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"}, 695 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"}, 696 697 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"}, 698 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"}, 699 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"}, 700 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"}, 701 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"}, 702 703 {"Right Line Out", NULL, "Right PGA Bypass Mixer"}, 704 {"Mono Out", NULL, "Right PGA Bypass Mixer"}, 705 {"Right HP Out", NULL, "Right PGA Bypass Mixer"}, 706 707 /* Left Line2 Bypass */ 708 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"}, 709 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"}, 710 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"}, 711 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"}, 712 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"}, 713 714 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"}, 715 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"}, 716 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"}, 717 718 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"}, 719 {"Mono Out", NULL, "Left Line2 Bypass Mixer"}, 720 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"}, 721 722 /* Right Line2 Bypass */ 723 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"}, 724 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"}, 725 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"}, 726 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"}, 727 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"}, 728 729 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"}, 730 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"}, 731 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"}, 732 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"}, 733 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"}, 734 735 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"}, 736 {"Mono Out", NULL, "Right Line2 Bypass Mixer"}, 737 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"}, 738 739 /* 740 * Logical path between digital mic enable and GPIO1 modulator clock 741 * output function 742 */ 743 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, 744 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, 745 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, 746 }; 747 748 static int aic3x_add_widgets(struct snd_soc_codec *codec) 749 { 750 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets, 751 ARRAY_SIZE(aic3x_dapm_widgets)); 752 753 /* set up audio path interconnects */ 754 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 755 756 snd_soc_dapm_new_widgets(codec); 757 return 0; 758 } 759 760 static int aic3x_hw_params(struct snd_pcm_substream *substream, 761 struct snd_pcm_hw_params *params, 762 struct snd_soc_dai *dai) 763 { 764 struct snd_soc_pcm_runtime *rtd = substream->private_data; 765 struct snd_soc_device *socdev = rtd->socdev; 766 struct snd_soc_codec *codec = socdev->card->codec; 767 struct aic3x_priv *aic3x = codec->private_data; 768 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 769 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 770 u16 pll_d = 1; 771 u8 reg; 772 773 /* select data word length */ 774 data = 775 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); 776 switch (params_format(params)) { 777 case SNDRV_PCM_FORMAT_S16_LE: 778 break; 779 case SNDRV_PCM_FORMAT_S20_3LE: 780 data |= (0x01 << 4); 781 break; 782 case SNDRV_PCM_FORMAT_S24_LE: 783 data |= (0x02 << 4); 784 break; 785 case SNDRV_PCM_FORMAT_S32_LE: 786 data |= (0x03 << 4); 787 break; 788 } 789 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data); 790 791 /* Fsref can be 44100 or 48000 */ 792 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; 793 794 /* Try to find a value for Q which allows us to bypass the PLL and 795 * generate CODEC_CLK directly. */ 796 for (pll_q = 2; pll_q < 18; pll_q++) 797 if (aic3x->sysclk / (128 * pll_q) == fsref) { 798 bypass_pll = 1; 799 break; 800 } 801 802 if (bypass_pll) { 803 pll_q &= 0xf; 804 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 805 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 806 /* disable PLL if it is bypassed */ 807 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 808 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE); 809 810 } else { 811 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 812 /* enable PLL when it is used */ 813 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 814 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE); 815 } 816 817 /* Route Left DAC to left channel input and 818 * right DAC to right channel input */ 819 data = (LDAC2LCH | RDAC2RCH); 820 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; 821 if (params_rate(params) >= 64000) 822 data |= DUAL_RATE_MODE; 823 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data); 824 825 /* codec sample rate select */ 826 data = (fsref * 20) / params_rate(params); 827 if (params_rate(params) < 64000) 828 data /= 2; 829 data /= 5; 830 data -= 2; 831 data |= (data << 4); 832 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); 833 834 if (bypass_pll) 835 return 0; 836 837 /* Use PLL 838 * find an apropriate setup for j, d, r and p by iterating over 839 * p and r - j and d are calculated for each fraction. 840 * Up to 128 values are probed, the closest one wins the game. 841 * The sysclk is divided by 1000 to prevent integer overflows. 842 */ 843 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); 844 845 for (r = 1; r <= 16; r++) 846 for (p = 1; p <= 8; p++) { 847 int clk, tmp = (codec_clk * pll_r * 10) / pll_p; 848 u8 j = tmp / 10000; 849 u16 d = tmp % 10000; 850 851 if (j > 63) 852 continue; 853 854 if (d != 0 && aic3x->sysclk < 10000000) 855 continue; 856 857 /* This is actually 1000 * ((j + (d/10000)) * r) / p 858 * The term had to be converted to get rid of the 859 * division by 10000 */ 860 clk = ((10000 * j * r) + (d * r)) / (10 * p); 861 862 /* check whether this values get closer than the best 863 * ones we had before */ 864 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { 865 pll_j = j; pll_d = d; pll_r = r; pll_p = p; 866 last_clk = clk; 867 } 868 869 /* Early exit for exact matches */ 870 if (clk == codec_clk) 871 break; 872 } 873 874 if (last_clk == 0) { 875 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); 876 return -EINVAL; 877 } 878 879 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 880 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT)); 881 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT); 882 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); 883 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT); 884 aic3x_write(codec, AIC3X_PLL_PROGD_REG, 885 (pll_d & 0x3F) << PLLD_LSB_SHIFT); 886 887 return 0; 888 } 889 890 static int aic3x_mute(struct snd_soc_dai *dai, int mute) 891 { 892 struct snd_soc_codec *codec = dai->codec; 893 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON; 894 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON; 895 896 if (mute) { 897 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); 898 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); 899 } else { 900 aic3x_write(codec, LDAC_VOL, ldac_reg); 901 aic3x_write(codec, RDAC_VOL, rdac_reg); 902 } 903 904 return 0; 905 } 906 907 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 908 int clk_id, unsigned int freq, int dir) 909 { 910 struct snd_soc_codec *codec = codec_dai->codec; 911 struct aic3x_priv *aic3x = codec->private_data; 912 913 aic3x->sysclk = freq; 914 return 0; 915 } 916 917 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, 918 unsigned int fmt) 919 { 920 struct snd_soc_codec *codec = codec_dai->codec; 921 struct aic3x_priv *aic3x = codec->private_data; 922 u8 iface_areg, iface_breg; 923 int delay = 0; 924 925 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; 926 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; 927 928 /* set master/slave audio interface */ 929 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 930 case SND_SOC_DAIFMT_CBM_CFM: 931 aic3x->master = 1; 932 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; 933 break; 934 case SND_SOC_DAIFMT_CBS_CFS: 935 aic3x->master = 0; 936 break; 937 default: 938 return -EINVAL; 939 } 940 941 /* 942 * match both interface format and signal polarities since they 943 * are fixed 944 */ 945 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | 946 SND_SOC_DAIFMT_INV_MASK)) { 947 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): 948 break; 949 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): 950 delay = 1; 951 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): 952 iface_breg |= (0x01 << 6); 953 break; 954 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): 955 iface_breg |= (0x02 << 6); 956 break; 957 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): 958 iface_breg |= (0x03 << 6); 959 break; 960 default: 961 return -EINVAL; 962 } 963 964 /* set iface */ 965 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); 966 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); 967 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay); 968 969 return 0; 970 } 971 972 static int aic3x_set_bias_level(struct snd_soc_codec *codec, 973 enum snd_soc_bias_level level) 974 { 975 struct aic3x_priv *aic3x = codec->private_data; 976 u8 reg; 977 978 switch (level) { 979 case SND_SOC_BIAS_ON: 980 /* all power is driven by DAPM system */ 981 if (aic3x->master) { 982 /* enable pll */ 983 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 984 aic3x_write(codec, AIC3X_PLL_PROGA_REG, 985 reg | PLL_ENABLE); 986 } 987 break; 988 case SND_SOC_BIAS_PREPARE: 989 break; 990 case SND_SOC_BIAS_STANDBY: 991 /* 992 * all power is driven by DAPM system, 993 * so output power is safe if bypass was set 994 */ 995 if (aic3x->master) { 996 /* disable pll */ 997 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 998 aic3x_write(codec, AIC3X_PLL_PROGA_REG, 999 reg & ~PLL_ENABLE); 1000 } 1001 break; 1002 case SND_SOC_BIAS_OFF: 1003 /* force all power off */ 1004 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL); 1005 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON); 1006 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL); 1007 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON); 1008 1009 reg = aic3x_read_reg_cache(codec, DAC_PWR); 1010 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON)); 1011 1012 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL); 1013 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON); 1014 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL); 1015 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON); 1016 1017 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL); 1018 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON); 1019 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL); 1020 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON); 1021 1022 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL); 1023 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON); 1024 1025 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL); 1026 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON); 1027 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL); 1028 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON); 1029 1030 if (aic3x->master) { 1031 /* disable pll */ 1032 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG); 1033 aic3x_write(codec, AIC3X_PLL_PROGA_REG, 1034 reg & ~PLL_ENABLE); 1035 } 1036 break; 1037 } 1038 codec->bias_level = level; 1039 1040 return 0; 1041 } 1042 1043 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state) 1044 { 1045 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; 1046 u8 bit = gpio ? 3: 0; 1047 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit); 1048 aic3x_write(codec, reg, val | (!!state << bit)); 1049 } 1050 EXPORT_SYMBOL_GPL(aic3x_set_gpio); 1051 1052 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio) 1053 { 1054 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; 1055 u8 val, bit = gpio ? 2: 1; 1056 1057 aic3x_read(codec, reg, &val); 1058 return (val >> bit) & 1; 1059 } 1060 EXPORT_SYMBOL_GPL(aic3x_get_gpio); 1061 1062 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect, 1063 int headset_debounce, int button_debounce) 1064 { 1065 u8 val; 1066 1067 val = ((detect & AIC3X_HEADSET_DETECT_MASK) 1068 << AIC3X_HEADSET_DETECT_SHIFT) | 1069 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK) 1070 << AIC3X_HEADSET_DEBOUNCE_SHIFT) | 1071 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK) 1072 << AIC3X_BUTTON_DEBOUNCE_SHIFT); 1073 1074 if (detect & AIC3X_HEADSET_DETECT_MASK) 1075 val |= AIC3X_HEADSET_DETECT_ENABLED; 1076 1077 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val); 1078 } 1079 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection); 1080 1081 int aic3x_headset_detected(struct snd_soc_codec *codec) 1082 { 1083 u8 val; 1084 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); 1085 return (val >> 4) & 1; 1086 } 1087 EXPORT_SYMBOL_GPL(aic3x_headset_detected); 1088 1089 int aic3x_button_pressed(struct snd_soc_codec *codec) 1090 { 1091 u8 val; 1092 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); 1093 return (val >> 5) & 1; 1094 } 1095 EXPORT_SYMBOL_GPL(aic3x_button_pressed); 1096 1097 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1098 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1099 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1100 1101 static struct snd_soc_dai_ops aic3x_dai_ops = { 1102 .hw_params = aic3x_hw_params, 1103 .digital_mute = aic3x_mute, 1104 .set_sysclk = aic3x_set_dai_sysclk, 1105 .set_fmt = aic3x_set_dai_fmt, 1106 }; 1107 1108 struct snd_soc_dai aic3x_dai = { 1109 .name = "tlv320aic3x", 1110 .playback = { 1111 .stream_name = "Playback", 1112 .channels_min = 1, 1113 .channels_max = 2, 1114 .rates = AIC3X_RATES, 1115 .formats = AIC3X_FORMATS,}, 1116 .capture = { 1117 .stream_name = "Capture", 1118 .channels_min = 1, 1119 .channels_max = 2, 1120 .rates = AIC3X_RATES, 1121 .formats = AIC3X_FORMATS,}, 1122 .ops = &aic3x_dai_ops, 1123 }; 1124 EXPORT_SYMBOL_GPL(aic3x_dai); 1125 1126 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state) 1127 { 1128 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1129 struct snd_soc_codec *codec = socdev->card->codec; 1130 1131 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1132 1133 return 0; 1134 } 1135 1136 static int aic3x_resume(struct platform_device *pdev) 1137 { 1138 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1139 struct snd_soc_codec *codec = socdev->card->codec; 1140 int i; 1141 u8 data[2]; 1142 u8 *cache = codec->reg_cache; 1143 1144 /* Sync reg_cache with the hardware */ 1145 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) { 1146 data[0] = i; 1147 data[1] = cache[i]; 1148 codec->hw_write(codec->control_data, data, 2); 1149 } 1150 1151 aic3x_set_bias_level(codec, codec->suspend_bias_level); 1152 1153 return 0; 1154 } 1155 1156 /* 1157 * initialise the AIC3X driver 1158 * register the mixer and dsp interfaces with the kernel 1159 */ 1160 static int aic3x_init(struct snd_soc_codec *codec) 1161 { 1162 int reg; 1163 1164 mutex_init(&codec->mutex); 1165 INIT_LIST_HEAD(&codec->dapm_widgets); 1166 INIT_LIST_HEAD(&codec->dapm_paths); 1167 1168 codec->name = "tlv320aic3x"; 1169 codec->owner = THIS_MODULE; 1170 codec->read = aic3x_read_reg_cache; 1171 codec->write = aic3x_write; 1172 codec->set_bias_level = aic3x_set_bias_level; 1173 codec->dai = &aic3x_dai; 1174 codec->num_dai = 1; 1175 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg); 1176 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL); 1177 if (codec->reg_cache == NULL) 1178 return -ENOMEM; 1179 1180 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); 1181 aic3x_write(codec, AIC3X_RESET, SOFT_RESET); 1182 1183 /* DAC default volume and mute */ 1184 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); 1185 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); 1186 1187 /* DAC to HP default volume and route to Output mixer */ 1188 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); 1189 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); 1190 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1191 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1192 /* DAC to Line Out default volume and route to Output mixer */ 1193 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1194 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1195 /* DAC to Mono Line Out default volume and route to Output mixer */ 1196 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1197 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1198 1199 /* unmute all outputs */ 1200 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL); 1201 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE); 1202 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL); 1203 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE); 1204 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL); 1205 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE); 1206 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL); 1207 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE); 1208 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL); 1209 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE); 1210 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL); 1211 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE); 1212 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL); 1213 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE); 1214 1215 /* ADC default volume and unmute */ 1216 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN); 1217 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN); 1218 /* By default route Line1 to ADC PGA mixer */ 1219 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0); 1220 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0); 1221 1222 /* PGA to HP Bypass default volume, disconnect from Output Mixer */ 1223 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); 1224 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); 1225 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); 1226 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); 1227 /* PGA to Line Out default volume, disconnect from Output Mixer */ 1228 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); 1229 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); 1230 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ 1231 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); 1232 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); 1233 1234 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ 1235 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); 1236 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); 1237 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); 1238 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); 1239 /* Line2 Line Out default volume, disconnect from Output Mixer */ 1240 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); 1241 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); 1242 /* Line2 to Mono Out default volume, disconnect from Output Mixer */ 1243 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); 1244 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); 1245 1246 /* off, with power on */ 1247 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1248 1249 return 0; 1250 } 1251 1252 static struct snd_soc_codec *aic3x_codec; 1253 1254 static int aic3x_register(struct snd_soc_codec *codec) 1255 { 1256 int ret; 1257 1258 ret = aic3x_init(codec); 1259 if (ret < 0) { 1260 dev_err(codec->dev, "Failed to initialise device\n"); 1261 return ret; 1262 } 1263 1264 aic3x_codec = codec; 1265 1266 ret = snd_soc_register_codec(codec); 1267 if (ret) { 1268 dev_err(codec->dev, "Failed to register codec\n"); 1269 return ret; 1270 } 1271 1272 ret = snd_soc_register_dai(&aic3x_dai); 1273 if (ret) { 1274 dev_err(codec->dev, "Failed to register dai\n"); 1275 snd_soc_unregister_codec(codec); 1276 return ret; 1277 } 1278 1279 return 0; 1280 } 1281 1282 static int aic3x_unregister(struct aic3x_priv *aic3x) 1283 { 1284 aic3x_set_bias_level(&aic3x->codec, SND_SOC_BIAS_OFF); 1285 1286 snd_soc_unregister_dai(&aic3x_dai); 1287 snd_soc_unregister_codec(&aic3x->codec); 1288 1289 kfree(aic3x); 1290 aic3x_codec = NULL; 1291 1292 return 0; 1293 } 1294 1295 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1296 /* 1297 * AIC3X 2 wire address can be up to 4 devices with device addresses 1298 * 0x18, 0x19, 0x1A, 0x1B 1299 */ 1300 1301 /* 1302 * If the i2c layer weren't so broken, we could pass this kind of data 1303 * around 1304 */ 1305 static int aic3x_i2c_probe(struct i2c_client *i2c, 1306 const struct i2c_device_id *id) 1307 { 1308 struct snd_soc_codec *codec; 1309 struct aic3x_priv *aic3x; 1310 1311 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL); 1312 if (aic3x == NULL) { 1313 dev_err(&i2c->dev, "failed to create private data\n"); 1314 return -ENOMEM; 1315 } 1316 1317 codec = &aic3x->codec; 1318 codec->dev = &i2c->dev; 1319 codec->private_data = aic3x; 1320 codec->control_data = i2c; 1321 codec->hw_write = (hw_write_t) i2c_master_send; 1322 1323 i2c_set_clientdata(i2c, aic3x); 1324 1325 return aic3x_register(codec); 1326 } 1327 1328 static int aic3x_i2c_remove(struct i2c_client *client) 1329 { 1330 struct aic3x_priv *aic3x = i2c_get_clientdata(client); 1331 1332 return aic3x_unregister(aic3x); 1333 } 1334 1335 static const struct i2c_device_id aic3x_i2c_id[] = { 1336 { "tlv320aic3x", 0 }, 1337 { "tlv320aic33", 0 }, 1338 { } 1339 }; 1340 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); 1341 1342 /* machine i2c codec control layer */ 1343 static struct i2c_driver aic3x_i2c_driver = { 1344 .driver = { 1345 .name = "aic3x I2C Codec", 1346 .owner = THIS_MODULE, 1347 }, 1348 .probe = aic3x_i2c_probe, 1349 .remove = aic3x_i2c_remove, 1350 .id_table = aic3x_i2c_id, 1351 }; 1352 1353 static inline void aic3x_i2c_init(void) 1354 { 1355 int ret; 1356 1357 ret = i2c_add_driver(&aic3x_i2c_driver); 1358 if (ret) 1359 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n", 1360 __func__, ret); 1361 } 1362 1363 static inline void aic3x_i2c_exit(void) 1364 { 1365 i2c_del_driver(&aic3x_i2c_driver); 1366 } 1367 #else 1368 static inline void aic3x_i2c_init(void) { } 1369 static inline void aic3x_i2c_exit(void) { } 1370 #endif 1371 1372 static int aic3x_probe(struct platform_device *pdev) 1373 { 1374 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1375 struct aic3x_setup_data *setup; 1376 struct snd_soc_codec *codec; 1377 int ret = 0; 1378 1379 codec = aic3x_codec; 1380 if (!codec) { 1381 dev_err(&pdev->dev, "Codec not registered\n"); 1382 return -ENODEV; 1383 } 1384 1385 socdev->card->codec = codec; 1386 setup = socdev->codec_data; 1387 1388 if (setup) { 1389 /* setup GPIO functions */ 1390 aic3x_write(codec, AIC3X_GPIO1_REG, 1391 (setup->gpio_func[0] & 0xf) << 4); 1392 aic3x_write(codec, AIC3X_GPIO2_REG, 1393 (setup->gpio_func[1] & 0xf) << 4); 1394 } 1395 1396 /* register pcms */ 1397 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); 1398 if (ret < 0) { 1399 printk(KERN_ERR "aic3x: failed to create pcms\n"); 1400 goto pcm_err; 1401 } 1402 1403 snd_soc_add_controls(codec, aic3x_snd_controls, 1404 ARRAY_SIZE(aic3x_snd_controls)); 1405 1406 aic3x_add_widgets(codec); 1407 1408 ret = snd_soc_init_card(socdev); 1409 if (ret < 0) { 1410 printk(KERN_ERR "aic3x: failed to register card\n"); 1411 goto card_err; 1412 } 1413 1414 return ret; 1415 1416 card_err: 1417 snd_soc_free_pcms(socdev); 1418 snd_soc_dapm_free(socdev); 1419 1420 pcm_err: 1421 kfree(codec->reg_cache); 1422 return ret; 1423 } 1424 1425 static int aic3x_remove(struct platform_device *pdev) 1426 { 1427 struct snd_soc_device *socdev = platform_get_drvdata(pdev); 1428 struct snd_soc_codec *codec = socdev->card->codec; 1429 1430 /* power down chip */ 1431 if (codec->control_data) 1432 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1433 1434 snd_soc_free_pcms(socdev); 1435 snd_soc_dapm_free(socdev); 1436 1437 kfree(codec->reg_cache); 1438 1439 return 0; 1440 } 1441 1442 struct snd_soc_codec_device soc_codec_dev_aic3x = { 1443 .probe = aic3x_probe, 1444 .remove = aic3x_remove, 1445 .suspend = aic3x_suspend, 1446 .resume = aic3x_resume, 1447 }; 1448 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x); 1449 1450 static int __init aic3x_modinit(void) 1451 { 1452 aic3x_i2c_init(); 1453 1454 return 0; 1455 } 1456 module_init(aic3x_modinit); 1457 1458 static void __exit aic3x_exit(void) 1459 { 1460 aic3x_i2c_exit(); 1461 } 1462 module_exit(aic3x_exit); 1463 1464 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); 1465 MODULE_AUTHOR("Vladimir Barinov"); 1466 MODULE_LICENSE("GPL"); 1467