1 // SPDX-License-Identifier: GPL-2.0-only 2 /* ALSA SoC TLV320AIC3X codec driver 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood 8 * 9 * Notes: 10 * The AIC3X is a driver for a low power stereo audio 11 * codecs aic31, aic32, aic33, aic3007. 12 * 13 * It supports full aic33 codec functionality. 14 * The compatibility with aic32, aic31 and aic3007 is as follows: 15 * aic32/aic3007 | aic31 16 * --------------------------------------- 17 * MONO_LOUT -> N/A | MONO_LOUT -> N/A 18 * | IN1L -> LINE1L 19 * | IN1R -> LINE1R 20 * | IN2L -> LINE2L 21 * | IN2R -> LINE2R 22 * | MIC3L/R -> N/A 23 * truncated internal functionality in 24 * accordance with documentation 25 * --------------------------------------- 26 * 27 * Hence the machine layer should disable unsupported inputs/outputs by 28 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. 29 */ 30 31 #include <linux/module.h> 32 #include <linux/moduleparam.h> 33 #include <linux/init.h> 34 #include <linux/delay.h> 35 #include <linux/pm.h> 36 #include <linux/i2c.h> 37 #include <linux/gpio.h> 38 #include <linux/regulator/consumer.h> 39 #include <linux/of.h> 40 #include <linux/of_gpio.h> 41 #include <linux/slab.h> 42 #include <sound/core.h> 43 #include <sound/pcm.h> 44 #include <sound/pcm_params.h> 45 #include <sound/soc.h> 46 #include <sound/initval.h> 47 #include <sound/tlv.h> 48 #include <sound/tlv320aic3x.h> 49 50 #include "tlv320aic3x.h" 51 52 #define AIC3X_NUM_SUPPLIES 4 53 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { 54 "IOVDD", /* I/O Voltage */ 55 "DVDD", /* Digital Core Voltage */ 56 "AVDD", /* Analog DAC Voltage */ 57 "DRVDD", /* ADC Analog and Output Driver Voltage */ 58 }; 59 60 static LIST_HEAD(reset_list); 61 62 struct aic3x_priv; 63 64 struct aic3x_disable_nb { 65 struct notifier_block nb; 66 struct aic3x_priv *aic3x; 67 }; 68 69 /* codec private data */ 70 struct aic3x_priv { 71 struct snd_soc_component *component; 72 struct regmap *regmap; 73 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; 74 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES]; 75 struct aic3x_setup_data *setup; 76 unsigned int sysclk; 77 unsigned int dai_fmt; 78 unsigned int tdm_delay; 79 unsigned int slot_width; 80 struct list_head list; 81 int master; 82 int gpio_reset; 83 int power; 84 u16 model; 85 86 /* Selects the micbias voltage */ 87 enum aic3x_micbias_voltage micbias_vg; 88 /* Output Common-Mode Voltage */ 89 u8 ocmv; 90 }; 91 92 static const struct reg_default aic3x_reg[] = { 93 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 }, 94 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 }, 95 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 }, 96 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 }, 97 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 }, 98 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 }, 99 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe }, 100 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 }, 101 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 }, 102 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 }, 103 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 }, 104 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 }, 105 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 }, 106 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 }, 107 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 }, 108 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 }, 109 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 }, 110 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 }, 111 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 }, 112 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 }, 113 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 }, 114 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 }, 115 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 }, 116 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 }, 117 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 }, 118 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 }, 119 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 }, 120 { 108, 0x00 }, { 109, 0x00 }, 121 }; 122 123 static bool aic3x_volatile_reg(struct device *dev, unsigned int reg) 124 { 125 switch (reg) { 126 case AIC3X_RESET: 127 return true; 128 default: 129 return false; 130 } 131 } 132 133 const struct regmap_config aic3x_regmap = { 134 .max_register = DAC_ICC_ADJ, 135 .reg_defaults = aic3x_reg, 136 .num_reg_defaults = ARRAY_SIZE(aic3x_reg), 137 138 .volatile_reg = aic3x_volatile_reg, 139 140 .cache_type = REGCACHE_RBTREE, 141 }; 142 EXPORT_SYMBOL_GPL(aic3x_regmap); 143 144 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ 145 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \ 146 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x) 147 148 /* 149 * All input lines are connected when !0xf and disconnected with 0xf bit field, 150 * so we have to use specific dapm_put call for input mixer 151 */ 152 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, 153 struct snd_ctl_elem_value *ucontrol) 154 { 155 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); 156 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 157 struct soc_mixer_control *mc = 158 (struct soc_mixer_control *)kcontrol->private_value; 159 unsigned int reg = mc->reg; 160 unsigned int shift = mc->shift; 161 int max = mc->max; 162 unsigned int mask = (1 << fls(max)) - 1; 163 unsigned int invert = mc->invert; 164 unsigned short val; 165 struct snd_soc_dapm_update update = {}; 166 int connect, change; 167 168 val = (ucontrol->value.integer.value[0] & mask); 169 170 mask = 0xf; 171 if (val) 172 val = mask; 173 174 connect = !!val; 175 176 if (invert) 177 val = mask - val; 178 179 mask <<= shift; 180 val <<= shift; 181 182 change = snd_soc_component_test_bits(component, reg, mask, val); 183 if (change) { 184 update.kcontrol = kcontrol; 185 update.reg = reg; 186 update.mask = mask; 187 update.val = val; 188 189 snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect, 190 &update); 191 } 192 193 return change; 194 } 195 196 /* 197 * mic bias power on/off share the same register bits with 198 * output voltage of mic bias. when power on mic bias, we 199 * need reclaim it to voltage value. 200 * 0x0 = Powered off 201 * 0x1 = MICBIAS output is powered to 2.0V, 202 * 0x2 = MICBIAS output is powered to 2.5V 203 * 0x3 = MICBIAS output is connected to AVDD 204 */ 205 static int mic_bias_event(struct snd_soc_dapm_widget *w, 206 struct snd_kcontrol *kcontrol, int event) 207 { 208 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 209 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 210 211 switch (event) { 212 case SND_SOC_DAPM_POST_PMU: 213 /* change mic bias voltage to user defined */ 214 snd_soc_component_update_bits(component, MICBIAS_CTRL, 215 MICBIAS_LEVEL_MASK, 216 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT); 217 break; 218 219 case SND_SOC_DAPM_PRE_PMD: 220 snd_soc_component_update_bits(component, MICBIAS_CTRL, 221 MICBIAS_LEVEL_MASK, 0); 222 break; 223 } 224 return 0; 225 } 226 227 static const char * const aic3x_left_dac_mux[] = { 228 "DAC_L1", "DAC_L3", "DAC_L2" }; 229 static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6, 230 aic3x_left_dac_mux); 231 232 static const char * const aic3x_right_dac_mux[] = { 233 "DAC_R1", "DAC_R3", "DAC_R2" }; 234 static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4, 235 aic3x_right_dac_mux); 236 237 static const char * const aic3x_left_hpcom_mux[] = { 238 "differential of HPLOUT", "constant VCM", "single-ended" }; 239 static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4, 240 aic3x_left_hpcom_mux); 241 242 static const char * const aic3x_right_hpcom_mux[] = { 243 "differential of HPROUT", "constant VCM", "single-ended", 244 "differential of HPLCOM", "external feedback" }; 245 static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3, 246 aic3x_right_hpcom_mux); 247 248 static const char * const aic3x_linein_mode_mux[] = { 249 "single-ended", "differential" }; 250 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7, 251 aic3x_linein_mode_mux); 252 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7, 253 aic3x_linein_mode_mux); 254 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7, 255 aic3x_linein_mode_mux); 256 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7, 257 aic3x_linein_mode_mux); 258 static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7, 259 aic3x_linein_mode_mux); 260 static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7, 261 aic3x_linein_mode_mux); 262 263 static const char * const aic3x_adc_hpf[] = { 264 "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; 265 static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4, 266 aic3x_adc_hpf); 267 268 static const char * const aic3x_agc_level[] = { 269 "-5.5dB", "-8dB", "-10dB", "-12dB", 270 "-14dB", "-17dB", "-20dB", "-24dB" }; 271 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4, 272 aic3x_agc_level); 273 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4, 274 aic3x_agc_level); 275 276 static const char * const aic3x_agc_attack[] = { 277 "8ms", "11ms", "16ms", "20ms" }; 278 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2, 279 aic3x_agc_attack); 280 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2, 281 aic3x_agc_attack); 282 283 static const char * const aic3x_agc_decay[] = { 284 "100ms", "200ms", "400ms", "500ms" }; 285 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0, 286 aic3x_agc_decay); 287 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0, 288 aic3x_agc_decay); 289 290 static const char * const aic3x_poweron_time[] = { 291 "0us", "10us", "100us", "1ms", "10ms", "50ms", 292 "100ms", "200ms", "400ms", "800ms", "2s", "4s" }; 293 static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4, 294 aic3x_poweron_time); 295 296 static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" }; 297 static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2, 298 aic3x_rampup_step); 299 300 /* 301 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps 302 */ 303 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); 304 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ 305 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); 306 /* 307 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. 308 * Step size is approximately 0.5 dB over most of the scale but increasing 309 * near the very low levels. 310 * Define dB scale so that it is mostly correct for range about -55 to 0 dB 311 * but having increasing dB difference below that (and where it doesn't count 312 * so much). This setting shows -50 dB (actual is -50.3 dB) for register 313 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. 314 */ 315 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); 316 317 /* Output volumes. From 0 to 9 dB in 1 dB steps */ 318 static const DECLARE_TLV_DB_SCALE(out_tlv, 0, 100, 0); 319 320 static const struct snd_kcontrol_new aic3x_snd_controls[] = { 321 /* Output */ 322 SOC_DOUBLE_R_TLV("PCM Playback Volume", 323 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 324 325 /* 326 * Output controls that map to output mixer switches. Note these are 327 * only for swapped L-to-R and R-to-L routes. See below stereo controls 328 * for direct L-to-L and R-to-R routes. 329 */ 330 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", 331 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 332 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", 333 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 334 335 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", 336 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 337 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", 338 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 339 340 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", 341 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 342 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", 343 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 344 345 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", 346 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 347 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", 348 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 349 350 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", 351 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 352 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", 353 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 354 355 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", 356 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 357 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", 358 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 359 360 /* Stereo output controls for direct L-to-L and R-to-R routes */ 361 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", 362 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, 363 0, 118, 1, output_stage_tlv), 364 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 365 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 366 0, 118, 1, output_stage_tlv), 367 368 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", 369 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 370 0, 118, 1, output_stage_tlv), 371 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 372 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 373 0, 118, 1, output_stage_tlv), 374 375 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", 376 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, 377 0, 118, 1, output_stage_tlv), 378 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 379 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 380 0, 118, 1, output_stage_tlv), 381 382 /* Output pin controls */ 383 SOC_DOUBLE_R_TLV("Line Playback Volume", LLOPM_CTRL, RLOPM_CTRL, 4, 384 9, 0, out_tlv), 385 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, 386 0x01, 0), 387 SOC_DOUBLE_R_TLV("HP Playback Volume", HPLOUT_CTRL, HPROUT_CTRL, 4, 388 9, 0, out_tlv), 389 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 390 0x01, 0), 391 SOC_DOUBLE_R_TLV("HPCOM Playback Volume", HPLCOM_CTRL, HPRCOM_CTRL, 392 4, 9, 0, out_tlv), 393 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 394 0x01, 0), 395 396 /* 397 * Note: enable Automatic input Gain Controller with care. It can 398 * adjust PGA to max value when ADC is on and will never go back. 399 */ 400 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), 401 SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum), 402 SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum), 403 SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum), 404 SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum), 405 SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum), 406 SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum), 407 408 /* De-emphasis */ 409 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0), 410 411 /* Input */ 412 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 413 0, 119, 0, adc_tlv), 414 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), 415 416 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum), 417 418 /* Pop reduction */ 419 SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum), 420 SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum), 421 }; 422 423 /* For other than tlv320aic3104 */ 424 static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = { 425 /* 426 * Output controls that map to output mixer switches. Note these are 427 * only for swapped L-to-R and R-to-L routes. See below stereo controls 428 * for direct L-to-L and R-to-R routes. 429 */ 430 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", 431 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 432 433 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", 434 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 435 436 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", 437 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 438 439 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", 440 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 441 442 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", 443 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 444 445 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", 446 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 447 448 /* Stereo output controls for direct L-to-L and R-to-R routes */ 449 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", 450 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, 451 0, 118, 1, output_stage_tlv), 452 453 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", 454 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 455 0, 118, 1, output_stage_tlv), 456 457 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", 458 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 459 0, 118, 1, output_stage_tlv), 460 }; 461 462 static const struct snd_kcontrol_new aic3x_mono_controls[] = { 463 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", 464 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 465 0, 118, 1, output_stage_tlv), 466 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", 467 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 468 0, 118, 1, output_stage_tlv), 469 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 470 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 471 0, 118, 1, output_stage_tlv), 472 473 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 474 SOC_SINGLE_TLV("Mono Playback Volume", MONOLOPM_CTRL, 4, 9, 0, 475 out_tlv), 476 477 }; 478 479 /* 480 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps 481 */ 482 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0); 483 484 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl = 485 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv); 486 487 /* Left DAC Mux */ 488 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = 489 SOC_DAPM_ENUM("Route", aic3x_left_dac_enum); 490 491 /* Right DAC Mux */ 492 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = 493 SOC_DAPM_ENUM("Route", aic3x_right_dac_enum); 494 495 /* Left HPCOM Mux */ 496 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = 497 SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum); 498 499 /* Right HPCOM Mux */ 500 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = 501 SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum); 502 503 /* Left Line Mixer */ 504 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { 505 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), 506 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), 507 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), 508 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), 509 /* Not on tlv320aic3104 */ 510 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), 511 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), 512 }; 513 514 /* Right Line Mixer */ 515 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { 516 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), 517 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), 518 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), 519 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), 520 /* Not on tlv320aic3104 */ 521 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), 522 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), 523 }; 524 525 /* Mono Mixer */ 526 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { 527 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), 528 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), 529 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), 530 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), 531 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), 532 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), 533 }; 534 535 /* Left HP Mixer */ 536 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { 537 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), 538 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), 539 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), 540 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), 541 /* Not on tlv320aic3104 */ 542 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), 543 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), 544 }; 545 546 /* Right HP Mixer */ 547 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { 548 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), 549 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), 550 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), 551 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), 552 /* Not on tlv320aic3104 */ 553 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), 554 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), 555 }; 556 557 /* Left HPCOM Mixer */ 558 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { 559 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), 560 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), 561 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), 562 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), 563 /* Not on tlv320aic3104 */ 564 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), 565 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), 566 }; 567 568 /* Right HPCOM Mixer */ 569 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { 570 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), 571 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), 572 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), 573 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), 574 /* Not on tlv320aic3104 */ 575 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), 576 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), 577 }; 578 579 /* Left PGA Mixer */ 580 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { 581 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 582 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 583 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), 584 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 585 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 586 }; 587 588 /* Right PGA Mixer */ 589 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { 590 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 591 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 592 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), 593 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 594 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 595 }; 596 597 /* Left PGA Mixer for tlv320aic3104 */ 598 static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = { 599 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 600 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 601 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 602 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 603 }; 604 605 /* Right PGA Mixer for tlv320aic3104 */ 606 static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = { 607 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 608 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 609 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 610 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 611 }; 612 613 /* Left Line1 Mux */ 614 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls = 615 SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum); 616 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls = 617 SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum); 618 619 /* Right Line1 Mux */ 620 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls = 621 SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum); 622 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls = 623 SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum); 624 625 /* Left Line2 Mux */ 626 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = 627 SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum); 628 629 /* Right Line2 Mux */ 630 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = 631 SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum); 632 633 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { 634 /* Left DAC to Left Outputs */ 635 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), 636 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, 637 &aic3x_left_dac_mux_controls), 638 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, 639 &aic3x_left_hpcom_mux_controls), 640 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), 641 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), 642 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), 643 644 /* Right DAC to Right Outputs */ 645 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), 646 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, 647 &aic3x_right_dac_mux_controls), 648 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, 649 &aic3x_right_hpcom_mux_controls), 650 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), 651 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), 652 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), 653 654 /* Inputs to Left ADC */ 655 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), 656 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, 657 &aic3x_left_line1l_mux_controls), 658 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, 659 &aic3x_left_line1r_mux_controls), 660 661 /* Inputs to Right ADC */ 662 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 663 LINE1R_2_RADC_CTRL, 2, 0), 664 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, 665 &aic3x_right_line1l_mux_controls), 666 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, 667 &aic3x_right_line1r_mux_controls), 668 669 /* Mic Bias */ 670 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0, 671 mic_bias_event, 672 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 673 674 SND_SOC_DAPM_OUTPUT("LLOUT"), 675 SND_SOC_DAPM_OUTPUT("RLOUT"), 676 SND_SOC_DAPM_OUTPUT("HPLOUT"), 677 SND_SOC_DAPM_OUTPUT("HPROUT"), 678 SND_SOC_DAPM_OUTPUT("HPLCOM"), 679 SND_SOC_DAPM_OUTPUT("HPRCOM"), 680 681 SND_SOC_DAPM_INPUT("LINE1L"), 682 SND_SOC_DAPM_INPUT("LINE1R"), 683 684 /* 685 * Virtual output pin to detection block inside codec. This can be 686 * used to keep codec bias on if gpio or detection features are needed. 687 * Force pin on or construct a path with an input jack and mic bias 688 * widgets. 689 */ 690 SND_SOC_DAPM_OUTPUT("Detection"), 691 }; 692 693 /* For other than tlv320aic3104 */ 694 static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = { 695 /* Inputs to Left ADC */ 696 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 697 &aic3x_left_pga_mixer_controls[0], 698 ARRAY_SIZE(aic3x_left_pga_mixer_controls)), 699 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, 700 &aic3x_left_line2_mux_controls), 701 702 /* Inputs to Right ADC */ 703 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 704 &aic3x_right_pga_mixer_controls[0], 705 ARRAY_SIZE(aic3x_right_pga_mixer_controls)), 706 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, 707 &aic3x_right_line2_mux_controls), 708 709 /* 710 * Not a real mic bias widget but similar function. This is for dynamic 711 * control of GPIO1 digital mic modulator clock output function when 712 * using digital mic. 713 */ 714 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", 715 AIC3X_GPIO1_REG, 4, 0xf, 716 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, 717 AIC3X_GPIO1_FUNC_DISABLED), 718 719 /* 720 * Also similar function like mic bias. Selects digital mic with 721 * configurable oversampling rate instead of ADC converter. 722 */ 723 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", 724 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), 725 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", 726 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), 727 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", 728 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 729 730 /* Output mixers */ 731 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 732 &aic3x_left_line_mixer_controls[0], 733 ARRAY_SIZE(aic3x_left_line_mixer_controls)), 734 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 735 &aic3x_right_line_mixer_controls[0], 736 ARRAY_SIZE(aic3x_right_line_mixer_controls)), 737 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 738 &aic3x_left_hp_mixer_controls[0], 739 ARRAY_SIZE(aic3x_left_hp_mixer_controls)), 740 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 741 &aic3x_right_hp_mixer_controls[0], 742 ARRAY_SIZE(aic3x_right_hp_mixer_controls)), 743 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 744 &aic3x_left_hpcom_mixer_controls[0], 745 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), 746 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 747 &aic3x_right_hpcom_mixer_controls[0], 748 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), 749 750 SND_SOC_DAPM_INPUT("MIC3L"), 751 SND_SOC_DAPM_INPUT("MIC3R"), 752 SND_SOC_DAPM_INPUT("LINE2L"), 753 SND_SOC_DAPM_INPUT("LINE2R"), 754 }; 755 756 /* For tlv320aic3104 */ 757 static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = { 758 /* Inputs to Left ADC */ 759 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 760 &aic3104_left_pga_mixer_controls[0], 761 ARRAY_SIZE(aic3104_left_pga_mixer_controls)), 762 763 /* Inputs to Right ADC */ 764 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 765 &aic3104_right_pga_mixer_controls[0], 766 ARRAY_SIZE(aic3104_right_pga_mixer_controls)), 767 768 /* Output mixers */ 769 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 770 &aic3x_left_line_mixer_controls[0], 771 ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2), 772 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 773 &aic3x_right_line_mixer_controls[0], 774 ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2), 775 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 776 &aic3x_left_hp_mixer_controls[0], 777 ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2), 778 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 779 &aic3x_right_hp_mixer_controls[0], 780 ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2), 781 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 782 &aic3x_left_hpcom_mixer_controls[0], 783 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2), 784 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 785 &aic3x_right_hpcom_mixer_controls[0], 786 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2), 787 788 SND_SOC_DAPM_INPUT("MIC2L"), 789 SND_SOC_DAPM_INPUT("MIC2R"), 790 }; 791 792 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = { 793 /* Mono Output */ 794 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), 795 796 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, 797 &aic3x_mono_mixer_controls[0], 798 ARRAY_SIZE(aic3x_mono_mixer_controls)), 799 800 SND_SOC_DAPM_OUTPUT("MONO_LOUT"), 801 }; 802 803 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { 804 /* Class-D outputs */ 805 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0), 806 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0), 807 808 SND_SOC_DAPM_OUTPUT("SPOP"), 809 SND_SOC_DAPM_OUTPUT("SPOM"), 810 }; 811 812 static const struct snd_soc_dapm_route intercon[] = { 813 /* Left Input */ 814 {"Left Line1L Mux", "single-ended", "LINE1L"}, 815 {"Left Line1L Mux", "differential", "LINE1L"}, 816 {"Left Line1R Mux", "single-ended", "LINE1R"}, 817 {"Left Line1R Mux", "differential", "LINE1R"}, 818 819 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, 820 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, 821 822 {"Left ADC", NULL, "Left PGA Mixer"}, 823 824 /* Right Input */ 825 {"Right Line1R Mux", "single-ended", "LINE1R"}, 826 {"Right Line1R Mux", "differential", "LINE1R"}, 827 {"Right Line1L Mux", "single-ended", "LINE1L"}, 828 {"Right Line1L Mux", "differential", "LINE1L"}, 829 830 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, 831 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, 832 833 {"Right ADC", NULL, "Right PGA Mixer"}, 834 835 /* Left DAC Output */ 836 {"Left DAC Mux", "DAC_L1", "Left DAC"}, 837 {"Left DAC Mux", "DAC_L2", "Left DAC"}, 838 {"Left DAC Mux", "DAC_L3", "Left DAC"}, 839 840 /* Right DAC Output */ 841 {"Right DAC Mux", "DAC_R1", "Right DAC"}, 842 {"Right DAC Mux", "DAC_R2", "Right DAC"}, 843 {"Right DAC Mux", "DAC_R3", "Right DAC"}, 844 845 /* Left Line Output */ 846 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 847 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 848 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 849 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 850 851 {"Left Line Out", NULL, "Left Line Mixer"}, 852 {"Left Line Out", NULL, "Left DAC Mux"}, 853 {"LLOUT", NULL, "Left Line Out"}, 854 855 /* Right Line Output */ 856 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 857 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 858 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 859 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 860 861 {"Right Line Out", NULL, "Right Line Mixer"}, 862 {"Right Line Out", NULL, "Right DAC Mux"}, 863 {"RLOUT", NULL, "Right Line Out"}, 864 865 /* Left HP Output */ 866 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 867 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 868 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 869 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 870 871 {"Left HP Out", NULL, "Left HP Mixer"}, 872 {"Left HP Out", NULL, "Left DAC Mux"}, 873 {"HPLOUT", NULL, "Left HP Out"}, 874 875 /* Right HP Output */ 876 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 877 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 878 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 879 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 880 881 {"Right HP Out", NULL, "Right HP Mixer"}, 882 {"Right HP Out", NULL, "Right DAC Mux"}, 883 {"HPROUT", NULL, "Right HP Out"}, 884 885 /* Left HPCOM Output */ 886 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 887 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 888 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 889 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 890 891 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, 892 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, 893 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, 894 {"Left HP Com", NULL, "Left HPCOM Mux"}, 895 {"HPLCOM", NULL, "Left HP Com"}, 896 897 /* Right HPCOM Output */ 898 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 899 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 900 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 901 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 902 903 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, 904 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, 905 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, 906 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, 907 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, 908 {"Right HP Com", NULL, "Right HPCOM Mux"}, 909 {"HPRCOM", NULL, "Right HP Com"}, 910 }; 911 912 /* For other than tlv320aic3104 */ 913 static const struct snd_soc_dapm_route intercon_extra[] = { 914 /* Left Input */ 915 {"Left Line2L Mux", "single-ended", "LINE2L"}, 916 {"Left Line2L Mux", "differential", "LINE2L"}, 917 918 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, 919 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, 920 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, 921 922 {"Left ADC", NULL, "GPIO1 dmic modclk"}, 923 924 /* Right Input */ 925 {"Right Line2R Mux", "single-ended", "LINE2R"}, 926 {"Right Line2R Mux", "differential", "LINE2R"}, 927 928 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, 929 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, 930 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, 931 932 {"Right ADC", NULL, "GPIO1 dmic modclk"}, 933 934 /* 935 * Logical path between digital mic enable and GPIO1 modulator clock 936 * output function 937 */ 938 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, 939 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, 940 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, 941 942 /* Left Line Output */ 943 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 944 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 945 946 /* Right Line Output */ 947 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 948 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 949 950 /* Left HP Output */ 951 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 952 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 953 954 /* Right HP Output */ 955 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 956 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 957 958 /* Left HPCOM Output */ 959 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 960 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 961 962 /* Right HPCOM Output */ 963 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 964 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 965 }; 966 967 /* For tlv320aic3104 */ 968 static const struct snd_soc_dapm_route intercon_extra_3104[] = { 969 /* Left Input */ 970 {"Left PGA Mixer", "Mic2L Switch", "MIC2L"}, 971 {"Left PGA Mixer", "Mic2R Switch", "MIC2R"}, 972 973 /* Right Input */ 974 {"Right PGA Mixer", "Mic2L Switch", "MIC2L"}, 975 {"Right PGA Mixer", "Mic2R Switch", "MIC2R"}, 976 }; 977 978 static const struct snd_soc_dapm_route intercon_mono[] = { 979 /* Mono Output */ 980 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 981 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 982 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, 983 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 984 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 985 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, 986 {"Mono Out", NULL, "Mono Mixer"}, 987 {"MONO_LOUT", NULL, "Mono Out"}, 988 }; 989 990 static const struct snd_soc_dapm_route intercon_3007[] = { 991 /* Class-D outputs */ 992 {"Left Class-D Out", NULL, "Left Line Out"}, 993 {"Right Class-D Out", NULL, "Left Line Out"}, 994 {"SPOP", NULL, "Left Class-D Out"}, 995 {"SPOM", NULL, "Right Class-D Out"}, 996 }; 997 998 static int aic3x_add_widgets(struct snd_soc_component *component) 999 { 1000 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1001 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1002 1003 switch (aic3x->model) { 1004 case AIC3X_MODEL_3X: 1005 case AIC3X_MODEL_33: 1006 case AIC3X_MODEL_3106: 1007 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets, 1008 ARRAY_SIZE(aic3x_extra_dapm_widgets)); 1009 snd_soc_dapm_add_routes(dapm, intercon_extra, 1010 ARRAY_SIZE(intercon_extra)); 1011 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets, 1012 ARRAY_SIZE(aic3x_dapm_mono_widgets)); 1013 snd_soc_dapm_add_routes(dapm, intercon_mono, 1014 ARRAY_SIZE(intercon_mono)); 1015 break; 1016 case AIC3X_MODEL_3007: 1017 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets, 1018 ARRAY_SIZE(aic3x_extra_dapm_widgets)); 1019 snd_soc_dapm_add_routes(dapm, intercon_extra, 1020 ARRAY_SIZE(intercon_extra)); 1021 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, 1022 ARRAY_SIZE(aic3007_dapm_widgets)); 1023 snd_soc_dapm_add_routes(dapm, intercon_3007, 1024 ARRAY_SIZE(intercon_3007)); 1025 break; 1026 case AIC3X_MODEL_3104: 1027 snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets, 1028 ARRAY_SIZE(aic3104_extra_dapm_widgets)); 1029 snd_soc_dapm_add_routes(dapm, intercon_extra_3104, 1030 ARRAY_SIZE(intercon_extra_3104)); 1031 break; 1032 } 1033 1034 return 0; 1035 } 1036 1037 static int aic3x_hw_params(struct snd_pcm_substream *substream, 1038 struct snd_pcm_hw_params *params, 1039 struct snd_soc_dai *dai) 1040 { 1041 struct snd_soc_component *component = dai->component; 1042 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1043 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 1044 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 1045 u16 d, pll_d = 1; 1046 int clk; 1047 int width = aic3x->slot_width; 1048 1049 if (!width) 1050 width = params_width(params); 1051 1052 /* select data word length */ 1053 data = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); 1054 switch (width) { 1055 case 16: 1056 break; 1057 case 20: 1058 data |= (0x01 << 4); 1059 break; 1060 case 24: 1061 data |= (0x02 << 4); 1062 break; 1063 case 32: 1064 data |= (0x03 << 4); 1065 break; 1066 } 1067 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, data); 1068 1069 /* Fsref can be 44100 or 48000 */ 1070 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; 1071 1072 /* Try to find a value for Q which allows us to bypass the PLL and 1073 * generate CODEC_CLK directly. */ 1074 for (pll_q = 2; pll_q < 18; pll_q++) 1075 if (aic3x->sysclk / (128 * pll_q) == fsref) { 1076 bypass_pll = 1; 1077 break; 1078 } 1079 1080 if (bypass_pll) { 1081 pll_q &= 0xf; 1082 snd_soc_component_write(component, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 1083 snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 1084 /* disable PLL if it is bypassed */ 1085 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); 1086 1087 } else { 1088 snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 1089 /* enable PLL when it is used */ 1090 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, 1091 PLL_ENABLE, PLL_ENABLE); 1092 } 1093 1094 /* Route Left DAC to left channel input and 1095 * right DAC to right channel input */ 1096 data = (LDAC2LCH | RDAC2RCH); 1097 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; 1098 if (params_rate(params) >= 64000) 1099 data |= DUAL_RATE_MODE; 1100 snd_soc_component_write(component, AIC3X_CODEC_DATAPATH_REG, data); 1101 1102 /* codec sample rate select */ 1103 data = (fsref * 20) / params_rate(params); 1104 if (params_rate(params) < 64000) 1105 data /= 2; 1106 data /= 5; 1107 data -= 2; 1108 data |= (data << 4); 1109 snd_soc_component_write(component, AIC3X_SAMPLE_RATE_SEL_REG, data); 1110 1111 if (bypass_pll) 1112 return 0; 1113 1114 /* Use PLL, compute appropriate setup for j, d, r and p, the closest 1115 * one wins the game. Try with d==0 first, next with d!=0. 1116 * Constraints for j are according to the datasheet. 1117 * The sysclk is divided by 1000 to prevent integer overflows. 1118 */ 1119 1120 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); 1121 1122 for (r = 1; r <= 16; r++) 1123 for (p = 1; p <= 8; p++) { 1124 for (j = 4; j <= 55; j++) { 1125 /* This is actually 1000*((j+(d/10000))*r)/p 1126 * The term had to be converted to get 1127 * rid of the division by 10000; d = 0 here 1128 */ 1129 int tmp_clk = (1000 * j * r) / p; 1130 1131 /* Check whether this values get closer than 1132 * the best ones we had before 1133 */ 1134 if (abs(codec_clk - tmp_clk) < 1135 abs(codec_clk - last_clk)) { 1136 pll_j = j; pll_d = 0; 1137 pll_r = r; pll_p = p; 1138 last_clk = tmp_clk; 1139 } 1140 1141 /* Early exit for exact matches */ 1142 if (tmp_clk == codec_clk) 1143 goto found; 1144 } 1145 } 1146 1147 /* try with d != 0 */ 1148 for (p = 1; p <= 8; p++) { 1149 j = codec_clk * p / 1000; 1150 1151 if (j < 4 || j > 11) 1152 continue; 1153 1154 /* do not use codec_clk here since we'd loose precision */ 1155 d = ((2048 * p * fsref) - j * aic3x->sysclk) 1156 * 100 / (aic3x->sysclk/100); 1157 1158 clk = (10000 * j + d) / (10 * p); 1159 1160 /* check whether this values get closer than the best 1161 * ones we had before */ 1162 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { 1163 pll_j = j; pll_d = d; pll_r = 1; pll_p = p; 1164 last_clk = clk; 1165 } 1166 1167 /* Early exit for exact matches */ 1168 if (clk == codec_clk) 1169 goto found; 1170 } 1171 1172 if (last_clk == 0) { 1173 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); 1174 return -EINVAL; 1175 } 1176 1177 found: 1178 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p); 1179 snd_soc_component_write(component, AIC3X_OVRF_STATUS_AND_PLLR_REG, 1180 pll_r << PLLR_SHIFT); 1181 snd_soc_component_write(component, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); 1182 snd_soc_component_write(component, AIC3X_PLL_PROGC_REG, 1183 (pll_d >> 6) << PLLD_MSB_SHIFT); 1184 snd_soc_component_write(component, AIC3X_PLL_PROGD_REG, 1185 (pll_d & 0x3F) << PLLD_LSB_SHIFT); 1186 1187 return 0; 1188 } 1189 1190 static int aic3x_prepare(struct snd_pcm_substream *substream, 1191 struct snd_soc_dai *dai) 1192 { 1193 struct snd_soc_component *component = dai->component; 1194 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1195 int delay = 0; 1196 int width = aic3x->slot_width; 1197 1198 if (!width) 1199 width = substream->runtime->sample_bits; 1200 1201 /* TDM slot selection only valid in DSP_A/_B mode */ 1202 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A) 1203 delay += (aic3x->tdm_delay*width + 1); 1204 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B) 1205 delay += aic3x->tdm_delay*width; 1206 1207 /* Configure data delay */ 1208 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLC, delay); 1209 1210 return 0; 1211 } 1212 1213 static int aic3x_mute(struct snd_soc_dai *dai, int mute, int direction) 1214 { 1215 struct snd_soc_component *component = dai->component; 1216 u8 ldac_reg = snd_soc_component_read(component, LDAC_VOL) & ~MUTE_ON; 1217 u8 rdac_reg = snd_soc_component_read(component, RDAC_VOL) & ~MUTE_ON; 1218 1219 if (mute) { 1220 snd_soc_component_write(component, LDAC_VOL, ldac_reg | MUTE_ON); 1221 snd_soc_component_write(component, RDAC_VOL, rdac_reg | MUTE_ON); 1222 } else { 1223 snd_soc_component_write(component, LDAC_VOL, ldac_reg); 1224 snd_soc_component_write(component, RDAC_VOL, rdac_reg); 1225 } 1226 1227 return 0; 1228 } 1229 1230 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1231 int clk_id, unsigned int freq, int dir) 1232 { 1233 struct snd_soc_component *component = codec_dai->component; 1234 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1235 1236 /* set clock on MCLK or GPIO2 or BCLK */ 1237 snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, 1238 clk_id << PLLCLK_IN_SHIFT); 1239 snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, 1240 clk_id << CLKDIV_IN_SHIFT); 1241 1242 aic3x->sysclk = freq; 1243 return 0; 1244 } 1245 1246 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, 1247 unsigned int fmt) 1248 { 1249 struct snd_soc_component *component = codec_dai->component; 1250 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1251 u8 iface_areg, iface_breg; 1252 1253 iface_areg = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLA) & 0x3f; 1254 iface_breg = snd_soc_component_read(component, AIC3X_ASD_INTF_CTRLB) & 0x3f; 1255 1256 /* set master/slave audio interface */ 1257 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1258 case SND_SOC_DAIFMT_CBM_CFM: 1259 aic3x->master = 1; 1260 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; 1261 break; 1262 case SND_SOC_DAIFMT_CBS_CFS: 1263 aic3x->master = 0; 1264 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER); 1265 break; 1266 case SND_SOC_DAIFMT_CBM_CFS: 1267 aic3x->master = 1; 1268 iface_areg |= BIT_CLK_MASTER; 1269 iface_areg &= ~WORD_CLK_MASTER; 1270 break; 1271 case SND_SOC_DAIFMT_CBS_CFM: 1272 aic3x->master = 1; 1273 iface_areg |= WORD_CLK_MASTER; 1274 iface_areg &= ~BIT_CLK_MASTER; 1275 break; 1276 default: 1277 return -EINVAL; 1278 } 1279 1280 /* 1281 * match both interface format and signal polarities since they 1282 * are fixed 1283 */ 1284 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | 1285 SND_SOC_DAIFMT_INV_MASK)) { 1286 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): 1287 break; 1288 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): 1289 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): 1290 iface_breg |= (0x01 << 6); 1291 break; 1292 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): 1293 iface_breg |= (0x02 << 6); 1294 break; 1295 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): 1296 iface_breg |= (0x03 << 6); 1297 break; 1298 default: 1299 return -EINVAL; 1300 } 1301 1302 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 1303 1304 /* set iface */ 1305 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLA, iface_areg); 1306 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, iface_breg); 1307 1308 return 0; 1309 } 1310 1311 static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai, 1312 unsigned int tx_mask, unsigned int rx_mask, 1313 int slots, int slot_width) 1314 { 1315 struct snd_soc_component *component = codec_dai->component; 1316 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1317 unsigned int lsb; 1318 1319 if (tx_mask != rx_mask) { 1320 dev_err(component->dev, "tx and rx masks must be symmetric\n"); 1321 return -EINVAL; 1322 } 1323 1324 if (unlikely(!tx_mask)) { 1325 dev_err(component->dev, "tx and rx masks need to be non 0\n"); 1326 return -EINVAL; 1327 } 1328 1329 /* TDM based on DSP mode requires slots to be adjacent */ 1330 lsb = __ffs(tx_mask); 1331 if ((lsb + 1) != __fls(tx_mask)) { 1332 dev_err(component->dev, "Invalid mask, slots must be adjacent\n"); 1333 return -EINVAL; 1334 } 1335 1336 switch (slot_width) { 1337 case 16: 1338 case 20: 1339 case 24: 1340 case 32: 1341 break; 1342 default: 1343 dev_err(component->dev, "Unsupported slot width %d\n", slot_width); 1344 return -EINVAL; 1345 } 1346 1347 1348 aic3x->tdm_delay = lsb; 1349 aic3x->slot_width = slot_width; 1350 1351 /* DOUT in high-impedance on inactive bit clocks */ 1352 snd_soc_component_update_bits(component, AIC3X_ASD_INTF_CTRLA, 1353 DOUT_TRISTATE, DOUT_TRISTATE); 1354 1355 return 0; 1356 } 1357 1358 static int aic3x_regulator_event(struct notifier_block *nb, 1359 unsigned long event, void *data) 1360 { 1361 struct aic3x_disable_nb *disable_nb = 1362 container_of(nb, struct aic3x_disable_nb, nb); 1363 struct aic3x_priv *aic3x = disable_nb->aic3x; 1364 1365 if (event & REGULATOR_EVENT_DISABLE) { 1366 /* 1367 * Put codec to reset and require cache sync as at least one 1368 * of the supplies was disabled 1369 */ 1370 if (gpio_is_valid(aic3x->gpio_reset)) 1371 gpio_set_value(aic3x->gpio_reset, 0); 1372 regcache_mark_dirty(aic3x->regmap); 1373 } 1374 1375 return 0; 1376 } 1377 1378 static int aic3x_set_power(struct snd_soc_component *component, int power) 1379 { 1380 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1381 unsigned int pll_c, pll_d; 1382 int ret; 1383 1384 if (power) { 1385 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), 1386 aic3x->supplies); 1387 if (ret) 1388 goto out; 1389 aic3x->power = 1; 1390 1391 if (gpio_is_valid(aic3x->gpio_reset)) { 1392 udelay(1); 1393 gpio_set_value(aic3x->gpio_reset, 1); 1394 } 1395 1396 /* Sync reg_cache with the hardware */ 1397 regcache_cache_only(aic3x->regmap, false); 1398 regcache_sync(aic3x->regmap); 1399 1400 /* Rewrite paired PLL D registers in case cached sync skipped 1401 * writing one of them and thus caused other one also not 1402 * being written 1403 */ 1404 pll_c = snd_soc_component_read(component, AIC3X_PLL_PROGC_REG); 1405 pll_d = snd_soc_component_read(component, AIC3X_PLL_PROGD_REG); 1406 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def || 1407 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) { 1408 snd_soc_component_write(component, AIC3X_PLL_PROGC_REG, pll_c); 1409 snd_soc_component_write(component, AIC3X_PLL_PROGD_REG, pll_d); 1410 } 1411 1412 /* 1413 * Delay is needed to reduce pop-noise after syncing back the 1414 * registers 1415 */ 1416 mdelay(50); 1417 } else { 1418 /* 1419 * Do soft reset to this codec instance in order to clear 1420 * possible VDD leakage currents in case the supply regulators 1421 * remain on 1422 */ 1423 snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET); 1424 regcache_mark_dirty(aic3x->regmap); 1425 aic3x->power = 0; 1426 /* HW writes are needless when bias is off */ 1427 regcache_cache_only(aic3x->regmap, true); 1428 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), 1429 aic3x->supplies); 1430 } 1431 out: 1432 return ret; 1433 } 1434 1435 static int aic3x_set_bias_level(struct snd_soc_component *component, 1436 enum snd_soc_bias_level level) 1437 { 1438 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1439 1440 switch (level) { 1441 case SND_SOC_BIAS_ON: 1442 break; 1443 case SND_SOC_BIAS_PREPARE: 1444 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY && 1445 aic3x->master) { 1446 /* enable pll */ 1447 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, 1448 PLL_ENABLE, PLL_ENABLE); 1449 } 1450 break; 1451 case SND_SOC_BIAS_STANDBY: 1452 if (!aic3x->power) 1453 aic3x_set_power(component, 1); 1454 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE && 1455 aic3x->master) { 1456 /* disable pll */ 1457 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, 1458 PLL_ENABLE, 0); 1459 } 1460 break; 1461 case SND_SOC_BIAS_OFF: 1462 if (aic3x->power) 1463 aic3x_set_power(component, 0); 1464 break; 1465 } 1466 1467 return 0; 1468 } 1469 1470 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1471 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1472 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1473 SNDRV_PCM_FMTBIT_S32_LE) 1474 1475 static const struct snd_soc_dai_ops aic3x_dai_ops = { 1476 .hw_params = aic3x_hw_params, 1477 .prepare = aic3x_prepare, 1478 .mute_stream = aic3x_mute, 1479 .set_sysclk = aic3x_set_dai_sysclk, 1480 .set_fmt = aic3x_set_dai_fmt, 1481 .set_tdm_slot = aic3x_set_dai_tdm_slot, 1482 .no_capture_mute = 1, 1483 }; 1484 1485 static struct snd_soc_dai_driver aic3x_dai = { 1486 .name = "tlv320aic3x-hifi", 1487 .playback = { 1488 .stream_name = "Playback", 1489 .channels_min = 2, 1490 .channels_max = 2, 1491 .rates = AIC3X_RATES, 1492 .formats = AIC3X_FORMATS,}, 1493 .capture = { 1494 .stream_name = "Capture", 1495 .channels_min = 2, 1496 .channels_max = 2, 1497 .rates = AIC3X_RATES, 1498 .formats = AIC3X_FORMATS,}, 1499 .ops = &aic3x_dai_ops, 1500 .symmetric_rate = 1, 1501 }; 1502 1503 static void aic3x_mono_init(struct snd_soc_component *component) 1504 { 1505 /* DAC to Mono Line Out default volume and route to Output mixer */ 1506 snd_soc_component_write(component, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1507 snd_soc_component_write(component, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1508 1509 /* unmute all outputs */ 1510 snd_soc_component_update_bits(component, MONOLOPM_CTRL, UNMUTE, UNMUTE); 1511 1512 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ 1513 snd_soc_component_write(component, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); 1514 snd_soc_component_write(component, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); 1515 1516 /* Line2 to Mono Out default volume, disconnect from Output Mixer */ 1517 snd_soc_component_write(component, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); 1518 snd_soc_component_write(component, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); 1519 } 1520 1521 /* 1522 * initialise the AIC3X driver 1523 * register the mixer and dsp interfaces with the kernel 1524 */ 1525 static int aic3x_init(struct snd_soc_component *component) 1526 { 1527 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1528 1529 snd_soc_component_write(component, AIC3X_PAGE_SELECT, PAGE0_SELECT); 1530 snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET); 1531 1532 /* DAC default volume and mute */ 1533 snd_soc_component_write(component, LDAC_VOL, DEFAULT_VOL | MUTE_ON); 1534 snd_soc_component_write(component, RDAC_VOL, DEFAULT_VOL | MUTE_ON); 1535 1536 /* DAC to HP default volume and route to Output mixer */ 1537 snd_soc_component_write(component, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); 1538 snd_soc_component_write(component, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); 1539 snd_soc_component_write(component, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1540 snd_soc_component_write(component, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1541 /* DAC to Line Out default volume and route to Output mixer */ 1542 snd_soc_component_write(component, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1543 snd_soc_component_write(component, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1544 1545 /* unmute all outputs */ 1546 snd_soc_component_update_bits(component, LLOPM_CTRL, UNMUTE, UNMUTE); 1547 snd_soc_component_update_bits(component, RLOPM_CTRL, UNMUTE, UNMUTE); 1548 snd_soc_component_update_bits(component, HPLOUT_CTRL, UNMUTE, UNMUTE); 1549 snd_soc_component_update_bits(component, HPROUT_CTRL, UNMUTE, UNMUTE); 1550 snd_soc_component_update_bits(component, HPLCOM_CTRL, UNMUTE, UNMUTE); 1551 snd_soc_component_update_bits(component, HPRCOM_CTRL, UNMUTE, UNMUTE); 1552 1553 /* ADC default volume and unmute */ 1554 snd_soc_component_write(component, LADC_VOL, DEFAULT_GAIN); 1555 snd_soc_component_write(component, RADC_VOL, DEFAULT_GAIN); 1556 /* By default route Line1 to ADC PGA mixer */ 1557 snd_soc_component_write(component, LINE1L_2_LADC_CTRL, 0x0); 1558 snd_soc_component_write(component, LINE1R_2_RADC_CTRL, 0x0); 1559 1560 /* PGA to HP Bypass default volume, disconnect from Output Mixer */ 1561 snd_soc_component_write(component, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); 1562 snd_soc_component_write(component, PGAR_2_HPROUT_VOL, DEFAULT_VOL); 1563 snd_soc_component_write(component, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); 1564 snd_soc_component_write(component, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); 1565 /* PGA to Line Out default volume, disconnect from Output Mixer */ 1566 snd_soc_component_write(component, PGAL_2_LLOPM_VOL, DEFAULT_VOL); 1567 snd_soc_component_write(component, PGAR_2_RLOPM_VOL, DEFAULT_VOL); 1568 1569 /* On tlv320aic3104, these registers are reserved and must not be written */ 1570 if (aic3x->model != AIC3X_MODEL_3104) { 1571 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ 1572 snd_soc_component_write(component, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); 1573 snd_soc_component_write(component, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); 1574 snd_soc_component_write(component, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); 1575 snd_soc_component_write(component, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); 1576 /* Line2 Line Out default volume, disconnect from Output Mixer */ 1577 snd_soc_component_write(component, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); 1578 snd_soc_component_write(component, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); 1579 } 1580 1581 switch (aic3x->model) { 1582 case AIC3X_MODEL_3X: 1583 case AIC3X_MODEL_33: 1584 case AIC3X_MODEL_3106: 1585 aic3x_mono_init(component); 1586 break; 1587 case AIC3X_MODEL_3007: 1588 snd_soc_component_write(component, CLASSD_CTRL, 0); 1589 break; 1590 } 1591 1592 /* Output common-mode voltage = 1.5 V */ 1593 snd_soc_component_update_bits(component, HPOUT_SC, HPOUT_SC_OCMV_MASK, 1594 aic3x->ocmv << HPOUT_SC_OCMV_SHIFT); 1595 1596 return 0; 1597 } 1598 1599 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x) 1600 { 1601 struct aic3x_priv *a; 1602 1603 list_for_each_entry(a, &reset_list, list) { 1604 if (gpio_is_valid(aic3x->gpio_reset) && 1605 aic3x->gpio_reset == a->gpio_reset) 1606 return true; 1607 } 1608 1609 return false; 1610 } 1611 1612 static int aic3x_component_probe(struct snd_soc_component *component) 1613 { 1614 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component); 1615 int ret, i; 1616 1617 aic3x->component = component; 1618 1619 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) { 1620 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; 1621 aic3x->disable_nb[i].aic3x = aic3x; 1622 ret = devm_regulator_register_notifier( 1623 aic3x->supplies[i].consumer, 1624 &aic3x->disable_nb[i].nb); 1625 if (ret) { 1626 dev_err(component->dev, 1627 "Failed to request regulator notifier: %d\n", 1628 ret); 1629 return ret; 1630 } 1631 } 1632 1633 regcache_mark_dirty(aic3x->regmap); 1634 aic3x_init(component); 1635 1636 if (aic3x->setup) { 1637 if (aic3x->model != AIC3X_MODEL_3104) { 1638 /* setup GPIO functions */ 1639 snd_soc_component_write(component, AIC3X_GPIO1_REG, 1640 (aic3x->setup->gpio_func[0] & 0xf) << 4); 1641 snd_soc_component_write(component, AIC3X_GPIO2_REG, 1642 (aic3x->setup->gpio_func[1] & 0xf) << 4); 1643 } else { 1644 dev_warn(component->dev, "GPIO functionality is not supported on tlv320aic3104\n"); 1645 } 1646 } 1647 1648 switch (aic3x->model) { 1649 case AIC3X_MODEL_3X: 1650 case AIC3X_MODEL_33: 1651 case AIC3X_MODEL_3106: 1652 snd_soc_add_component_controls(component, aic3x_extra_snd_controls, 1653 ARRAY_SIZE(aic3x_extra_snd_controls)); 1654 snd_soc_add_component_controls(component, aic3x_mono_controls, 1655 ARRAY_SIZE(aic3x_mono_controls)); 1656 break; 1657 case AIC3X_MODEL_3007: 1658 snd_soc_add_component_controls(component, aic3x_extra_snd_controls, 1659 ARRAY_SIZE(aic3x_extra_snd_controls)); 1660 snd_soc_add_component_controls(component, 1661 &aic3x_classd_amp_gain_ctrl, 1); 1662 break; 1663 case AIC3X_MODEL_3104: 1664 break; 1665 } 1666 1667 /* set mic bias voltage */ 1668 switch (aic3x->micbias_vg) { 1669 case AIC3X_MICBIAS_2_0V: 1670 case AIC3X_MICBIAS_2_5V: 1671 case AIC3X_MICBIAS_AVDDV: 1672 snd_soc_component_update_bits(component, MICBIAS_CTRL, 1673 MICBIAS_LEVEL_MASK, 1674 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT); 1675 break; 1676 case AIC3X_MICBIAS_OFF: 1677 /* 1678 * noting to do. target won't enter here. This is just to avoid 1679 * compile time warning "warning: enumeration value 1680 * 'AIC3X_MICBIAS_OFF' not handled in switch" 1681 */ 1682 break; 1683 } 1684 1685 aic3x_add_widgets(component); 1686 1687 return 0; 1688 } 1689 1690 static const struct snd_soc_component_driver soc_component_dev_aic3x = { 1691 .set_bias_level = aic3x_set_bias_level, 1692 .probe = aic3x_component_probe, 1693 .controls = aic3x_snd_controls, 1694 .num_controls = ARRAY_SIZE(aic3x_snd_controls), 1695 .dapm_widgets = aic3x_dapm_widgets, 1696 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets), 1697 .dapm_routes = intercon, 1698 .num_dapm_routes = ARRAY_SIZE(intercon), 1699 .use_pmdown_time = 1, 1700 .endianness = 1, 1701 .non_legacy_dai_naming = 1, 1702 }; 1703 1704 static void aic3x_configure_ocmv(struct device *dev, struct aic3x_priv *aic3x) 1705 { 1706 struct device_node *np = dev->of_node; 1707 u32 value; 1708 int dvdd, avdd; 1709 1710 if (np && !of_property_read_u32(np, "ai3x-ocmv", &value)) { 1711 /* OCMV setting is forced by DT */ 1712 if (value <= 3) { 1713 aic3x->ocmv = value; 1714 return; 1715 } 1716 } 1717 1718 dvdd = regulator_get_voltage(aic3x->supplies[1].consumer); 1719 avdd = regulator_get_voltage(aic3x->supplies[2].consumer); 1720 1721 if (avdd > 3600000 || dvdd > 1950000) { 1722 dev_warn(dev, 1723 "Too high supply voltage(s) AVDD: %d, DVDD: %d\n", 1724 avdd, dvdd); 1725 } else if (avdd == 3600000 && dvdd == 1950000) { 1726 aic3x->ocmv = HPOUT_SC_OCMV_1_8V; 1727 } else if (avdd > 3300000 && dvdd > 1800000) { 1728 aic3x->ocmv = HPOUT_SC_OCMV_1_65V; 1729 } else if (avdd > 3000000 && dvdd > 1650000) { 1730 aic3x->ocmv = HPOUT_SC_OCMV_1_5V; 1731 } else if (avdd >= 2700000 && dvdd >= 1525000) { 1732 aic3x->ocmv = HPOUT_SC_OCMV_1_35V; 1733 } else { 1734 dev_warn(dev, 1735 "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n", 1736 avdd, dvdd); 1737 } 1738 } 1739 1740 1741 static const struct reg_sequence aic3007_class_d[] = { 1742 /* Class-D speaker driver init; datasheet p. 46 */ 1743 { AIC3X_PAGE_SELECT, 0x0D }, 1744 { 0xD, 0x0D }, 1745 { 0x8, 0x5C }, 1746 { 0x8, 0x5D }, 1747 { 0x8, 0x5C }, 1748 { AIC3X_PAGE_SELECT, 0x00 }, 1749 }; 1750 1751 int aic3x_probe(struct device *dev, struct regmap *regmap, kernel_ulong_t driver_data) 1752 { 1753 struct aic3x_pdata *pdata = dev->platform_data; 1754 struct aic3x_priv *aic3x; 1755 struct aic3x_setup_data *ai3x_setup; 1756 struct device_node *np = dev->of_node; 1757 int ret, i; 1758 u32 value; 1759 1760 aic3x = devm_kzalloc(dev, sizeof(struct aic3x_priv), GFP_KERNEL); 1761 if (!aic3x) 1762 return -ENOMEM; 1763 1764 aic3x->regmap = regmap; 1765 if (IS_ERR(aic3x->regmap)) { 1766 ret = PTR_ERR(aic3x->regmap); 1767 return ret; 1768 } 1769 1770 regcache_cache_only(aic3x->regmap, true); 1771 1772 dev_set_drvdata(dev, aic3x); 1773 if (pdata) { 1774 aic3x->gpio_reset = pdata->gpio_reset; 1775 aic3x->setup = pdata->setup; 1776 aic3x->micbias_vg = pdata->micbias_vg; 1777 } else if (np) { 1778 ai3x_setup = devm_kzalloc(dev, sizeof(*ai3x_setup), GFP_KERNEL); 1779 if (!ai3x_setup) 1780 return -ENOMEM; 1781 1782 ret = of_get_named_gpio(np, "reset-gpios", 0); 1783 if (ret >= 0) { 1784 aic3x->gpio_reset = ret; 1785 } else { 1786 ret = of_get_named_gpio(np, "gpio-reset", 0); 1787 if (ret > 0) { 1788 dev_warn(dev, "Using deprecated property \"gpio-reset\", please update your DT"); 1789 aic3x->gpio_reset = ret; 1790 } else { 1791 aic3x->gpio_reset = -1; 1792 } 1793 } 1794 1795 if (of_property_read_u32_array(np, "ai3x-gpio-func", 1796 ai3x_setup->gpio_func, 2) >= 0) { 1797 aic3x->setup = ai3x_setup; 1798 } 1799 1800 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) { 1801 switch (value) { 1802 case 1 : 1803 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V; 1804 break; 1805 case 2 : 1806 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V; 1807 break; 1808 case 3 : 1809 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV; 1810 break; 1811 default : 1812 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; 1813 dev_err(dev, "Unsuitable MicBias voltage " 1814 "found in DT\n"); 1815 } 1816 } else { 1817 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; 1818 } 1819 1820 } else { 1821 aic3x->gpio_reset = -1; 1822 } 1823 1824 aic3x->model = driver_data; 1825 1826 if (gpio_is_valid(aic3x->gpio_reset) && 1827 !aic3x_is_shared_reset(aic3x)) { 1828 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); 1829 if (ret != 0) 1830 goto err; 1831 gpio_direction_output(aic3x->gpio_reset, 0); 1832 } 1833 1834 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1835 aic3x->supplies[i].supply = aic3x_supply_names[i]; 1836 1837 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(aic3x->supplies), 1838 aic3x->supplies); 1839 if (ret != 0) { 1840 dev_err(dev, "Failed to request supplies: %d\n", ret); 1841 goto err_gpio; 1842 } 1843 1844 aic3x_configure_ocmv(dev, aic3x); 1845 1846 if (aic3x->model == AIC3X_MODEL_3007) { 1847 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d, 1848 ARRAY_SIZE(aic3007_class_d)); 1849 if (ret != 0) 1850 dev_err(dev, "Failed to init class D: %d\n", 1851 ret); 1852 } 1853 1854 ret = devm_snd_soc_register_component(dev, &soc_component_dev_aic3x, &aic3x_dai, 1); 1855 1856 if (ret != 0) 1857 goto err_gpio; 1858 1859 INIT_LIST_HEAD(&aic3x->list); 1860 list_add(&aic3x->list, &reset_list); 1861 1862 return 0; 1863 1864 err_gpio: 1865 if (gpio_is_valid(aic3x->gpio_reset) && 1866 !aic3x_is_shared_reset(aic3x)) 1867 gpio_free(aic3x->gpio_reset); 1868 err: 1869 return ret; 1870 } 1871 EXPORT_SYMBOL(aic3x_probe); 1872 1873 void aic3x_remove(struct device *dev) 1874 { 1875 struct aic3x_priv *aic3x = dev_get_drvdata(dev); 1876 1877 list_del(&aic3x->list); 1878 1879 if (gpio_is_valid(aic3x->gpio_reset) && 1880 !aic3x_is_shared_reset(aic3x)) { 1881 gpio_set_value(aic3x->gpio_reset, 0); 1882 gpio_free(aic3x->gpio_reset); 1883 } 1884 } 1885 EXPORT_SYMBOL(aic3x_remove); 1886 1887 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); 1888 MODULE_AUTHOR("Vladimir Barinov"); 1889 MODULE_LICENSE("GPL"); 1890