1 /* 2 * ALSA SoC TLV320AIC3X codec driver 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Notes: 14 * The AIC3X is a driver for a low power stereo audio 15 * codecs aic31, aic32, aic33, aic3007. 16 * 17 * It supports full aic33 codec functionality. 18 * The compatibility with aic32, aic31 and aic3007 is as follows: 19 * aic32/aic3007 | aic31 20 * --------------------------------------- 21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A 22 * | IN1L -> LINE1L 23 * | IN1R -> LINE1R 24 * | IN2L -> LINE2L 25 * | IN2R -> LINE2R 26 * | MIC3L/R -> N/A 27 * truncated internal functionality in 28 * accordance with documentation 29 * --------------------------------------- 30 * 31 * Hence the machine layer should disable unsupported inputs/outputs by 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/init.h> 38 #include <linux/delay.h> 39 #include <linux/pm.h> 40 #include <linux/i2c.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/platform_device.h> 44 #include <linux/slab.h> 45 #include <sound/core.h> 46 #include <sound/pcm.h> 47 #include <sound/pcm_params.h> 48 #include <sound/soc.h> 49 #include <sound/soc-dapm.h> 50 #include <sound/initval.h> 51 #include <sound/tlv.h> 52 #include <sound/tlv320aic3x.h> 53 54 #include "tlv320aic3x.h" 55 56 #define AIC3X_NUM_SUPPLIES 4 57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { 58 "IOVDD", /* I/O Voltage */ 59 "DVDD", /* Digital Core Voltage */ 60 "AVDD", /* Analog DAC Voltage */ 61 "DRVDD", /* ADC Analog and Output Driver Voltage */ 62 }; 63 64 struct aic3x_priv; 65 66 struct aic3x_disable_nb { 67 struct notifier_block nb; 68 struct aic3x_priv *aic3x; 69 }; 70 71 /* codec private data */ 72 struct aic3x_priv { 73 struct snd_soc_codec *codec; 74 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; 75 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES]; 76 enum snd_soc_control_type control_type; 77 struct aic3x_setup_data *setup; 78 void *control_data; 79 unsigned int sysclk; 80 int master; 81 int gpio_reset; 82 int power; 83 #define AIC3X_MODEL_3X 0 84 #define AIC3X_MODEL_33 1 85 #define AIC3X_MODEL_3007 2 86 u16 model; 87 }; 88 89 /* 90 * AIC3X register cache 91 * We can't read the AIC3X register space when we are 92 * using 2 wire for device control, so we cache them instead. 93 * There is no point in caching the reset register 94 */ 95 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { 96 0x00, 0x00, 0x00, 0x10, /* 0 */ 97 0x04, 0x00, 0x00, 0x00, /* 4 */ 98 0x00, 0x00, 0x00, 0x01, /* 8 */ 99 0x00, 0x00, 0x00, 0x80, /* 12 */ 100 0x80, 0xff, 0xff, 0x78, /* 16 */ 101 0x78, 0x78, 0x78, 0x78, /* 20 */ 102 0x78, 0x00, 0x00, 0xfe, /* 24 */ 103 0x00, 0x00, 0xfe, 0x00, /* 28 */ 104 0x18, 0x18, 0x00, 0x00, /* 32 */ 105 0x00, 0x00, 0x00, 0x00, /* 36 */ 106 0x00, 0x00, 0x00, 0x80, /* 40 */ 107 0x80, 0x00, 0x00, 0x00, /* 44 */ 108 0x00, 0x00, 0x00, 0x04, /* 48 */ 109 0x00, 0x00, 0x00, 0x00, /* 52 */ 110 0x00, 0x00, 0x04, 0x00, /* 56 */ 111 0x00, 0x00, 0x00, 0x00, /* 60 */ 112 0x00, 0x04, 0x00, 0x00, /* 64 */ 113 0x00, 0x00, 0x00, 0x00, /* 68 */ 114 0x04, 0x00, 0x00, 0x00, /* 72 */ 115 0x00, 0x00, 0x00, 0x00, /* 76 */ 116 0x00, 0x00, 0x00, 0x00, /* 80 */ 117 0x00, 0x00, 0x00, 0x00, /* 84 */ 118 0x00, 0x00, 0x00, 0x00, /* 88 */ 119 0x00, 0x00, 0x00, 0x00, /* 92 */ 120 0x00, 0x00, 0x00, 0x00, /* 96 */ 121 0x00, 0x00, 0x02, /* 100 */ 122 }; 123 124 /* 125 * read from the aic3x register space. Only use for this function is if 126 * wanting to read volatile bits from those registers that has both read-only 127 * and read/write bits. All other cases should use snd_soc_read. 128 */ 129 static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg, 130 u8 *value) 131 { 132 u8 *cache = codec->reg_cache; 133 134 if (codec->cache_only) 135 return -EINVAL; 136 if (reg >= AIC3X_CACHEREGNUM) 137 return -1; 138 139 *value = codec->hw_read(codec, reg); 140 cache[reg] = *value; 141 142 return 0; 143 } 144 145 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ 146 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 147 .info = snd_soc_info_volsw, \ 148 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \ 149 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) } 150 151 /* 152 * All input lines are connected when !0xf and disconnected with 0xf bit field, 153 * so we have to use specific dapm_put call for input mixer 154 */ 155 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, 156 struct snd_ctl_elem_value *ucontrol) 157 { 158 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); 159 struct soc_mixer_control *mc = 160 (struct soc_mixer_control *)kcontrol->private_value; 161 unsigned int reg = mc->reg; 162 unsigned int shift = mc->shift; 163 int max = mc->max; 164 unsigned int mask = (1 << fls(max)) - 1; 165 unsigned int invert = mc->invert; 166 unsigned short val, val_mask; 167 int ret; 168 struct snd_soc_dapm_path *path; 169 int found = 0; 170 171 val = (ucontrol->value.integer.value[0] & mask); 172 173 mask = 0xf; 174 if (val) 175 val = mask; 176 177 if (invert) 178 val = mask - val; 179 val_mask = mask << shift; 180 val = val << shift; 181 182 mutex_lock(&widget->codec->mutex); 183 184 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { 185 /* find dapm widget path assoc with kcontrol */ 186 list_for_each_entry(path, &widget->codec->dapm_paths, list) { 187 if (path->kcontrol != kcontrol) 188 continue; 189 190 /* found, now check type */ 191 found = 1; 192 if (val) 193 /* new connection */ 194 path->connect = invert ? 0 : 1; 195 else 196 /* old connection must be powered down */ 197 path->connect = invert ? 1 : 0; 198 break; 199 } 200 201 if (found) 202 snd_soc_dapm_sync(widget->codec); 203 } 204 205 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); 206 207 mutex_unlock(&widget->codec->mutex); 208 return ret; 209 } 210 211 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; 212 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; 213 static const char *aic3x_left_hpcom_mux[] = 214 { "differential of HPLOUT", "constant VCM", "single-ended" }; 215 static const char *aic3x_right_hpcom_mux[] = 216 { "differential of HPROUT", "constant VCM", "single-ended", 217 "differential of HPLCOM", "external feedback" }; 218 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; 219 static const char *aic3x_adc_hpf[] = 220 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; 221 222 #define LDAC_ENUM 0 223 #define RDAC_ENUM 1 224 #define LHPCOM_ENUM 2 225 #define RHPCOM_ENUM 3 226 #define LINE1L_ENUM 4 227 #define LINE1R_ENUM 5 228 #define LINE2L_ENUM 6 229 #define LINE2R_ENUM 7 230 #define ADC_HPF_ENUM 8 231 232 static const struct soc_enum aic3x_enum[] = { 233 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), 234 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), 235 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), 236 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), 237 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 238 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 239 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 240 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 241 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf), 242 }; 243 244 /* 245 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps 246 */ 247 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); 248 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ 249 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); 250 /* 251 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. 252 * Step size is approximately 0.5 dB over most of the scale but increasing 253 * near the very low levels. 254 * Define dB scale so that it is mostly correct for range about -55 to 0 dB 255 * but having increasing dB difference below that (and where it doesn't count 256 * so much). This setting shows -50 dB (actual is -50.3 dB) for register 257 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. 258 */ 259 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); 260 261 static const struct snd_kcontrol_new aic3x_snd_controls[] = { 262 /* Output */ 263 SOC_DOUBLE_R_TLV("PCM Playback Volume", 264 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 265 266 /* 267 * Output controls that map to output mixer switches. Note these are 268 * only for swapped L-to-R and R-to-L routes. See below stereo controls 269 * for direct L-to-L and R-to-R routes. 270 */ 271 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", 272 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 273 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", 274 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 275 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", 276 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 277 278 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", 279 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 280 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", 281 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 282 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", 283 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 284 285 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", 286 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 287 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", 288 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 289 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", 290 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 291 292 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", 293 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 294 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", 295 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 296 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", 297 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 298 299 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", 300 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 301 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", 302 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 303 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", 304 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 305 306 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", 307 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 308 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", 309 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 310 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", 311 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 312 313 /* Stereo output controls for direct L-to-L and R-to-R routes */ 314 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", 315 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, 316 0, 118, 1, output_stage_tlv), 317 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", 318 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, 319 0, 118, 1, output_stage_tlv), 320 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 321 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 322 0, 118, 1, output_stage_tlv), 323 324 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", 325 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 326 0, 118, 1, output_stage_tlv), 327 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", 328 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 329 0, 118, 1, output_stage_tlv), 330 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 331 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 332 0, 118, 1, output_stage_tlv), 333 334 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", 335 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 336 0, 118, 1, output_stage_tlv), 337 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", 338 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 339 0, 118, 1, output_stage_tlv), 340 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 341 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 342 0, 118, 1, output_stage_tlv), 343 344 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", 345 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 346 0, 118, 1, output_stage_tlv), 347 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", 348 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, 349 0, 118, 1, output_stage_tlv), 350 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 351 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 352 0, 118, 1, output_stage_tlv), 353 354 /* Output pin mute controls */ 355 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, 356 0x01, 0), 357 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 358 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 359 0x01, 0), 360 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 361 0x01, 0), 362 363 /* 364 * Note: enable Automatic input Gain Controller with care. It can 365 * adjust PGA to max value when ADC is on and will never go back. 366 */ 367 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), 368 369 /* Input */ 370 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 371 0, 119, 0, adc_tlv), 372 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), 373 374 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]), 375 }; 376 377 /* 378 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps 379 */ 380 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0); 381 382 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl = 383 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv); 384 385 /* Left DAC Mux */ 386 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = 387 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); 388 389 /* Right DAC Mux */ 390 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = 391 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); 392 393 /* Left HPCOM Mux */ 394 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = 395 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); 396 397 /* Right HPCOM Mux */ 398 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = 399 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); 400 401 /* Left Line Mixer */ 402 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { 403 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), 404 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), 405 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), 406 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), 407 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), 408 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), 409 }; 410 411 /* Right Line Mixer */ 412 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { 413 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), 414 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), 415 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), 416 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), 417 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), 418 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), 419 }; 420 421 /* Mono Mixer */ 422 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { 423 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), 424 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), 425 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), 426 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), 427 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), 428 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), 429 }; 430 431 /* Left HP Mixer */ 432 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { 433 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), 434 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), 435 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), 436 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), 437 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), 438 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), 439 }; 440 441 /* Right HP Mixer */ 442 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { 443 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), 444 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), 445 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), 446 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), 447 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), 448 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), 449 }; 450 451 /* Left HPCOM Mixer */ 452 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { 453 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), 454 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), 455 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), 456 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), 457 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), 458 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), 459 }; 460 461 /* Right HPCOM Mixer */ 462 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { 463 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), 464 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), 465 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), 466 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), 467 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), 468 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), 469 }; 470 471 /* Left PGA Mixer */ 472 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { 473 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 474 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 475 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), 476 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 477 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 478 }; 479 480 /* Right PGA Mixer */ 481 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { 482 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 483 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 484 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), 485 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 486 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 487 }; 488 489 /* Left Line1 Mux */ 490 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls = 491 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]); 492 493 /* Right Line1 Mux */ 494 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls = 495 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]); 496 497 /* Left Line2 Mux */ 498 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = 499 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); 500 501 /* Right Line2 Mux */ 502 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = 503 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); 504 505 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { 506 /* Left DAC to Left Outputs */ 507 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), 508 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, 509 &aic3x_left_dac_mux_controls), 510 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, 511 &aic3x_left_hpcom_mux_controls), 512 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), 513 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), 514 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), 515 516 /* Right DAC to Right Outputs */ 517 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), 518 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, 519 &aic3x_right_dac_mux_controls), 520 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, 521 &aic3x_right_hpcom_mux_controls), 522 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), 523 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), 524 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), 525 526 /* Mono Output */ 527 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), 528 529 /* Inputs to Left ADC */ 530 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), 531 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 532 &aic3x_left_pga_mixer_controls[0], 533 ARRAY_SIZE(aic3x_left_pga_mixer_controls)), 534 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, 535 &aic3x_left_line1_mux_controls), 536 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, 537 &aic3x_left_line1_mux_controls), 538 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, 539 &aic3x_left_line2_mux_controls), 540 541 /* Inputs to Right ADC */ 542 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 543 LINE1R_2_RADC_CTRL, 2, 0), 544 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 545 &aic3x_right_pga_mixer_controls[0], 546 ARRAY_SIZE(aic3x_right_pga_mixer_controls)), 547 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, 548 &aic3x_right_line1_mux_controls), 549 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, 550 &aic3x_right_line1_mux_controls), 551 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, 552 &aic3x_right_line2_mux_controls), 553 554 /* 555 * Not a real mic bias widget but similar function. This is for dynamic 556 * control of GPIO1 digital mic modulator clock output function when 557 * using digital mic. 558 */ 559 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", 560 AIC3X_GPIO1_REG, 4, 0xf, 561 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, 562 AIC3X_GPIO1_FUNC_DISABLED), 563 564 /* 565 * Also similar function like mic bias. Selects digital mic with 566 * configurable oversampling rate instead of ADC converter. 567 */ 568 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", 569 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), 570 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", 571 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), 572 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", 573 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 574 575 /* Mic Bias */ 576 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V", 577 MICBIAS_CTRL, 6, 3, 1, 0), 578 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V", 579 MICBIAS_CTRL, 6, 3, 2, 0), 580 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD", 581 MICBIAS_CTRL, 6, 3, 3, 0), 582 583 /* Output mixers */ 584 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 585 &aic3x_left_line_mixer_controls[0], 586 ARRAY_SIZE(aic3x_left_line_mixer_controls)), 587 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 588 &aic3x_right_line_mixer_controls[0], 589 ARRAY_SIZE(aic3x_right_line_mixer_controls)), 590 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, 591 &aic3x_mono_mixer_controls[0], 592 ARRAY_SIZE(aic3x_mono_mixer_controls)), 593 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 594 &aic3x_left_hp_mixer_controls[0], 595 ARRAY_SIZE(aic3x_left_hp_mixer_controls)), 596 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 597 &aic3x_right_hp_mixer_controls[0], 598 ARRAY_SIZE(aic3x_right_hp_mixer_controls)), 599 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 600 &aic3x_left_hpcom_mixer_controls[0], 601 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), 602 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 603 &aic3x_right_hpcom_mixer_controls[0], 604 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), 605 606 SND_SOC_DAPM_OUTPUT("LLOUT"), 607 SND_SOC_DAPM_OUTPUT("RLOUT"), 608 SND_SOC_DAPM_OUTPUT("MONO_LOUT"), 609 SND_SOC_DAPM_OUTPUT("HPLOUT"), 610 SND_SOC_DAPM_OUTPUT("HPROUT"), 611 SND_SOC_DAPM_OUTPUT("HPLCOM"), 612 SND_SOC_DAPM_OUTPUT("HPRCOM"), 613 614 SND_SOC_DAPM_INPUT("MIC3L"), 615 SND_SOC_DAPM_INPUT("MIC3R"), 616 SND_SOC_DAPM_INPUT("LINE1L"), 617 SND_SOC_DAPM_INPUT("LINE1R"), 618 SND_SOC_DAPM_INPUT("LINE2L"), 619 SND_SOC_DAPM_INPUT("LINE2R"), 620 621 /* 622 * Virtual output pin to detection block inside codec. This can be 623 * used to keep codec bias on if gpio or detection features are needed. 624 * Force pin on or construct a path with an input jack and mic bias 625 * widgets. 626 */ 627 SND_SOC_DAPM_OUTPUT("Detection"), 628 }; 629 630 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { 631 /* Class-D outputs */ 632 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0), 633 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0), 634 635 SND_SOC_DAPM_OUTPUT("SPOP"), 636 SND_SOC_DAPM_OUTPUT("SPOM"), 637 }; 638 639 static const struct snd_soc_dapm_route intercon[] = { 640 /* Left Input */ 641 {"Left Line1L Mux", "single-ended", "LINE1L"}, 642 {"Left Line1L Mux", "differential", "LINE1L"}, 643 644 {"Left Line2L Mux", "single-ended", "LINE2L"}, 645 {"Left Line2L Mux", "differential", "LINE2L"}, 646 647 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, 648 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, 649 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, 650 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, 651 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, 652 653 {"Left ADC", NULL, "Left PGA Mixer"}, 654 {"Left ADC", NULL, "GPIO1 dmic modclk"}, 655 656 /* Right Input */ 657 {"Right Line1R Mux", "single-ended", "LINE1R"}, 658 {"Right Line1R Mux", "differential", "LINE1R"}, 659 660 {"Right Line2R Mux", "single-ended", "LINE2R"}, 661 {"Right Line2R Mux", "differential", "LINE2R"}, 662 663 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, 664 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, 665 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, 666 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, 667 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, 668 669 {"Right ADC", NULL, "Right PGA Mixer"}, 670 {"Right ADC", NULL, "GPIO1 dmic modclk"}, 671 672 /* 673 * Logical path between digital mic enable and GPIO1 modulator clock 674 * output function 675 */ 676 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, 677 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, 678 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, 679 680 /* Left DAC Output */ 681 {"Left DAC Mux", "DAC_L1", "Left DAC"}, 682 {"Left DAC Mux", "DAC_L2", "Left DAC"}, 683 {"Left DAC Mux", "DAC_L3", "Left DAC"}, 684 685 /* Right DAC Output */ 686 {"Right DAC Mux", "DAC_R1", "Right DAC"}, 687 {"Right DAC Mux", "DAC_R2", "Right DAC"}, 688 {"Right DAC Mux", "DAC_R3", "Right DAC"}, 689 690 /* Left Line Output */ 691 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 692 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 693 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 694 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 695 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 696 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 697 698 {"Left Line Out", NULL, "Left Line Mixer"}, 699 {"Left Line Out", NULL, "Left DAC Mux"}, 700 {"LLOUT", NULL, "Left Line Out"}, 701 702 /* Right Line Output */ 703 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 704 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 705 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 706 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 707 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 708 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 709 710 {"Right Line Out", NULL, "Right Line Mixer"}, 711 {"Right Line Out", NULL, "Right DAC Mux"}, 712 {"RLOUT", NULL, "Right Line Out"}, 713 714 /* Mono Output */ 715 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 716 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 717 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, 718 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 719 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 720 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, 721 722 {"Mono Out", NULL, "Mono Mixer"}, 723 {"MONO_LOUT", NULL, "Mono Out"}, 724 725 /* Left HP Output */ 726 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 727 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 728 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 729 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 730 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 731 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 732 733 {"Left HP Out", NULL, "Left HP Mixer"}, 734 {"Left HP Out", NULL, "Left DAC Mux"}, 735 {"HPLOUT", NULL, "Left HP Out"}, 736 737 /* Right HP Output */ 738 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 739 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 740 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 741 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 742 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 743 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 744 745 {"Right HP Out", NULL, "Right HP Mixer"}, 746 {"Right HP Out", NULL, "Right DAC Mux"}, 747 {"HPROUT", NULL, "Right HP Out"}, 748 749 /* Left HPCOM Output */ 750 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 751 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 752 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 753 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 754 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 755 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 756 757 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, 758 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, 759 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, 760 {"Left HP Com", NULL, "Left HPCOM Mux"}, 761 {"HPLCOM", NULL, "Left HP Com"}, 762 763 /* Right HPCOM Output */ 764 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 765 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 766 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 767 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 768 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 769 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 770 771 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, 772 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, 773 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, 774 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, 775 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, 776 {"Right HP Com", NULL, "Right HPCOM Mux"}, 777 {"HPRCOM", NULL, "Right HP Com"}, 778 }; 779 780 static const struct snd_soc_dapm_route intercon_3007[] = { 781 /* Class-D outputs */ 782 {"Left Class-D Out", NULL, "Left Line Out"}, 783 {"Right Class-D Out", NULL, "Left Line Out"}, 784 {"SPOP", NULL, "Left Class-D Out"}, 785 {"SPOM", NULL, "Right Class-D Out"}, 786 }; 787 788 static int aic3x_add_widgets(struct snd_soc_codec *codec) 789 { 790 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 791 792 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets, 793 ARRAY_SIZE(aic3x_dapm_widgets)); 794 795 /* set up audio path interconnects */ 796 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); 797 798 if (aic3x->model == AIC3X_MODEL_3007) { 799 snd_soc_dapm_new_controls(codec, aic3007_dapm_widgets, 800 ARRAY_SIZE(aic3007_dapm_widgets)); 801 snd_soc_dapm_add_routes(codec, intercon_3007, ARRAY_SIZE(intercon_3007)); 802 } 803 804 return 0; 805 } 806 807 static int aic3x_hw_params(struct snd_pcm_substream *substream, 808 struct snd_pcm_hw_params *params, 809 struct snd_soc_dai *dai) 810 { 811 struct snd_soc_pcm_runtime *rtd = substream->private_data; 812 struct snd_soc_codec *codec =rtd->codec; 813 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 814 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 815 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 816 u16 d, pll_d = 1; 817 u8 reg; 818 int clk; 819 820 /* select data word length */ 821 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); 822 switch (params_format(params)) { 823 case SNDRV_PCM_FORMAT_S16_LE: 824 break; 825 case SNDRV_PCM_FORMAT_S20_3LE: 826 data |= (0x01 << 4); 827 break; 828 case SNDRV_PCM_FORMAT_S24_LE: 829 data |= (0x02 << 4); 830 break; 831 case SNDRV_PCM_FORMAT_S32_LE: 832 data |= (0x03 << 4); 833 break; 834 } 835 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data); 836 837 /* Fsref can be 44100 or 48000 */ 838 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; 839 840 /* Try to find a value for Q which allows us to bypass the PLL and 841 * generate CODEC_CLK directly. */ 842 for (pll_q = 2; pll_q < 18; pll_q++) 843 if (aic3x->sysclk / (128 * pll_q) == fsref) { 844 bypass_pll = 1; 845 break; 846 } 847 848 if (bypass_pll) { 849 pll_q &= 0xf; 850 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 851 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 852 /* disable PLL if it is bypassed */ 853 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); 854 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE); 855 856 } else { 857 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 858 /* enable PLL when it is used */ 859 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); 860 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE); 861 } 862 863 /* Route Left DAC to left channel input and 864 * right DAC to right channel input */ 865 data = (LDAC2LCH | RDAC2RCH); 866 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; 867 if (params_rate(params) >= 64000) 868 data |= DUAL_RATE_MODE; 869 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data); 870 871 /* codec sample rate select */ 872 data = (fsref * 20) / params_rate(params); 873 if (params_rate(params) < 64000) 874 data /= 2; 875 data /= 5; 876 data -= 2; 877 data |= (data << 4); 878 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); 879 880 if (bypass_pll) 881 return 0; 882 883 /* Use PLL, compute apropriate setup for j, d, r and p, the closest 884 * one wins the game. Try with d==0 first, next with d!=0. 885 * Constraints for j are according to the datasheet. 886 * The sysclk is divided by 1000 to prevent integer overflows. 887 */ 888 889 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); 890 891 for (r = 1; r <= 16; r++) 892 for (p = 1; p <= 8; p++) { 893 for (j = 4; j <= 55; j++) { 894 /* This is actually 1000*((j+(d/10000))*r)/p 895 * The term had to be converted to get 896 * rid of the division by 10000; d = 0 here 897 */ 898 int tmp_clk = (1000 * j * r) / p; 899 900 /* Check whether this values get closer than 901 * the best ones we had before 902 */ 903 if (abs(codec_clk - tmp_clk) < 904 abs(codec_clk - last_clk)) { 905 pll_j = j; pll_d = 0; 906 pll_r = r; pll_p = p; 907 last_clk = tmp_clk; 908 } 909 910 /* Early exit for exact matches */ 911 if (tmp_clk == codec_clk) 912 goto found; 913 } 914 } 915 916 /* try with d != 0 */ 917 for (p = 1; p <= 8; p++) { 918 j = codec_clk * p / 1000; 919 920 if (j < 4 || j > 11) 921 continue; 922 923 /* do not use codec_clk here since we'd loose precision */ 924 d = ((2048 * p * fsref) - j * aic3x->sysclk) 925 * 100 / (aic3x->sysclk/100); 926 927 clk = (10000 * j + d) / (10 * p); 928 929 /* check whether this values get closer than the best 930 * ones we had before */ 931 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { 932 pll_j = j; pll_d = d; pll_r = 1; pll_p = p; 933 last_clk = clk; 934 } 935 936 /* Early exit for exact matches */ 937 if (clk == codec_clk) 938 goto found; 939 } 940 941 if (last_clk == 0) { 942 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); 943 return -EINVAL; 944 } 945 946 found: 947 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); 948 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, 949 data | (pll_p << PLLP_SHIFT)); 950 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, 951 pll_r << PLLR_SHIFT); 952 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); 953 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, 954 (pll_d >> 6) << PLLD_MSB_SHIFT); 955 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, 956 (pll_d & 0x3F) << PLLD_LSB_SHIFT); 957 958 return 0; 959 } 960 961 static int aic3x_mute(struct snd_soc_dai *dai, int mute) 962 { 963 struct snd_soc_codec *codec = dai->codec; 964 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON; 965 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON; 966 967 if (mute) { 968 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); 969 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); 970 } else { 971 snd_soc_write(codec, LDAC_VOL, ldac_reg); 972 snd_soc_write(codec, RDAC_VOL, rdac_reg); 973 } 974 975 return 0; 976 } 977 978 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 979 int clk_id, unsigned int freq, int dir) 980 { 981 struct snd_soc_codec *codec = codec_dai->codec; 982 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 983 984 aic3x->sysclk = freq; 985 return 0; 986 } 987 988 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, 989 unsigned int fmt) 990 { 991 struct snd_soc_codec *codec = codec_dai->codec; 992 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 993 u8 iface_areg, iface_breg; 994 int delay = 0; 995 996 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; 997 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; 998 999 /* set master/slave audio interface */ 1000 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1001 case SND_SOC_DAIFMT_CBM_CFM: 1002 aic3x->master = 1; 1003 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; 1004 break; 1005 case SND_SOC_DAIFMT_CBS_CFS: 1006 aic3x->master = 0; 1007 break; 1008 default: 1009 return -EINVAL; 1010 } 1011 1012 /* 1013 * match both interface format and signal polarities since they 1014 * are fixed 1015 */ 1016 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | 1017 SND_SOC_DAIFMT_INV_MASK)) { 1018 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): 1019 break; 1020 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): 1021 delay = 1; 1022 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): 1023 iface_breg |= (0x01 << 6); 1024 break; 1025 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): 1026 iface_breg |= (0x02 << 6); 1027 break; 1028 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): 1029 iface_breg |= (0x03 << 6); 1030 break; 1031 default: 1032 return -EINVAL; 1033 } 1034 1035 /* set iface */ 1036 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); 1037 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); 1038 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay); 1039 1040 return 0; 1041 } 1042 1043 static int aic3x_init_3007(struct snd_soc_codec *codec) 1044 { 1045 u8 tmp1, tmp2, *cache = codec->reg_cache; 1046 1047 /* 1048 * There is no need to cache writes to undocumented page 0xD but 1049 * respective page 0 register cache entries must be preserved 1050 */ 1051 tmp1 = cache[0xD]; 1052 tmp2 = cache[0x8]; 1053 /* Class-D speaker driver init; datasheet p. 46 */ 1054 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D); 1055 snd_soc_write(codec, 0xD, 0x0D); 1056 snd_soc_write(codec, 0x8, 0x5C); 1057 snd_soc_write(codec, 0x8, 0x5D); 1058 snd_soc_write(codec, 0x8, 0x5C); 1059 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00); 1060 cache[0xD] = tmp1; 1061 cache[0x8] = tmp2; 1062 1063 return 0; 1064 } 1065 1066 static int aic3x_regulator_event(struct notifier_block *nb, 1067 unsigned long event, void *data) 1068 { 1069 struct aic3x_disable_nb *disable_nb = 1070 container_of(nb, struct aic3x_disable_nb, nb); 1071 struct aic3x_priv *aic3x = disable_nb->aic3x; 1072 1073 if (event & REGULATOR_EVENT_DISABLE) { 1074 /* 1075 * Put codec to reset and require cache sync as at least one 1076 * of the supplies was disabled 1077 */ 1078 if (aic3x->gpio_reset >= 0) 1079 gpio_set_value(aic3x->gpio_reset, 0); 1080 aic3x->codec->cache_sync = 1; 1081 } 1082 1083 return 0; 1084 } 1085 1086 static int aic3x_set_power(struct snd_soc_codec *codec, int power) 1087 { 1088 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1089 int i, ret; 1090 u8 *cache = codec->reg_cache; 1091 1092 if (power) { 1093 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), 1094 aic3x->supplies); 1095 if (ret) 1096 goto out; 1097 aic3x->power = 1; 1098 /* 1099 * Reset release and cache sync is necessary only if some 1100 * supply was off or if there were cached writes 1101 */ 1102 if (!codec->cache_sync) 1103 goto out; 1104 1105 if (aic3x->gpio_reset >= 0) { 1106 udelay(1); 1107 gpio_set_value(aic3x->gpio_reset, 1); 1108 } 1109 1110 /* Sync reg_cache with the hardware */ 1111 codec->cache_only = 0; 1112 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) 1113 snd_soc_write(codec, i, cache[i]); 1114 if (aic3x->model == AIC3X_MODEL_3007) 1115 aic3x_init_3007(codec); 1116 codec->cache_sync = 0; 1117 } else { 1118 aic3x->power = 0; 1119 /* HW writes are needless when bias is off */ 1120 codec->cache_only = 1; 1121 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), 1122 aic3x->supplies); 1123 } 1124 out: 1125 return ret; 1126 } 1127 1128 static int aic3x_set_bias_level(struct snd_soc_codec *codec, 1129 enum snd_soc_bias_level level) 1130 { 1131 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1132 u8 reg; 1133 1134 switch (level) { 1135 case SND_SOC_BIAS_ON: 1136 break; 1137 case SND_SOC_BIAS_PREPARE: 1138 if (codec->bias_level == SND_SOC_BIAS_STANDBY && 1139 aic3x->master) { 1140 /* enable pll */ 1141 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); 1142 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, 1143 reg | PLL_ENABLE); 1144 } 1145 break; 1146 case SND_SOC_BIAS_STANDBY: 1147 if (!aic3x->power) 1148 aic3x_set_power(codec, 1); 1149 if (codec->bias_level == SND_SOC_BIAS_PREPARE && 1150 aic3x->master) { 1151 /* disable pll */ 1152 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); 1153 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, 1154 reg & ~PLL_ENABLE); 1155 } 1156 break; 1157 case SND_SOC_BIAS_OFF: 1158 if (aic3x->power) 1159 aic3x_set_power(codec, 0); 1160 break; 1161 } 1162 codec->bias_level = level; 1163 1164 return 0; 1165 } 1166 1167 void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state) 1168 { 1169 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; 1170 u8 bit = gpio ? 3: 0; 1171 u8 val = snd_soc_read(codec, reg) & ~(1 << bit); 1172 snd_soc_write(codec, reg, val | (!!state << bit)); 1173 } 1174 EXPORT_SYMBOL_GPL(aic3x_set_gpio); 1175 1176 int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio) 1177 { 1178 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; 1179 u8 val = 0, bit = gpio ? 2 : 1; 1180 1181 aic3x_read(codec, reg, &val); 1182 return (val >> bit) & 1; 1183 } 1184 EXPORT_SYMBOL_GPL(aic3x_get_gpio); 1185 1186 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect, 1187 int headset_debounce, int button_debounce) 1188 { 1189 u8 val; 1190 1191 val = ((detect & AIC3X_HEADSET_DETECT_MASK) 1192 << AIC3X_HEADSET_DETECT_SHIFT) | 1193 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK) 1194 << AIC3X_HEADSET_DEBOUNCE_SHIFT) | 1195 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK) 1196 << AIC3X_BUTTON_DEBOUNCE_SHIFT); 1197 1198 if (detect & AIC3X_HEADSET_DETECT_MASK) 1199 val |= AIC3X_HEADSET_DETECT_ENABLED; 1200 1201 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val); 1202 } 1203 EXPORT_SYMBOL_GPL(aic3x_set_headset_detection); 1204 1205 int aic3x_headset_detected(struct snd_soc_codec *codec) 1206 { 1207 u8 val = 0; 1208 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); 1209 return (val >> 4) & 1; 1210 } 1211 EXPORT_SYMBOL_GPL(aic3x_headset_detected); 1212 1213 int aic3x_button_pressed(struct snd_soc_codec *codec) 1214 { 1215 u8 val = 0; 1216 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); 1217 return (val >> 5) & 1; 1218 } 1219 EXPORT_SYMBOL_GPL(aic3x_button_pressed); 1220 1221 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1222 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1223 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1224 1225 static struct snd_soc_dai_ops aic3x_dai_ops = { 1226 .hw_params = aic3x_hw_params, 1227 .digital_mute = aic3x_mute, 1228 .set_sysclk = aic3x_set_dai_sysclk, 1229 .set_fmt = aic3x_set_dai_fmt, 1230 }; 1231 1232 static struct snd_soc_dai_driver aic3x_dai = { 1233 .name = "tlv320aic3x-hifi", 1234 .playback = { 1235 .stream_name = "Playback", 1236 .channels_min = 1, 1237 .channels_max = 2, 1238 .rates = AIC3X_RATES, 1239 .formats = AIC3X_FORMATS,}, 1240 .capture = { 1241 .stream_name = "Capture", 1242 .channels_min = 1, 1243 .channels_max = 2, 1244 .rates = AIC3X_RATES, 1245 .formats = AIC3X_FORMATS,}, 1246 .ops = &aic3x_dai_ops, 1247 .symmetric_rates = 1, 1248 }; 1249 1250 static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state) 1251 { 1252 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1253 1254 return 0; 1255 } 1256 1257 static int aic3x_resume(struct snd_soc_codec *codec) 1258 { 1259 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1260 1261 return 0; 1262 } 1263 1264 /* 1265 * initialise the AIC3X driver 1266 * register the mixer and dsp interfaces with the kernel 1267 */ 1268 static int aic3x_init(struct snd_soc_codec *codec) 1269 { 1270 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1271 int reg; 1272 1273 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); 1274 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1275 1276 /* DAC default volume and mute */ 1277 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); 1278 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); 1279 1280 /* DAC to HP default volume and route to Output mixer */ 1281 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); 1282 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); 1283 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1284 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1285 /* DAC to Line Out default volume and route to Output mixer */ 1286 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1287 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1288 /* DAC to Mono Line Out default volume and route to Output mixer */ 1289 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1290 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1291 1292 /* unmute all outputs */ 1293 reg = snd_soc_read(codec, LLOPM_CTRL); 1294 snd_soc_write(codec, LLOPM_CTRL, reg | UNMUTE); 1295 reg = snd_soc_read(codec, RLOPM_CTRL); 1296 snd_soc_write(codec, RLOPM_CTRL, reg | UNMUTE); 1297 reg = snd_soc_read(codec, MONOLOPM_CTRL); 1298 snd_soc_write(codec, MONOLOPM_CTRL, reg | UNMUTE); 1299 reg = snd_soc_read(codec, HPLOUT_CTRL); 1300 snd_soc_write(codec, HPLOUT_CTRL, reg | UNMUTE); 1301 reg = snd_soc_read(codec, HPROUT_CTRL); 1302 snd_soc_write(codec, HPROUT_CTRL, reg | UNMUTE); 1303 reg = snd_soc_read(codec, HPLCOM_CTRL); 1304 snd_soc_write(codec, HPLCOM_CTRL, reg | UNMUTE); 1305 reg = snd_soc_read(codec, HPRCOM_CTRL); 1306 snd_soc_write(codec, HPRCOM_CTRL, reg | UNMUTE); 1307 1308 /* ADC default volume and unmute */ 1309 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN); 1310 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN); 1311 /* By default route Line1 to ADC PGA mixer */ 1312 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0); 1313 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0); 1314 1315 /* PGA to HP Bypass default volume, disconnect from Output Mixer */ 1316 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); 1317 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); 1318 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); 1319 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); 1320 /* PGA to Line Out default volume, disconnect from Output Mixer */ 1321 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); 1322 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); 1323 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ 1324 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); 1325 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); 1326 1327 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ 1328 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); 1329 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); 1330 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); 1331 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); 1332 /* Line2 Line Out default volume, disconnect from Output Mixer */ 1333 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); 1334 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); 1335 /* Line2 to Mono Out default volume, disconnect from Output Mixer */ 1336 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); 1337 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); 1338 1339 if (aic3x->model == AIC3X_MODEL_3007) { 1340 aic3x_init_3007(codec); 1341 snd_soc_write(codec, CLASSD_CTRL, 0); 1342 } 1343 1344 return 0; 1345 } 1346 1347 static int aic3x_probe(struct snd_soc_codec *codec) 1348 { 1349 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1350 int ret, i; 1351 1352 codec->control_data = aic3x->control_data; 1353 aic3x->codec = codec; 1354 codec->idle_bias_off = 1; 1355 1356 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type); 1357 if (ret != 0) { 1358 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1359 return ret; 1360 } 1361 1362 if (aic3x->gpio_reset >= 0) { 1363 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); 1364 if (ret != 0) 1365 goto err_gpio; 1366 gpio_direction_output(aic3x->gpio_reset, 0); 1367 } 1368 1369 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1370 aic3x->supplies[i].supply = aic3x_supply_names[i]; 1371 1372 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies), 1373 aic3x->supplies); 1374 if (ret != 0) { 1375 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 1376 goto err_get; 1377 } 1378 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) { 1379 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; 1380 aic3x->disable_nb[i].aic3x = aic3x; 1381 ret = regulator_register_notifier(aic3x->supplies[i].consumer, 1382 &aic3x->disable_nb[i].nb); 1383 if (ret) { 1384 dev_err(codec->dev, 1385 "Failed to request regulator notifier: %d\n", 1386 ret); 1387 goto err_notif; 1388 } 1389 } 1390 1391 codec->cache_only = 1; 1392 aic3x_init(codec); 1393 1394 if (aic3x->setup) { 1395 /* setup GPIO functions */ 1396 snd_soc_write(codec, AIC3X_GPIO1_REG, 1397 (aic3x->setup->gpio_func[0] & 0xf) << 4); 1398 snd_soc_write(codec, AIC3X_GPIO2_REG, 1399 (aic3x->setup->gpio_func[1] & 0xf) << 4); 1400 } 1401 1402 snd_soc_add_controls(codec, aic3x_snd_controls, 1403 ARRAY_SIZE(aic3x_snd_controls)); 1404 if (aic3x->model == AIC3X_MODEL_3007) 1405 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1); 1406 1407 aic3x_add_widgets(codec); 1408 1409 return 0; 1410 1411 err_notif: 1412 while (i--) 1413 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1414 &aic3x->disable_nb[i].nb); 1415 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1416 err_get: 1417 if (aic3x->gpio_reset >= 0) 1418 gpio_free(aic3x->gpio_reset); 1419 err_gpio: 1420 kfree(aic3x); 1421 return ret; 1422 } 1423 1424 static int aic3x_remove(struct snd_soc_codec *codec) 1425 { 1426 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1427 int i; 1428 1429 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1430 if (aic3x->gpio_reset >= 0) { 1431 gpio_set_value(aic3x->gpio_reset, 0); 1432 gpio_free(aic3x->gpio_reset); 1433 } 1434 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1435 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1436 &aic3x->disable_nb[i].nb); 1437 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1438 1439 return 0; 1440 } 1441 1442 static struct snd_soc_codec_driver soc_codec_dev_aic3x = { 1443 .set_bias_level = aic3x_set_bias_level, 1444 .reg_cache_size = ARRAY_SIZE(aic3x_reg), 1445 .reg_word_size = sizeof(u8), 1446 .reg_cache_default = aic3x_reg, 1447 .probe = aic3x_probe, 1448 .remove = aic3x_remove, 1449 .suspend = aic3x_suspend, 1450 .resume = aic3x_resume, 1451 }; 1452 1453 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1454 /* 1455 * AIC3X 2 wire address can be up to 4 devices with device addresses 1456 * 0x18, 0x19, 0x1A, 0x1B 1457 */ 1458 1459 static const struct i2c_device_id aic3x_i2c_id[] = { 1460 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 }, 1461 [AIC3X_MODEL_33] = { "tlv320aic33", 0 }, 1462 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 }, 1463 { } 1464 }; 1465 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); 1466 1467 /* 1468 * If the i2c layer weren't so broken, we could pass this kind of data 1469 * around 1470 */ 1471 static int aic3x_i2c_probe(struct i2c_client *i2c, 1472 const struct i2c_device_id *id) 1473 { 1474 struct aic3x_pdata *pdata = i2c->dev.platform_data; 1475 struct aic3x_priv *aic3x; 1476 int ret; 1477 const struct i2c_device_id *tbl; 1478 1479 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL); 1480 if (aic3x == NULL) { 1481 dev_err(&i2c->dev, "failed to create private data\n"); 1482 return -ENOMEM; 1483 } 1484 1485 aic3x->control_data = i2c; 1486 aic3x->control_type = SND_SOC_I2C; 1487 1488 i2c_set_clientdata(i2c, aic3x); 1489 if (pdata) { 1490 aic3x->gpio_reset = pdata->gpio_reset; 1491 aic3x->setup = pdata->setup; 1492 } else { 1493 aic3x->gpio_reset = -1; 1494 } 1495 1496 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) { 1497 if (!strcmp(tbl->name, id->name)) 1498 break; 1499 } 1500 aic3x->model = tbl - aic3x_i2c_id; 1501 1502 ret = snd_soc_register_codec(&i2c->dev, 1503 &soc_codec_dev_aic3x, &aic3x_dai, 1); 1504 if (ret < 0) 1505 kfree(aic3x); 1506 return ret; 1507 } 1508 1509 static int aic3x_i2c_remove(struct i2c_client *client) 1510 { 1511 snd_soc_unregister_codec(&client->dev); 1512 kfree(i2c_get_clientdata(client)); 1513 return 0; 1514 } 1515 1516 /* machine i2c codec control layer */ 1517 static struct i2c_driver aic3x_i2c_driver = { 1518 .driver = { 1519 .name = "tlv320aic3x-codec", 1520 .owner = THIS_MODULE, 1521 }, 1522 .probe = aic3x_i2c_probe, 1523 .remove = aic3x_i2c_remove, 1524 .id_table = aic3x_i2c_id, 1525 }; 1526 1527 static inline void aic3x_i2c_init(void) 1528 { 1529 int ret; 1530 1531 ret = i2c_add_driver(&aic3x_i2c_driver); 1532 if (ret) 1533 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n", 1534 __func__, ret); 1535 } 1536 1537 static inline void aic3x_i2c_exit(void) 1538 { 1539 i2c_del_driver(&aic3x_i2c_driver); 1540 } 1541 #endif 1542 1543 static int __init aic3x_modinit(void) 1544 { 1545 int ret = 0; 1546 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1547 ret = i2c_add_driver(&aic3x_i2c_driver); 1548 if (ret != 0) { 1549 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n", 1550 ret); 1551 } 1552 #endif 1553 return ret; 1554 } 1555 module_init(aic3x_modinit); 1556 1557 static void __exit aic3x_exit(void) 1558 { 1559 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 1560 i2c_del_driver(&aic3x_i2c_driver); 1561 #endif 1562 } 1563 module_exit(aic3x_exit); 1564 1565 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); 1566 MODULE_AUTHOR("Vladimir Barinov"); 1567 MODULE_LICENSE("GPL"); 1568