1 /* 2 * ALSA SoC TLV320AIC3X codec driver 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Notes: 14 * The AIC3X is a driver for a low power stereo audio 15 * codecs aic31, aic32, aic33, aic3007. 16 * 17 * It supports full aic33 codec functionality. 18 * The compatibility with aic32, aic31 and aic3007 is as follows: 19 * aic32/aic3007 | aic31 20 * --------------------------------------- 21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A 22 * | IN1L -> LINE1L 23 * | IN1R -> LINE1R 24 * | IN2L -> LINE2L 25 * | IN2R -> LINE2R 26 * | MIC3L/R -> N/A 27 * truncated internal functionality in 28 * accordance with documentation 29 * --------------------------------------- 30 * 31 * Hence the machine layer should disable unsupported inputs/outputs by 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/init.h> 38 #include <linux/delay.h> 39 #include <linux/pm.h> 40 #include <linux/i2c.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/slab.h> 44 #include <sound/core.h> 45 #include <sound/pcm.h> 46 #include <sound/pcm_params.h> 47 #include <sound/soc.h> 48 #include <sound/initval.h> 49 #include <sound/tlv.h> 50 #include <sound/tlv320aic3x.h> 51 52 #include "tlv320aic3x.h" 53 54 #define AIC3X_NUM_SUPPLIES 4 55 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { 56 "IOVDD", /* I/O Voltage */ 57 "DVDD", /* Digital Core Voltage */ 58 "AVDD", /* Analog DAC Voltage */ 59 "DRVDD", /* ADC Analog and Output Driver Voltage */ 60 }; 61 62 static LIST_HEAD(reset_list); 63 64 struct aic3x_priv; 65 66 struct aic3x_disable_nb { 67 struct notifier_block nb; 68 struct aic3x_priv *aic3x; 69 }; 70 71 /* codec private data */ 72 struct aic3x_priv { 73 struct snd_soc_codec *codec; 74 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; 75 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES]; 76 enum snd_soc_control_type control_type; 77 struct aic3x_setup_data *setup; 78 unsigned int sysclk; 79 struct list_head list; 80 int master; 81 int gpio_reset; 82 int power; 83 #define AIC3X_MODEL_3X 0 84 #define AIC3X_MODEL_33 1 85 #define AIC3X_MODEL_3007 2 86 u16 model; 87 }; 88 89 /* 90 * AIC3X register cache 91 * We can't read the AIC3X register space when we are 92 * using 2 wire for device control, so we cache them instead. 93 * There is no point in caching the reset register 94 */ 95 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { 96 0x00, 0x00, 0x00, 0x10, /* 0 */ 97 0x04, 0x00, 0x00, 0x00, /* 4 */ 98 0x00, 0x00, 0x00, 0x01, /* 8 */ 99 0x00, 0x00, 0x00, 0x80, /* 12 */ 100 0x80, 0xff, 0xff, 0x78, /* 16 */ 101 0x78, 0x78, 0x78, 0x78, /* 20 */ 102 0x78, 0x00, 0x00, 0xfe, /* 24 */ 103 0x00, 0x00, 0xfe, 0x00, /* 28 */ 104 0x18, 0x18, 0x00, 0x00, /* 32 */ 105 0x00, 0x00, 0x00, 0x00, /* 36 */ 106 0x00, 0x00, 0x00, 0x80, /* 40 */ 107 0x80, 0x00, 0x00, 0x00, /* 44 */ 108 0x00, 0x00, 0x00, 0x04, /* 48 */ 109 0x00, 0x00, 0x00, 0x00, /* 52 */ 110 0x00, 0x00, 0x04, 0x00, /* 56 */ 111 0x00, 0x00, 0x00, 0x00, /* 60 */ 112 0x00, 0x04, 0x00, 0x00, /* 64 */ 113 0x00, 0x00, 0x00, 0x00, /* 68 */ 114 0x04, 0x00, 0x00, 0x00, /* 72 */ 115 0x00, 0x00, 0x00, 0x00, /* 76 */ 116 0x00, 0x00, 0x00, 0x00, /* 80 */ 117 0x00, 0x00, 0x00, 0x00, /* 84 */ 118 0x00, 0x00, 0x00, 0x00, /* 88 */ 119 0x00, 0x00, 0x00, 0x00, /* 92 */ 120 0x00, 0x00, 0x00, 0x00, /* 96 */ 121 0x00, 0x00, 0x02, 0x00, /* 100 */ 122 0x00, 0x00, 0x00, 0x00, /* 104 */ 123 0x00, 0x00, /* 108 */ 124 }; 125 126 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ 127 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 128 .info = snd_soc_info_volsw, \ 129 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \ 130 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) } 131 132 /* 133 * All input lines are connected when !0xf and disconnected with 0xf bit field, 134 * so we have to use specific dapm_put call for input mixer 135 */ 136 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, 137 struct snd_ctl_elem_value *ucontrol) 138 { 139 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); 140 struct snd_soc_dapm_widget *widget = wlist->widgets[0]; 141 struct soc_mixer_control *mc = 142 (struct soc_mixer_control *)kcontrol->private_value; 143 unsigned int reg = mc->reg; 144 unsigned int shift = mc->shift; 145 int max = mc->max; 146 unsigned int mask = (1 << fls(max)) - 1; 147 unsigned int invert = mc->invert; 148 unsigned short val, val_mask; 149 int ret; 150 struct snd_soc_dapm_path *path; 151 int found = 0; 152 153 val = (ucontrol->value.integer.value[0] & mask); 154 155 mask = 0xf; 156 if (val) 157 val = mask; 158 159 if (invert) 160 val = mask - val; 161 val_mask = mask << shift; 162 val = val << shift; 163 164 mutex_lock(&widget->codec->mutex); 165 166 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { 167 /* find dapm widget path assoc with kcontrol */ 168 list_for_each_entry(path, &widget->dapm->card->paths, list) { 169 if (path->kcontrol != kcontrol) 170 continue; 171 172 /* found, now check type */ 173 found = 1; 174 if (val) 175 /* new connection */ 176 path->connect = invert ? 0 : 1; 177 else 178 /* old connection must be powered down */ 179 path->connect = invert ? 1 : 0; 180 181 dapm_mark_dirty(path->source, "tlv320aic3x source"); 182 dapm_mark_dirty(path->sink, "tlv320aic3x sink"); 183 184 break; 185 } 186 187 if (found) 188 snd_soc_dapm_sync(widget->dapm); 189 } 190 191 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); 192 193 mutex_unlock(&widget->codec->mutex); 194 return ret; 195 } 196 197 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; 198 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; 199 static const char *aic3x_left_hpcom_mux[] = 200 { "differential of HPLOUT", "constant VCM", "single-ended" }; 201 static const char *aic3x_right_hpcom_mux[] = 202 { "differential of HPROUT", "constant VCM", "single-ended", 203 "differential of HPLCOM", "external feedback" }; 204 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; 205 static const char *aic3x_adc_hpf[] = 206 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; 207 208 #define LDAC_ENUM 0 209 #define RDAC_ENUM 1 210 #define LHPCOM_ENUM 2 211 #define RHPCOM_ENUM 3 212 #define LINE1L_2_L_ENUM 4 213 #define LINE1L_2_R_ENUM 5 214 #define LINE1R_2_L_ENUM 6 215 #define LINE1R_2_R_ENUM 7 216 #define LINE2L_ENUM 8 217 #define LINE2R_ENUM 9 218 #define ADC_HPF_ENUM 10 219 220 static const struct soc_enum aic3x_enum[] = { 221 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), 222 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), 223 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), 224 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), 225 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 226 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 227 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 228 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 229 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 230 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 231 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf), 232 }; 233 234 static const char *aic3x_agc_level[] = 235 { "-5.5dB", "-8dB", "-10dB", "-12dB", "-14dB", "-17dB", "-20dB", "-24dB" }; 236 static const struct soc_enum aic3x_agc_level_enum[] = { 237 SOC_ENUM_SINGLE(LAGC_CTRL_A, 4, 8, aic3x_agc_level), 238 SOC_ENUM_SINGLE(RAGC_CTRL_A, 4, 8, aic3x_agc_level), 239 }; 240 241 static const char *aic3x_agc_attack[] = { "8ms", "11ms", "16ms", "20ms" }; 242 static const struct soc_enum aic3x_agc_attack_enum[] = { 243 SOC_ENUM_SINGLE(LAGC_CTRL_A, 2, 4, aic3x_agc_attack), 244 SOC_ENUM_SINGLE(RAGC_CTRL_A, 2, 4, aic3x_agc_attack), 245 }; 246 247 static const char *aic3x_agc_decay[] = { "100ms", "200ms", "400ms", "500ms" }; 248 static const struct soc_enum aic3x_agc_decay_enum[] = { 249 SOC_ENUM_SINGLE(LAGC_CTRL_A, 0, 4, aic3x_agc_decay), 250 SOC_ENUM_SINGLE(RAGC_CTRL_A, 0, 4, aic3x_agc_decay), 251 }; 252 253 /* 254 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps 255 */ 256 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); 257 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ 258 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); 259 /* 260 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. 261 * Step size is approximately 0.5 dB over most of the scale but increasing 262 * near the very low levels. 263 * Define dB scale so that it is mostly correct for range about -55 to 0 dB 264 * but having increasing dB difference below that (and where it doesn't count 265 * so much). This setting shows -50 dB (actual is -50.3 dB) for register 266 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. 267 */ 268 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); 269 270 static const struct snd_kcontrol_new aic3x_snd_controls[] = { 271 /* Output */ 272 SOC_DOUBLE_R_TLV("PCM Playback Volume", 273 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 274 275 /* 276 * Output controls that map to output mixer switches. Note these are 277 * only for swapped L-to-R and R-to-L routes. See below stereo controls 278 * for direct L-to-L and R-to-R routes. 279 */ 280 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", 281 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 282 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", 283 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 284 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", 285 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 286 287 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", 288 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 289 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", 290 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 291 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", 292 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 293 294 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", 295 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 296 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", 297 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 298 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", 299 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 300 301 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", 302 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 303 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", 304 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 305 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", 306 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 307 308 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", 309 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 310 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", 311 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 312 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", 313 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 314 315 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", 316 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 317 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", 318 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 319 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", 320 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 321 322 /* Stereo output controls for direct L-to-L and R-to-R routes */ 323 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", 324 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, 325 0, 118, 1, output_stage_tlv), 326 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", 327 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, 328 0, 118, 1, output_stage_tlv), 329 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 330 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 331 0, 118, 1, output_stage_tlv), 332 333 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", 334 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 335 0, 118, 1, output_stage_tlv), 336 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", 337 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 338 0, 118, 1, output_stage_tlv), 339 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 340 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 341 0, 118, 1, output_stage_tlv), 342 343 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", 344 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 345 0, 118, 1, output_stage_tlv), 346 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", 347 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 348 0, 118, 1, output_stage_tlv), 349 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 350 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 351 0, 118, 1, output_stage_tlv), 352 353 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", 354 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 355 0, 118, 1, output_stage_tlv), 356 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", 357 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, 358 0, 118, 1, output_stage_tlv), 359 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 360 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 361 0, 118, 1, output_stage_tlv), 362 363 /* Output pin mute controls */ 364 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, 365 0x01, 0), 366 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 367 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 368 0x01, 0), 369 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 370 0x01, 0), 371 372 /* 373 * Note: enable Automatic input Gain Controller with care. It can 374 * adjust PGA to max value when ADC is on and will never go back. 375 */ 376 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), 377 SOC_ENUM("Left AGC Target level", aic3x_agc_level_enum[0]), 378 SOC_ENUM("Right AGC Target level", aic3x_agc_level_enum[1]), 379 SOC_ENUM("Left AGC Attack time", aic3x_agc_attack_enum[0]), 380 SOC_ENUM("Right AGC Attack time", aic3x_agc_attack_enum[1]), 381 SOC_ENUM("Left AGC Decay time", aic3x_agc_decay_enum[0]), 382 SOC_ENUM("Right AGC Decay time", aic3x_agc_decay_enum[1]), 383 384 /* De-emphasis */ 385 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0), 386 387 /* Input */ 388 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 389 0, 119, 0, adc_tlv), 390 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), 391 392 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]), 393 }; 394 395 /* 396 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps 397 */ 398 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0); 399 400 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl = 401 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv); 402 403 /* Left DAC Mux */ 404 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = 405 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); 406 407 /* Right DAC Mux */ 408 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = 409 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); 410 411 /* Left HPCOM Mux */ 412 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = 413 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); 414 415 /* Right HPCOM Mux */ 416 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = 417 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); 418 419 /* Left Line Mixer */ 420 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { 421 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), 422 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), 423 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), 424 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), 425 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), 426 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), 427 }; 428 429 /* Right Line Mixer */ 430 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { 431 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), 432 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), 433 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), 434 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), 435 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), 436 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), 437 }; 438 439 /* Mono Mixer */ 440 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { 441 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), 442 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), 443 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), 444 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), 445 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), 446 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), 447 }; 448 449 /* Left HP Mixer */ 450 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { 451 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), 452 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), 453 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), 454 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), 455 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), 456 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), 457 }; 458 459 /* Right HP Mixer */ 460 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { 461 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), 462 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), 463 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), 464 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), 465 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), 466 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), 467 }; 468 469 /* Left HPCOM Mixer */ 470 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { 471 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), 472 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), 473 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), 474 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), 475 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), 476 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), 477 }; 478 479 /* Right HPCOM Mixer */ 480 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { 481 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), 482 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), 483 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), 484 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), 485 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), 486 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), 487 }; 488 489 /* Left PGA Mixer */ 490 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { 491 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 492 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 493 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), 494 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 495 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 496 }; 497 498 /* Right PGA Mixer */ 499 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { 500 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 501 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 502 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), 503 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 504 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 505 }; 506 507 /* Left Line1 Mux */ 508 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls = 509 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]); 510 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls = 511 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]); 512 513 /* Right Line1 Mux */ 514 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls = 515 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]); 516 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls = 517 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]); 518 519 /* Left Line2 Mux */ 520 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = 521 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); 522 523 /* Right Line2 Mux */ 524 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = 525 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); 526 527 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { 528 /* Left DAC to Left Outputs */ 529 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), 530 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, 531 &aic3x_left_dac_mux_controls), 532 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, 533 &aic3x_left_hpcom_mux_controls), 534 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), 535 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), 536 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), 537 538 /* Right DAC to Right Outputs */ 539 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), 540 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, 541 &aic3x_right_dac_mux_controls), 542 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, 543 &aic3x_right_hpcom_mux_controls), 544 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), 545 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), 546 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), 547 548 /* Mono Output */ 549 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), 550 551 /* Inputs to Left ADC */ 552 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), 553 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 554 &aic3x_left_pga_mixer_controls[0], 555 ARRAY_SIZE(aic3x_left_pga_mixer_controls)), 556 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, 557 &aic3x_left_line1l_mux_controls), 558 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, 559 &aic3x_left_line1r_mux_controls), 560 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, 561 &aic3x_left_line2_mux_controls), 562 563 /* Inputs to Right ADC */ 564 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 565 LINE1R_2_RADC_CTRL, 2, 0), 566 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 567 &aic3x_right_pga_mixer_controls[0], 568 ARRAY_SIZE(aic3x_right_pga_mixer_controls)), 569 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, 570 &aic3x_right_line1l_mux_controls), 571 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, 572 &aic3x_right_line1r_mux_controls), 573 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, 574 &aic3x_right_line2_mux_controls), 575 576 /* 577 * Not a real mic bias widget but similar function. This is for dynamic 578 * control of GPIO1 digital mic modulator clock output function when 579 * using digital mic. 580 */ 581 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", 582 AIC3X_GPIO1_REG, 4, 0xf, 583 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, 584 AIC3X_GPIO1_FUNC_DISABLED), 585 586 /* 587 * Also similar function like mic bias. Selects digital mic with 588 * configurable oversampling rate instead of ADC converter. 589 */ 590 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", 591 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), 592 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", 593 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), 594 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", 595 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 596 597 /* Mic Bias */ 598 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V", 599 MICBIAS_CTRL, 6, 3, 1, 0), 600 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V", 601 MICBIAS_CTRL, 6, 3, 2, 0), 602 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD", 603 MICBIAS_CTRL, 6, 3, 3, 0), 604 605 /* Output mixers */ 606 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 607 &aic3x_left_line_mixer_controls[0], 608 ARRAY_SIZE(aic3x_left_line_mixer_controls)), 609 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 610 &aic3x_right_line_mixer_controls[0], 611 ARRAY_SIZE(aic3x_right_line_mixer_controls)), 612 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, 613 &aic3x_mono_mixer_controls[0], 614 ARRAY_SIZE(aic3x_mono_mixer_controls)), 615 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 616 &aic3x_left_hp_mixer_controls[0], 617 ARRAY_SIZE(aic3x_left_hp_mixer_controls)), 618 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 619 &aic3x_right_hp_mixer_controls[0], 620 ARRAY_SIZE(aic3x_right_hp_mixer_controls)), 621 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 622 &aic3x_left_hpcom_mixer_controls[0], 623 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), 624 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 625 &aic3x_right_hpcom_mixer_controls[0], 626 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), 627 628 SND_SOC_DAPM_OUTPUT("LLOUT"), 629 SND_SOC_DAPM_OUTPUT("RLOUT"), 630 SND_SOC_DAPM_OUTPUT("MONO_LOUT"), 631 SND_SOC_DAPM_OUTPUT("HPLOUT"), 632 SND_SOC_DAPM_OUTPUT("HPROUT"), 633 SND_SOC_DAPM_OUTPUT("HPLCOM"), 634 SND_SOC_DAPM_OUTPUT("HPRCOM"), 635 636 SND_SOC_DAPM_INPUT("MIC3L"), 637 SND_SOC_DAPM_INPUT("MIC3R"), 638 SND_SOC_DAPM_INPUT("LINE1L"), 639 SND_SOC_DAPM_INPUT("LINE1R"), 640 SND_SOC_DAPM_INPUT("LINE2L"), 641 SND_SOC_DAPM_INPUT("LINE2R"), 642 643 /* 644 * Virtual output pin to detection block inside codec. This can be 645 * used to keep codec bias on if gpio or detection features are needed. 646 * Force pin on or construct a path with an input jack and mic bias 647 * widgets. 648 */ 649 SND_SOC_DAPM_OUTPUT("Detection"), 650 }; 651 652 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { 653 /* Class-D outputs */ 654 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0), 655 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0), 656 657 SND_SOC_DAPM_OUTPUT("SPOP"), 658 SND_SOC_DAPM_OUTPUT("SPOM"), 659 }; 660 661 static const struct snd_soc_dapm_route intercon[] = { 662 /* Left Input */ 663 {"Left Line1L Mux", "single-ended", "LINE1L"}, 664 {"Left Line1L Mux", "differential", "LINE1L"}, 665 666 {"Left Line2L Mux", "single-ended", "LINE2L"}, 667 {"Left Line2L Mux", "differential", "LINE2L"}, 668 669 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, 670 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, 671 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, 672 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, 673 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, 674 675 {"Left ADC", NULL, "Left PGA Mixer"}, 676 {"Left ADC", NULL, "GPIO1 dmic modclk"}, 677 678 /* Right Input */ 679 {"Right Line1R Mux", "single-ended", "LINE1R"}, 680 {"Right Line1R Mux", "differential", "LINE1R"}, 681 682 {"Right Line2R Mux", "single-ended", "LINE2R"}, 683 {"Right Line2R Mux", "differential", "LINE2R"}, 684 685 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, 686 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, 687 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, 688 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, 689 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, 690 691 {"Right ADC", NULL, "Right PGA Mixer"}, 692 {"Right ADC", NULL, "GPIO1 dmic modclk"}, 693 694 /* 695 * Logical path between digital mic enable and GPIO1 modulator clock 696 * output function 697 */ 698 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, 699 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, 700 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, 701 702 /* Left DAC Output */ 703 {"Left DAC Mux", "DAC_L1", "Left DAC"}, 704 {"Left DAC Mux", "DAC_L2", "Left DAC"}, 705 {"Left DAC Mux", "DAC_L3", "Left DAC"}, 706 707 /* Right DAC Output */ 708 {"Right DAC Mux", "DAC_R1", "Right DAC"}, 709 {"Right DAC Mux", "DAC_R2", "Right DAC"}, 710 {"Right DAC Mux", "DAC_R3", "Right DAC"}, 711 712 /* Left Line Output */ 713 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 714 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 715 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 716 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 717 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 718 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 719 720 {"Left Line Out", NULL, "Left Line Mixer"}, 721 {"Left Line Out", NULL, "Left DAC Mux"}, 722 {"LLOUT", NULL, "Left Line Out"}, 723 724 /* Right Line Output */ 725 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 726 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 727 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 728 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 729 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 730 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 731 732 {"Right Line Out", NULL, "Right Line Mixer"}, 733 {"Right Line Out", NULL, "Right DAC Mux"}, 734 {"RLOUT", NULL, "Right Line Out"}, 735 736 /* Mono Output */ 737 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 738 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 739 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, 740 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 741 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 742 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, 743 744 {"Mono Out", NULL, "Mono Mixer"}, 745 {"MONO_LOUT", NULL, "Mono Out"}, 746 747 /* Left HP Output */ 748 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 749 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 750 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 751 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 752 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 753 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 754 755 {"Left HP Out", NULL, "Left HP Mixer"}, 756 {"Left HP Out", NULL, "Left DAC Mux"}, 757 {"HPLOUT", NULL, "Left HP Out"}, 758 759 /* Right HP Output */ 760 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 761 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 762 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 763 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 764 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 765 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 766 767 {"Right HP Out", NULL, "Right HP Mixer"}, 768 {"Right HP Out", NULL, "Right DAC Mux"}, 769 {"HPROUT", NULL, "Right HP Out"}, 770 771 /* Left HPCOM Output */ 772 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 773 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 774 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 775 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 776 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 777 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 778 779 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, 780 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, 781 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, 782 {"Left HP Com", NULL, "Left HPCOM Mux"}, 783 {"HPLCOM", NULL, "Left HP Com"}, 784 785 /* Right HPCOM Output */ 786 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 787 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 788 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 789 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 790 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 791 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 792 793 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, 794 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, 795 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, 796 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, 797 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, 798 {"Right HP Com", NULL, "Right HPCOM Mux"}, 799 {"HPRCOM", NULL, "Right HP Com"}, 800 }; 801 802 static const struct snd_soc_dapm_route intercon_3007[] = { 803 /* Class-D outputs */ 804 {"Left Class-D Out", NULL, "Left Line Out"}, 805 {"Right Class-D Out", NULL, "Left Line Out"}, 806 {"SPOP", NULL, "Left Class-D Out"}, 807 {"SPOM", NULL, "Right Class-D Out"}, 808 }; 809 810 static int aic3x_add_widgets(struct snd_soc_codec *codec) 811 { 812 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 813 struct snd_soc_dapm_context *dapm = &codec->dapm; 814 815 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets, 816 ARRAY_SIZE(aic3x_dapm_widgets)); 817 818 /* set up audio path interconnects */ 819 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 820 821 if (aic3x->model == AIC3X_MODEL_3007) { 822 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, 823 ARRAY_SIZE(aic3007_dapm_widgets)); 824 snd_soc_dapm_add_routes(dapm, intercon_3007, 825 ARRAY_SIZE(intercon_3007)); 826 } 827 828 return 0; 829 } 830 831 static int aic3x_hw_params(struct snd_pcm_substream *substream, 832 struct snd_pcm_hw_params *params, 833 struct snd_soc_dai *dai) 834 { 835 struct snd_soc_codec *codec = dai->codec; 836 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 837 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 838 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 839 u16 d, pll_d = 1; 840 int clk; 841 842 /* select data word length */ 843 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); 844 switch (params_format(params)) { 845 case SNDRV_PCM_FORMAT_S16_LE: 846 break; 847 case SNDRV_PCM_FORMAT_S20_3LE: 848 data |= (0x01 << 4); 849 break; 850 case SNDRV_PCM_FORMAT_S24_LE: 851 data |= (0x02 << 4); 852 break; 853 case SNDRV_PCM_FORMAT_S32_LE: 854 data |= (0x03 << 4); 855 break; 856 } 857 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data); 858 859 /* Fsref can be 44100 or 48000 */ 860 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; 861 862 /* Try to find a value for Q which allows us to bypass the PLL and 863 * generate CODEC_CLK directly. */ 864 for (pll_q = 2; pll_q < 18; pll_q++) 865 if (aic3x->sysclk / (128 * pll_q) == fsref) { 866 bypass_pll = 1; 867 break; 868 } 869 870 if (bypass_pll) { 871 pll_q &= 0xf; 872 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 873 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 874 /* disable PLL if it is bypassed */ 875 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); 876 877 } else { 878 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 879 /* enable PLL when it is used */ 880 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 881 PLL_ENABLE, PLL_ENABLE); 882 } 883 884 /* Route Left DAC to left channel input and 885 * right DAC to right channel input */ 886 data = (LDAC2LCH | RDAC2RCH); 887 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; 888 if (params_rate(params) >= 64000) 889 data |= DUAL_RATE_MODE; 890 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data); 891 892 /* codec sample rate select */ 893 data = (fsref * 20) / params_rate(params); 894 if (params_rate(params) < 64000) 895 data /= 2; 896 data /= 5; 897 data -= 2; 898 data |= (data << 4); 899 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); 900 901 if (bypass_pll) 902 return 0; 903 904 /* Use PLL, compute appropriate setup for j, d, r and p, the closest 905 * one wins the game. Try with d==0 first, next with d!=0. 906 * Constraints for j are according to the datasheet. 907 * The sysclk is divided by 1000 to prevent integer overflows. 908 */ 909 910 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); 911 912 for (r = 1; r <= 16; r++) 913 for (p = 1; p <= 8; p++) { 914 for (j = 4; j <= 55; j++) { 915 /* This is actually 1000*((j+(d/10000))*r)/p 916 * The term had to be converted to get 917 * rid of the division by 10000; d = 0 here 918 */ 919 int tmp_clk = (1000 * j * r) / p; 920 921 /* Check whether this values get closer than 922 * the best ones we had before 923 */ 924 if (abs(codec_clk - tmp_clk) < 925 abs(codec_clk - last_clk)) { 926 pll_j = j; pll_d = 0; 927 pll_r = r; pll_p = p; 928 last_clk = tmp_clk; 929 } 930 931 /* Early exit for exact matches */ 932 if (tmp_clk == codec_clk) 933 goto found; 934 } 935 } 936 937 /* try with d != 0 */ 938 for (p = 1; p <= 8; p++) { 939 j = codec_clk * p / 1000; 940 941 if (j < 4 || j > 11) 942 continue; 943 944 /* do not use codec_clk here since we'd loose precision */ 945 d = ((2048 * p * fsref) - j * aic3x->sysclk) 946 * 100 / (aic3x->sysclk/100); 947 948 clk = (10000 * j + d) / (10 * p); 949 950 /* check whether this values get closer than the best 951 * ones we had before */ 952 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { 953 pll_j = j; pll_d = d; pll_r = 1; pll_p = p; 954 last_clk = clk; 955 } 956 957 /* Early exit for exact matches */ 958 if (clk == codec_clk) 959 goto found; 960 } 961 962 if (last_clk == 0) { 963 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); 964 return -EINVAL; 965 } 966 967 found: 968 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p); 969 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, 970 pll_r << PLLR_SHIFT); 971 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); 972 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, 973 (pll_d >> 6) << PLLD_MSB_SHIFT); 974 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, 975 (pll_d & 0x3F) << PLLD_LSB_SHIFT); 976 977 return 0; 978 } 979 980 static int aic3x_mute(struct snd_soc_dai *dai, int mute) 981 { 982 struct snd_soc_codec *codec = dai->codec; 983 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON; 984 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON; 985 986 if (mute) { 987 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); 988 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); 989 } else { 990 snd_soc_write(codec, LDAC_VOL, ldac_reg); 991 snd_soc_write(codec, RDAC_VOL, rdac_reg); 992 } 993 994 return 0; 995 } 996 997 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 998 int clk_id, unsigned int freq, int dir) 999 { 1000 struct snd_soc_codec *codec = codec_dai->codec; 1001 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1002 1003 /* set clock on MCLK or GPIO2 or BCLK */ 1004 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, 1005 clk_id << PLLCLK_IN_SHIFT); 1006 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, 1007 clk_id << CLKDIV_IN_SHIFT); 1008 1009 aic3x->sysclk = freq; 1010 return 0; 1011 } 1012 1013 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, 1014 unsigned int fmt) 1015 { 1016 struct snd_soc_codec *codec = codec_dai->codec; 1017 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1018 u8 iface_areg, iface_breg; 1019 int delay = 0; 1020 1021 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; 1022 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; 1023 1024 /* set master/slave audio interface */ 1025 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1026 case SND_SOC_DAIFMT_CBM_CFM: 1027 aic3x->master = 1; 1028 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; 1029 break; 1030 case SND_SOC_DAIFMT_CBS_CFS: 1031 aic3x->master = 0; 1032 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER); 1033 break; 1034 default: 1035 return -EINVAL; 1036 } 1037 1038 /* 1039 * match both interface format and signal polarities since they 1040 * are fixed 1041 */ 1042 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | 1043 SND_SOC_DAIFMT_INV_MASK)) { 1044 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): 1045 break; 1046 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): 1047 delay = 1; 1048 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): 1049 iface_breg |= (0x01 << 6); 1050 break; 1051 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): 1052 iface_breg |= (0x02 << 6); 1053 break; 1054 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): 1055 iface_breg |= (0x03 << 6); 1056 break; 1057 default: 1058 return -EINVAL; 1059 } 1060 1061 /* set iface */ 1062 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); 1063 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); 1064 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay); 1065 1066 return 0; 1067 } 1068 1069 static int aic3x_init_3007(struct snd_soc_codec *codec) 1070 { 1071 u8 tmp1, tmp2, *cache = codec->reg_cache; 1072 1073 /* 1074 * There is no need to cache writes to undocumented page 0xD but 1075 * respective page 0 register cache entries must be preserved 1076 */ 1077 tmp1 = cache[0xD]; 1078 tmp2 = cache[0x8]; 1079 /* Class-D speaker driver init; datasheet p. 46 */ 1080 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D); 1081 snd_soc_write(codec, 0xD, 0x0D); 1082 snd_soc_write(codec, 0x8, 0x5C); 1083 snd_soc_write(codec, 0x8, 0x5D); 1084 snd_soc_write(codec, 0x8, 0x5C); 1085 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00); 1086 cache[0xD] = tmp1; 1087 cache[0x8] = tmp2; 1088 1089 return 0; 1090 } 1091 1092 static int aic3x_regulator_event(struct notifier_block *nb, 1093 unsigned long event, void *data) 1094 { 1095 struct aic3x_disable_nb *disable_nb = 1096 container_of(nb, struct aic3x_disable_nb, nb); 1097 struct aic3x_priv *aic3x = disable_nb->aic3x; 1098 1099 if (event & REGULATOR_EVENT_DISABLE) { 1100 /* 1101 * Put codec to reset and require cache sync as at least one 1102 * of the supplies was disabled 1103 */ 1104 if (gpio_is_valid(aic3x->gpio_reset)) 1105 gpio_set_value(aic3x->gpio_reset, 0); 1106 aic3x->codec->cache_sync = 1; 1107 } 1108 1109 return 0; 1110 } 1111 1112 static int aic3x_set_power(struct snd_soc_codec *codec, int power) 1113 { 1114 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1115 int i, ret; 1116 u8 *cache = codec->reg_cache; 1117 1118 if (power) { 1119 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), 1120 aic3x->supplies); 1121 if (ret) 1122 goto out; 1123 aic3x->power = 1; 1124 /* 1125 * Reset release and cache sync is necessary only if some 1126 * supply was off or if there were cached writes 1127 */ 1128 if (!codec->cache_sync) 1129 goto out; 1130 1131 if (gpio_is_valid(aic3x->gpio_reset)) { 1132 udelay(1); 1133 gpio_set_value(aic3x->gpio_reset, 1); 1134 } 1135 1136 /* Sync reg_cache with the hardware */ 1137 codec->cache_only = 0; 1138 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++) 1139 snd_soc_write(codec, i, cache[i]); 1140 if (aic3x->model == AIC3X_MODEL_3007) 1141 aic3x_init_3007(codec); 1142 codec->cache_sync = 0; 1143 } else { 1144 /* 1145 * Do soft reset to this codec instance in order to clear 1146 * possible VDD leakage currents in case the supply regulators 1147 * remain on 1148 */ 1149 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1150 codec->cache_sync = 1; 1151 aic3x->power = 0; 1152 /* HW writes are needless when bias is off */ 1153 codec->cache_only = 1; 1154 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), 1155 aic3x->supplies); 1156 } 1157 out: 1158 return ret; 1159 } 1160 1161 static int aic3x_set_bias_level(struct snd_soc_codec *codec, 1162 enum snd_soc_bias_level level) 1163 { 1164 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1165 1166 switch (level) { 1167 case SND_SOC_BIAS_ON: 1168 break; 1169 case SND_SOC_BIAS_PREPARE: 1170 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY && 1171 aic3x->master) { 1172 /* enable pll */ 1173 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1174 PLL_ENABLE, PLL_ENABLE); 1175 } 1176 break; 1177 case SND_SOC_BIAS_STANDBY: 1178 if (!aic3x->power) 1179 aic3x_set_power(codec, 1); 1180 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE && 1181 aic3x->master) { 1182 /* disable pll */ 1183 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1184 PLL_ENABLE, 0); 1185 } 1186 break; 1187 case SND_SOC_BIAS_OFF: 1188 if (aic3x->power) 1189 aic3x_set_power(codec, 0); 1190 break; 1191 } 1192 codec->dapm.bias_level = level; 1193 1194 return 0; 1195 } 1196 1197 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1198 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1199 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1200 1201 static const struct snd_soc_dai_ops aic3x_dai_ops = { 1202 .hw_params = aic3x_hw_params, 1203 .digital_mute = aic3x_mute, 1204 .set_sysclk = aic3x_set_dai_sysclk, 1205 .set_fmt = aic3x_set_dai_fmt, 1206 }; 1207 1208 static struct snd_soc_dai_driver aic3x_dai = { 1209 .name = "tlv320aic3x-hifi", 1210 .playback = { 1211 .stream_name = "Playback", 1212 .channels_min = 1, 1213 .channels_max = 2, 1214 .rates = AIC3X_RATES, 1215 .formats = AIC3X_FORMATS,}, 1216 .capture = { 1217 .stream_name = "Capture", 1218 .channels_min = 1, 1219 .channels_max = 2, 1220 .rates = AIC3X_RATES, 1221 .formats = AIC3X_FORMATS,}, 1222 .ops = &aic3x_dai_ops, 1223 .symmetric_rates = 1, 1224 }; 1225 1226 static int aic3x_suspend(struct snd_soc_codec *codec) 1227 { 1228 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1229 1230 return 0; 1231 } 1232 1233 static int aic3x_resume(struct snd_soc_codec *codec) 1234 { 1235 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1236 1237 return 0; 1238 } 1239 1240 /* 1241 * initialise the AIC3X driver 1242 * register the mixer and dsp interfaces with the kernel 1243 */ 1244 static int aic3x_init(struct snd_soc_codec *codec) 1245 { 1246 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1247 1248 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); 1249 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1250 1251 /* DAC default volume and mute */ 1252 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); 1253 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); 1254 1255 /* DAC to HP default volume and route to Output mixer */ 1256 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); 1257 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); 1258 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1259 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1260 /* DAC to Line Out default volume and route to Output mixer */ 1261 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1262 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1263 /* DAC to Mono Line Out default volume and route to Output mixer */ 1264 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1265 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1266 1267 /* unmute all outputs */ 1268 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE); 1269 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE); 1270 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE); 1271 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE); 1272 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE); 1273 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE); 1274 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE); 1275 1276 /* ADC default volume and unmute */ 1277 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN); 1278 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN); 1279 /* By default route Line1 to ADC PGA mixer */ 1280 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0); 1281 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0); 1282 1283 /* PGA to HP Bypass default volume, disconnect from Output Mixer */ 1284 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); 1285 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); 1286 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); 1287 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); 1288 /* PGA to Line Out default volume, disconnect from Output Mixer */ 1289 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); 1290 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); 1291 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ 1292 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); 1293 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); 1294 1295 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ 1296 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); 1297 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); 1298 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); 1299 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); 1300 /* Line2 Line Out default volume, disconnect from Output Mixer */ 1301 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); 1302 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); 1303 /* Line2 to Mono Out default volume, disconnect from Output Mixer */ 1304 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); 1305 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); 1306 1307 if (aic3x->model == AIC3X_MODEL_3007) { 1308 aic3x_init_3007(codec); 1309 snd_soc_write(codec, CLASSD_CTRL, 0); 1310 } 1311 1312 return 0; 1313 } 1314 1315 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x) 1316 { 1317 struct aic3x_priv *a; 1318 1319 list_for_each_entry(a, &reset_list, list) { 1320 if (gpio_is_valid(aic3x->gpio_reset) && 1321 aic3x->gpio_reset == a->gpio_reset) 1322 return true; 1323 } 1324 1325 return false; 1326 } 1327 1328 static int aic3x_probe(struct snd_soc_codec *codec) 1329 { 1330 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1331 int ret, i; 1332 1333 INIT_LIST_HEAD(&aic3x->list); 1334 aic3x->codec = codec; 1335 1336 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type); 1337 if (ret != 0) { 1338 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1339 return ret; 1340 } 1341 1342 if (gpio_is_valid(aic3x->gpio_reset) && 1343 !aic3x_is_shared_reset(aic3x)) { 1344 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); 1345 if (ret != 0) 1346 goto err_gpio; 1347 gpio_direction_output(aic3x->gpio_reset, 0); 1348 } 1349 1350 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1351 aic3x->supplies[i].supply = aic3x_supply_names[i]; 1352 1353 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies), 1354 aic3x->supplies); 1355 if (ret != 0) { 1356 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 1357 goto err_get; 1358 } 1359 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) { 1360 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; 1361 aic3x->disable_nb[i].aic3x = aic3x; 1362 ret = regulator_register_notifier(aic3x->supplies[i].consumer, 1363 &aic3x->disable_nb[i].nb); 1364 if (ret) { 1365 dev_err(codec->dev, 1366 "Failed to request regulator notifier: %d\n", 1367 ret); 1368 goto err_notif; 1369 } 1370 } 1371 1372 codec->cache_only = 1; 1373 aic3x_init(codec); 1374 1375 if (aic3x->setup) { 1376 /* setup GPIO functions */ 1377 snd_soc_write(codec, AIC3X_GPIO1_REG, 1378 (aic3x->setup->gpio_func[0] & 0xf) << 4); 1379 snd_soc_write(codec, AIC3X_GPIO2_REG, 1380 (aic3x->setup->gpio_func[1] & 0xf) << 4); 1381 } 1382 1383 snd_soc_add_codec_controls(codec, aic3x_snd_controls, 1384 ARRAY_SIZE(aic3x_snd_controls)); 1385 if (aic3x->model == AIC3X_MODEL_3007) 1386 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1); 1387 1388 aic3x_add_widgets(codec); 1389 list_add(&aic3x->list, &reset_list); 1390 1391 return 0; 1392 1393 err_notif: 1394 while (i--) 1395 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1396 &aic3x->disable_nb[i].nb); 1397 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1398 err_get: 1399 if (gpio_is_valid(aic3x->gpio_reset) && 1400 !aic3x_is_shared_reset(aic3x)) 1401 gpio_free(aic3x->gpio_reset); 1402 err_gpio: 1403 return ret; 1404 } 1405 1406 static int aic3x_remove(struct snd_soc_codec *codec) 1407 { 1408 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1409 int i; 1410 1411 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1412 list_del(&aic3x->list); 1413 if (gpio_is_valid(aic3x->gpio_reset) && 1414 !aic3x_is_shared_reset(aic3x)) { 1415 gpio_set_value(aic3x->gpio_reset, 0); 1416 gpio_free(aic3x->gpio_reset); 1417 } 1418 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1419 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1420 &aic3x->disable_nb[i].nb); 1421 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1422 1423 return 0; 1424 } 1425 1426 static struct snd_soc_codec_driver soc_codec_dev_aic3x = { 1427 .set_bias_level = aic3x_set_bias_level, 1428 .idle_bias_off = true, 1429 .reg_cache_size = ARRAY_SIZE(aic3x_reg), 1430 .reg_word_size = sizeof(u8), 1431 .reg_cache_default = aic3x_reg, 1432 .probe = aic3x_probe, 1433 .remove = aic3x_remove, 1434 .suspend = aic3x_suspend, 1435 .resume = aic3x_resume, 1436 }; 1437 1438 /* 1439 * AIC3X 2 wire address can be up to 4 devices with device addresses 1440 * 0x18, 0x19, 0x1A, 0x1B 1441 */ 1442 1443 static const struct i2c_device_id aic3x_i2c_id[] = { 1444 { "tlv320aic3x", AIC3X_MODEL_3X }, 1445 { "tlv320aic33", AIC3X_MODEL_33 }, 1446 { "tlv320aic3007", AIC3X_MODEL_3007 }, 1447 { } 1448 }; 1449 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); 1450 1451 /* 1452 * If the i2c layer weren't so broken, we could pass this kind of data 1453 * around 1454 */ 1455 static int aic3x_i2c_probe(struct i2c_client *i2c, 1456 const struct i2c_device_id *id) 1457 { 1458 struct aic3x_pdata *pdata = i2c->dev.platform_data; 1459 struct aic3x_priv *aic3x; 1460 int ret; 1461 1462 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL); 1463 if (aic3x == NULL) { 1464 dev_err(&i2c->dev, "failed to create private data\n"); 1465 return -ENOMEM; 1466 } 1467 1468 aic3x->control_type = SND_SOC_I2C; 1469 1470 i2c_set_clientdata(i2c, aic3x); 1471 if (pdata) { 1472 aic3x->gpio_reset = pdata->gpio_reset; 1473 aic3x->setup = pdata->setup; 1474 } else { 1475 aic3x->gpio_reset = -1; 1476 } 1477 1478 aic3x->model = id->driver_data; 1479 1480 ret = snd_soc_register_codec(&i2c->dev, 1481 &soc_codec_dev_aic3x, &aic3x_dai, 1); 1482 return ret; 1483 } 1484 1485 static int aic3x_i2c_remove(struct i2c_client *client) 1486 { 1487 snd_soc_unregister_codec(&client->dev); 1488 return 0; 1489 } 1490 1491 /* machine i2c codec control layer */ 1492 static struct i2c_driver aic3x_i2c_driver = { 1493 .driver = { 1494 .name = "tlv320aic3x-codec", 1495 .owner = THIS_MODULE, 1496 }, 1497 .probe = aic3x_i2c_probe, 1498 .remove = aic3x_i2c_remove, 1499 .id_table = aic3x_i2c_id, 1500 }; 1501 1502 static int __init aic3x_modinit(void) 1503 { 1504 int ret = 0; 1505 ret = i2c_add_driver(&aic3x_i2c_driver); 1506 if (ret != 0) { 1507 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n", 1508 ret); 1509 } 1510 return ret; 1511 } 1512 module_init(aic3x_modinit); 1513 1514 static void __exit aic3x_exit(void) 1515 { 1516 i2c_del_driver(&aic3x_i2c_driver); 1517 } 1518 module_exit(aic3x_exit); 1519 1520 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); 1521 MODULE_AUTHOR("Vladimir Barinov"); 1522 MODULE_LICENSE("GPL"); 1523