1 /* 2 * ALSA SoC TLV320AIC3X codec driver 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Notes: 14 * The AIC3X is a driver for a low power stereo audio 15 * codecs aic31, aic32, aic33, aic3007. 16 * 17 * It supports full aic33 codec functionality. 18 * The compatibility with aic32, aic31 and aic3007 is as follows: 19 * aic32/aic3007 | aic31 20 * --------------------------------------- 21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A 22 * | IN1L -> LINE1L 23 * | IN1R -> LINE1R 24 * | IN2L -> LINE2L 25 * | IN2R -> LINE2R 26 * | MIC3L/R -> N/A 27 * truncated internal functionality in 28 * accordance with documentation 29 * --------------------------------------- 30 * 31 * Hence the machine layer should disable unsupported inputs/outputs by 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/init.h> 38 #include <linux/delay.h> 39 #include <linux/pm.h> 40 #include <linux/i2c.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/of.h> 44 #include <linux/of_gpio.h> 45 #include <linux/slab.h> 46 #include <sound/core.h> 47 #include <sound/pcm.h> 48 #include <sound/pcm_params.h> 49 #include <sound/soc.h> 50 #include <sound/initval.h> 51 #include <sound/tlv.h> 52 #include <sound/tlv320aic3x.h> 53 54 #include "tlv320aic3x.h" 55 56 #define AIC3X_NUM_SUPPLIES 4 57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { 58 "IOVDD", /* I/O Voltage */ 59 "DVDD", /* Digital Core Voltage */ 60 "AVDD", /* Analog DAC Voltage */ 61 "DRVDD", /* ADC Analog and Output Driver Voltage */ 62 }; 63 64 static LIST_HEAD(reset_list); 65 66 struct aic3x_priv; 67 68 struct aic3x_disable_nb { 69 struct notifier_block nb; 70 struct aic3x_priv *aic3x; 71 }; 72 73 /* codec private data */ 74 struct aic3x_priv { 75 struct snd_soc_codec *codec; 76 struct regmap *regmap; 77 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; 78 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES]; 79 struct aic3x_setup_data *setup; 80 unsigned int sysclk; 81 unsigned int dai_fmt; 82 unsigned int tdm_delay; 83 unsigned int slot_width; 84 struct list_head list; 85 int master; 86 int gpio_reset; 87 int power; 88 #define AIC3X_MODEL_3X 0 89 #define AIC3X_MODEL_33 1 90 #define AIC3X_MODEL_3007 2 91 #define AIC3X_MODEL_3104 3 92 u16 model; 93 94 /* Selects the micbias voltage */ 95 enum aic3x_micbias_voltage micbias_vg; 96 }; 97 98 static const struct reg_default aic3x_reg[] = { 99 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 }, 100 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 }, 101 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 }, 102 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 }, 103 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 }, 104 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 }, 105 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe }, 106 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 }, 107 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 }, 108 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 }, 109 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 }, 110 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 }, 111 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 }, 112 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 }, 113 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 }, 114 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 }, 115 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 }, 116 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 }, 117 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 }, 118 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 }, 119 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 }, 120 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 }, 121 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 }, 122 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 }, 123 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 }, 124 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 }, 125 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 }, 126 { 108, 0x00 }, { 109, 0x00 }, 127 }; 128 129 static bool aic3x_volatile_reg(struct device *dev, unsigned int reg) 130 { 131 switch (reg) { 132 case AIC3X_RESET: 133 return true; 134 default: 135 return false; 136 } 137 } 138 139 static const struct regmap_config aic3x_regmap = { 140 .reg_bits = 8, 141 .val_bits = 8, 142 143 .max_register = DAC_ICC_ADJ, 144 .reg_defaults = aic3x_reg, 145 .num_reg_defaults = ARRAY_SIZE(aic3x_reg), 146 147 .volatile_reg = aic3x_volatile_reg, 148 149 .cache_type = REGCACHE_RBTREE, 150 }; 151 152 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ 153 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \ 154 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x) 155 156 /* 157 * All input lines are connected when !0xf and disconnected with 0xf bit field, 158 * so we have to use specific dapm_put call for input mixer 159 */ 160 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, 161 struct snd_ctl_elem_value *ucontrol) 162 { 163 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); 164 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 165 struct soc_mixer_control *mc = 166 (struct soc_mixer_control *)kcontrol->private_value; 167 unsigned int reg = mc->reg; 168 unsigned int shift = mc->shift; 169 int max = mc->max; 170 unsigned int mask = (1 << fls(max)) - 1; 171 unsigned int invert = mc->invert; 172 unsigned short val; 173 struct snd_soc_dapm_update update = { 0 }; 174 int connect, change; 175 176 val = (ucontrol->value.integer.value[0] & mask); 177 178 mask = 0xf; 179 if (val) 180 val = mask; 181 182 connect = !!val; 183 184 if (invert) 185 val = mask - val; 186 187 mask <<= shift; 188 val <<= shift; 189 190 change = snd_soc_test_bits(codec, reg, mask, val); 191 if (change) { 192 update.kcontrol = kcontrol; 193 update.reg = reg; 194 update.mask = mask; 195 update.val = val; 196 197 snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect, 198 &update); 199 } 200 201 return change; 202 } 203 204 /* 205 * mic bias power on/off share the same register bits with 206 * output voltage of mic bias. when power on mic bias, we 207 * need reclaim it to voltage value. 208 * 0x0 = Powered off 209 * 0x1 = MICBIAS output is powered to 2.0V, 210 * 0x2 = MICBIAS output is powered to 2.5V 211 * 0x3 = MICBIAS output is connected to AVDD 212 */ 213 static int mic_bias_event(struct snd_soc_dapm_widget *w, 214 struct snd_kcontrol *kcontrol, int event) 215 { 216 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 217 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 218 219 switch (event) { 220 case SND_SOC_DAPM_POST_PMU: 221 /* change mic bias voltage to user defined */ 222 snd_soc_update_bits(codec, MICBIAS_CTRL, 223 MICBIAS_LEVEL_MASK, 224 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT); 225 break; 226 227 case SND_SOC_DAPM_PRE_PMD: 228 snd_soc_update_bits(codec, MICBIAS_CTRL, 229 MICBIAS_LEVEL_MASK, 0); 230 break; 231 } 232 return 0; 233 } 234 235 static const char * const aic3x_left_dac_mux[] = { 236 "DAC_L1", "DAC_L3", "DAC_L2" }; 237 static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6, 238 aic3x_left_dac_mux); 239 240 static const char * const aic3x_right_dac_mux[] = { 241 "DAC_R1", "DAC_R3", "DAC_R2" }; 242 static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4, 243 aic3x_right_dac_mux); 244 245 static const char * const aic3x_left_hpcom_mux[] = { 246 "differential of HPLOUT", "constant VCM", "single-ended" }; 247 static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4, 248 aic3x_left_hpcom_mux); 249 250 static const char * const aic3x_right_hpcom_mux[] = { 251 "differential of HPROUT", "constant VCM", "single-ended", 252 "differential of HPLCOM", "external feedback" }; 253 static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3, 254 aic3x_right_hpcom_mux); 255 256 static const char * const aic3x_linein_mode_mux[] = { 257 "single-ended", "differential" }; 258 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7, 259 aic3x_linein_mode_mux); 260 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7, 261 aic3x_linein_mode_mux); 262 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7, 263 aic3x_linein_mode_mux); 264 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7, 265 aic3x_linein_mode_mux); 266 static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7, 267 aic3x_linein_mode_mux); 268 static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7, 269 aic3x_linein_mode_mux); 270 271 static const char * const aic3x_adc_hpf[] = { 272 "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; 273 static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4, 274 aic3x_adc_hpf); 275 276 static const char * const aic3x_agc_level[] = { 277 "-5.5dB", "-8dB", "-10dB", "-12dB", 278 "-14dB", "-17dB", "-20dB", "-24dB" }; 279 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4, 280 aic3x_agc_level); 281 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4, 282 aic3x_agc_level); 283 284 static const char * const aic3x_agc_attack[] = { 285 "8ms", "11ms", "16ms", "20ms" }; 286 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2, 287 aic3x_agc_attack); 288 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2, 289 aic3x_agc_attack); 290 291 static const char * const aic3x_agc_decay[] = { 292 "100ms", "200ms", "400ms", "500ms" }; 293 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0, 294 aic3x_agc_decay); 295 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0, 296 aic3x_agc_decay); 297 298 static const char * const aic3x_poweron_time[] = { 299 "0us", "10us", "100us", "1ms", "10ms", "50ms", 300 "100ms", "200ms", "400ms", "800ms", "2s", "4s" }; 301 static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4, 302 aic3x_poweron_time); 303 304 static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" }; 305 static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2, 306 aic3x_rampup_step); 307 308 /* 309 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps 310 */ 311 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); 312 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ 313 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); 314 /* 315 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. 316 * Step size is approximately 0.5 dB over most of the scale but increasing 317 * near the very low levels. 318 * Define dB scale so that it is mostly correct for range about -55 to 0 dB 319 * but having increasing dB difference below that (and where it doesn't count 320 * so much). This setting shows -50 dB (actual is -50.3 dB) for register 321 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. 322 */ 323 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); 324 325 static const struct snd_kcontrol_new aic3x_snd_controls[] = { 326 /* Output */ 327 SOC_DOUBLE_R_TLV("PCM Playback Volume", 328 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 329 330 /* 331 * Output controls that map to output mixer switches. Note these are 332 * only for swapped L-to-R and R-to-L routes. See below stereo controls 333 * for direct L-to-L and R-to-R routes. 334 */ 335 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", 336 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 337 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", 338 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 339 340 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", 341 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 342 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", 343 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 344 345 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", 346 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 347 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", 348 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 349 350 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", 351 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 352 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", 353 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 354 355 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", 356 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 357 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", 358 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 359 360 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", 361 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 362 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", 363 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 364 365 /* Stereo output controls for direct L-to-L and R-to-R routes */ 366 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", 367 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, 368 0, 118, 1, output_stage_tlv), 369 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 370 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 371 0, 118, 1, output_stage_tlv), 372 373 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", 374 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 375 0, 118, 1, output_stage_tlv), 376 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 377 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 378 0, 118, 1, output_stage_tlv), 379 380 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", 381 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, 382 0, 118, 1, output_stage_tlv), 383 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 384 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 385 0, 118, 1, output_stage_tlv), 386 387 /* Output pin mute controls */ 388 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, 389 0x01, 0), 390 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 391 0x01, 0), 392 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 393 0x01, 0), 394 395 /* 396 * Note: enable Automatic input Gain Controller with care. It can 397 * adjust PGA to max value when ADC is on and will never go back. 398 */ 399 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), 400 SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum), 401 SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum), 402 SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum), 403 SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum), 404 SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum), 405 SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum), 406 407 /* De-emphasis */ 408 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0), 409 410 /* Input */ 411 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 412 0, 119, 0, adc_tlv), 413 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), 414 415 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum), 416 417 /* Pop reduction */ 418 SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum), 419 SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum), 420 }; 421 422 /* For other than tlv320aic3104 */ 423 static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = { 424 /* 425 * Output controls that map to output mixer switches. Note these are 426 * only for swapped L-to-R and R-to-L routes. See below stereo controls 427 * for direct L-to-L and R-to-R routes. 428 */ 429 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", 430 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 431 432 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", 433 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 434 435 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", 436 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 437 438 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", 439 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 440 441 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", 442 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 443 444 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", 445 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 446 447 /* Stereo output controls for direct L-to-L and R-to-R routes */ 448 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", 449 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, 450 0, 118, 1, output_stage_tlv), 451 452 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", 453 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 454 0, 118, 1, output_stage_tlv), 455 456 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", 457 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 458 0, 118, 1, output_stage_tlv), 459 }; 460 461 static const struct snd_kcontrol_new aic3x_mono_controls[] = { 462 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", 463 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 464 0, 118, 1, output_stage_tlv), 465 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", 466 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 467 0, 118, 1, output_stage_tlv), 468 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 469 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 470 0, 118, 1, output_stage_tlv), 471 472 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 473 }; 474 475 /* 476 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps 477 */ 478 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0); 479 480 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl = 481 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv); 482 483 /* Left DAC Mux */ 484 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = 485 SOC_DAPM_ENUM("Route", aic3x_left_dac_enum); 486 487 /* Right DAC Mux */ 488 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = 489 SOC_DAPM_ENUM("Route", aic3x_right_dac_enum); 490 491 /* Left HPCOM Mux */ 492 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = 493 SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum); 494 495 /* Right HPCOM Mux */ 496 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = 497 SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum); 498 499 /* Left Line Mixer */ 500 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { 501 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), 502 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), 503 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), 504 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), 505 /* Not on tlv320aic3104 */ 506 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), 507 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), 508 }; 509 510 /* Right Line Mixer */ 511 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { 512 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), 513 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), 514 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), 515 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), 516 /* Not on tlv320aic3104 */ 517 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), 518 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), 519 }; 520 521 /* Mono Mixer */ 522 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { 523 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), 524 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), 525 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), 526 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), 527 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), 528 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), 529 }; 530 531 /* Left HP Mixer */ 532 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { 533 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), 534 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), 535 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), 536 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), 537 /* Not on tlv320aic3104 */ 538 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), 539 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), 540 }; 541 542 /* Right HP Mixer */ 543 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { 544 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), 545 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), 546 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), 547 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), 548 /* Not on tlv320aic3104 */ 549 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), 550 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), 551 }; 552 553 /* Left HPCOM Mixer */ 554 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { 555 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), 556 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), 557 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), 558 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), 559 /* Not on tlv320aic3104 */ 560 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), 561 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), 562 }; 563 564 /* Right HPCOM Mixer */ 565 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { 566 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), 567 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), 568 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), 569 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), 570 /* Not on tlv320aic3104 */ 571 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), 572 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), 573 }; 574 575 /* Left PGA Mixer */ 576 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { 577 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 578 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 579 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), 580 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 581 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 582 }; 583 584 /* Right PGA Mixer */ 585 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { 586 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 587 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 588 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), 589 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 590 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 591 }; 592 593 /* Left PGA Mixer for tlv320aic3104 */ 594 static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = { 595 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 596 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 597 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 598 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 599 }; 600 601 /* Right PGA Mixer for tlv320aic3104 */ 602 static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = { 603 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 604 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 605 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 606 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 607 }; 608 609 /* Left Line1 Mux */ 610 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls = 611 SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum); 612 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls = 613 SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum); 614 615 /* Right Line1 Mux */ 616 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls = 617 SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum); 618 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls = 619 SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum); 620 621 /* Left Line2 Mux */ 622 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = 623 SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum); 624 625 /* Right Line2 Mux */ 626 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = 627 SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum); 628 629 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { 630 /* Left DAC to Left Outputs */ 631 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), 632 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, 633 &aic3x_left_dac_mux_controls), 634 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, 635 &aic3x_left_hpcom_mux_controls), 636 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), 637 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), 638 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), 639 640 /* Right DAC to Right Outputs */ 641 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), 642 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, 643 &aic3x_right_dac_mux_controls), 644 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, 645 &aic3x_right_hpcom_mux_controls), 646 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), 647 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), 648 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), 649 650 /* Inputs to Left ADC */ 651 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), 652 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, 653 &aic3x_left_line1l_mux_controls), 654 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, 655 &aic3x_left_line1r_mux_controls), 656 657 /* Inputs to Right ADC */ 658 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 659 LINE1R_2_RADC_CTRL, 2, 0), 660 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, 661 &aic3x_right_line1l_mux_controls), 662 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, 663 &aic3x_right_line1r_mux_controls), 664 665 /* Mic Bias */ 666 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0, 667 mic_bias_event, 668 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 669 670 SND_SOC_DAPM_OUTPUT("LLOUT"), 671 SND_SOC_DAPM_OUTPUT("RLOUT"), 672 SND_SOC_DAPM_OUTPUT("HPLOUT"), 673 SND_SOC_DAPM_OUTPUT("HPROUT"), 674 SND_SOC_DAPM_OUTPUT("HPLCOM"), 675 SND_SOC_DAPM_OUTPUT("HPRCOM"), 676 677 SND_SOC_DAPM_INPUT("LINE1L"), 678 SND_SOC_DAPM_INPUT("LINE1R"), 679 680 /* 681 * Virtual output pin to detection block inside codec. This can be 682 * used to keep codec bias on if gpio or detection features are needed. 683 * Force pin on or construct a path with an input jack and mic bias 684 * widgets. 685 */ 686 SND_SOC_DAPM_OUTPUT("Detection"), 687 }; 688 689 /* For other than tlv320aic3104 */ 690 static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = { 691 /* Inputs to Left ADC */ 692 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 693 &aic3x_left_pga_mixer_controls[0], 694 ARRAY_SIZE(aic3x_left_pga_mixer_controls)), 695 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, 696 &aic3x_left_line2_mux_controls), 697 698 /* Inputs to Right ADC */ 699 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 700 &aic3x_right_pga_mixer_controls[0], 701 ARRAY_SIZE(aic3x_right_pga_mixer_controls)), 702 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, 703 &aic3x_right_line2_mux_controls), 704 705 /* 706 * Not a real mic bias widget but similar function. This is for dynamic 707 * control of GPIO1 digital mic modulator clock output function when 708 * using digital mic. 709 */ 710 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", 711 AIC3X_GPIO1_REG, 4, 0xf, 712 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, 713 AIC3X_GPIO1_FUNC_DISABLED), 714 715 /* 716 * Also similar function like mic bias. Selects digital mic with 717 * configurable oversampling rate instead of ADC converter. 718 */ 719 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", 720 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), 721 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", 722 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), 723 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", 724 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 725 726 /* Output mixers */ 727 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 728 &aic3x_left_line_mixer_controls[0], 729 ARRAY_SIZE(aic3x_left_line_mixer_controls)), 730 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 731 &aic3x_right_line_mixer_controls[0], 732 ARRAY_SIZE(aic3x_right_line_mixer_controls)), 733 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 734 &aic3x_left_hp_mixer_controls[0], 735 ARRAY_SIZE(aic3x_left_hp_mixer_controls)), 736 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 737 &aic3x_right_hp_mixer_controls[0], 738 ARRAY_SIZE(aic3x_right_hp_mixer_controls)), 739 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 740 &aic3x_left_hpcom_mixer_controls[0], 741 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), 742 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 743 &aic3x_right_hpcom_mixer_controls[0], 744 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), 745 746 SND_SOC_DAPM_INPUT("MIC3L"), 747 SND_SOC_DAPM_INPUT("MIC3R"), 748 SND_SOC_DAPM_INPUT("LINE2L"), 749 SND_SOC_DAPM_INPUT("LINE2R"), 750 }; 751 752 /* For tlv320aic3104 */ 753 static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = { 754 /* Inputs to Left ADC */ 755 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 756 &aic3104_left_pga_mixer_controls[0], 757 ARRAY_SIZE(aic3104_left_pga_mixer_controls)), 758 759 /* Inputs to Right ADC */ 760 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 761 &aic3104_right_pga_mixer_controls[0], 762 ARRAY_SIZE(aic3104_right_pga_mixer_controls)), 763 764 /* Output mixers */ 765 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 766 &aic3x_left_line_mixer_controls[0], 767 ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2), 768 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 769 &aic3x_right_line_mixer_controls[0], 770 ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2), 771 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 772 &aic3x_left_hp_mixer_controls[0], 773 ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2), 774 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 775 &aic3x_right_hp_mixer_controls[0], 776 ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2), 777 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 778 &aic3x_left_hpcom_mixer_controls[0], 779 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2), 780 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 781 &aic3x_right_hpcom_mixer_controls[0], 782 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2), 783 784 SND_SOC_DAPM_INPUT("MIC2L"), 785 SND_SOC_DAPM_INPUT("MIC2R"), 786 }; 787 788 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = { 789 /* Mono Output */ 790 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), 791 792 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, 793 &aic3x_mono_mixer_controls[0], 794 ARRAY_SIZE(aic3x_mono_mixer_controls)), 795 796 SND_SOC_DAPM_OUTPUT("MONO_LOUT"), 797 }; 798 799 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { 800 /* Class-D outputs */ 801 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0), 802 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0), 803 804 SND_SOC_DAPM_OUTPUT("SPOP"), 805 SND_SOC_DAPM_OUTPUT("SPOM"), 806 }; 807 808 static const struct snd_soc_dapm_route intercon[] = { 809 /* Left Input */ 810 {"Left Line1L Mux", "single-ended", "LINE1L"}, 811 {"Left Line1L Mux", "differential", "LINE1L"}, 812 {"Left Line1R Mux", "single-ended", "LINE1R"}, 813 {"Left Line1R Mux", "differential", "LINE1R"}, 814 815 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, 816 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, 817 818 {"Left ADC", NULL, "Left PGA Mixer"}, 819 820 /* Right Input */ 821 {"Right Line1R Mux", "single-ended", "LINE1R"}, 822 {"Right Line1R Mux", "differential", "LINE1R"}, 823 {"Right Line1L Mux", "single-ended", "LINE1L"}, 824 {"Right Line1L Mux", "differential", "LINE1L"}, 825 826 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, 827 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, 828 829 {"Right ADC", NULL, "Right PGA Mixer"}, 830 831 /* Left DAC Output */ 832 {"Left DAC Mux", "DAC_L1", "Left DAC"}, 833 {"Left DAC Mux", "DAC_L2", "Left DAC"}, 834 {"Left DAC Mux", "DAC_L3", "Left DAC"}, 835 836 /* Right DAC Output */ 837 {"Right DAC Mux", "DAC_R1", "Right DAC"}, 838 {"Right DAC Mux", "DAC_R2", "Right DAC"}, 839 {"Right DAC Mux", "DAC_R3", "Right DAC"}, 840 841 /* Left Line Output */ 842 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 843 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 844 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 845 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 846 847 {"Left Line Out", NULL, "Left Line Mixer"}, 848 {"Left Line Out", NULL, "Left DAC Mux"}, 849 {"LLOUT", NULL, "Left Line Out"}, 850 851 /* Right Line Output */ 852 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 853 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 854 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 855 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 856 857 {"Right Line Out", NULL, "Right Line Mixer"}, 858 {"Right Line Out", NULL, "Right DAC Mux"}, 859 {"RLOUT", NULL, "Right Line Out"}, 860 861 /* Left HP Output */ 862 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 863 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 864 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 865 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 866 867 {"Left HP Out", NULL, "Left HP Mixer"}, 868 {"Left HP Out", NULL, "Left DAC Mux"}, 869 {"HPLOUT", NULL, "Left HP Out"}, 870 871 /* Right HP Output */ 872 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 873 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 874 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 875 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 876 877 {"Right HP Out", NULL, "Right HP Mixer"}, 878 {"Right HP Out", NULL, "Right DAC Mux"}, 879 {"HPROUT", NULL, "Right HP Out"}, 880 881 /* Left HPCOM Output */ 882 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 883 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 884 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 885 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 886 887 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, 888 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, 889 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, 890 {"Left HP Com", NULL, "Left HPCOM Mux"}, 891 {"HPLCOM", NULL, "Left HP Com"}, 892 893 /* Right HPCOM Output */ 894 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 895 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 896 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 897 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 898 899 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, 900 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, 901 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, 902 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, 903 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, 904 {"Right HP Com", NULL, "Right HPCOM Mux"}, 905 {"HPRCOM", NULL, "Right HP Com"}, 906 }; 907 908 /* For other than tlv320aic3104 */ 909 static const struct snd_soc_dapm_route intercon_extra[] = { 910 /* Left Input */ 911 {"Left Line2L Mux", "single-ended", "LINE2L"}, 912 {"Left Line2L Mux", "differential", "LINE2L"}, 913 914 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, 915 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, 916 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, 917 918 {"Left ADC", NULL, "GPIO1 dmic modclk"}, 919 920 /* Right Input */ 921 {"Right Line2R Mux", "single-ended", "LINE2R"}, 922 {"Right Line2R Mux", "differential", "LINE2R"}, 923 924 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, 925 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, 926 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, 927 928 {"Right ADC", NULL, "GPIO1 dmic modclk"}, 929 930 /* 931 * Logical path between digital mic enable and GPIO1 modulator clock 932 * output function 933 */ 934 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, 935 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, 936 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, 937 938 /* Left Line Output */ 939 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 940 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 941 942 /* Right Line Output */ 943 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 944 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 945 946 /* Left HP Output */ 947 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 948 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 949 950 /* Right HP Output */ 951 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 952 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 953 954 /* Left HPCOM Output */ 955 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 956 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 957 958 /* Right HPCOM Output */ 959 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 960 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 961 }; 962 963 /* For tlv320aic3104 */ 964 static const struct snd_soc_dapm_route intercon_extra_3104[] = { 965 /* Left Input */ 966 {"Left PGA Mixer", "Mic2L Switch", "MIC2L"}, 967 {"Left PGA Mixer", "Mic2R Switch", "MIC2R"}, 968 969 /* Right Input */ 970 {"Right PGA Mixer", "Mic2L Switch", "MIC2L"}, 971 {"Right PGA Mixer", "Mic2R Switch", "MIC2R"}, 972 }; 973 974 static const struct snd_soc_dapm_route intercon_mono[] = { 975 /* Mono Output */ 976 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 977 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 978 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, 979 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 980 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 981 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, 982 {"Mono Out", NULL, "Mono Mixer"}, 983 {"MONO_LOUT", NULL, "Mono Out"}, 984 }; 985 986 static const struct snd_soc_dapm_route intercon_3007[] = { 987 /* Class-D outputs */ 988 {"Left Class-D Out", NULL, "Left Line Out"}, 989 {"Right Class-D Out", NULL, "Left Line Out"}, 990 {"SPOP", NULL, "Left Class-D Out"}, 991 {"SPOM", NULL, "Right Class-D Out"}, 992 }; 993 994 static int aic3x_add_widgets(struct snd_soc_codec *codec) 995 { 996 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 997 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 998 999 switch (aic3x->model) { 1000 case AIC3X_MODEL_3X: 1001 case AIC3X_MODEL_33: 1002 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets, 1003 ARRAY_SIZE(aic3x_extra_dapm_widgets)); 1004 snd_soc_dapm_add_routes(dapm, intercon_extra, 1005 ARRAY_SIZE(intercon_extra)); 1006 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets, 1007 ARRAY_SIZE(aic3x_dapm_mono_widgets)); 1008 snd_soc_dapm_add_routes(dapm, intercon_mono, 1009 ARRAY_SIZE(intercon_mono)); 1010 break; 1011 case AIC3X_MODEL_3007: 1012 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets, 1013 ARRAY_SIZE(aic3x_extra_dapm_widgets)); 1014 snd_soc_dapm_add_routes(dapm, intercon_extra, 1015 ARRAY_SIZE(intercon_extra)); 1016 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, 1017 ARRAY_SIZE(aic3007_dapm_widgets)); 1018 snd_soc_dapm_add_routes(dapm, intercon_3007, 1019 ARRAY_SIZE(intercon_3007)); 1020 break; 1021 case AIC3X_MODEL_3104: 1022 snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets, 1023 ARRAY_SIZE(aic3104_extra_dapm_widgets)); 1024 snd_soc_dapm_add_routes(dapm, intercon_extra_3104, 1025 ARRAY_SIZE(intercon_extra_3104)); 1026 break; 1027 } 1028 1029 return 0; 1030 } 1031 1032 static int aic3x_hw_params(struct snd_pcm_substream *substream, 1033 struct snd_pcm_hw_params *params, 1034 struct snd_soc_dai *dai) 1035 { 1036 struct snd_soc_codec *codec = dai->codec; 1037 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1038 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 1039 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 1040 u16 d, pll_d = 1; 1041 int clk; 1042 int width = aic3x->slot_width; 1043 1044 if (!width) 1045 width = params_width(params); 1046 1047 /* select data word length */ 1048 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); 1049 switch (width) { 1050 case 16: 1051 break; 1052 case 20: 1053 data |= (0x01 << 4); 1054 break; 1055 case 24: 1056 data |= (0x02 << 4); 1057 break; 1058 case 32: 1059 data |= (0x03 << 4); 1060 break; 1061 } 1062 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data); 1063 1064 /* Fsref can be 44100 or 48000 */ 1065 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; 1066 1067 /* Try to find a value for Q which allows us to bypass the PLL and 1068 * generate CODEC_CLK directly. */ 1069 for (pll_q = 2; pll_q < 18; pll_q++) 1070 if (aic3x->sysclk / (128 * pll_q) == fsref) { 1071 bypass_pll = 1; 1072 break; 1073 } 1074 1075 if (bypass_pll) { 1076 pll_q &= 0xf; 1077 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 1078 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 1079 /* disable PLL if it is bypassed */ 1080 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); 1081 1082 } else { 1083 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 1084 /* enable PLL when it is used */ 1085 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1086 PLL_ENABLE, PLL_ENABLE); 1087 } 1088 1089 /* Route Left DAC to left channel input and 1090 * right DAC to right channel input */ 1091 data = (LDAC2LCH | RDAC2RCH); 1092 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; 1093 if (params_rate(params) >= 64000) 1094 data |= DUAL_RATE_MODE; 1095 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data); 1096 1097 /* codec sample rate select */ 1098 data = (fsref * 20) / params_rate(params); 1099 if (params_rate(params) < 64000) 1100 data /= 2; 1101 data /= 5; 1102 data -= 2; 1103 data |= (data << 4); 1104 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); 1105 1106 if (bypass_pll) 1107 return 0; 1108 1109 /* Use PLL, compute appropriate setup for j, d, r and p, the closest 1110 * one wins the game. Try with d==0 first, next with d!=0. 1111 * Constraints for j are according to the datasheet. 1112 * The sysclk is divided by 1000 to prevent integer overflows. 1113 */ 1114 1115 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); 1116 1117 for (r = 1; r <= 16; r++) 1118 for (p = 1; p <= 8; p++) { 1119 for (j = 4; j <= 55; j++) { 1120 /* This is actually 1000*((j+(d/10000))*r)/p 1121 * The term had to be converted to get 1122 * rid of the division by 10000; d = 0 here 1123 */ 1124 int tmp_clk = (1000 * j * r) / p; 1125 1126 /* Check whether this values get closer than 1127 * the best ones we had before 1128 */ 1129 if (abs(codec_clk - tmp_clk) < 1130 abs(codec_clk - last_clk)) { 1131 pll_j = j; pll_d = 0; 1132 pll_r = r; pll_p = p; 1133 last_clk = tmp_clk; 1134 } 1135 1136 /* Early exit for exact matches */ 1137 if (tmp_clk == codec_clk) 1138 goto found; 1139 } 1140 } 1141 1142 /* try with d != 0 */ 1143 for (p = 1; p <= 8; p++) { 1144 j = codec_clk * p / 1000; 1145 1146 if (j < 4 || j > 11) 1147 continue; 1148 1149 /* do not use codec_clk here since we'd loose precision */ 1150 d = ((2048 * p * fsref) - j * aic3x->sysclk) 1151 * 100 / (aic3x->sysclk/100); 1152 1153 clk = (10000 * j + d) / (10 * p); 1154 1155 /* check whether this values get closer than the best 1156 * ones we had before */ 1157 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { 1158 pll_j = j; pll_d = d; pll_r = 1; pll_p = p; 1159 last_clk = clk; 1160 } 1161 1162 /* Early exit for exact matches */ 1163 if (clk == codec_clk) 1164 goto found; 1165 } 1166 1167 if (last_clk == 0) { 1168 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); 1169 return -EINVAL; 1170 } 1171 1172 found: 1173 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p); 1174 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, 1175 pll_r << PLLR_SHIFT); 1176 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); 1177 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, 1178 (pll_d >> 6) << PLLD_MSB_SHIFT); 1179 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, 1180 (pll_d & 0x3F) << PLLD_LSB_SHIFT); 1181 1182 return 0; 1183 } 1184 1185 static int aic3x_prepare(struct snd_pcm_substream *substream, 1186 struct snd_soc_dai *dai) 1187 { 1188 struct snd_soc_codec *codec = dai->codec; 1189 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1190 int delay = 0; 1191 int width = aic3x->slot_width; 1192 1193 if (!width) 1194 width = substream->runtime->sample_bits; 1195 1196 /* TDM slot selection only valid in DSP_A/_B mode */ 1197 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A) 1198 delay += (aic3x->tdm_delay*width + 1); 1199 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B) 1200 delay += aic3x->tdm_delay*width; 1201 1202 /* Configure data delay */ 1203 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay); 1204 1205 return 0; 1206 } 1207 1208 static int aic3x_mute(struct snd_soc_dai *dai, int mute) 1209 { 1210 struct snd_soc_codec *codec = dai->codec; 1211 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON; 1212 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON; 1213 1214 if (mute) { 1215 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); 1216 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); 1217 } else { 1218 snd_soc_write(codec, LDAC_VOL, ldac_reg); 1219 snd_soc_write(codec, RDAC_VOL, rdac_reg); 1220 } 1221 1222 return 0; 1223 } 1224 1225 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1226 int clk_id, unsigned int freq, int dir) 1227 { 1228 struct snd_soc_codec *codec = codec_dai->codec; 1229 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1230 1231 /* set clock on MCLK or GPIO2 or BCLK */ 1232 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, 1233 clk_id << PLLCLK_IN_SHIFT); 1234 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, 1235 clk_id << CLKDIV_IN_SHIFT); 1236 1237 aic3x->sysclk = freq; 1238 return 0; 1239 } 1240 1241 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, 1242 unsigned int fmt) 1243 { 1244 struct snd_soc_codec *codec = codec_dai->codec; 1245 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1246 u8 iface_areg, iface_breg; 1247 1248 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; 1249 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; 1250 1251 /* set master/slave audio interface */ 1252 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1253 case SND_SOC_DAIFMT_CBM_CFM: 1254 aic3x->master = 1; 1255 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; 1256 break; 1257 case SND_SOC_DAIFMT_CBS_CFS: 1258 aic3x->master = 0; 1259 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER); 1260 break; 1261 default: 1262 return -EINVAL; 1263 } 1264 1265 /* 1266 * match both interface format and signal polarities since they 1267 * are fixed 1268 */ 1269 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | 1270 SND_SOC_DAIFMT_INV_MASK)) { 1271 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): 1272 break; 1273 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): 1274 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): 1275 iface_breg |= (0x01 << 6); 1276 break; 1277 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): 1278 iface_breg |= (0x02 << 6); 1279 break; 1280 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): 1281 iface_breg |= (0x03 << 6); 1282 break; 1283 default: 1284 return -EINVAL; 1285 } 1286 1287 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 1288 1289 /* set iface */ 1290 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); 1291 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); 1292 1293 return 0; 1294 } 1295 1296 static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai, 1297 unsigned int tx_mask, unsigned int rx_mask, 1298 int slots, int slot_width) 1299 { 1300 struct snd_soc_codec *codec = codec_dai->codec; 1301 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1302 unsigned int lsb; 1303 1304 if (tx_mask != rx_mask) { 1305 dev_err(codec->dev, "tx and rx masks must be symmetric\n"); 1306 return -EINVAL; 1307 } 1308 1309 if (unlikely(!tx_mask)) { 1310 dev_err(codec->dev, "tx and rx masks need to be non 0\n"); 1311 return -EINVAL; 1312 } 1313 1314 /* TDM based on DSP mode requires slots to be adjacent */ 1315 lsb = __ffs(tx_mask); 1316 if ((lsb + 1) != __fls(tx_mask)) { 1317 dev_err(codec->dev, "Invalid mask, slots must be adjacent\n"); 1318 return -EINVAL; 1319 } 1320 1321 switch (slot_width) { 1322 case 16: 1323 case 20: 1324 case 24: 1325 case 32: 1326 break; 1327 default: 1328 dev_err(codec->dev, "Unsupported slot width %d\n", slot_width); 1329 return -EINVAL; 1330 } 1331 1332 1333 aic3x->tdm_delay = lsb; 1334 aic3x->slot_width = slot_width; 1335 1336 /* DOUT in high-impedance on inactive bit clocks */ 1337 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA, 1338 DOUT_TRISTATE, DOUT_TRISTATE); 1339 1340 return 0; 1341 } 1342 1343 static int aic3x_regulator_event(struct notifier_block *nb, 1344 unsigned long event, void *data) 1345 { 1346 struct aic3x_disable_nb *disable_nb = 1347 container_of(nb, struct aic3x_disable_nb, nb); 1348 struct aic3x_priv *aic3x = disable_nb->aic3x; 1349 1350 if (event & REGULATOR_EVENT_DISABLE) { 1351 /* 1352 * Put codec to reset and require cache sync as at least one 1353 * of the supplies was disabled 1354 */ 1355 if (gpio_is_valid(aic3x->gpio_reset)) 1356 gpio_set_value(aic3x->gpio_reset, 0); 1357 regcache_mark_dirty(aic3x->regmap); 1358 } 1359 1360 return 0; 1361 } 1362 1363 static int aic3x_set_power(struct snd_soc_codec *codec, int power) 1364 { 1365 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1366 unsigned int pll_c, pll_d; 1367 int ret; 1368 1369 if (power) { 1370 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), 1371 aic3x->supplies); 1372 if (ret) 1373 goto out; 1374 aic3x->power = 1; 1375 1376 if (gpio_is_valid(aic3x->gpio_reset)) { 1377 udelay(1); 1378 gpio_set_value(aic3x->gpio_reset, 1); 1379 } 1380 1381 /* Sync reg_cache with the hardware */ 1382 regcache_cache_only(aic3x->regmap, false); 1383 regcache_sync(aic3x->regmap); 1384 1385 /* Rewrite paired PLL D registers in case cached sync skipped 1386 * writing one of them and thus caused other one also not 1387 * being written 1388 */ 1389 pll_c = snd_soc_read(codec, AIC3X_PLL_PROGC_REG); 1390 pll_d = snd_soc_read(codec, AIC3X_PLL_PROGD_REG); 1391 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def || 1392 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) { 1393 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, pll_c); 1394 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, pll_d); 1395 } 1396 1397 /* 1398 * Delay is needed to reduce pop-noise after syncing back the 1399 * registers 1400 */ 1401 mdelay(50); 1402 } else { 1403 /* 1404 * Do soft reset to this codec instance in order to clear 1405 * possible VDD leakage currents in case the supply regulators 1406 * remain on 1407 */ 1408 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1409 regcache_mark_dirty(aic3x->regmap); 1410 aic3x->power = 0; 1411 /* HW writes are needless when bias is off */ 1412 regcache_cache_only(aic3x->regmap, true); 1413 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), 1414 aic3x->supplies); 1415 } 1416 out: 1417 return ret; 1418 } 1419 1420 static int aic3x_set_bias_level(struct snd_soc_codec *codec, 1421 enum snd_soc_bias_level level) 1422 { 1423 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1424 1425 switch (level) { 1426 case SND_SOC_BIAS_ON: 1427 break; 1428 case SND_SOC_BIAS_PREPARE: 1429 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY && 1430 aic3x->master) { 1431 /* enable pll */ 1432 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1433 PLL_ENABLE, PLL_ENABLE); 1434 } 1435 break; 1436 case SND_SOC_BIAS_STANDBY: 1437 if (!aic3x->power) 1438 aic3x_set_power(codec, 1); 1439 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE && 1440 aic3x->master) { 1441 /* disable pll */ 1442 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1443 PLL_ENABLE, 0); 1444 } 1445 break; 1446 case SND_SOC_BIAS_OFF: 1447 if (aic3x->power) 1448 aic3x_set_power(codec, 0); 1449 break; 1450 } 1451 1452 return 0; 1453 } 1454 1455 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1456 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1457 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1458 SNDRV_PCM_FMTBIT_S32_LE) 1459 1460 static const struct snd_soc_dai_ops aic3x_dai_ops = { 1461 .hw_params = aic3x_hw_params, 1462 .prepare = aic3x_prepare, 1463 .digital_mute = aic3x_mute, 1464 .set_sysclk = aic3x_set_dai_sysclk, 1465 .set_fmt = aic3x_set_dai_fmt, 1466 .set_tdm_slot = aic3x_set_dai_tdm_slot, 1467 }; 1468 1469 static struct snd_soc_dai_driver aic3x_dai = { 1470 .name = "tlv320aic3x-hifi", 1471 .playback = { 1472 .stream_name = "Playback", 1473 .channels_min = 2, 1474 .channels_max = 2, 1475 .rates = AIC3X_RATES, 1476 .formats = AIC3X_FORMATS,}, 1477 .capture = { 1478 .stream_name = "Capture", 1479 .channels_min = 2, 1480 .channels_max = 2, 1481 .rates = AIC3X_RATES, 1482 .formats = AIC3X_FORMATS,}, 1483 .ops = &aic3x_dai_ops, 1484 .symmetric_rates = 1, 1485 }; 1486 1487 static void aic3x_mono_init(struct snd_soc_codec *codec) 1488 { 1489 /* DAC to Mono Line Out default volume and route to Output mixer */ 1490 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1491 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1492 1493 /* unmute all outputs */ 1494 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE); 1495 1496 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ 1497 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); 1498 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); 1499 1500 /* Line2 to Mono Out default volume, disconnect from Output Mixer */ 1501 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); 1502 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); 1503 } 1504 1505 /* 1506 * initialise the AIC3X driver 1507 * register the mixer and dsp interfaces with the kernel 1508 */ 1509 static int aic3x_init(struct snd_soc_codec *codec) 1510 { 1511 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1512 1513 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); 1514 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1515 1516 /* DAC default volume and mute */ 1517 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); 1518 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); 1519 1520 /* DAC to HP default volume and route to Output mixer */ 1521 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); 1522 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); 1523 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1524 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1525 /* DAC to Line Out default volume and route to Output mixer */ 1526 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1527 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1528 1529 /* unmute all outputs */ 1530 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE); 1531 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE); 1532 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE); 1533 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE); 1534 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE); 1535 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE); 1536 1537 /* ADC default volume and unmute */ 1538 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN); 1539 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN); 1540 /* By default route Line1 to ADC PGA mixer */ 1541 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0); 1542 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0); 1543 1544 /* PGA to HP Bypass default volume, disconnect from Output Mixer */ 1545 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); 1546 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); 1547 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); 1548 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); 1549 /* PGA to Line Out default volume, disconnect from Output Mixer */ 1550 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); 1551 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); 1552 1553 /* On tlv320aic3104, these registers are reserved and must not be written */ 1554 if (aic3x->model != AIC3X_MODEL_3104) { 1555 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ 1556 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); 1557 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); 1558 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); 1559 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); 1560 /* Line2 Line Out default volume, disconnect from Output Mixer */ 1561 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); 1562 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); 1563 } 1564 1565 switch (aic3x->model) { 1566 case AIC3X_MODEL_3X: 1567 case AIC3X_MODEL_33: 1568 aic3x_mono_init(codec); 1569 break; 1570 case AIC3X_MODEL_3007: 1571 snd_soc_write(codec, CLASSD_CTRL, 0); 1572 break; 1573 } 1574 1575 return 0; 1576 } 1577 1578 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x) 1579 { 1580 struct aic3x_priv *a; 1581 1582 list_for_each_entry(a, &reset_list, list) { 1583 if (gpio_is_valid(aic3x->gpio_reset) && 1584 aic3x->gpio_reset == a->gpio_reset) 1585 return true; 1586 } 1587 1588 return false; 1589 } 1590 1591 static int aic3x_probe(struct snd_soc_codec *codec) 1592 { 1593 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1594 int ret, i; 1595 1596 INIT_LIST_HEAD(&aic3x->list); 1597 aic3x->codec = codec; 1598 1599 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) { 1600 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; 1601 aic3x->disable_nb[i].aic3x = aic3x; 1602 ret = regulator_register_notifier(aic3x->supplies[i].consumer, 1603 &aic3x->disable_nb[i].nb); 1604 if (ret) { 1605 dev_err(codec->dev, 1606 "Failed to request regulator notifier: %d\n", 1607 ret); 1608 goto err_notif; 1609 } 1610 } 1611 1612 regcache_mark_dirty(aic3x->regmap); 1613 aic3x_init(codec); 1614 1615 if (aic3x->setup) { 1616 if (aic3x->model != AIC3X_MODEL_3104) { 1617 /* setup GPIO functions */ 1618 snd_soc_write(codec, AIC3X_GPIO1_REG, 1619 (aic3x->setup->gpio_func[0] & 0xf) << 4); 1620 snd_soc_write(codec, AIC3X_GPIO2_REG, 1621 (aic3x->setup->gpio_func[1] & 0xf) << 4); 1622 } else { 1623 dev_warn(codec->dev, "GPIO functionality is not supported on tlv320aic3104\n"); 1624 } 1625 } 1626 1627 switch (aic3x->model) { 1628 case AIC3X_MODEL_3X: 1629 case AIC3X_MODEL_33: 1630 snd_soc_add_codec_controls(codec, aic3x_extra_snd_controls, 1631 ARRAY_SIZE(aic3x_extra_snd_controls)); 1632 snd_soc_add_codec_controls(codec, aic3x_mono_controls, 1633 ARRAY_SIZE(aic3x_mono_controls)); 1634 break; 1635 case AIC3X_MODEL_3007: 1636 snd_soc_add_codec_controls(codec, aic3x_extra_snd_controls, 1637 ARRAY_SIZE(aic3x_extra_snd_controls)); 1638 snd_soc_add_codec_controls(codec, 1639 &aic3x_classd_amp_gain_ctrl, 1); 1640 break; 1641 case AIC3X_MODEL_3104: 1642 break; 1643 } 1644 1645 /* set mic bias voltage */ 1646 switch (aic3x->micbias_vg) { 1647 case AIC3X_MICBIAS_2_0V: 1648 case AIC3X_MICBIAS_2_5V: 1649 case AIC3X_MICBIAS_AVDDV: 1650 snd_soc_update_bits(codec, MICBIAS_CTRL, 1651 MICBIAS_LEVEL_MASK, 1652 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT); 1653 break; 1654 case AIC3X_MICBIAS_OFF: 1655 /* 1656 * noting to do. target won't enter here. This is just to avoid 1657 * compile time warning "warning: enumeration value 1658 * 'AIC3X_MICBIAS_OFF' not handled in switch" 1659 */ 1660 break; 1661 } 1662 1663 aic3x_add_widgets(codec); 1664 1665 return 0; 1666 1667 err_notif: 1668 while (i--) 1669 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1670 &aic3x->disable_nb[i].nb); 1671 return ret; 1672 } 1673 1674 static int aic3x_remove(struct snd_soc_codec *codec) 1675 { 1676 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1677 int i; 1678 1679 list_del(&aic3x->list); 1680 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1681 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1682 &aic3x->disable_nb[i].nb); 1683 1684 return 0; 1685 } 1686 1687 static struct snd_soc_codec_driver soc_codec_dev_aic3x = { 1688 .set_bias_level = aic3x_set_bias_level, 1689 .idle_bias_off = true, 1690 .probe = aic3x_probe, 1691 .remove = aic3x_remove, 1692 .component_driver = { 1693 .controls = aic3x_snd_controls, 1694 .num_controls = ARRAY_SIZE(aic3x_snd_controls), 1695 .dapm_widgets = aic3x_dapm_widgets, 1696 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets), 1697 .dapm_routes = intercon, 1698 .num_dapm_routes = ARRAY_SIZE(intercon), 1699 }, 1700 }; 1701 1702 /* 1703 * AIC3X 2 wire address can be up to 4 devices with device addresses 1704 * 0x18, 0x19, 0x1A, 0x1B 1705 */ 1706 1707 static const struct i2c_device_id aic3x_i2c_id[] = { 1708 { "tlv320aic3x", AIC3X_MODEL_3X }, 1709 { "tlv320aic33", AIC3X_MODEL_33 }, 1710 { "tlv320aic3007", AIC3X_MODEL_3007 }, 1711 { "tlv320aic3106", AIC3X_MODEL_3X }, 1712 { "tlv320aic3104", AIC3X_MODEL_3104 }, 1713 { } 1714 }; 1715 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); 1716 1717 static const struct reg_sequence aic3007_class_d[] = { 1718 /* Class-D speaker driver init; datasheet p. 46 */ 1719 { AIC3X_PAGE_SELECT, 0x0D }, 1720 { 0xD, 0x0D }, 1721 { 0x8, 0x5C }, 1722 { 0x8, 0x5D }, 1723 { 0x8, 0x5C }, 1724 { AIC3X_PAGE_SELECT, 0x00 }, 1725 }; 1726 1727 /* 1728 * If the i2c layer weren't so broken, we could pass this kind of data 1729 * around 1730 */ 1731 static int aic3x_i2c_probe(struct i2c_client *i2c, 1732 const struct i2c_device_id *id) 1733 { 1734 struct aic3x_pdata *pdata = i2c->dev.platform_data; 1735 struct aic3x_priv *aic3x; 1736 struct aic3x_setup_data *ai3x_setup; 1737 struct device_node *np = i2c->dev.of_node; 1738 int ret, i; 1739 u32 value; 1740 1741 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL); 1742 if (!aic3x) 1743 return -ENOMEM; 1744 1745 aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap); 1746 if (IS_ERR(aic3x->regmap)) { 1747 ret = PTR_ERR(aic3x->regmap); 1748 return ret; 1749 } 1750 1751 regcache_cache_only(aic3x->regmap, true); 1752 1753 i2c_set_clientdata(i2c, aic3x); 1754 if (pdata) { 1755 aic3x->gpio_reset = pdata->gpio_reset; 1756 aic3x->setup = pdata->setup; 1757 aic3x->micbias_vg = pdata->micbias_vg; 1758 } else if (np) { 1759 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup), 1760 GFP_KERNEL); 1761 if (!ai3x_setup) 1762 return -ENOMEM; 1763 1764 ret = of_get_named_gpio(np, "gpio-reset", 0); 1765 if (ret >= 0) 1766 aic3x->gpio_reset = ret; 1767 else 1768 aic3x->gpio_reset = -1; 1769 1770 if (of_property_read_u32_array(np, "ai3x-gpio-func", 1771 ai3x_setup->gpio_func, 2) >= 0) { 1772 aic3x->setup = ai3x_setup; 1773 } 1774 1775 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) { 1776 switch (value) { 1777 case 1 : 1778 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V; 1779 break; 1780 case 2 : 1781 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V; 1782 break; 1783 case 3 : 1784 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV; 1785 break; 1786 default : 1787 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; 1788 dev_err(&i2c->dev, "Unsuitable MicBias voltage " 1789 "found in DT\n"); 1790 } 1791 } else { 1792 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; 1793 } 1794 1795 } else { 1796 aic3x->gpio_reset = -1; 1797 } 1798 1799 aic3x->model = id->driver_data; 1800 1801 if (gpio_is_valid(aic3x->gpio_reset) && 1802 !aic3x_is_shared_reset(aic3x)) { 1803 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); 1804 if (ret != 0) 1805 goto err; 1806 gpio_direction_output(aic3x->gpio_reset, 0); 1807 } 1808 1809 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1810 aic3x->supplies[i].supply = aic3x_supply_names[i]; 1811 1812 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies), 1813 aic3x->supplies); 1814 if (ret != 0) { 1815 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 1816 goto err_gpio; 1817 } 1818 1819 if (aic3x->model == AIC3X_MODEL_3007) { 1820 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d, 1821 ARRAY_SIZE(aic3007_class_d)); 1822 if (ret != 0) 1823 dev_err(&i2c->dev, "Failed to init class D: %d\n", 1824 ret); 1825 } 1826 1827 ret = snd_soc_register_codec(&i2c->dev, 1828 &soc_codec_dev_aic3x, &aic3x_dai, 1); 1829 1830 if (ret != 0) 1831 goto err_gpio; 1832 1833 list_add(&aic3x->list, &reset_list); 1834 1835 return 0; 1836 1837 err_gpio: 1838 if (gpio_is_valid(aic3x->gpio_reset) && 1839 !aic3x_is_shared_reset(aic3x)) 1840 gpio_free(aic3x->gpio_reset); 1841 err: 1842 return ret; 1843 } 1844 1845 static int aic3x_i2c_remove(struct i2c_client *client) 1846 { 1847 struct aic3x_priv *aic3x = i2c_get_clientdata(client); 1848 1849 snd_soc_unregister_codec(&client->dev); 1850 if (gpio_is_valid(aic3x->gpio_reset) && 1851 !aic3x_is_shared_reset(aic3x)) { 1852 gpio_set_value(aic3x->gpio_reset, 0); 1853 gpio_free(aic3x->gpio_reset); 1854 } 1855 return 0; 1856 } 1857 1858 #if defined(CONFIG_OF) 1859 static const struct of_device_id tlv320aic3x_of_match[] = { 1860 { .compatible = "ti,tlv320aic3x", }, 1861 { .compatible = "ti,tlv320aic33" }, 1862 { .compatible = "ti,tlv320aic3007" }, 1863 { .compatible = "ti,tlv320aic3106" }, 1864 { .compatible = "ti,tlv320aic3104" }, 1865 {}, 1866 }; 1867 MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match); 1868 #endif 1869 1870 /* machine i2c codec control layer */ 1871 static struct i2c_driver aic3x_i2c_driver = { 1872 .driver = { 1873 .name = "tlv320aic3x-codec", 1874 .of_match_table = of_match_ptr(tlv320aic3x_of_match), 1875 }, 1876 .probe = aic3x_i2c_probe, 1877 .remove = aic3x_i2c_remove, 1878 .id_table = aic3x_i2c_id, 1879 }; 1880 1881 module_i2c_driver(aic3x_i2c_driver); 1882 1883 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); 1884 MODULE_AUTHOR("Vladimir Barinov"); 1885 MODULE_LICENSE("GPL"); 1886