1 /* 2 * ALSA SoC TLV320AIC3X codec driver 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Notes: 14 * The AIC3X is a driver for a low power stereo audio 15 * codecs aic31, aic32, aic33, aic3007. 16 * 17 * It supports full aic33 codec functionality. 18 * The compatibility with aic32, aic31 and aic3007 is as follows: 19 * aic32/aic3007 | aic31 20 * --------------------------------------- 21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A 22 * | IN1L -> LINE1L 23 * | IN1R -> LINE1R 24 * | IN2L -> LINE2L 25 * | IN2R -> LINE2R 26 * | MIC3L/R -> N/A 27 * truncated internal functionality in 28 * accordance with documentation 29 * --------------------------------------- 30 * 31 * Hence the machine layer should disable unsupported inputs/outputs by 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/init.h> 38 #include <linux/delay.h> 39 #include <linux/pm.h> 40 #include <linux/i2c.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/of.h> 44 #include <linux/of_gpio.h> 45 #include <linux/slab.h> 46 #include <sound/core.h> 47 #include <sound/pcm.h> 48 #include <sound/pcm_params.h> 49 #include <sound/soc.h> 50 #include <sound/initval.h> 51 #include <sound/tlv.h> 52 #include <sound/tlv320aic3x.h> 53 54 #include "tlv320aic3x.h" 55 56 #define AIC3X_NUM_SUPPLIES 4 57 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { 58 "IOVDD", /* I/O Voltage */ 59 "DVDD", /* Digital Core Voltage */ 60 "AVDD", /* Analog DAC Voltage */ 61 "DRVDD", /* ADC Analog and Output Driver Voltage */ 62 }; 63 64 static LIST_HEAD(reset_list); 65 66 struct aic3x_priv; 67 68 struct aic3x_disable_nb { 69 struct notifier_block nb; 70 struct aic3x_priv *aic3x; 71 }; 72 73 /* codec private data */ 74 struct aic3x_priv { 75 struct snd_soc_codec *codec; 76 struct regmap *regmap; 77 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; 78 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES]; 79 struct aic3x_setup_data *setup; 80 unsigned int sysclk; 81 unsigned int dai_fmt; 82 unsigned int tdm_delay; 83 unsigned int slot_width; 84 struct list_head list; 85 int master; 86 int gpio_reset; 87 int power; 88 #define AIC3X_MODEL_3X 0 89 #define AIC3X_MODEL_33 1 90 #define AIC3X_MODEL_3007 2 91 #define AIC3X_MODEL_3104 3 92 u16 model; 93 94 /* Selects the micbias voltage */ 95 enum aic3x_micbias_voltage micbias_vg; 96 }; 97 98 static const struct reg_default aic3x_reg[] = { 99 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 }, 100 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 }, 101 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 }, 102 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 }, 103 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 }, 104 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 }, 105 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe }, 106 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 }, 107 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 }, 108 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 }, 109 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 }, 110 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 }, 111 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 }, 112 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 }, 113 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 }, 114 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 }, 115 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 }, 116 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 }, 117 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 }, 118 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 }, 119 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 }, 120 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 }, 121 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 }, 122 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 }, 123 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 }, 124 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 }, 125 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 }, 126 { 108, 0x00 }, { 109, 0x00 }, 127 }; 128 129 static const struct regmap_config aic3x_regmap = { 130 .reg_bits = 8, 131 .val_bits = 8, 132 133 .max_register = DAC_ICC_ADJ, 134 .reg_defaults = aic3x_reg, 135 .num_reg_defaults = ARRAY_SIZE(aic3x_reg), 136 .cache_type = REGCACHE_RBTREE, 137 }; 138 139 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ 140 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \ 141 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x) 142 143 /* 144 * All input lines are connected when !0xf and disconnected with 0xf bit field, 145 * so we have to use specific dapm_put call for input mixer 146 */ 147 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, 148 struct snd_ctl_elem_value *ucontrol) 149 { 150 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); 151 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 152 struct soc_mixer_control *mc = 153 (struct soc_mixer_control *)kcontrol->private_value; 154 unsigned int reg = mc->reg; 155 unsigned int shift = mc->shift; 156 int max = mc->max; 157 unsigned int mask = (1 << fls(max)) - 1; 158 unsigned int invert = mc->invert; 159 unsigned short val; 160 struct snd_soc_dapm_update update; 161 int connect, change; 162 163 val = (ucontrol->value.integer.value[0] & mask); 164 165 mask = 0xf; 166 if (val) 167 val = mask; 168 169 connect = !!val; 170 171 if (invert) 172 val = mask - val; 173 174 mask <<= shift; 175 val <<= shift; 176 177 change = snd_soc_test_bits(codec, reg, mask, val); 178 if (change) { 179 update.kcontrol = kcontrol; 180 update.reg = reg; 181 update.mask = mask; 182 update.val = val; 183 184 snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect, 185 &update); 186 } 187 188 return change; 189 } 190 191 /* 192 * mic bias power on/off share the same register bits with 193 * output voltage of mic bias. when power on mic bias, we 194 * need reclaim it to voltage value. 195 * 0x0 = Powered off 196 * 0x1 = MICBIAS output is powered to 2.0V, 197 * 0x2 = MICBIAS output is powered to 2.5V 198 * 0x3 = MICBIAS output is connected to AVDD 199 */ 200 static int mic_bias_event(struct snd_soc_dapm_widget *w, 201 struct snd_kcontrol *kcontrol, int event) 202 { 203 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 204 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 205 206 switch (event) { 207 case SND_SOC_DAPM_POST_PMU: 208 /* change mic bias voltage to user defined */ 209 snd_soc_update_bits(codec, MICBIAS_CTRL, 210 MICBIAS_LEVEL_MASK, 211 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT); 212 break; 213 214 case SND_SOC_DAPM_PRE_PMD: 215 snd_soc_update_bits(codec, MICBIAS_CTRL, 216 MICBIAS_LEVEL_MASK, 0); 217 break; 218 } 219 return 0; 220 } 221 222 static const char * const aic3x_left_dac_mux[] = { 223 "DAC_L1", "DAC_L3", "DAC_L2" }; 224 static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6, 225 aic3x_left_dac_mux); 226 227 static const char * const aic3x_right_dac_mux[] = { 228 "DAC_R1", "DAC_R3", "DAC_R2" }; 229 static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4, 230 aic3x_right_dac_mux); 231 232 static const char * const aic3x_left_hpcom_mux[] = { 233 "differential of HPLOUT", "constant VCM", "single-ended" }; 234 static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4, 235 aic3x_left_hpcom_mux); 236 237 static const char * const aic3x_right_hpcom_mux[] = { 238 "differential of HPROUT", "constant VCM", "single-ended", 239 "differential of HPLCOM", "external feedback" }; 240 static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3, 241 aic3x_right_hpcom_mux); 242 243 static const char * const aic3x_linein_mode_mux[] = { 244 "single-ended", "differential" }; 245 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7, 246 aic3x_linein_mode_mux); 247 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7, 248 aic3x_linein_mode_mux); 249 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7, 250 aic3x_linein_mode_mux); 251 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7, 252 aic3x_linein_mode_mux); 253 static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7, 254 aic3x_linein_mode_mux); 255 static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7, 256 aic3x_linein_mode_mux); 257 258 static const char * const aic3x_adc_hpf[] = { 259 "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; 260 static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4, 261 aic3x_adc_hpf); 262 263 static const char * const aic3x_agc_level[] = { 264 "-5.5dB", "-8dB", "-10dB", "-12dB", 265 "-14dB", "-17dB", "-20dB", "-24dB" }; 266 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4, 267 aic3x_agc_level); 268 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4, 269 aic3x_agc_level); 270 271 static const char * const aic3x_agc_attack[] = { 272 "8ms", "11ms", "16ms", "20ms" }; 273 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2, 274 aic3x_agc_attack); 275 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2, 276 aic3x_agc_attack); 277 278 static const char * const aic3x_agc_decay[] = { 279 "100ms", "200ms", "400ms", "500ms" }; 280 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0, 281 aic3x_agc_decay); 282 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0, 283 aic3x_agc_decay); 284 285 static const char * const aic3x_poweron_time[] = { 286 "0us", "10us", "100us", "1ms", "10ms", "50ms", 287 "100ms", "200ms", "400ms", "800ms", "2s", "4s" }; 288 static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4, 289 aic3x_poweron_time); 290 291 static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" }; 292 static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2, 293 aic3x_rampup_step); 294 295 /* 296 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps 297 */ 298 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); 299 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ 300 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); 301 /* 302 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. 303 * Step size is approximately 0.5 dB over most of the scale but increasing 304 * near the very low levels. 305 * Define dB scale so that it is mostly correct for range about -55 to 0 dB 306 * but having increasing dB difference below that (and where it doesn't count 307 * so much). This setting shows -50 dB (actual is -50.3 dB) for register 308 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. 309 */ 310 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); 311 312 static const struct snd_kcontrol_new aic3x_snd_controls[] = { 313 /* Output */ 314 SOC_DOUBLE_R_TLV("PCM Playback Volume", 315 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 316 317 /* 318 * Output controls that map to output mixer switches. Note these are 319 * only for swapped L-to-R and R-to-L routes. See below stereo controls 320 * for direct L-to-L and R-to-R routes. 321 */ 322 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", 323 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 324 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", 325 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 326 327 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", 328 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 329 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", 330 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 331 332 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", 333 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 334 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", 335 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 336 337 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", 338 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 339 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", 340 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 341 342 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", 343 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 344 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", 345 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 346 347 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", 348 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 349 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", 350 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 351 352 /* Stereo output controls for direct L-to-L and R-to-R routes */ 353 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", 354 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, 355 0, 118, 1, output_stage_tlv), 356 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 357 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 358 0, 118, 1, output_stage_tlv), 359 360 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", 361 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 362 0, 118, 1, output_stage_tlv), 363 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 364 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 365 0, 118, 1, output_stage_tlv), 366 367 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", 368 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, 369 0, 118, 1, output_stage_tlv), 370 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 371 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 372 0, 118, 1, output_stage_tlv), 373 374 /* Output pin mute controls */ 375 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, 376 0x01, 0), 377 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 378 0x01, 0), 379 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 380 0x01, 0), 381 382 /* 383 * Note: enable Automatic input Gain Controller with care. It can 384 * adjust PGA to max value when ADC is on and will never go back. 385 */ 386 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), 387 SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum), 388 SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum), 389 SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum), 390 SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum), 391 SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum), 392 SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum), 393 394 /* De-emphasis */ 395 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0), 396 397 /* Input */ 398 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 399 0, 119, 0, adc_tlv), 400 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), 401 402 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum), 403 404 /* Pop reduction */ 405 SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum), 406 SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum), 407 }; 408 409 /* For other than tlv320aic3104 */ 410 static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = { 411 /* 412 * Output controls that map to output mixer switches. Note these are 413 * only for swapped L-to-R and R-to-L routes. See below stereo controls 414 * for direct L-to-L and R-to-R routes. 415 */ 416 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", 417 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 418 419 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", 420 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 421 422 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", 423 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 424 425 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", 426 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 427 428 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", 429 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 430 431 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", 432 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 433 434 /* Stereo output controls for direct L-to-L and R-to-R routes */ 435 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", 436 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, 437 0, 118, 1, output_stage_tlv), 438 439 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", 440 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 441 0, 118, 1, output_stage_tlv), 442 443 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", 444 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 445 0, 118, 1, output_stage_tlv), 446 }; 447 448 static const struct snd_kcontrol_new aic3x_mono_controls[] = { 449 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", 450 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 451 0, 118, 1, output_stage_tlv), 452 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", 453 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 454 0, 118, 1, output_stage_tlv), 455 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 456 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 457 0, 118, 1, output_stage_tlv), 458 459 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 460 }; 461 462 /* 463 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps 464 */ 465 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0); 466 467 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl = 468 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv); 469 470 /* Left DAC Mux */ 471 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = 472 SOC_DAPM_ENUM("Route", aic3x_left_dac_enum); 473 474 /* Right DAC Mux */ 475 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = 476 SOC_DAPM_ENUM("Route", aic3x_right_dac_enum); 477 478 /* Left HPCOM Mux */ 479 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = 480 SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum); 481 482 /* Right HPCOM Mux */ 483 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = 484 SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum); 485 486 /* Left Line Mixer */ 487 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { 488 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), 489 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), 490 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), 491 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), 492 /* Not on tlv320aic3104 */ 493 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), 494 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), 495 }; 496 497 /* Right Line Mixer */ 498 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { 499 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), 500 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), 501 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), 502 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), 503 /* Not on tlv320aic3104 */ 504 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), 505 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), 506 }; 507 508 /* Mono Mixer */ 509 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { 510 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), 511 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), 512 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), 513 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), 514 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), 515 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), 516 }; 517 518 /* Left HP Mixer */ 519 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { 520 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), 521 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), 522 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), 523 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), 524 /* Not on tlv320aic3104 */ 525 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), 526 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), 527 }; 528 529 /* Right HP Mixer */ 530 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { 531 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), 532 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), 533 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), 534 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), 535 /* Not on tlv320aic3104 */ 536 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), 537 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), 538 }; 539 540 /* Left HPCOM Mixer */ 541 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { 542 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), 543 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), 544 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), 545 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), 546 /* Not on tlv320aic3104 */ 547 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), 548 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), 549 }; 550 551 /* Right HPCOM Mixer */ 552 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { 553 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), 554 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), 555 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), 556 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), 557 /* Not on tlv320aic3104 */ 558 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), 559 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), 560 }; 561 562 /* Left PGA Mixer */ 563 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { 564 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 565 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 566 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), 567 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 568 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 569 }; 570 571 /* Right PGA Mixer */ 572 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { 573 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 574 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 575 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), 576 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 577 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 578 }; 579 580 /* Left PGA Mixer for tlv320aic3104 */ 581 static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = { 582 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 583 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 584 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 585 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 586 }; 587 588 /* Right PGA Mixer for tlv320aic3104 */ 589 static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = { 590 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 591 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 592 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 593 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 594 }; 595 596 /* Left Line1 Mux */ 597 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls = 598 SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum); 599 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls = 600 SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum); 601 602 /* Right Line1 Mux */ 603 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls = 604 SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum); 605 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls = 606 SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum); 607 608 /* Left Line2 Mux */ 609 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = 610 SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum); 611 612 /* Right Line2 Mux */ 613 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = 614 SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum); 615 616 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { 617 /* Left DAC to Left Outputs */ 618 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), 619 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, 620 &aic3x_left_dac_mux_controls), 621 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, 622 &aic3x_left_hpcom_mux_controls), 623 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), 624 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), 625 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), 626 627 /* Right DAC to Right Outputs */ 628 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), 629 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, 630 &aic3x_right_dac_mux_controls), 631 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, 632 &aic3x_right_hpcom_mux_controls), 633 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), 634 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), 635 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), 636 637 /* Inputs to Left ADC */ 638 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), 639 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, 640 &aic3x_left_line1l_mux_controls), 641 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, 642 &aic3x_left_line1r_mux_controls), 643 644 /* Inputs to Right ADC */ 645 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 646 LINE1R_2_RADC_CTRL, 2, 0), 647 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, 648 &aic3x_right_line1l_mux_controls), 649 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, 650 &aic3x_right_line1r_mux_controls), 651 652 /* Mic Bias */ 653 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0, 654 mic_bias_event, 655 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 656 657 SND_SOC_DAPM_OUTPUT("LLOUT"), 658 SND_SOC_DAPM_OUTPUT("RLOUT"), 659 SND_SOC_DAPM_OUTPUT("HPLOUT"), 660 SND_SOC_DAPM_OUTPUT("HPROUT"), 661 SND_SOC_DAPM_OUTPUT("HPLCOM"), 662 SND_SOC_DAPM_OUTPUT("HPRCOM"), 663 664 SND_SOC_DAPM_INPUT("LINE1L"), 665 SND_SOC_DAPM_INPUT("LINE1R"), 666 667 /* 668 * Virtual output pin to detection block inside codec. This can be 669 * used to keep codec bias on if gpio or detection features are needed. 670 * Force pin on or construct a path with an input jack and mic bias 671 * widgets. 672 */ 673 SND_SOC_DAPM_OUTPUT("Detection"), 674 }; 675 676 /* For other than tlv320aic3104 */ 677 static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = { 678 /* Inputs to Left ADC */ 679 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 680 &aic3x_left_pga_mixer_controls[0], 681 ARRAY_SIZE(aic3x_left_pga_mixer_controls)), 682 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, 683 &aic3x_left_line2_mux_controls), 684 685 /* Inputs to Right ADC */ 686 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 687 &aic3x_right_pga_mixer_controls[0], 688 ARRAY_SIZE(aic3x_right_pga_mixer_controls)), 689 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, 690 &aic3x_right_line2_mux_controls), 691 692 /* 693 * Not a real mic bias widget but similar function. This is for dynamic 694 * control of GPIO1 digital mic modulator clock output function when 695 * using digital mic. 696 */ 697 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", 698 AIC3X_GPIO1_REG, 4, 0xf, 699 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, 700 AIC3X_GPIO1_FUNC_DISABLED), 701 702 /* 703 * Also similar function like mic bias. Selects digital mic with 704 * configurable oversampling rate instead of ADC converter. 705 */ 706 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", 707 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), 708 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", 709 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), 710 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", 711 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 712 713 /* Output mixers */ 714 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 715 &aic3x_left_line_mixer_controls[0], 716 ARRAY_SIZE(aic3x_left_line_mixer_controls)), 717 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 718 &aic3x_right_line_mixer_controls[0], 719 ARRAY_SIZE(aic3x_right_line_mixer_controls)), 720 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 721 &aic3x_left_hp_mixer_controls[0], 722 ARRAY_SIZE(aic3x_left_hp_mixer_controls)), 723 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 724 &aic3x_right_hp_mixer_controls[0], 725 ARRAY_SIZE(aic3x_right_hp_mixer_controls)), 726 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 727 &aic3x_left_hpcom_mixer_controls[0], 728 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), 729 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 730 &aic3x_right_hpcom_mixer_controls[0], 731 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), 732 733 SND_SOC_DAPM_INPUT("MIC3L"), 734 SND_SOC_DAPM_INPUT("MIC3R"), 735 SND_SOC_DAPM_INPUT("LINE2L"), 736 SND_SOC_DAPM_INPUT("LINE2R"), 737 }; 738 739 /* For tlv320aic3104 */ 740 static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = { 741 /* Inputs to Left ADC */ 742 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 743 &aic3104_left_pga_mixer_controls[0], 744 ARRAY_SIZE(aic3104_left_pga_mixer_controls)), 745 746 /* Inputs to Right ADC */ 747 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 748 &aic3104_right_pga_mixer_controls[0], 749 ARRAY_SIZE(aic3104_right_pga_mixer_controls)), 750 751 /* Output mixers */ 752 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 753 &aic3x_left_line_mixer_controls[0], 754 ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2), 755 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 756 &aic3x_right_line_mixer_controls[0], 757 ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2), 758 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 759 &aic3x_left_hp_mixer_controls[0], 760 ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2), 761 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 762 &aic3x_right_hp_mixer_controls[0], 763 ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2), 764 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 765 &aic3x_left_hpcom_mixer_controls[0], 766 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2), 767 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 768 &aic3x_right_hpcom_mixer_controls[0], 769 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2), 770 771 SND_SOC_DAPM_INPUT("MIC2L"), 772 SND_SOC_DAPM_INPUT("MIC2R"), 773 }; 774 775 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = { 776 /* Mono Output */ 777 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), 778 779 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, 780 &aic3x_mono_mixer_controls[0], 781 ARRAY_SIZE(aic3x_mono_mixer_controls)), 782 783 SND_SOC_DAPM_OUTPUT("MONO_LOUT"), 784 }; 785 786 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { 787 /* Class-D outputs */ 788 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0), 789 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0), 790 791 SND_SOC_DAPM_OUTPUT("SPOP"), 792 SND_SOC_DAPM_OUTPUT("SPOM"), 793 }; 794 795 static const struct snd_soc_dapm_route intercon[] = { 796 /* Left Input */ 797 {"Left Line1L Mux", "single-ended", "LINE1L"}, 798 {"Left Line1L Mux", "differential", "LINE1L"}, 799 {"Left Line1R Mux", "single-ended", "LINE1R"}, 800 {"Left Line1R Mux", "differential", "LINE1R"}, 801 802 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, 803 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, 804 805 {"Left ADC", NULL, "Left PGA Mixer"}, 806 807 /* Right Input */ 808 {"Right Line1R Mux", "single-ended", "LINE1R"}, 809 {"Right Line1R Mux", "differential", "LINE1R"}, 810 {"Right Line1L Mux", "single-ended", "LINE1L"}, 811 {"Right Line1L Mux", "differential", "LINE1L"}, 812 813 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, 814 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, 815 816 {"Right ADC", NULL, "Right PGA Mixer"}, 817 818 /* Left DAC Output */ 819 {"Left DAC Mux", "DAC_L1", "Left DAC"}, 820 {"Left DAC Mux", "DAC_L2", "Left DAC"}, 821 {"Left DAC Mux", "DAC_L3", "Left DAC"}, 822 823 /* Right DAC Output */ 824 {"Right DAC Mux", "DAC_R1", "Right DAC"}, 825 {"Right DAC Mux", "DAC_R2", "Right DAC"}, 826 {"Right DAC Mux", "DAC_R3", "Right DAC"}, 827 828 /* Left Line Output */ 829 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 830 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 831 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 832 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 833 834 {"Left Line Out", NULL, "Left Line Mixer"}, 835 {"Left Line Out", NULL, "Left DAC Mux"}, 836 {"LLOUT", NULL, "Left Line Out"}, 837 838 /* Right Line Output */ 839 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 840 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 841 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 842 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 843 844 {"Right Line Out", NULL, "Right Line Mixer"}, 845 {"Right Line Out", NULL, "Right DAC Mux"}, 846 {"RLOUT", NULL, "Right Line Out"}, 847 848 /* Left HP Output */ 849 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 850 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 851 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 852 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 853 854 {"Left HP Out", NULL, "Left HP Mixer"}, 855 {"Left HP Out", NULL, "Left DAC Mux"}, 856 {"HPLOUT", NULL, "Left HP Out"}, 857 858 /* Right HP Output */ 859 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 860 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 861 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 862 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 863 864 {"Right HP Out", NULL, "Right HP Mixer"}, 865 {"Right HP Out", NULL, "Right DAC Mux"}, 866 {"HPROUT", NULL, "Right HP Out"}, 867 868 /* Left HPCOM Output */ 869 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 870 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 871 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 872 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 873 874 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, 875 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, 876 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, 877 {"Left HP Com", NULL, "Left HPCOM Mux"}, 878 {"HPLCOM", NULL, "Left HP Com"}, 879 880 /* Right HPCOM Output */ 881 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 882 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 883 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 884 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 885 886 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, 887 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, 888 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, 889 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, 890 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, 891 {"Right HP Com", NULL, "Right HPCOM Mux"}, 892 {"HPRCOM", NULL, "Right HP Com"}, 893 }; 894 895 /* For other than tlv320aic3104 */ 896 static const struct snd_soc_dapm_route intercon_extra[] = { 897 /* Left Input */ 898 {"Left Line2L Mux", "single-ended", "LINE2L"}, 899 {"Left Line2L Mux", "differential", "LINE2L"}, 900 901 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, 902 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, 903 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, 904 905 {"Left ADC", NULL, "GPIO1 dmic modclk"}, 906 907 /* Right Input */ 908 {"Right Line2R Mux", "single-ended", "LINE2R"}, 909 {"Right Line2R Mux", "differential", "LINE2R"}, 910 911 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, 912 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, 913 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, 914 915 {"Right ADC", NULL, "GPIO1 dmic modclk"}, 916 917 /* 918 * Logical path between digital mic enable and GPIO1 modulator clock 919 * output function 920 */ 921 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, 922 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, 923 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, 924 925 /* Left Line Output */ 926 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 927 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 928 929 /* Right Line Output */ 930 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 931 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 932 933 /* Left HP Output */ 934 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 935 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 936 937 /* Right HP Output */ 938 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 939 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 940 941 /* Left HPCOM Output */ 942 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 943 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 944 945 /* Right HPCOM Output */ 946 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 947 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 948 }; 949 950 /* For tlv320aic3104 */ 951 static const struct snd_soc_dapm_route intercon_extra_3104[] = { 952 /* Left Input */ 953 {"Left PGA Mixer", "Mic2L Switch", "MIC2L"}, 954 {"Left PGA Mixer", "Mic2R Switch", "MIC2R"}, 955 956 /* Right Input */ 957 {"Right PGA Mixer", "Mic2L Switch", "MIC2L"}, 958 {"Right PGA Mixer", "Mic2R Switch", "MIC2R"}, 959 }; 960 961 static const struct snd_soc_dapm_route intercon_mono[] = { 962 /* Mono Output */ 963 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 964 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 965 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, 966 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 967 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 968 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, 969 {"Mono Out", NULL, "Mono Mixer"}, 970 {"MONO_LOUT", NULL, "Mono Out"}, 971 }; 972 973 static const struct snd_soc_dapm_route intercon_3007[] = { 974 /* Class-D outputs */ 975 {"Left Class-D Out", NULL, "Left Line Out"}, 976 {"Right Class-D Out", NULL, "Left Line Out"}, 977 {"SPOP", NULL, "Left Class-D Out"}, 978 {"SPOM", NULL, "Right Class-D Out"}, 979 }; 980 981 static int aic3x_add_widgets(struct snd_soc_codec *codec) 982 { 983 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 984 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 985 986 switch (aic3x->model) { 987 case AIC3X_MODEL_3X: 988 case AIC3X_MODEL_33: 989 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets, 990 ARRAY_SIZE(aic3x_extra_dapm_widgets)); 991 snd_soc_dapm_add_routes(dapm, intercon_extra, 992 ARRAY_SIZE(intercon_extra)); 993 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets, 994 ARRAY_SIZE(aic3x_dapm_mono_widgets)); 995 snd_soc_dapm_add_routes(dapm, intercon_mono, 996 ARRAY_SIZE(intercon_mono)); 997 break; 998 case AIC3X_MODEL_3007: 999 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets, 1000 ARRAY_SIZE(aic3x_extra_dapm_widgets)); 1001 snd_soc_dapm_add_routes(dapm, intercon_extra, 1002 ARRAY_SIZE(intercon_extra)); 1003 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, 1004 ARRAY_SIZE(aic3007_dapm_widgets)); 1005 snd_soc_dapm_add_routes(dapm, intercon_3007, 1006 ARRAY_SIZE(intercon_3007)); 1007 break; 1008 case AIC3X_MODEL_3104: 1009 snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets, 1010 ARRAY_SIZE(aic3104_extra_dapm_widgets)); 1011 snd_soc_dapm_add_routes(dapm, intercon_extra_3104, 1012 ARRAY_SIZE(intercon_extra_3104)); 1013 break; 1014 } 1015 1016 return 0; 1017 } 1018 1019 static int aic3x_hw_params(struct snd_pcm_substream *substream, 1020 struct snd_pcm_hw_params *params, 1021 struct snd_soc_dai *dai) 1022 { 1023 struct snd_soc_codec *codec = dai->codec; 1024 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1025 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 1026 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 1027 u16 d, pll_d = 1; 1028 int clk; 1029 int width = aic3x->slot_width; 1030 1031 if (!width) 1032 width = params_width(params); 1033 1034 /* select data word length */ 1035 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); 1036 switch (width) { 1037 case 16: 1038 break; 1039 case 20: 1040 data |= (0x01 << 4); 1041 break; 1042 case 24: 1043 data |= (0x02 << 4); 1044 break; 1045 case 32: 1046 data |= (0x03 << 4); 1047 break; 1048 } 1049 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data); 1050 1051 /* Fsref can be 44100 or 48000 */ 1052 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; 1053 1054 /* Try to find a value for Q which allows us to bypass the PLL and 1055 * generate CODEC_CLK directly. */ 1056 for (pll_q = 2; pll_q < 18; pll_q++) 1057 if (aic3x->sysclk / (128 * pll_q) == fsref) { 1058 bypass_pll = 1; 1059 break; 1060 } 1061 1062 if (bypass_pll) { 1063 pll_q &= 0xf; 1064 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 1065 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 1066 /* disable PLL if it is bypassed */ 1067 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); 1068 1069 } else { 1070 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 1071 /* enable PLL when it is used */ 1072 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1073 PLL_ENABLE, PLL_ENABLE); 1074 } 1075 1076 /* Route Left DAC to left channel input and 1077 * right DAC to right channel input */ 1078 data = (LDAC2LCH | RDAC2RCH); 1079 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; 1080 if (params_rate(params) >= 64000) 1081 data |= DUAL_RATE_MODE; 1082 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data); 1083 1084 /* codec sample rate select */ 1085 data = (fsref * 20) / params_rate(params); 1086 if (params_rate(params) < 64000) 1087 data /= 2; 1088 data /= 5; 1089 data -= 2; 1090 data |= (data << 4); 1091 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); 1092 1093 if (bypass_pll) 1094 return 0; 1095 1096 /* Use PLL, compute appropriate setup for j, d, r and p, the closest 1097 * one wins the game. Try with d==0 first, next with d!=0. 1098 * Constraints for j are according to the datasheet. 1099 * The sysclk is divided by 1000 to prevent integer overflows. 1100 */ 1101 1102 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); 1103 1104 for (r = 1; r <= 16; r++) 1105 for (p = 1; p <= 8; p++) { 1106 for (j = 4; j <= 55; j++) { 1107 /* This is actually 1000*((j+(d/10000))*r)/p 1108 * The term had to be converted to get 1109 * rid of the division by 10000; d = 0 here 1110 */ 1111 int tmp_clk = (1000 * j * r) / p; 1112 1113 /* Check whether this values get closer than 1114 * the best ones we had before 1115 */ 1116 if (abs(codec_clk - tmp_clk) < 1117 abs(codec_clk - last_clk)) { 1118 pll_j = j; pll_d = 0; 1119 pll_r = r; pll_p = p; 1120 last_clk = tmp_clk; 1121 } 1122 1123 /* Early exit for exact matches */ 1124 if (tmp_clk == codec_clk) 1125 goto found; 1126 } 1127 } 1128 1129 /* try with d != 0 */ 1130 for (p = 1; p <= 8; p++) { 1131 j = codec_clk * p / 1000; 1132 1133 if (j < 4 || j > 11) 1134 continue; 1135 1136 /* do not use codec_clk here since we'd loose precision */ 1137 d = ((2048 * p * fsref) - j * aic3x->sysclk) 1138 * 100 / (aic3x->sysclk/100); 1139 1140 clk = (10000 * j + d) / (10 * p); 1141 1142 /* check whether this values get closer than the best 1143 * ones we had before */ 1144 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { 1145 pll_j = j; pll_d = d; pll_r = 1; pll_p = p; 1146 last_clk = clk; 1147 } 1148 1149 /* Early exit for exact matches */ 1150 if (clk == codec_clk) 1151 goto found; 1152 } 1153 1154 if (last_clk == 0) { 1155 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); 1156 return -EINVAL; 1157 } 1158 1159 found: 1160 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p); 1161 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, 1162 pll_r << PLLR_SHIFT); 1163 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); 1164 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, 1165 (pll_d >> 6) << PLLD_MSB_SHIFT); 1166 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, 1167 (pll_d & 0x3F) << PLLD_LSB_SHIFT); 1168 1169 return 0; 1170 } 1171 1172 static int aic3x_prepare(struct snd_pcm_substream *substream, 1173 struct snd_soc_dai *dai) 1174 { 1175 struct snd_soc_codec *codec = dai->codec; 1176 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1177 int delay = 0; 1178 int width = aic3x->slot_width; 1179 1180 if (!width) 1181 width = substream->runtime->sample_bits; 1182 1183 /* TDM slot selection only valid in DSP_A/_B mode */ 1184 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A) 1185 delay += (aic3x->tdm_delay*width + 1); 1186 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B) 1187 delay += aic3x->tdm_delay*width; 1188 1189 /* Configure data delay */ 1190 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay); 1191 1192 return 0; 1193 } 1194 1195 static int aic3x_mute(struct snd_soc_dai *dai, int mute) 1196 { 1197 struct snd_soc_codec *codec = dai->codec; 1198 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON; 1199 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON; 1200 1201 if (mute) { 1202 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); 1203 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); 1204 } else { 1205 snd_soc_write(codec, LDAC_VOL, ldac_reg); 1206 snd_soc_write(codec, RDAC_VOL, rdac_reg); 1207 } 1208 1209 return 0; 1210 } 1211 1212 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1213 int clk_id, unsigned int freq, int dir) 1214 { 1215 struct snd_soc_codec *codec = codec_dai->codec; 1216 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1217 1218 /* set clock on MCLK or GPIO2 or BCLK */ 1219 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, 1220 clk_id << PLLCLK_IN_SHIFT); 1221 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, 1222 clk_id << CLKDIV_IN_SHIFT); 1223 1224 aic3x->sysclk = freq; 1225 return 0; 1226 } 1227 1228 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, 1229 unsigned int fmt) 1230 { 1231 struct snd_soc_codec *codec = codec_dai->codec; 1232 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1233 u8 iface_areg, iface_breg; 1234 1235 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; 1236 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; 1237 1238 /* set master/slave audio interface */ 1239 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1240 case SND_SOC_DAIFMT_CBM_CFM: 1241 aic3x->master = 1; 1242 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; 1243 break; 1244 case SND_SOC_DAIFMT_CBS_CFS: 1245 aic3x->master = 0; 1246 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER); 1247 break; 1248 default: 1249 return -EINVAL; 1250 } 1251 1252 /* 1253 * match both interface format and signal polarities since they 1254 * are fixed 1255 */ 1256 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | 1257 SND_SOC_DAIFMT_INV_MASK)) { 1258 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): 1259 break; 1260 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): 1261 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): 1262 iface_breg |= (0x01 << 6); 1263 break; 1264 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): 1265 iface_breg |= (0x02 << 6); 1266 break; 1267 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): 1268 iface_breg |= (0x03 << 6); 1269 break; 1270 default: 1271 return -EINVAL; 1272 } 1273 1274 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 1275 1276 /* set iface */ 1277 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); 1278 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); 1279 1280 return 0; 1281 } 1282 1283 static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai, 1284 unsigned int tx_mask, unsigned int rx_mask, 1285 int slots, int slot_width) 1286 { 1287 struct snd_soc_codec *codec = codec_dai->codec; 1288 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1289 unsigned int lsb; 1290 1291 if (tx_mask != rx_mask) { 1292 dev_err(codec->dev, "tx and rx masks must be symmetric\n"); 1293 return -EINVAL; 1294 } 1295 1296 if (unlikely(!tx_mask)) { 1297 dev_err(codec->dev, "tx and rx masks need to be non 0\n"); 1298 return -EINVAL; 1299 } 1300 1301 /* TDM based on DSP mode requires slots to be adjacent */ 1302 lsb = __ffs(tx_mask); 1303 if ((lsb + 1) != __fls(tx_mask)) { 1304 dev_err(codec->dev, "Invalid mask, slots must be adjacent\n"); 1305 return -EINVAL; 1306 } 1307 1308 switch (slot_width) { 1309 case 16: 1310 case 20: 1311 case 24: 1312 case 32: 1313 break; 1314 default: 1315 dev_err(codec->dev, "Unsupported slot width %d\n", slot_width); 1316 return -EINVAL; 1317 } 1318 1319 1320 aic3x->tdm_delay = lsb; 1321 aic3x->slot_width = slot_width; 1322 1323 /* DOUT in high-impedance on inactive bit clocks */ 1324 snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA, 1325 DOUT_TRISTATE, DOUT_TRISTATE); 1326 1327 return 0; 1328 } 1329 1330 static int aic3x_regulator_event(struct notifier_block *nb, 1331 unsigned long event, void *data) 1332 { 1333 struct aic3x_disable_nb *disable_nb = 1334 container_of(nb, struct aic3x_disable_nb, nb); 1335 struct aic3x_priv *aic3x = disable_nb->aic3x; 1336 1337 if (event & REGULATOR_EVENT_DISABLE) { 1338 /* 1339 * Put codec to reset and require cache sync as at least one 1340 * of the supplies was disabled 1341 */ 1342 if (gpio_is_valid(aic3x->gpio_reset)) 1343 gpio_set_value(aic3x->gpio_reset, 0); 1344 regcache_mark_dirty(aic3x->regmap); 1345 } 1346 1347 return 0; 1348 } 1349 1350 static int aic3x_set_power(struct snd_soc_codec *codec, int power) 1351 { 1352 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1353 unsigned int pll_c, pll_d; 1354 int ret; 1355 1356 if (power) { 1357 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), 1358 aic3x->supplies); 1359 if (ret) 1360 goto out; 1361 aic3x->power = 1; 1362 1363 if (gpio_is_valid(aic3x->gpio_reset)) { 1364 udelay(1); 1365 gpio_set_value(aic3x->gpio_reset, 1); 1366 } 1367 1368 /* Sync reg_cache with the hardware */ 1369 regcache_cache_only(aic3x->regmap, false); 1370 regcache_sync(aic3x->regmap); 1371 1372 /* Rewrite paired PLL D registers in case cached sync skipped 1373 * writing one of them and thus caused other one also not 1374 * being written 1375 */ 1376 pll_c = snd_soc_read(codec, AIC3X_PLL_PROGC_REG); 1377 pll_d = snd_soc_read(codec, AIC3X_PLL_PROGD_REG); 1378 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def || 1379 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) { 1380 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, pll_c); 1381 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, pll_d); 1382 } 1383 } else { 1384 /* 1385 * Do soft reset to this codec instance in order to clear 1386 * possible VDD leakage currents in case the supply regulators 1387 * remain on 1388 */ 1389 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1390 regcache_mark_dirty(aic3x->regmap); 1391 aic3x->power = 0; 1392 /* HW writes are needless when bias is off */ 1393 regcache_cache_only(aic3x->regmap, true); 1394 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), 1395 aic3x->supplies); 1396 } 1397 out: 1398 return ret; 1399 } 1400 1401 static int aic3x_set_bias_level(struct snd_soc_codec *codec, 1402 enum snd_soc_bias_level level) 1403 { 1404 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1405 1406 switch (level) { 1407 case SND_SOC_BIAS_ON: 1408 break; 1409 case SND_SOC_BIAS_PREPARE: 1410 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY && 1411 aic3x->master) { 1412 /* enable pll */ 1413 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1414 PLL_ENABLE, PLL_ENABLE); 1415 } 1416 break; 1417 case SND_SOC_BIAS_STANDBY: 1418 if (!aic3x->power) 1419 aic3x_set_power(codec, 1); 1420 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE && 1421 aic3x->master) { 1422 /* disable pll */ 1423 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1424 PLL_ENABLE, 0); 1425 } 1426 break; 1427 case SND_SOC_BIAS_OFF: 1428 if (aic3x->power) 1429 aic3x_set_power(codec, 0); 1430 break; 1431 } 1432 1433 return 0; 1434 } 1435 1436 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1437 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1438 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \ 1439 SNDRV_PCM_FMTBIT_S32_LE) 1440 1441 static const struct snd_soc_dai_ops aic3x_dai_ops = { 1442 .hw_params = aic3x_hw_params, 1443 .prepare = aic3x_prepare, 1444 .digital_mute = aic3x_mute, 1445 .set_sysclk = aic3x_set_dai_sysclk, 1446 .set_fmt = aic3x_set_dai_fmt, 1447 .set_tdm_slot = aic3x_set_dai_tdm_slot, 1448 }; 1449 1450 static struct snd_soc_dai_driver aic3x_dai = { 1451 .name = "tlv320aic3x-hifi", 1452 .playback = { 1453 .stream_name = "Playback", 1454 .channels_min = 2, 1455 .channels_max = 2, 1456 .rates = AIC3X_RATES, 1457 .formats = AIC3X_FORMATS,}, 1458 .capture = { 1459 .stream_name = "Capture", 1460 .channels_min = 2, 1461 .channels_max = 2, 1462 .rates = AIC3X_RATES, 1463 .formats = AIC3X_FORMATS,}, 1464 .ops = &aic3x_dai_ops, 1465 .symmetric_rates = 1, 1466 }; 1467 1468 static void aic3x_mono_init(struct snd_soc_codec *codec) 1469 { 1470 /* DAC to Mono Line Out default volume and route to Output mixer */ 1471 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1472 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1473 1474 /* unmute all outputs */ 1475 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE); 1476 1477 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ 1478 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); 1479 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); 1480 1481 /* Line2 to Mono Out default volume, disconnect from Output Mixer */ 1482 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); 1483 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); 1484 } 1485 1486 /* 1487 * initialise the AIC3X driver 1488 * register the mixer and dsp interfaces with the kernel 1489 */ 1490 static int aic3x_init(struct snd_soc_codec *codec) 1491 { 1492 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1493 1494 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); 1495 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1496 1497 /* DAC default volume and mute */ 1498 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); 1499 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); 1500 1501 /* DAC to HP default volume and route to Output mixer */ 1502 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); 1503 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); 1504 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1505 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1506 /* DAC to Line Out default volume and route to Output mixer */ 1507 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1508 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1509 1510 /* unmute all outputs */ 1511 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE); 1512 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE); 1513 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE); 1514 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE); 1515 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE); 1516 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE); 1517 1518 /* ADC default volume and unmute */ 1519 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN); 1520 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN); 1521 /* By default route Line1 to ADC PGA mixer */ 1522 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0); 1523 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0); 1524 1525 /* PGA to HP Bypass default volume, disconnect from Output Mixer */ 1526 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); 1527 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); 1528 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); 1529 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); 1530 /* PGA to Line Out default volume, disconnect from Output Mixer */ 1531 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); 1532 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); 1533 1534 /* On tlv320aic3104, these registers are reserved and must not be written */ 1535 if (aic3x->model != AIC3X_MODEL_3104) { 1536 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ 1537 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); 1538 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); 1539 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); 1540 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); 1541 /* Line2 Line Out default volume, disconnect from Output Mixer */ 1542 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); 1543 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); 1544 } 1545 1546 switch (aic3x->model) { 1547 case AIC3X_MODEL_3X: 1548 case AIC3X_MODEL_33: 1549 aic3x_mono_init(codec); 1550 break; 1551 case AIC3X_MODEL_3007: 1552 snd_soc_write(codec, CLASSD_CTRL, 0); 1553 break; 1554 } 1555 1556 return 0; 1557 } 1558 1559 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x) 1560 { 1561 struct aic3x_priv *a; 1562 1563 list_for_each_entry(a, &reset_list, list) { 1564 if (gpio_is_valid(aic3x->gpio_reset) && 1565 aic3x->gpio_reset == a->gpio_reset) 1566 return true; 1567 } 1568 1569 return false; 1570 } 1571 1572 static int aic3x_probe(struct snd_soc_codec *codec) 1573 { 1574 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1575 int ret, i; 1576 1577 INIT_LIST_HEAD(&aic3x->list); 1578 aic3x->codec = codec; 1579 1580 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) { 1581 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; 1582 aic3x->disable_nb[i].aic3x = aic3x; 1583 ret = regulator_register_notifier(aic3x->supplies[i].consumer, 1584 &aic3x->disable_nb[i].nb); 1585 if (ret) { 1586 dev_err(codec->dev, 1587 "Failed to request regulator notifier: %d\n", 1588 ret); 1589 goto err_notif; 1590 } 1591 } 1592 1593 regcache_mark_dirty(aic3x->regmap); 1594 aic3x_init(codec); 1595 1596 if (aic3x->setup) { 1597 if (aic3x->model != AIC3X_MODEL_3104) { 1598 /* setup GPIO functions */ 1599 snd_soc_write(codec, AIC3X_GPIO1_REG, 1600 (aic3x->setup->gpio_func[0] & 0xf) << 4); 1601 snd_soc_write(codec, AIC3X_GPIO2_REG, 1602 (aic3x->setup->gpio_func[1] & 0xf) << 4); 1603 } else { 1604 dev_warn(codec->dev, "GPIO functionality is not supported on tlv320aic3104\n"); 1605 } 1606 } 1607 1608 switch (aic3x->model) { 1609 case AIC3X_MODEL_3X: 1610 case AIC3X_MODEL_33: 1611 snd_soc_add_codec_controls(codec, aic3x_extra_snd_controls, 1612 ARRAY_SIZE(aic3x_extra_snd_controls)); 1613 snd_soc_add_codec_controls(codec, aic3x_mono_controls, 1614 ARRAY_SIZE(aic3x_mono_controls)); 1615 break; 1616 case AIC3X_MODEL_3007: 1617 snd_soc_add_codec_controls(codec, aic3x_extra_snd_controls, 1618 ARRAY_SIZE(aic3x_extra_snd_controls)); 1619 snd_soc_add_codec_controls(codec, 1620 &aic3x_classd_amp_gain_ctrl, 1); 1621 break; 1622 case AIC3X_MODEL_3104: 1623 break; 1624 } 1625 1626 /* set mic bias voltage */ 1627 switch (aic3x->micbias_vg) { 1628 case AIC3X_MICBIAS_2_0V: 1629 case AIC3X_MICBIAS_2_5V: 1630 case AIC3X_MICBIAS_AVDDV: 1631 snd_soc_update_bits(codec, MICBIAS_CTRL, 1632 MICBIAS_LEVEL_MASK, 1633 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT); 1634 break; 1635 case AIC3X_MICBIAS_OFF: 1636 /* 1637 * noting to do. target won't enter here. This is just to avoid 1638 * compile time warning "warning: enumeration value 1639 * 'AIC3X_MICBIAS_OFF' not handled in switch" 1640 */ 1641 break; 1642 } 1643 1644 aic3x_add_widgets(codec); 1645 1646 return 0; 1647 1648 err_notif: 1649 while (i--) 1650 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1651 &aic3x->disable_nb[i].nb); 1652 return ret; 1653 } 1654 1655 static int aic3x_remove(struct snd_soc_codec *codec) 1656 { 1657 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1658 int i; 1659 1660 list_del(&aic3x->list); 1661 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1662 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1663 &aic3x->disable_nb[i].nb); 1664 1665 return 0; 1666 } 1667 1668 static struct snd_soc_codec_driver soc_codec_dev_aic3x = { 1669 .set_bias_level = aic3x_set_bias_level, 1670 .idle_bias_off = true, 1671 .probe = aic3x_probe, 1672 .remove = aic3x_remove, 1673 .component_driver = { 1674 .controls = aic3x_snd_controls, 1675 .num_controls = ARRAY_SIZE(aic3x_snd_controls), 1676 .dapm_widgets = aic3x_dapm_widgets, 1677 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets), 1678 .dapm_routes = intercon, 1679 .num_dapm_routes = ARRAY_SIZE(intercon), 1680 }, 1681 }; 1682 1683 /* 1684 * AIC3X 2 wire address can be up to 4 devices with device addresses 1685 * 0x18, 0x19, 0x1A, 0x1B 1686 */ 1687 1688 static const struct i2c_device_id aic3x_i2c_id[] = { 1689 { "tlv320aic3x", AIC3X_MODEL_3X }, 1690 { "tlv320aic33", AIC3X_MODEL_33 }, 1691 { "tlv320aic3007", AIC3X_MODEL_3007 }, 1692 { "tlv320aic3106", AIC3X_MODEL_3X }, 1693 { "tlv320aic3104", AIC3X_MODEL_3104 }, 1694 { } 1695 }; 1696 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); 1697 1698 static const struct reg_sequence aic3007_class_d[] = { 1699 /* Class-D speaker driver init; datasheet p. 46 */ 1700 { AIC3X_PAGE_SELECT, 0x0D }, 1701 { 0xD, 0x0D }, 1702 { 0x8, 0x5C }, 1703 { 0x8, 0x5D }, 1704 { 0x8, 0x5C }, 1705 { AIC3X_PAGE_SELECT, 0x00 }, 1706 }; 1707 1708 /* 1709 * If the i2c layer weren't so broken, we could pass this kind of data 1710 * around 1711 */ 1712 static int aic3x_i2c_probe(struct i2c_client *i2c, 1713 const struct i2c_device_id *id) 1714 { 1715 struct aic3x_pdata *pdata = i2c->dev.platform_data; 1716 struct aic3x_priv *aic3x; 1717 struct aic3x_setup_data *ai3x_setup; 1718 struct device_node *np = i2c->dev.of_node; 1719 int ret, i; 1720 u32 value; 1721 1722 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL); 1723 if (!aic3x) 1724 return -ENOMEM; 1725 1726 aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap); 1727 if (IS_ERR(aic3x->regmap)) { 1728 ret = PTR_ERR(aic3x->regmap); 1729 return ret; 1730 } 1731 1732 regcache_cache_only(aic3x->regmap, true); 1733 1734 i2c_set_clientdata(i2c, aic3x); 1735 if (pdata) { 1736 aic3x->gpio_reset = pdata->gpio_reset; 1737 aic3x->setup = pdata->setup; 1738 aic3x->micbias_vg = pdata->micbias_vg; 1739 } else if (np) { 1740 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup), 1741 GFP_KERNEL); 1742 if (!ai3x_setup) 1743 return -ENOMEM; 1744 1745 ret = of_get_named_gpio(np, "gpio-reset", 0); 1746 if (ret >= 0) 1747 aic3x->gpio_reset = ret; 1748 else 1749 aic3x->gpio_reset = -1; 1750 1751 if (of_property_read_u32_array(np, "ai3x-gpio-func", 1752 ai3x_setup->gpio_func, 2) >= 0) { 1753 aic3x->setup = ai3x_setup; 1754 } 1755 1756 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) { 1757 switch (value) { 1758 case 1 : 1759 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V; 1760 break; 1761 case 2 : 1762 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V; 1763 break; 1764 case 3 : 1765 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV; 1766 break; 1767 default : 1768 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; 1769 dev_err(&i2c->dev, "Unsuitable MicBias voltage " 1770 "found in DT\n"); 1771 } 1772 } else { 1773 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; 1774 } 1775 1776 } else { 1777 aic3x->gpio_reset = -1; 1778 } 1779 1780 aic3x->model = id->driver_data; 1781 1782 if (gpio_is_valid(aic3x->gpio_reset) && 1783 !aic3x_is_shared_reset(aic3x)) { 1784 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); 1785 if (ret != 0) 1786 goto err; 1787 gpio_direction_output(aic3x->gpio_reset, 0); 1788 } 1789 1790 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1791 aic3x->supplies[i].supply = aic3x_supply_names[i]; 1792 1793 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies), 1794 aic3x->supplies); 1795 if (ret != 0) { 1796 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 1797 goto err_gpio; 1798 } 1799 1800 if (aic3x->model == AIC3X_MODEL_3007) { 1801 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d, 1802 ARRAY_SIZE(aic3007_class_d)); 1803 if (ret != 0) 1804 dev_err(&i2c->dev, "Failed to init class D: %d\n", 1805 ret); 1806 } 1807 1808 ret = snd_soc_register_codec(&i2c->dev, 1809 &soc_codec_dev_aic3x, &aic3x_dai, 1); 1810 1811 if (ret != 0) 1812 goto err_gpio; 1813 1814 list_add(&aic3x->list, &reset_list); 1815 1816 return 0; 1817 1818 err_gpio: 1819 if (gpio_is_valid(aic3x->gpio_reset) && 1820 !aic3x_is_shared_reset(aic3x)) 1821 gpio_free(aic3x->gpio_reset); 1822 err: 1823 return ret; 1824 } 1825 1826 static int aic3x_i2c_remove(struct i2c_client *client) 1827 { 1828 struct aic3x_priv *aic3x = i2c_get_clientdata(client); 1829 1830 snd_soc_unregister_codec(&client->dev); 1831 if (gpio_is_valid(aic3x->gpio_reset) && 1832 !aic3x_is_shared_reset(aic3x)) { 1833 gpio_set_value(aic3x->gpio_reset, 0); 1834 gpio_free(aic3x->gpio_reset); 1835 } 1836 return 0; 1837 } 1838 1839 #if defined(CONFIG_OF) 1840 static const struct of_device_id tlv320aic3x_of_match[] = { 1841 { .compatible = "ti,tlv320aic3x", }, 1842 { .compatible = "ti,tlv320aic33" }, 1843 { .compatible = "ti,tlv320aic3007" }, 1844 { .compatible = "ti,tlv320aic3106" }, 1845 { .compatible = "ti,tlv320aic3104" }, 1846 {}, 1847 }; 1848 MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match); 1849 #endif 1850 1851 /* machine i2c codec control layer */ 1852 static struct i2c_driver aic3x_i2c_driver = { 1853 .driver = { 1854 .name = "tlv320aic3x-codec", 1855 .of_match_table = of_match_ptr(tlv320aic3x_of_match), 1856 }, 1857 .probe = aic3x_i2c_probe, 1858 .remove = aic3x_i2c_remove, 1859 .id_table = aic3x_i2c_id, 1860 }; 1861 1862 module_i2c_driver(aic3x_i2c_driver); 1863 1864 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); 1865 MODULE_AUTHOR("Vladimir Barinov"); 1866 MODULE_LICENSE("GPL"); 1867