1 /* 2 * ALSA SoC TLV320AIC3X codec driver 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Notes: 14 * The AIC3X is a driver for a low power stereo audio 15 * codecs aic31, aic32, aic33, aic3007. 16 * 17 * It supports full aic33 codec functionality. 18 * The compatibility with aic32, aic31 and aic3007 is as follows: 19 * aic32/aic3007 | aic31 20 * --------------------------------------- 21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A 22 * | IN1L -> LINE1L 23 * | IN1R -> LINE1R 24 * | IN2L -> LINE2L 25 * | IN2R -> LINE2R 26 * | MIC3L/R -> N/A 27 * truncated internal functionality in 28 * accordance with documentation 29 * --------------------------------------- 30 * 31 * Hence the machine layer should disable unsupported inputs/outputs by 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/init.h> 38 #include <linux/delay.h> 39 #include <linux/pm.h> 40 #include <linux/i2c.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/slab.h> 44 #include <sound/core.h> 45 #include <sound/pcm.h> 46 #include <sound/pcm_params.h> 47 #include <sound/soc.h> 48 #include <sound/initval.h> 49 #include <sound/tlv.h> 50 #include <sound/tlv320aic3x.h> 51 52 #include "tlv320aic3x.h" 53 54 #define AIC3X_NUM_SUPPLIES 4 55 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { 56 "IOVDD", /* I/O Voltage */ 57 "DVDD", /* Digital Core Voltage */ 58 "AVDD", /* Analog DAC Voltage */ 59 "DRVDD", /* ADC Analog and Output Driver Voltage */ 60 }; 61 62 static LIST_HEAD(reset_list); 63 64 struct aic3x_priv; 65 66 struct aic3x_disable_nb { 67 struct notifier_block nb; 68 struct aic3x_priv *aic3x; 69 }; 70 71 /* codec private data */ 72 struct aic3x_priv { 73 struct snd_soc_codec *codec; 74 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; 75 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES]; 76 enum snd_soc_control_type control_type; 77 struct aic3x_setup_data *setup; 78 unsigned int sysclk; 79 struct list_head list; 80 int master; 81 int gpio_reset; 82 int power; 83 #define AIC3X_MODEL_3X 0 84 #define AIC3X_MODEL_33 1 85 #define AIC3X_MODEL_3007 2 86 u16 model; 87 }; 88 89 /* 90 * AIC3X register cache 91 * We can't read the AIC3X register space when we are 92 * using 2 wire for device control, so we cache them instead. 93 * There is no point in caching the reset register 94 */ 95 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { 96 0x00, 0x00, 0x00, 0x10, /* 0 */ 97 0x04, 0x00, 0x00, 0x00, /* 4 */ 98 0x00, 0x00, 0x00, 0x01, /* 8 */ 99 0x00, 0x00, 0x00, 0x80, /* 12 */ 100 0x80, 0xff, 0xff, 0x78, /* 16 */ 101 0x78, 0x78, 0x78, 0x78, /* 20 */ 102 0x78, 0x00, 0x00, 0xfe, /* 24 */ 103 0x00, 0x00, 0xfe, 0x00, /* 28 */ 104 0x18, 0x18, 0x00, 0x00, /* 32 */ 105 0x00, 0x00, 0x00, 0x00, /* 36 */ 106 0x00, 0x00, 0x00, 0x80, /* 40 */ 107 0x80, 0x00, 0x00, 0x00, /* 44 */ 108 0x00, 0x00, 0x00, 0x04, /* 48 */ 109 0x00, 0x00, 0x00, 0x00, /* 52 */ 110 0x00, 0x00, 0x04, 0x00, /* 56 */ 111 0x00, 0x00, 0x00, 0x00, /* 60 */ 112 0x00, 0x04, 0x00, 0x00, /* 64 */ 113 0x00, 0x00, 0x00, 0x00, /* 68 */ 114 0x04, 0x00, 0x00, 0x00, /* 72 */ 115 0x00, 0x00, 0x00, 0x00, /* 76 */ 116 0x00, 0x00, 0x00, 0x00, /* 80 */ 117 0x00, 0x00, 0x00, 0x00, /* 84 */ 118 0x00, 0x00, 0x00, 0x00, /* 88 */ 119 0x00, 0x00, 0x00, 0x00, /* 92 */ 120 0x00, 0x00, 0x00, 0x00, /* 96 */ 121 0x00, 0x00, 0x02, /* 100 */ 122 }; 123 124 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ 125 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 126 .info = snd_soc_info_volsw, \ 127 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \ 128 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) } 129 130 /* 131 * All input lines are connected when !0xf and disconnected with 0xf bit field, 132 * so we have to use specific dapm_put call for input mixer 133 */ 134 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, 135 struct snd_ctl_elem_value *ucontrol) 136 { 137 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); 138 struct snd_soc_dapm_widget *widget = wlist->widgets[0]; 139 struct soc_mixer_control *mc = 140 (struct soc_mixer_control *)kcontrol->private_value; 141 unsigned int reg = mc->reg; 142 unsigned int shift = mc->shift; 143 int max = mc->max; 144 unsigned int mask = (1 << fls(max)) - 1; 145 unsigned int invert = mc->invert; 146 unsigned short val, val_mask; 147 int ret; 148 struct snd_soc_dapm_path *path; 149 int found = 0; 150 151 val = (ucontrol->value.integer.value[0] & mask); 152 153 mask = 0xf; 154 if (val) 155 val = mask; 156 157 if (invert) 158 val = mask - val; 159 val_mask = mask << shift; 160 val = val << shift; 161 162 mutex_lock(&widget->codec->mutex); 163 164 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { 165 /* find dapm widget path assoc with kcontrol */ 166 list_for_each_entry(path, &widget->dapm->card->paths, list) { 167 if (path->kcontrol != kcontrol) 168 continue; 169 170 /* found, now check type */ 171 found = 1; 172 if (val) 173 /* new connection */ 174 path->connect = invert ? 0 : 1; 175 else 176 /* old connection must be powered down */ 177 path->connect = invert ? 1 : 0; 178 179 dapm_mark_dirty(path->source, "tlv320aic3x source"); 180 dapm_mark_dirty(path->sink, "tlv320aic3x sink"); 181 182 break; 183 } 184 185 if (found) 186 snd_soc_dapm_sync(widget->dapm); 187 } 188 189 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); 190 191 mutex_unlock(&widget->codec->mutex); 192 return ret; 193 } 194 195 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; 196 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; 197 static const char *aic3x_left_hpcom_mux[] = 198 { "differential of HPLOUT", "constant VCM", "single-ended" }; 199 static const char *aic3x_right_hpcom_mux[] = 200 { "differential of HPROUT", "constant VCM", "single-ended", 201 "differential of HPLCOM", "external feedback" }; 202 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; 203 static const char *aic3x_adc_hpf[] = 204 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; 205 206 #define LDAC_ENUM 0 207 #define RDAC_ENUM 1 208 #define LHPCOM_ENUM 2 209 #define RHPCOM_ENUM 3 210 #define LINE1L_2_L_ENUM 4 211 #define LINE1L_2_R_ENUM 5 212 #define LINE1R_2_L_ENUM 6 213 #define LINE1R_2_R_ENUM 7 214 #define LINE2L_ENUM 8 215 #define LINE2R_ENUM 9 216 #define ADC_HPF_ENUM 10 217 218 static const struct soc_enum aic3x_enum[] = { 219 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), 220 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), 221 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), 222 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), 223 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 224 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 225 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 226 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 227 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 228 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 229 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf), 230 }; 231 232 /* 233 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps 234 */ 235 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); 236 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ 237 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); 238 /* 239 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. 240 * Step size is approximately 0.5 dB over most of the scale but increasing 241 * near the very low levels. 242 * Define dB scale so that it is mostly correct for range about -55 to 0 dB 243 * but having increasing dB difference below that (and where it doesn't count 244 * so much). This setting shows -50 dB (actual is -50.3 dB) for register 245 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. 246 */ 247 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); 248 249 static const struct snd_kcontrol_new aic3x_snd_controls[] = { 250 /* Output */ 251 SOC_DOUBLE_R_TLV("PCM Playback Volume", 252 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 253 254 /* 255 * Output controls that map to output mixer switches. Note these are 256 * only for swapped L-to-R and R-to-L routes. See below stereo controls 257 * for direct L-to-L and R-to-R routes. 258 */ 259 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", 260 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 261 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", 262 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 263 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", 264 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 265 266 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", 267 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 268 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", 269 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 270 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", 271 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 272 273 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", 274 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 275 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", 276 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 277 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", 278 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 279 280 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", 281 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 282 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", 283 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 284 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", 285 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 286 287 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", 288 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 289 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", 290 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 291 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", 292 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 293 294 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", 295 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 296 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", 297 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 298 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", 299 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 300 301 /* Stereo output controls for direct L-to-L and R-to-R routes */ 302 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", 303 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, 304 0, 118, 1, output_stage_tlv), 305 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", 306 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, 307 0, 118, 1, output_stage_tlv), 308 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 309 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 310 0, 118, 1, output_stage_tlv), 311 312 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", 313 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 314 0, 118, 1, output_stage_tlv), 315 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", 316 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 317 0, 118, 1, output_stage_tlv), 318 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 319 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 320 0, 118, 1, output_stage_tlv), 321 322 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", 323 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 324 0, 118, 1, output_stage_tlv), 325 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", 326 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 327 0, 118, 1, output_stage_tlv), 328 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 329 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 330 0, 118, 1, output_stage_tlv), 331 332 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", 333 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 334 0, 118, 1, output_stage_tlv), 335 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", 336 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, 337 0, 118, 1, output_stage_tlv), 338 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 339 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 340 0, 118, 1, output_stage_tlv), 341 342 /* Output pin mute controls */ 343 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, 344 0x01, 0), 345 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 346 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 347 0x01, 0), 348 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 349 0x01, 0), 350 351 /* 352 * Note: enable Automatic input Gain Controller with care. It can 353 * adjust PGA to max value when ADC is on and will never go back. 354 */ 355 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), 356 357 /* Input */ 358 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 359 0, 119, 0, adc_tlv), 360 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), 361 362 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]), 363 }; 364 365 /* 366 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps 367 */ 368 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0); 369 370 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl = 371 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv); 372 373 /* Left DAC Mux */ 374 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = 375 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); 376 377 /* Right DAC Mux */ 378 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = 379 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); 380 381 /* Left HPCOM Mux */ 382 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = 383 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); 384 385 /* Right HPCOM Mux */ 386 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = 387 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); 388 389 /* Left Line Mixer */ 390 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { 391 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), 392 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), 393 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), 394 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), 395 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), 396 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), 397 }; 398 399 /* Right Line Mixer */ 400 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { 401 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), 402 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), 403 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), 404 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), 405 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), 406 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), 407 }; 408 409 /* Mono Mixer */ 410 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { 411 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), 412 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), 413 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), 414 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), 415 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), 416 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), 417 }; 418 419 /* Left HP Mixer */ 420 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { 421 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), 422 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), 423 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), 424 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), 425 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), 426 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), 427 }; 428 429 /* Right HP Mixer */ 430 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { 431 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), 432 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), 433 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), 434 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), 435 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), 436 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), 437 }; 438 439 /* Left HPCOM Mixer */ 440 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { 441 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), 442 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), 443 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), 444 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), 445 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), 446 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), 447 }; 448 449 /* Right HPCOM Mixer */ 450 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { 451 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), 452 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), 453 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), 454 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), 455 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), 456 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), 457 }; 458 459 /* Left PGA Mixer */ 460 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { 461 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 462 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 463 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), 464 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 465 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 466 }; 467 468 /* Right PGA Mixer */ 469 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { 470 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 471 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 472 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), 473 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 474 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 475 }; 476 477 /* Left Line1 Mux */ 478 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls = 479 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]); 480 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls = 481 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]); 482 483 /* Right Line1 Mux */ 484 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls = 485 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]); 486 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls = 487 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]); 488 489 /* Left Line2 Mux */ 490 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = 491 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); 492 493 /* Right Line2 Mux */ 494 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = 495 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); 496 497 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { 498 /* Left DAC to Left Outputs */ 499 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), 500 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, 501 &aic3x_left_dac_mux_controls), 502 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, 503 &aic3x_left_hpcom_mux_controls), 504 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), 505 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), 506 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), 507 508 /* Right DAC to Right Outputs */ 509 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), 510 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, 511 &aic3x_right_dac_mux_controls), 512 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, 513 &aic3x_right_hpcom_mux_controls), 514 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), 515 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), 516 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), 517 518 /* Mono Output */ 519 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), 520 521 /* Inputs to Left ADC */ 522 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), 523 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 524 &aic3x_left_pga_mixer_controls[0], 525 ARRAY_SIZE(aic3x_left_pga_mixer_controls)), 526 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, 527 &aic3x_left_line1l_mux_controls), 528 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, 529 &aic3x_left_line1r_mux_controls), 530 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, 531 &aic3x_left_line2_mux_controls), 532 533 /* Inputs to Right ADC */ 534 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 535 LINE1R_2_RADC_CTRL, 2, 0), 536 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 537 &aic3x_right_pga_mixer_controls[0], 538 ARRAY_SIZE(aic3x_right_pga_mixer_controls)), 539 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, 540 &aic3x_right_line1l_mux_controls), 541 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, 542 &aic3x_right_line1r_mux_controls), 543 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, 544 &aic3x_right_line2_mux_controls), 545 546 /* 547 * Not a real mic bias widget but similar function. This is for dynamic 548 * control of GPIO1 digital mic modulator clock output function when 549 * using digital mic. 550 */ 551 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", 552 AIC3X_GPIO1_REG, 4, 0xf, 553 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, 554 AIC3X_GPIO1_FUNC_DISABLED), 555 556 /* 557 * Also similar function like mic bias. Selects digital mic with 558 * configurable oversampling rate instead of ADC converter. 559 */ 560 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", 561 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), 562 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", 563 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), 564 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", 565 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 566 567 /* Mic Bias */ 568 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V", 569 MICBIAS_CTRL, 6, 3, 1, 0), 570 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V", 571 MICBIAS_CTRL, 6, 3, 2, 0), 572 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD", 573 MICBIAS_CTRL, 6, 3, 3, 0), 574 575 /* Output mixers */ 576 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 577 &aic3x_left_line_mixer_controls[0], 578 ARRAY_SIZE(aic3x_left_line_mixer_controls)), 579 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 580 &aic3x_right_line_mixer_controls[0], 581 ARRAY_SIZE(aic3x_right_line_mixer_controls)), 582 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, 583 &aic3x_mono_mixer_controls[0], 584 ARRAY_SIZE(aic3x_mono_mixer_controls)), 585 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 586 &aic3x_left_hp_mixer_controls[0], 587 ARRAY_SIZE(aic3x_left_hp_mixer_controls)), 588 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 589 &aic3x_right_hp_mixer_controls[0], 590 ARRAY_SIZE(aic3x_right_hp_mixer_controls)), 591 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 592 &aic3x_left_hpcom_mixer_controls[0], 593 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), 594 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 595 &aic3x_right_hpcom_mixer_controls[0], 596 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), 597 598 SND_SOC_DAPM_OUTPUT("LLOUT"), 599 SND_SOC_DAPM_OUTPUT("RLOUT"), 600 SND_SOC_DAPM_OUTPUT("MONO_LOUT"), 601 SND_SOC_DAPM_OUTPUT("HPLOUT"), 602 SND_SOC_DAPM_OUTPUT("HPROUT"), 603 SND_SOC_DAPM_OUTPUT("HPLCOM"), 604 SND_SOC_DAPM_OUTPUT("HPRCOM"), 605 606 SND_SOC_DAPM_INPUT("MIC3L"), 607 SND_SOC_DAPM_INPUT("MIC3R"), 608 SND_SOC_DAPM_INPUT("LINE1L"), 609 SND_SOC_DAPM_INPUT("LINE1R"), 610 SND_SOC_DAPM_INPUT("LINE2L"), 611 SND_SOC_DAPM_INPUT("LINE2R"), 612 613 /* 614 * Virtual output pin to detection block inside codec. This can be 615 * used to keep codec bias on if gpio or detection features are needed. 616 * Force pin on or construct a path with an input jack and mic bias 617 * widgets. 618 */ 619 SND_SOC_DAPM_OUTPUT("Detection"), 620 }; 621 622 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { 623 /* Class-D outputs */ 624 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0), 625 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0), 626 627 SND_SOC_DAPM_OUTPUT("SPOP"), 628 SND_SOC_DAPM_OUTPUT("SPOM"), 629 }; 630 631 static const struct snd_soc_dapm_route intercon[] = { 632 /* Left Input */ 633 {"Left Line1L Mux", "single-ended", "LINE1L"}, 634 {"Left Line1L Mux", "differential", "LINE1L"}, 635 636 {"Left Line2L Mux", "single-ended", "LINE2L"}, 637 {"Left Line2L Mux", "differential", "LINE2L"}, 638 639 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, 640 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, 641 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, 642 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, 643 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, 644 645 {"Left ADC", NULL, "Left PGA Mixer"}, 646 {"Left ADC", NULL, "GPIO1 dmic modclk"}, 647 648 /* Right Input */ 649 {"Right Line1R Mux", "single-ended", "LINE1R"}, 650 {"Right Line1R Mux", "differential", "LINE1R"}, 651 652 {"Right Line2R Mux", "single-ended", "LINE2R"}, 653 {"Right Line2R Mux", "differential", "LINE2R"}, 654 655 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, 656 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, 657 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, 658 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, 659 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, 660 661 {"Right ADC", NULL, "Right PGA Mixer"}, 662 {"Right ADC", NULL, "GPIO1 dmic modclk"}, 663 664 /* 665 * Logical path between digital mic enable and GPIO1 modulator clock 666 * output function 667 */ 668 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, 669 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, 670 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, 671 672 /* Left DAC Output */ 673 {"Left DAC Mux", "DAC_L1", "Left DAC"}, 674 {"Left DAC Mux", "DAC_L2", "Left DAC"}, 675 {"Left DAC Mux", "DAC_L3", "Left DAC"}, 676 677 /* Right DAC Output */ 678 {"Right DAC Mux", "DAC_R1", "Right DAC"}, 679 {"Right DAC Mux", "DAC_R2", "Right DAC"}, 680 {"Right DAC Mux", "DAC_R3", "Right DAC"}, 681 682 /* Left Line Output */ 683 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 684 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 685 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 686 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 687 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 688 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 689 690 {"Left Line Out", NULL, "Left Line Mixer"}, 691 {"Left Line Out", NULL, "Left DAC Mux"}, 692 {"LLOUT", NULL, "Left Line Out"}, 693 694 /* Right Line Output */ 695 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 696 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 697 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 698 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 699 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 700 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 701 702 {"Right Line Out", NULL, "Right Line Mixer"}, 703 {"Right Line Out", NULL, "Right DAC Mux"}, 704 {"RLOUT", NULL, "Right Line Out"}, 705 706 /* Mono Output */ 707 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 708 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 709 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, 710 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 711 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 712 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, 713 714 {"Mono Out", NULL, "Mono Mixer"}, 715 {"MONO_LOUT", NULL, "Mono Out"}, 716 717 /* Left HP Output */ 718 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 719 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 720 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 721 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 722 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 723 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 724 725 {"Left HP Out", NULL, "Left HP Mixer"}, 726 {"Left HP Out", NULL, "Left DAC Mux"}, 727 {"HPLOUT", NULL, "Left HP Out"}, 728 729 /* Right HP Output */ 730 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 731 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 732 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 733 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 734 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 735 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 736 737 {"Right HP Out", NULL, "Right HP Mixer"}, 738 {"Right HP Out", NULL, "Right DAC Mux"}, 739 {"HPROUT", NULL, "Right HP Out"}, 740 741 /* Left HPCOM Output */ 742 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 743 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 744 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 745 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 746 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 747 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 748 749 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, 750 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, 751 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, 752 {"Left HP Com", NULL, "Left HPCOM Mux"}, 753 {"HPLCOM", NULL, "Left HP Com"}, 754 755 /* Right HPCOM Output */ 756 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 757 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 758 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 759 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 760 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 761 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 762 763 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, 764 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, 765 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, 766 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, 767 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, 768 {"Right HP Com", NULL, "Right HPCOM Mux"}, 769 {"HPRCOM", NULL, "Right HP Com"}, 770 }; 771 772 static const struct snd_soc_dapm_route intercon_3007[] = { 773 /* Class-D outputs */ 774 {"Left Class-D Out", NULL, "Left Line Out"}, 775 {"Right Class-D Out", NULL, "Left Line Out"}, 776 {"SPOP", NULL, "Left Class-D Out"}, 777 {"SPOM", NULL, "Right Class-D Out"}, 778 }; 779 780 static int aic3x_add_widgets(struct snd_soc_codec *codec) 781 { 782 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 783 struct snd_soc_dapm_context *dapm = &codec->dapm; 784 785 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets, 786 ARRAY_SIZE(aic3x_dapm_widgets)); 787 788 /* set up audio path interconnects */ 789 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 790 791 if (aic3x->model == AIC3X_MODEL_3007) { 792 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, 793 ARRAY_SIZE(aic3007_dapm_widgets)); 794 snd_soc_dapm_add_routes(dapm, intercon_3007, 795 ARRAY_SIZE(intercon_3007)); 796 } 797 798 return 0; 799 } 800 801 static int aic3x_hw_params(struct snd_pcm_substream *substream, 802 struct snd_pcm_hw_params *params, 803 struct snd_soc_dai *dai) 804 { 805 struct snd_soc_pcm_runtime *rtd = substream->private_data; 806 struct snd_soc_codec *codec =rtd->codec; 807 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 808 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 809 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 810 u16 d, pll_d = 1; 811 int clk; 812 813 /* select data word length */ 814 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); 815 switch (params_format(params)) { 816 case SNDRV_PCM_FORMAT_S16_LE: 817 break; 818 case SNDRV_PCM_FORMAT_S20_3LE: 819 data |= (0x01 << 4); 820 break; 821 case SNDRV_PCM_FORMAT_S24_LE: 822 data |= (0x02 << 4); 823 break; 824 case SNDRV_PCM_FORMAT_S32_LE: 825 data |= (0x03 << 4); 826 break; 827 } 828 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data); 829 830 /* Fsref can be 44100 or 48000 */ 831 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; 832 833 /* Try to find a value for Q which allows us to bypass the PLL and 834 * generate CODEC_CLK directly. */ 835 for (pll_q = 2; pll_q < 18; pll_q++) 836 if (aic3x->sysclk / (128 * pll_q) == fsref) { 837 bypass_pll = 1; 838 break; 839 } 840 841 if (bypass_pll) { 842 pll_q &= 0xf; 843 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 844 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 845 /* disable PLL if it is bypassed */ 846 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); 847 848 } else { 849 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 850 /* enable PLL when it is used */ 851 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 852 PLL_ENABLE, PLL_ENABLE); 853 } 854 855 /* Route Left DAC to left channel input and 856 * right DAC to right channel input */ 857 data = (LDAC2LCH | RDAC2RCH); 858 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; 859 if (params_rate(params) >= 64000) 860 data |= DUAL_RATE_MODE; 861 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data); 862 863 /* codec sample rate select */ 864 data = (fsref * 20) / params_rate(params); 865 if (params_rate(params) < 64000) 866 data /= 2; 867 data /= 5; 868 data -= 2; 869 data |= (data << 4); 870 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); 871 872 if (bypass_pll) 873 return 0; 874 875 /* Use PLL, compute appropriate setup for j, d, r and p, the closest 876 * one wins the game. Try with d==0 first, next with d!=0. 877 * Constraints for j are according to the datasheet. 878 * The sysclk is divided by 1000 to prevent integer overflows. 879 */ 880 881 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); 882 883 for (r = 1; r <= 16; r++) 884 for (p = 1; p <= 8; p++) { 885 for (j = 4; j <= 55; j++) { 886 /* This is actually 1000*((j+(d/10000))*r)/p 887 * The term had to be converted to get 888 * rid of the division by 10000; d = 0 here 889 */ 890 int tmp_clk = (1000 * j * r) / p; 891 892 /* Check whether this values get closer than 893 * the best ones we had before 894 */ 895 if (abs(codec_clk - tmp_clk) < 896 abs(codec_clk - last_clk)) { 897 pll_j = j; pll_d = 0; 898 pll_r = r; pll_p = p; 899 last_clk = tmp_clk; 900 } 901 902 /* Early exit for exact matches */ 903 if (tmp_clk == codec_clk) 904 goto found; 905 } 906 } 907 908 /* try with d != 0 */ 909 for (p = 1; p <= 8; p++) { 910 j = codec_clk * p / 1000; 911 912 if (j < 4 || j > 11) 913 continue; 914 915 /* do not use codec_clk here since we'd loose precision */ 916 d = ((2048 * p * fsref) - j * aic3x->sysclk) 917 * 100 / (aic3x->sysclk/100); 918 919 clk = (10000 * j + d) / (10 * p); 920 921 /* check whether this values get closer than the best 922 * ones we had before */ 923 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { 924 pll_j = j; pll_d = d; pll_r = 1; pll_p = p; 925 last_clk = clk; 926 } 927 928 /* Early exit for exact matches */ 929 if (clk == codec_clk) 930 goto found; 931 } 932 933 if (last_clk == 0) { 934 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); 935 return -EINVAL; 936 } 937 938 found: 939 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); 940 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, 941 data | (pll_p << PLLP_SHIFT)); 942 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, 943 pll_r << PLLR_SHIFT); 944 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); 945 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, 946 (pll_d >> 6) << PLLD_MSB_SHIFT); 947 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, 948 (pll_d & 0x3F) << PLLD_LSB_SHIFT); 949 950 return 0; 951 } 952 953 static int aic3x_mute(struct snd_soc_dai *dai, int mute) 954 { 955 struct snd_soc_codec *codec = dai->codec; 956 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON; 957 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON; 958 959 if (mute) { 960 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); 961 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); 962 } else { 963 snd_soc_write(codec, LDAC_VOL, ldac_reg); 964 snd_soc_write(codec, RDAC_VOL, rdac_reg); 965 } 966 967 return 0; 968 } 969 970 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 971 int clk_id, unsigned int freq, int dir) 972 { 973 struct snd_soc_codec *codec = codec_dai->codec; 974 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 975 976 aic3x->sysclk = freq; 977 return 0; 978 } 979 980 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, 981 unsigned int fmt) 982 { 983 struct snd_soc_codec *codec = codec_dai->codec; 984 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 985 u8 iface_areg, iface_breg; 986 int delay = 0; 987 988 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; 989 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; 990 991 /* set master/slave audio interface */ 992 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 993 case SND_SOC_DAIFMT_CBM_CFM: 994 aic3x->master = 1; 995 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; 996 break; 997 case SND_SOC_DAIFMT_CBS_CFS: 998 aic3x->master = 0; 999 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER); 1000 break; 1001 default: 1002 return -EINVAL; 1003 } 1004 1005 /* 1006 * match both interface format and signal polarities since they 1007 * are fixed 1008 */ 1009 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | 1010 SND_SOC_DAIFMT_INV_MASK)) { 1011 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): 1012 break; 1013 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): 1014 delay = 1; 1015 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): 1016 iface_breg |= (0x01 << 6); 1017 break; 1018 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): 1019 iface_breg |= (0x02 << 6); 1020 break; 1021 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): 1022 iface_breg |= (0x03 << 6); 1023 break; 1024 default: 1025 return -EINVAL; 1026 } 1027 1028 /* set iface */ 1029 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); 1030 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); 1031 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay); 1032 1033 return 0; 1034 } 1035 1036 static int aic3x_init_3007(struct snd_soc_codec *codec) 1037 { 1038 u8 tmp1, tmp2, *cache = codec->reg_cache; 1039 1040 /* 1041 * There is no need to cache writes to undocumented page 0xD but 1042 * respective page 0 register cache entries must be preserved 1043 */ 1044 tmp1 = cache[0xD]; 1045 tmp2 = cache[0x8]; 1046 /* Class-D speaker driver init; datasheet p. 46 */ 1047 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D); 1048 snd_soc_write(codec, 0xD, 0x0D); 1049 snd_soc_write(codec, 0x8, 0x5C); 1050 snd_soc_write(codec, 0x8, 0x5D); 1051 snd_soc_write(codec, 0x8, 0x5C); 1052 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00); 1053 cache[0xD] = tmp1; 1054 cache[0x8] = tmp2; 1055 1056 return 0; 1057 } 1058 1059 static int aic3x_regulator_event(struct notifier_block *nb, 1060 unsigned long event, void *data) 1061 { 1062 struct aic3x_disable_nb *disable_nb = 1063 container_of(nb, struct aic3x_disable_nb, nb); 1064 struct aic3x_priv *aic3x = disable_nb->aic3x; 1065 1066 if (event & REGULATOR_EVENT_DISABLE) { 1067 /* 1068 * Put codec to reset and require cache sync as at least one 1069 * of the supplies was disabled 1070 */ 1071 if (gpio_is_valid(aic3x->gpio_reset)) 1072 gpio_set_value(aic3x->gpio_reset, 0); 1073 aic3x->codec->cache_sync = 1; 1074 } 1075 1076 return 0; 1077 } 1078 1079 static int aic3x_set_power(struct snd_soc_codec *codec, int power) 1080 { 1081 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1082 int i, ret; 1083 u8 *cache = codec->reg_cache; 1084 1085 if (power) { 1086 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), 1087 aic3x->supplies); 1088 if (ret) 1089 goto out; 1090 aic3x->power = 1; 1091 /* 1092 * Reset release and cache sync is necessary only if some 1093 * supply was off or if there were cached writes 1094 */ 1095 if (!codec->cache_sync) 1096 goto out; 1097 1098 if (gpio_is_valid(aic3x->gpio_reset)) { 1099 udelay(1); 1100 gpio_set_value(aic3x->gpio_reset, 1); 1101 } 1102 1103 /* Sync reg_cache with the hardware */ 1104 codec->cache_only = 0; 1105 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++) 1106 snd_soc_write(codec, i, cache[i]); 1107 if (aic3x->model == AIC3X_MODEL_3007) 1108 aic3x_init_3007(codec); 1109 codec->cache_sync = 0; 1110 } else { 1111 /* 1112 * Do soft reset to this codec instance in order to clear 1113 * possible VDD leakage currents in case the supply regulators 1114 * remain on 1115 */ 1116 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1117 codec->cache_sync = 1; 1118 aic3x->power = 0; 1119 /* HW writes are needless when bias is off */ 1120 codec->cache_only = 1; 1121 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), 1122 aic3x->supplies); 1123 } 1124 out: 1125 return ret; 1126 } 1127 1128 static int aic3x_set_bias_level(struct snd_soc_codec *codec, 1129 enum snd_soc_bias_level level) 1130 { 1131 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1132 1133 switch (level) { 1134 case SND_SOC_BIAS_ON: 1135 break; 1136 case SND_SOC_BIAS_PREPARE: 1137 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY && 1138 aic3x->master) { 1139 /* enable pll */ 1140 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1141 PLL_ENABLE, PLL_ENABLE); 1142 } 1143 break; 1144 case SND_SOC_BIAS_STANDBY: 1145 if (!aic3x->power) 1146 aic3x_set_power(codec, 1); 1147 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE && 1148 aic3x->master) { 1149 /* disable pll */ 1150 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1151 PLL_ENABLE, 0); 1152 } 1153 break; 1154 case SND_SOC_BIAS_OFF: 1155 if (aic3x->power) 1156 aic3x_set_power(codec, 0); 1157 break; 1158 } 1159 codec->dapm.bias_level = level; 1160 1161 return 0; 1162 } 1163 1164 void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect, 1165 int headset_debounce, int button_debounce) 1166 { 1167 u8 val; 1168 1169 val = ((detect & AIC3X_HEADSET_DETECT_MASK) 1170 << AIC3X_HEADSET_DETECT_SHIFT) | 1171 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK) 1172 << AIC3X_HEADSET_DEBOUNCE_SHIFT) | 1173 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK) 1174 << AIC3X_BUTTON_DEBOUNCE_SHIFT); 1175 1176 if (detect & AIC3X_HEADSET_DETECT_MASK) 1177 val |= AIC3X_HEADSET_DETECT_ENABLED; 1178 1179 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val); 1180 } 1181 1182 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1183 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1184 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1185 1186 static const struct snd_soc_dai_ops aic3x_dai_ops = { 1187 .hw_params = aic3x_hw_params, 1188 .digital_mute = aic3x_mute, 1189 .set_sysclk = aic3x_set_dai_sysclk, 1190 .set_fmt = aic3x_set_dai_fmt, 1191 }; 1192 1193 static struct snd_soc_dai_driver aic3x_dai = { 1194 .name = "tlv320aic3x-hifi", 1195 .playback = { 1196 .stream_name = "Playback", 1197 .channels_min = 1, 1198 .channels_max = 2, 1199 .rates = AIC3X_RATES, 1200 .formats = AIC3X_FORMATS,}, 1201 .capture = { 1202 .stream_name = "Capture", 1203 .channels_min = 1, 1204 .channels_max = 2, 1205 .rates = AIC3X_RATES, 1206 .formats = AIC3X_FORMATS,}, 1207 .ops = &aic3x_dai_ops, 1208 .symmetric_rates = 1, 1209 }; 1210 1211 static int aic3x_suspend(struct snd_soc_codec *codec) 1212 { 1213 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1214 1215 return 0; 1216 } 1217 1218 static int aic3x_resume(struct snd_soc_codec *codec) 1219 { 1220 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1221 1222 return 0; 1223 } 1224 1225 /* 1226 * initialise the AIC3X driver 1227 * register the mixer and dsp interfaces with the kernel 1228 */ 1229 static int aic3x_init(struct snd_soc_codec *codec) 1230 { 1231 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1232 1233 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); 1234 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1235 1236 /* DAC default volume and mute */ 1237 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); 1238 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); 1239 1240 /* DAC to HP default volume and route to Output mixer */ 1241 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); 1242 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); 1243 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1244 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1245 /* DAC to Line Out default volume and route to Output mixer */ 1246 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1247 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1248 /* DAC to Mono Line Out default volume and route to Output mixer */ 1249 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1250 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1251 1252 /* unmute all outputs */ 1253 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE); 1254 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE); 1255 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE); 1256 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE); 1257 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE); 1258 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE); 1259 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE); 1260 1261 /* ADC default volume and unmute */ 1262 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN); 1263 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN); 1264 /* By default route Line1 to ADC PGA mixer */ 1265 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0); 1266 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0); 1267 1268 /* PGA to HP Bypass default volume, disconnect from Output Mixer */ 1269 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); 1270 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); 1271 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); 1272 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); 1273 /* PGA to Line Out default volume, disconnect from Output Mixer */ 1274 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); 1275 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); 1276 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ 1277 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); 1278 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); 1279 1280 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ 1281 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); 1282 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); 1283 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); 1284 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); 1285 /* Line2 Line Out default volume, disconnect from Output Mixer */ 1286 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); 1287 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); 1288 /* Line2 to Mono Out default volume, disconnect from Output Mixer */ 1289 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); 1290 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); 1291 1292 if (aic3x->model == AIC3X_MODEL_3007) { 1293 aic3x_init_3007(codec); 1294 snd_soc_write(codec, CLASSD_CTRL, 0); 1295 } 1296 1297 return 0; 1298 } 1299 1300 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x) 1301 { 1302 struct aic3x_priv *a; 1303 1304 list_for_each_entry(a, &reset_list, list) { 1305 if (gpio_is_valid(aic3x->gpio_reset) && 1306 aic3x->gpio_reset == a->gpio_reset) 1307 return true; 1308 } 1309 1310 return false; 1311 } 1312 1313 static int aic3x_probe(struct snd_soc_codec *codec) 1314 { 1315 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1316 int ret, i; 1317 1318 INIT_LIST_HEAD(&aic3x->list); 1319 aic3x->codec = codec; 1320 1321 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type); 1322 if (ret != 0) { 1323 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1324 return ret; 1325 } 1326 1327 if (gpio_is_valid(aic3x->gpio_reset) && 1328 !aic3x_is_shared_reset(aic3x)) { 1329 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); 1330 if (ret != 0) 1331 goto err_gpio; 1332 gpio_direction_output(aic3x->gpio_reset, 0); 1333 } 1334 1335 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1336 aic3x->supplies[i].supply = aic3x_supply_names[i]; 1337 1338 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies), 1339 aic3x->supplies); 1340 if (ret != 0) { 1341 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 1342 goto err_get; 1343 } 1344 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) { 1345 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; 1346 aic3x->disable_nb[i].aic3x = aic3x; 1347 ret = regulator_register_notifier(aic3x->supplies[i].consumer, 1348 &aic3x->disable_nb[i].nb); 1349 if (ret) { 1350 dev_err(codec->dev, 1351 "Failed to request regulator notifier: %d\n", 1352 ret); 1353 goto err_notif; 1354 } 1355 } 1356 1357 codec->cache_only = 1; 1358 aic3x_init(codec); 1359 1360 if (aic3x->setup) { 1361 /* setup GPIO functions */ 1362 snd_soc_write(codec, AIC3X_GPIO1_REG, 1363 (aic3x->setup->gpio_func[0] & 0xf) << 4); 1364 snd_soc_write(codec, AIC3X_GPIO2_REG, 1365 (aic3x->setup->gpio_func[1] & 0xf) << 4); 1366 } 1367 1368 snd_soc_add_codec_controls(codec, aic3x_snd_controls, 1369 ARRAY_SIZE(aic3x_snd_controls)); 1370 if (aic3x->model == AIC3X_MODEL_3007) 1371 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1); 1372 1373 aic3x_add_widgets(codec); 1374 list_add(&aic3x->list, &reset_list); 1375 1376 return 0; 1377 1378 err_notif: 1379 while (i--) 1380 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1381 &aic3x->disable_nb[i].nb); 1382 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1383 err_get: 1384 if (gpio_is_valid(aic3x->gpio_reset) && 1385 !aic3x_is_shared_reset(aic3x)) 1386 gpio_free(aic3x->gpio_reset); 1387 err_gpio: 1388 return ret; 1389 } 1390 1391 static int aic3x_remove(struct snd_soc_codec *codec) 1392 { 1393 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1394 int i; 1395 1396 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1397 list_del(&aic3x->list); 1398 if (gpio_is_valid(aic3x->gpio_reset) && 1399 !aic3x_is_shared_reset(aic3x)) { 1400 gpio_set_value(aic3x->gpio_reset, 0); 1401 gpio_free(aic3x->gpio_reset); 1402 } 1403 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1404 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1405 &aic3x->disable_nb[i].nb); 1406 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1407 1408 return 0; 1409 } 1410 1411 static struct snd_soc_codec_driver soc_codec_dev_aic3x = { 1412 .set_bias_level = aic3x_set_bias_level, 1413 .idle_bias_off = true, 1414 .reg_cache_size = ARRAY_SIZE(aic3x_reg), 1415 .reg_word_size = sizeof(u8), 1416 .reg_cache_default = aic3x_reg, 1417 .probe = aic3x_probe, 1418 .remove = aic3x_remove, 1419 .suspend = aic3x_suspend, 1420 .resume = aic3x_resume, 1421 }; 1422 1423 /* 1424 * AIC3X 2 wire address can be up to 4 devices with device addresses 1425 * 0x18, 0x19, 0x1A, 0x1B 1426 */ 1427 1428 static const struct i2c_device_id aic3x_i2c_id[] = { 1429 { "tlv320aic3x", AIC3X_MODEL_3X }, 1430 { "tlv320aic33", AIC3X_MODEL_33 }, 1431 { "tlv320aic3007", AIC3X_MODEL_3007 }, 1432 { } 1433 }; 1434 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); 1435 1436 /* 1437 * If the i2c layer weren't so broken, we could pass this kind of data 1438 * around 1439 */ 1440 static int aic3x_i2c_probe(struct i2c_client *i2c, 1441 const struct i2c_device_id *id) 1442 { 1443 struct aic3x_pdata *pdata = i2c->dev.platform_data; 1444 struct aic3x_priv *aic3x; 1445 int ret; 1446 1447 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL); 1448 if (aic3x == NULL) { 1449 dev_err(&i2c->dev, "failed to create private data\n"); 1450 return -ENOMEM; 1451 } 1452 1453 aic3x->control_type = SND_SOC_I2C; 1454 1455 i2c_set_clientdata(i2c, aic3x); 1456 if (pdata) { 1457 aic3x->gpio_reset = pdata->gpio_reset; 1458 aic3x->setup = pdata->setup; 1459 } else { 1460 aic3x->gpio_reset = -1; 1461 } 1462 1463 aic3x->model = id->driver_data; 1464 1465 ret = snd_soc_register_codec(&i2c->dev, 1466 &soc_codec_dev_aic3x, &aic3x_dai, 1); 1467 return ret; 1468 } 1469 1470 static int aic3x_i2c_remove(struct i2c_client *client) 1471 { 1472 snd_soc_unregister_codec(&client->dev); 1473 return 0; 1474 } 1475 1476 /* machine i2c codec control layer */ 1477 static struct i2c_driver aic3x_i2c_driver = { 1478 .driver = { 1479 .name = "tlv320aic3x-codec", 1480 .owner = THIS_MODULE, 1481 }, 1482 .probe = aic3x_i2c_probe, 1483 .remove = aic3x_i2c_remove, 1484 .id_table = aic3x_i2c_id, 1485 }; 1486 1487 static int __init aic3x_modinit(void) 1488 { 1489 int ret = 0; 1490 ret = i2c_add_driver(&aic3x_i2c_driver); 1491 if (ret != 0) { 1492 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n", 1493 ret); 1494 } 1495 return ret; 1496 } 1497 module_init(aic3x_modinit); 1498 1499 static void __exit aic3x_exit(void) 1500 { 1501 i2c_del_driver(&aic3x_i2c_driver); 1502 } 1503 module_exit(aic3x_exit); 1504 1505 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); 1506 MODULE_AUTHOR("Vladimir Barinov"); 1507 MODULE_LICENSE("GPL"); 1508