xref: /openbmc/linux/sound/soc/codecs/tlv320aic3x.c (revision 22246614)
1 /*
2  * ALSA SoC TLV320AIC3X codec driver
3  *
4  * Author:      Vladimir Barinov, <vbarinov@ru.mvista.com>
5  * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6  *
7  * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  *
13  * Notes:
14  *  The AIC3X is a driver for a low power stereo audio
15  *  codecs aic31, aic32, aic33.
16  *
17  *  It supports full aic33 codec functionality.
18  *  The compatibility with aic32, aic31 is as follows:
19  *        aic32        |        aic31
20  *  ---------------------------------------
21  *   MONO_LOUT -> N/A  |  MONO_LOUT -> N/A
22  *                     |  IN1L -> LINE1L
23  *                     |  IN1R -> LINE1R
24  *                     |  IN2L -> LINE2L
25  *                     |  IN2R -> LINE2R
26  *                     |  MIC3L/R -> N/A
27  *   truncated internal functionality in
28  *   accordance with documentation
29  *  ---------------------------------------
30  *
31  *  Hence the machine layer should disable unsupported inputs/outputs by
32  *  snd_soc_dapm_set_endpoint(codec, "MONO_LOUT", 0), etc.
33  */
34 
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/pm.h>
40 #include <linux/i2c.h>
41 #include <linux/platform_device.h>
42 #include <sound/core.h>
43 #include <sound/pcm.h>
44 #include <sound/pcm_params.h>
45 #include <sound/soc.h>
46 #include <sound/soc-dapm.h>
47 #include <sound/initval.h>
48 
49 #include "tlv320aic3x.h"
50 
51 #define AUDIO_NAME "aic3x"
52 #define AIC3X_VERSION "0.1"
53 
54 /* codec private data */
55 struct aic3x_priv {
56 	unsigned int sysclk;
57 	int master;
58 };
59 
60 /*
61  * AIC3X register cache
62  * We can't read the AIC3X register space when we are
63  * using 2 wire for device control, so we cache them instead.
64  * There is no point in caching the reset register
65  */
66 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
67 	0x00, 0x00, 0x00, 0x10,	/* 0 */
68 	0x04, 0x00, 0x00, 0x00,	/* 4 */
69 	0x00, 0x00, 0x00, 0x01,	/* 8 */
70 	0x00, 0x00, 0x00, 0x80,	/* 12 */
71 	0x80, 0xff, 0xff, 0x78,	/* 16 */
72 	0x78, 0x78, 0x78, 0x78,	/* 20 */
73 	0x78, 0x00, 0x00, 0xfe,	/* 24 */
74 	0x00, 0x00, 0xfe, 0x00,	/* 28 */
75 	0x18, 0x18, 0x00, 0x00,	/* 32 */
76 	0x00, 0x00, 0x00, 0x00,	/* 36 */
77 	0x00, 0x00, 0x00, 0x80,	/* 40 */
78 	0x80, 0x00, 0x00, 0x00,	/* 44 */
79 	0x00, 0x00, 0x00, 0x04,	/* 48 */
80 	0x00, 0x00, 0x00, 0x00,	/* 52 */
81 	0x00, 0x00, 0x04, 0x00,	/* 56 */
82 	0x00, 0x00, 0x00, 0x00,	/* 60 */
83 	0x00, 0x04, 0x00, 0x00,	/* 64 */
84 	0x00, 0x00, 0x00, 0x00,	/* 68 */
85 	0x04, 0x00, 0x00, 0x00,	/* 72 */
86 	0x00, 0x00, 0x00, 0x00,	/* 76 */
87 	0x00, 0x00, 0x00, 0x00,	/* 80 */
88 	0x00, 0x00, 0x00, 0x00,	/* 84 */
89 	0x00, 0x00, 0x00, 0x00,	/* 88 */
90 	0x00, 0x00, 0x00, 0x00,	/* 92 */
91 	0x00, 0x00, 0x00, 0x00,	/* 96 */
92 	0x00, 0x00, 0x02,	/* 100 */
93 };
94 
95 /*
96  * read aic3x register cache
97  */
98 static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
99 						unsigned int reg)
100 {
101 	u8 *cache = codec->reg_cache;
102 	if (reg >= AIC3X_CACHEREGNUM)
103 		return -1;
104 	return cache[reg];
105 }
106 
107 /*
108  * write aic3x register cache
109  */
110 static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
111 					 u8 reg, u8 value)
112 {
113 	u8 *cache = codec->reg_cache;
114 	if (reg >= AIC3X_CACHEREGNUM)
115 		return;
116 	cache[reg] = value;
117 }
118 
119 /*
120  * write to the aic3x register space
121  */
122 static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
123 		       unsigned int value)
124 {
125 	u8 data[2];
126 
127 	/* data is
128 	 *   D15..D8 aic3x register offset
129 	 *   D7...D0 register data
130 	 */
131 	data[0] = reg & 0xff;
132 	data[1] = value & 0xff;
133 
134 	aic3x_write_reg_cache(codec, data[0], data[1]);
135 	if (codec->hw_write(codec->control_data, data, 2) == 2)
136 		return 0;
137 	else
138 		return -EIO;
139 }
140 
141 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
142 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
143 	.info = snd_soc_info_volsw, \
144 	.get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
145 	.private_value =  SOC_SINGLE_VALUE(reg, shift, mask, invert) }
146 
147 /*
148  * All input lines are connected when !0xf and disconnected with 0xf bit field,
149  * so we have to use specific dapm_put call for input mixer
150  */
151 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
152 					struct snd_ctl_elem_value *ucontrol)
153 {
154 	struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
155 	int reg = kcontrol->private_value & 0xff;
156 	int shift = (kcontrol->private_value >> 8) & 0x0f;
157 	int mask = (kcontrol->private_value >> 16) & 0xff;
158 	int invert = (kcontrol->private_value >> 24) & 0x01;
159 	unsigned short val, val_mask;
160 	int ret;
161 	struct snd_soc_dapm_path *path;
162 	int found = 0;
163 
164 	val = (ucontrol->value.integer.value[0] & mask);
165 
166 	mask = 0xf;
167 	if (val)
168 		val = mask;
169 
170 	if (invert)
171 		val = mask - val;
172 	val_mask = mask << shift;
173 	val = val << shift;
174 
175 	mutex_lock(&widget->codec->mutex);
176 
177 	if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
178 		/* find dapm widget path assoc with kcontrol */
179 		list_for_each_entry(path, &widget->codec->dapm_paths, list) {
180 			if (path->kcontrol != kcontrol)
181 				continue;
182 
183 			/* found, now check type */
184 			found = 1;
185 			if (val)
186 				/* new connection */
187 				path->connect = invert ? 0 : 1;
188 			else
189 				/* old connection must be powered down */
190 				path->connect = invert ? 1 : 0;
191 			break;
192 		}
193 
194 		if (found)
195 			snd_soc_dapm_sync_endpoints(widget->codec);
196 	}
197 
198 	ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
199 
200 	mutex_unlock(&widget->codec->mutex);
201 	return ret;
202 }
203 
204 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
205 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
206 static const char *aic3x_left_hpcom_mux[] =
207     { "differential of HPLOUT", "constant VCM", "single-ended" };
208 static const char *aic3x_right_hpcom_mux[] =
209     { "differential of HPROUT", "constant VCM", "single-ended",
210       "differential of HPLCOM", "external feedback" };
211 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
212 
213 #define LDAC_ENUM	0
214 #define RDAC_ENUM	1
215 #define LHPCOM_ENUM	2
216 #define RHPCOM_ENUM	3
217 #define LINE1L_ENUM	4
218 #define LINE1R_ENUM	5
219 #define LINE2L_ENUM	6
220 #define LINE2R_ENUM	7
221 
222 static const struct soc_enum aic3x_enum[] = {
223 	SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
224 	SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
225 	SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
226 	SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
227 	SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
228 	SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
229 	SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
230 	SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
231 };
232 
233 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
234 	/* Output */
235 	SOC_DOUBLE_R("PCM Playback Volume", LDAC_VOL, RDAC_VOL, 0, 0x7f, 1),
236 
237 	SOC_DOUBLE_R("Line DAC Playback Volume", DACL1_2_LLOPM_VOL,
238 		     DACR1_2_RLOPM_VOL, 0, 0x7f, 1),
239 	SOC_DOUBLE_R("Line DAC Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
240 		     0x01, 0),
241 	SOC_DOUBLE_R("Line PGA Bypass Playback Volume", PGAL_2_LLOPM_VOL,
242 		     PGAR_2_RLOPM_VOL, 0, 0x7f, 1),
243 	SOC_DOUBLE_R("Line Line2 Bypass Playback Volume", LINE2L_2_LLOPM_VOL,
244 		     LINE2R_2_RLOPM_VOL, 0, 0x7f, 1),
245 
246 	SOC_DOUBLE_R("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL,
247 		     DACR1_2_MONOLOPM_VOL, 0, 0x7f, 1),
248 	SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
249 	SOC_DOUBLE_R("Mono PGA Bypass Playback Volume", PGAL_2_MONOLOPM_VOL,
250 		     PGAR_2_MONOLOPM_VOL, 0, 0x7f, 1),
251 	SOC_DOUBLE_R("Mono Line2 Bypass Playback Volume", LINE2L_2_MONOLOPM_VOL,
252 		     LINE2R_2_MONOLOPM_VOL, 0, 0x7f, 1),
253 
254 	SOC_DOUBLE_R("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL,
255 		     DACR1_2_HPROUT_VOL, 0, 0x7f, 1),
256 	SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
257 		     0x01, 0),
258 	SOC_DOUBLE_R("HP PGA Bypass Playback Volume", PGAL_2_HPLOUT_VOL,
259 		     PGAR_2_HPROUT_VOL, 0, 0x7f, 1),
260 	SOC_DOUBLE_R("HP Line2 Bypass Playback Volume", LINE2L_2_HPLOUT_VOL,
261 		     LINE2R_2_HPROUT_VOL, 0, 0x7f, 1),
262 
263 	SOC_DOUBLE_R("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL,
264 		     DACR1_2_HPRCOM_VOL, 0, 0x7f, 1),
265 	SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
266 		     0x01, 0),
267 	SOC_DOUBLE_R("HPCOM PGA Bypass Playback Volume", PGAL_2_HPLCOM_VOL,
268 		     PGAR_2_HPRCOM_VOL, 0, 0x7f, 1),
269 	SOC_DOUBLE_R("HPCOM Line2 Bypass Playback Volume", LINE2L_2_HPLCOM_VOL,
270 		     LINE2R_2_HPRCOM_VOL, 0, 0x7f, 1),
271 
272 	/*
273 	 * Note: enable Automatic input Gain Controller with care. It can
274 	 * adjust PGA to max value when ADC is on and will never go back.
275 	*/
276 	SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
277 
278 	/* Input */
279 	SOC_DOUBLE_R("PGA Capture Volume", LADC_VOL, RADC_VOL, 0, 0x7f, 0),
280 	SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
281 };
282 
283 /* add non dapm controls */
284 static int aic3x_add_controls(struct snd_soc_codec *codec)
285 {
286 	int err, i;
287 
288 	for (i = 0; i < ARRAY_SIZE(aic3x_snd_controls); i++) {
289 		err = snd_ctl_add(codec->card,
290 				  snd_soc_cnew(&aic3x_snd_controls[i],
291 					       codec, NULL));
292 		if (err < 0)
293 			return err;
294 	}
295 
296 	return 0;
297 }
298 
299 /* Left DAC Mux */
300 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
301 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
302 
303 /* Right DAC Mux */
304 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
305 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
306 
307 /* Left HPCOM Mux */
308 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
309 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
310 
311 /* Right HPCOM Mux */
312 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
313 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
314 
315 /* Left DAC_L1 Mixer */
316 static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
317 	SOC_DAPM_SINGLE("Line Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
318 	SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
319 	SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
320 	SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
321 };
322 
323 /* Right DAC_R1 Mixer */
324 static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
325 	SOC_DAPM_SINGLE("Line Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
326 	SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
327 	SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
328 	SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
329 };
330 
331 /* Left PGA Mixer */
332 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
333 	SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
334 	SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
335 	SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
336 };
337 
338 /* Right PGA Mixer */
339 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
340 	SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
341 	SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
342 	SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
343 };
344 
345 /* Left Line1 Mux */
346 static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
347 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
348 
349 /* Right Line1 Mux */
350 static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
351 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
352 
353 /* Left Line2 Mux */
354 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
355 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
356 
357 /* Right Line2 Mux */
358 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
359 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
360 
361 /* Left PGA Bypass Mixer */
362 static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
363 	SOC_DAPM_SINGLE("Line Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
364 	SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
365 	SOC_DAPM_SINGLE("HP Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
366 	SOC_DAPM_SINGLE("HPCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
367 };
368 
369 /* Right PGA Bypass Mixer */
370 static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
371 	SOC_DAPM_SINGLE("Line Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
372 	SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
373 	SOC_DAPM_SINGLE("HP Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
374 	SOC_DAPM_SINGLE("HPCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
375 };
376 
377 /* Left Line2 Bypass Mixer */
378 static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
379 	SOC_DAPM_SINGLE("Line Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
380 	SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
381 	SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
382 	SOC_DAPM_SINGLE("HPCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
383 };
384 
385 /* Right Line2 Bypass Mixer */
386 static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
387 	SOC_DAPM_SINGLE("Line Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
388 	SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
389 	SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
390 	SOC_DAPM_SINGLE("HPCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
391 };
392 
393 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
394 	/* Left DAC to Left Outputs */
395 	SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
396 	SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
397 			 &aic3x_left_dac_mux_controls),
398 	SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
399 			   &aic3x_left_dac_mixer_controls[0],
400 			   ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
401 	SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
402 			 &aic3x_left_hpcom_mux_controls),
403 	SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
404 	SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
405 	SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
406 
407 	/* Right DAC to Right Outputs */
408 	SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
409 	SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
410 			 &aic3x_right_dac_mux_controls),
411 	SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
412 			   &aic3x_right_dac_mixer_controls[0],
413 			   ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
414 	SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
415 			 &aic3x_right_hpcom_mux_controls),
416 	SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
417 	SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
418 	SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
419 
420 	/* Mono Output */
421 	SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
422 
423 	/* Left Inputs to Left ADC */
424 	SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
425 	SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
426 			   &aic3x_left_pga_mixer_controls[0],
427 			   ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
428 	SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
429 			 &aic3x_left_line1_mux_controls),
430 	SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
431 			 &aic3x_left_line2_mux_controls),
432 
433 	/* Right Inputs to Right ADC */
434 	SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
435 			 LINE1R_2_RADC_CTRL, 2, 0),
436 	SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
437 			   &aic3x_right_pga_mixer_controls[0],
438 			   ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
439 	SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
440 			 &aic3x_right_line1_mux_controls),
441 	SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
442 			 &aic3x_right_line2_mux_controls),
443 
444 	/* Mic Bias */
445 	SND_SOC_DAPM_MICBIAS("Mic Bias 2V", MICBIAS_CTRL, 6, 0),
446 	SND_SOC_DAPM_MICBIAS("Mic Bias 2.5V", MICBIAS_CTRL, 7, 0),
447 	SND_SOC_DAPM_MICBIAS("Mic Bias AVDD", MICBIAS_CTRL, 6, 0),
448 	SND_SOC_DAPM_MICBIAS("Mic Bias AVDD", MICBIAS_CTRL, 7, 0),
449 
450 	/* Left PGA to Left Output bypass */
451 	SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
452 			   &aic3x_left_pga_bp_mixer_controls[0],
453 			   ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
454 
455 	/* Right PGA to Right Output bypass */
456 	SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
457 			   &aic3x_right_pga_bp_mixer_controls[0],
458 			   ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
459 
460 	/* Left Line2 to Left Output bypass */
461 	SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
462 			   &aic3x_left_line2_bp_mixer_controls[0],
463 			   ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
464 
465 	/* Right Line2 to Right Output bypass */
466 	SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
467 			   &aic3x_right_line2_bp_mixer_controls[0],
468 			   ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
469 
470 	SND_SOC_DAPM_OUTPUT("LLOUT"),
471 	SND_SOC_DAPM_OUTPUT("RLOUT"),
472 	SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
473 	SND_SOC_DAPM_OUTPUT("HPLOUT"),
474 	SND_SOC_DAPM_OUTPUT("HPROUT"),
475 	SND_SOC_DAPM_OUTPUT("HPLCOM"),
476 	SND_SOC_DAPM_OUTPUT("HPRCOM"),
477 
478 	SND_SOC_DAPM_INPUT("MIC3L"),
479 	SND_SOC_DAPM_INPUT("MIC3R"),
480 	SND_SOC_DAPM_INPUT("LINE1L"),
481 	SND_SOC_DAPM_INPUT("LINE1R"),
482 	SND_SOC_DAPM_INPUT("LINE2L"),
483 	SND_SOC_DAPM_INPUT("LINE2R"),
484 };
485 
486 static const char *intercon[][3] = {
487 	/* Left Output */
488 	{"Left DAC Mux", "DAC_L1", "Left DAC"},
489 	{"Left DAC Mux", "DAC_L2", "Left DAC"},
490 	{"Left DAC Mux", "DAC_L3", "Left DAC"},
491 
492 	{"Left DAC_L1 Mixer", "Line Switch", "Left DAC Mux"},
493 	{"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
494 	{"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
495 	{"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
496 	{"Left Line Out", NULL, "Left DAC Mux"},
497 	{"Left HP Out", NULL, "Left DAC Mux"},
498 
499 	{"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
500 	{"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
501 	{"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
502 
503 	{"Left Line Out", NULL, "Left DAC_L1 Mixer"},
504 	{"Mono Out", NULL, "Left DAC_L1 Mixer"},
505 	{"Left HP Out", NULL, "Left DAC_L1 Mixer"},
506 	{"Left HP Com", NULL, "Left HPCOM Mux"},
507 
508 	{"LLOUT", NULL, "Left Line Out"},
509 	{"LLOUT", NULL, "Left Line Out"},
510 	{"HPLOUT", NULL, "Left HP Out"},
511 	{"HPLCOM", NULL, "Left HP Com"},
512 
513 	/* Right Output */
514 	{"Right DAC Mux", "DAC_R1", "Right DAC"},
515 	{"Right DAC Mux", "DAC_R2", "Right DAC"},
516 	{"Right DAC Mux", "DAC_R3", "Right DAC"},
517 
518 	{"Right DAC_R1 Mixer", "Line Switch", "Right DAC Mux"},
519 	{"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
520 	{"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
521 	{"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
522 	{"Right Line Out", NULL, "Right DAC Mux"},
523 	{"Right HP Out", NULL, "Right DAC Mux"},
524 
525 	{"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
526 	{"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
527 	{"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
528 	{"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
529 	{"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
530 
531 	{"Right Line Out", NULL, "Right DAC_R1 Mixer"},
532 	{"Mono Out", NULL, "Right DAC_R1 Mixer"},
533 	{"Right HP Out", NULL, "Right DAC_R1 Mixer"},
534 	{"Right HP Com", NULL, "Right HPCOM Mux"},
535 
536 	{"RLOUT", NULL, "Right Line Out"},
537 	{"RLOUT", NULL, "Right Line Out"},
538 	{"HPROUT", NULL, "Right HP Out"},
539 	{"HPRCOM", NULL, "Right HP Com"},
540 
541 	/* Mono Output */
542 	{"MONO_LOUT", NULL, "Mono Out"},
543 	{"MONO_LOUT", NULL, "Mono Out"},
544 
545 	/* Left Input */
546 	{"Left Line1L Mux", "single-ended", "LINE1L"},
547 	{"Left Line1L Mux", "differential", "LINE1L"},
548 
549 	{"Left Line2L Mux", "single-ended", "LINE2L"},
550 	{"Left Line2L Mux", "differential", "LINE2L"},
551 
552 	{"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
553 	{"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
554 	{"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
555 
556 	{"Left ADC", NULL, "Left PGA Mixer"},
557 
558 	/* Right Input */
559 	{"Right Line1R Mux", "single-ended", "LINE1R"},
560 	{"Right Line1R Mux", "differential", "LINE1R"},
561 
562 	{"Right Line2R Mux", "single-ended", "LINE2R"},
563 	{"Right Line2R Mux", "differential", "LINE2R"},
564 
565 	{"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
566 	{"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
567 	{"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
568 
569 	{"Right ADC", NULL, "Right PGA Mixer"},
570 
571 	/* Left PGA Bypass */
572 	{"Left PGA Bypass Mixer", "Line Switch", "Left PGA Mixer"},
573 	{"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
574 	{"Left PGA Bypass Mixer", "HP Switch", "Left PGA Mixer"},
575 	{"Left PGA Bypass Mixer", "HPCOM Switch", "Left PGA Mixer"},
576 
577 	{"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
578 	{"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
579 	{"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
580 
581 	{"Left Line Out", NULL, "Left PGA Bypass Mixer"},
582 	{"Mono Out", NULL, "Left PGA Bypass Mixer"},
583 	{"Left HP Out", NULL, "Left PGA Bypass Mixer"},
584 
585 	/* Right PGA Bypass */
586 	{"Right PGA Bypass Mixer", "Line Switch", "Right PGA Mixer"},
587 	{"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
588 	{"Right PGA Bypass Mixer", "HP Switch", "Right PGA Mixer"},
589 	{"Right PGA Bypass Mixer", "HPCOM Switch", "Right PGA Mixer"},
590 
591 	{"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
592 	{"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
593 	{"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
594 	{"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
595 	{"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
596 
597 	{"Right Line Out", NULL, "Right PGA Bypass Mixer"},
598 	{"Mono Out", NULL, "Right PGA Bypass Mixer"},
599 	{"Right HP Out", NULL, "Right PGA Bypass Mixer"},
600 
601 	/* Left Line2 Bypass */
602 	{"Left Line2 Bypass Mixer", "Line Switch", "Left Line2L Mux"},
603 	{"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
604 	{"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
605 	{"Left Line2 Bypass Mixer", "HPCOM Switch", "Left Line2L Mux"},
606 
607 	{"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
608 	{"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
609 	{"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
610 
611 	{"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
612 	{"Mono Out", NULL, "Left Line2 Bypass Mixer"},
613 	{"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
614 
615 	/* Right Line2 Bypass */
616 	{"Right Line2 Bypass Mixer", "Line Switch", "Right Line2R Mux"},
617 	{"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
618 	{"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
619 	{"Right Line2 Bypass Mixer", "HPCOM Switch", "Right Line2R Mux"},
620 
621 	{"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
622 	{"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
623 	{"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
624 	{"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
625 	{"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
626 
627 	{"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
628 	{"Mono Out", NULL, "Right Line2 Bypass Mixer"},
629 	{"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
630 
631 	/* terminator */
632 	{NULL, NULL, NULL},
633 };
634 
635 static int aic3x_add_widgets(struct snd_soc_codec *codec)
636 {
637 	int i;
638 
639 	for (i = 0; i < ARRAY_SIZE(aic3x_dapm_widgets); i++)
640 		snd_soc_dapm_new_control(codec, &aic3x_dapm_widgets[i]);
641 
642 	/* set up audio path interconnects */
643 	for (i = 0; intercon[i][0] != NULL; i++)
644 		snd_soc_dapm_connect_input(codec, intercon[i][0],
645 					   intercon[i][1], intercon[i][2]);
646 
647 	snd_soc_dapm_new_widgets(codec);
648 	return 0;
649 }
650 
651 struct aic3x_rate_divs {
652 	u32 mclk;
653 	u32 rate;
654 	u32 fsref_reg;
655 	u8 sr_reg:4;
656 	u8 pllj_reg;
657 	u16 plld_reg;
658 };
659 
660 /* AIC3X codec mclk clock divider coefficients */
661 static const struct aic3x_rate_divs aic3x_divs[] = {
662 	/* 8k */
663 	{12000000, 8000, 48000, 0xa, 16, 3840},
664 	{19200000, 8000, 48000, 0xa, 10, 2400},
665 	{22579200, 8000, 48000, 0xa, 8, 7075},
666 	{33868800, 8000, 48000, 0xa, 5, 8049},
667 	/* 11.025k */
668 	{12000000, 11025, 44100, 0x6, 15, 528},
669 	{19200000, 11025, 44100, 0x6, 9, 4080},
670 	{22579200, 11025, 44100, 0x6, 8, 0},
671 	{33868800, 11025, 44100, 0x6, 5, 3333},
672 	/* 16k */
673 	{12000000, 16000, 48000, 0x4, 16, 3840},
674 	{19200000, 16000, 48000, 0x4, 10, 2400},
675 	{22579200, 16000, 48000, 0x4, 8, 7075},
676 	{33868800, 16000, 48000, 0x4, 5, 8049},
677 	/* 22.05k */
678 	{12000000, 22050, 44100, 0x2, 15, 528},
679 	{19200000, 22050, 44100, 0x2, 9, 4080},
680 	{22579200, 22050, 44100, 0x2, 8, 0},
681 	{33868800, 22050, 44100, 0x2, 5, 3333},
682 	/* 32k */
683 	{12000000, 32000, 48000, 0x1, 16, 3840},
684 	{19200000, 32000, 48000, 0x1, 10, 2400},
685 	{22579200, 32000, 48000, 0x1, 8, 7075},
686 	{33868800, 32000, 48000, 0x1, 5, 8049},
687 	/* 44.1k */
688 	{12000000, 44100, 44100, 0x0, 15, 528},
689 	{19200000, 44100, 44100, 0x0, 9, 4080},
690 	{22579200, 44100, 44100, 0x0, 8, 0},
691 	{33868800, 44100, 44100, 0x0, 5, 3333},
692 	/* 48k */
693 	{12000000, 48000, 48000, 0x0, 16, 3840},
694 	{19200000, 48000, 48000, 0x0, 10, 2400},
695 	{22579200, 48000, 48000, 0x0, 8, 7075},
696 	{33868800, 48000, 48000, 0x0, 5, 8049},
697 	/* 64k */
698 	{12000000, 64000, 96000, 0x1, 16, 3840},
699 	{19200000, 64000, 96000, 0x1, 10, 2400},
700 	{22579200, 64000, 96000, 0x1, 8, 7075},
701 	{33868800, 64000, 96000, 0x1, 5, 8049},
702 	/* 88.2k */
703 	{12000000, 88200, 88200, 0x0, 15, 528},
704 	{19200000, 88200, 88200, 0x0, 9, 4080},
705 	{22579200, 88200, 88200, 0x0, 8, 0},
706 	{33868800, 88200, 88200, 0x0, 5, 3333},
707 	/* 96k */
708 	{12000000, 96000, 96000, 0x0, 16, 3840},
709 	{19200000, 96000, 96000, 0x0, 10, 2400},
710 	{22579200, 96000, 96000, 0x0, 8, 7075},
711 	{33868800, 96000, 96000, 0x0, 5, 8049},
712 };
713 
714 static inline int aic3x_get_divs(int mclk, int rate)
715 {
716 	int i;
717 
718 	for (i = 0; i < ARRAY_SIZE(aic3x_divs); i++) {
719 		if (aic3x_divs[i].rate == rate && aic3x_divs[i].mclk == mclk)
720 			return i;
721 	}
722 
723 	return 0;
724 }
725 
726 static int aic3x_hw_params(struct snd_pcm_substream *substream,
727 			   struct snd_pcm_hw_params *params)
728 {
729 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
730 	struct snd_soc_device *socdev = rtd->socdev;
731 	struct snd_soc_codec *codec = socdev->codec;
732 	struct aic3x_priv *aic3x = codec->private_data;
733 	int i;
734 	u8 data, pll_p, pll_r, pll_j;
735 	u16 pll_d;
736 
737 	i = aic3x_get_divs(aic3x->sysclk, params_rate(params));
738 
739 	/* Route Left DAC to left channel input and
740 	 * right DAC to right channel input */
741 	data = (LDAC2LCH | RDAC2RCH);
742 	switch (aic3x_divs[i].fsref_reg) {
743 	case 44100:
744 		data |= FSREF_44100;
745 		break;
746 	case 48000:
747 		data |= FSREF_48000;
748 		break;
749 	case 88200:
750 		data |= FSREF_44100 | DUAL_RATE_MODE;
751 		break;
752 	case 96000:
753 		data |= FSREF_48000 | DUAL_RATE_MODE;
754 		break;
755 	}
756 	aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
757 
758 	/* codec sample rate select */
759 	data = aic3x_divs[i].sr_reg;
760 	data |= (data << 4);
761 	aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
762 
763 	/* Use PLL for generation Fsref by equation:
764 	 * Fsref = (MCLK * K * R)/(2048 * P);
765 	 * Fix P = 2 and R = 1 and calculate K, if
766 	 * K = J.D, i.e. J - an interger portion of K and D is the fractional
767 	 * one with 4 digits of precision;
768 	 * Example:
769 	 * For MCLK = 22.5792 MHz and Fsref = 48kHz:
770 	 * Select P = 2, R= 1, K = 8.7074, which results in J = 8, D = 7074
771 	 */
772 	pll_p = 2;
773 	pll_r = 1;
774 	pll_j = aic3x_divs[i].pllj_reg;
775 	pll_d = aic3x_divs[i].plld_reg;
776 
777 	data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
778 	aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
779 	aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
780 	aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
781 	aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
782 	aic3x_write(codec, AIC3X_PLL_PROGD_REG,
783 		    (pll_d & 0x3F) << PLLD_LSB_SHIFT);
784 
785 	/* select data word length */
786 	data =
787 	    aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
788 	switch (params_format(params)) {
789 	case SNDRV_PCM_FORMAT_S16_LE:
790 		break;
791 	case SNDRV_PCM_FORMAT_S20_3LE:
792 		data |= (0x01 << 4);
793 		break;
794 	case SNDRV_PCM_FORMAT_S24_LE:
795 		data |= (0x02 << 4);
796 		break;
797 	case SNDRV_PCM_FORMAT_S32_LE:
798 		data |= (0x03 << 4);
799 		break;
800 	}
801 	aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
802 
803 	return 0;
804 }
805 
806 static int aic3x_mute(struct snd_soc_codec_dai *dai, int mute)
807 {
808 	struct snd_soc_codec *codec = dai->codec;
809 	u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
810 	u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
811 
812 	if (mute) {
813 		aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
814 		aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
815 	} else {
816 		aic3x_write(codec, LDAC_VOL, ldac_reg);
817 		aic3x_write(codec, RDAC_VOL, rdac_reg);
818 	}
819 
820 	return 0;
821 }
822 
823 static int aic3x_set_dai_sysclk(struct snd_soc_codec_dai *codec_dai,
824 				int clk_id, unsigned int freq, int dir)
825 {
826 	struct snd_soc_codec *codec = codec_dai->codec;
827 	struct aic3x_priv *aic3x = codec->private_data;
828 
829 	switch (freq) {
830 	case 12000000:
831 	case 19200000:
832 	case 22579200:
833 	case 33868800:
834 		aic3x->sysclk = freq;
835 		return 0;
836 	}
837 
838 	return -EINVAL;
839 }
840 
841 static int aic3x_set_dai_fmt(struct snd_soc_codec_dai *codec_dai,
842 			     unsigned int fmt)
843 {
844 	struct snd_soc_codec *codec = codec_dai->codec;
845 	struct aic3x_priv *aic3x = codec->private_data;
846 	u8 iface_areg = 0;
847 	u8 iface_breg = 0;
848 
849 	/* set master/slave audio interface */
850 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
851 	case SND_SOC_DAIFMT_CBM_CFM:
852 		aic3x->master = 1;
853 		iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
854 		break;
855 	case SND_SOC_DAIFMT_CBS_CFS:
856 		aic3x->master = 0;
857 		break;
858 	default:
859 		return -EINVAL;
860 	}
861 
862 	/* interface format */
863 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
864 	case SND_SOC_DAIFMT_I2S:
865 		break;
866 	case SND_SOC_DAIFMT_DSP_A:
867 		iface_breg |= (0x01 << 6);
868 		break;
869 	case SND_SOC_DAIFMT_RIGHT_J:
870 		iface_breg |= (0x02 << 6);
871 		break;
872 	case SND_SOC_DAIFMT_LEFT_J:
873 		iface_breg |= (0x03 << 6);
874 		break;
875 	default:
876 		return -EINVAL;
877 	}
878 
879 	/* set iface */
880 	aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
881 	aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
882 
883 	return 0;
884 }
885 
886 static int aic3x_dapm_event(struct snd_soc_codec *codec, int event)
887 {
888 	struct aic3x_priv *aic3x = codec->private_data;
889 	u8 reg;
890 
891 	switch (event) {
892 	case SNDRV_CTL_POWER_D0:
893 		/* all power is driven by DAPM system */
894 		if (aic3x->master) {
895 			/* enable pll */
896 			reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
897 			aic3x_write(codec, AIC3X_PLL_PROGA_REG,
898 				    reg | PLL_ENABLE);
899 		}
900 		break;
901 	case SNDRV_CTL_POWER_D1:
902 	case SNDRV_CTL_POWER_D2:
903 		break;
904 	case SNDRV_CTL_POWER_D3hot:
905 		/*
906 		 * all power is driven by DAPM system,
907 		 * so output power is safe if bypass was set
908 		 */
909 		if (aic3x->master) {
910 			/* disable pll */
911 			reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
912 			aic3x_write(codec, AIC3X_PLL_PROGA_REG,
913 				    reg & ~PLL_ENABLE);
914 		}
915 		break;
916 	case SNDRV_CTL_POWER_D3cold:
917 		/* force all power off */
918 		reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
919 		aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
920 		reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
921 		aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
922 
923 		reg = aic3x_read_reg_cache(codec, DAC_PWR);
924 		aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
925 
926 		reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
927 		aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
928 		reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
929 		aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
930 
931 		reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
932 		aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
933 		reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
934 		aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
935 
936 		reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
937 		aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
938 
939 		reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
940 		aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
941 		reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
942 		aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
943 
944 		if (aic3x->master) {
945 			/* disable pll */
946 			reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
947 			aic3x_write(codec, AIC3X_PLL_PROGA_REG,
948 				    reg & ~PLL_ENABLE);
949 		}
950 		break;
951 	}
952 	codec->dapm_state = event;
953 
954 	return 0;
955 }
956 
957 #define AIC3X_RATES	SNDRV_PCM_RATE_8000_96000
958 #define AIC3X_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
959 			 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
960 
961 struct snd_soc_codec_dai aic3x_dai = {
962 	.name = "aic3x",
963 	.playback = {
964 		.stream_name = "Playback",
965 		.channels_min = 1,
966 		.channels_max = 2,
967 		.rates = AIC3X_RATES,
968 		.formats = AIC3X_FORMATS,},
969 	.capture = {
970 		.stream_name = "Capture",
971 		.channels_min = 1,
972 		.channels_max = 2,
973 		.rates = AIC3X_RATES,
974 		.formats = AIC3X_FORMATS,},
975 	.ops = {
976 		.hw_params = aic3x_hw_params,
977 	},
978 	.dai_ops = {
979 		.digital_mute = aic3x_mute,
980 		.set_sysclk = aic3x_set_dai_sysclk,
981 		.set_fmt = aic3x_set_dai_fmt,
982 	}
983 };
984 EXPORT_SYMBOL_GPL(aic3x_dai);
985 
986 static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
987 {
988 	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
989 	struct snd_soc_codec *codec = socdev->codec;
990 
991 	aic3x_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
992 
993 	return 0;
994 }
995 
996 static int aic3x_resume(struct platform_device *pdev)
997 {
998 	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
999 	struct snd_soc_codec *codec = socdev->codec;
1000 	int i;
1001 	u8 data[2];
1002 	u8 *cache = codec->reg_cache;
1003 
1004 	/* Sync reg_cache with the hardware */
1005 	for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1006 		data[0] = i;
1007 		data[1] = cache[i];
1008 		codec->hw_write(codec->control_data, data, 2);
1009 	}
1010 
1011 	aic3x_dapm_event(codec, codec->suspend_dapm_state);
1012 
1013 	return 0;
1014 }
1015 
1016 /*
1017  * initialise the AIC3X driver
1018  * register the mixer and dsp interfaces with the kernel
1019  */
1020 static int aic3x_init(struct snd_soc_device *socdev)
1021 {
1022 	struct snd_soc_codec *codec = socdev->codec;
1023 	int reg, ret = 0;
1024 
1025 	codec->name = "aic3x";
1026 	codec->owner = THIS_MODULE;
1027 	codec->read = aic3x_read_reg_cache;
1028 	codec->write = aic3x_write;
1029 	codec->dapm_event = aic3x_dapm_event;
1030 	codec->dai = &aic3x_dai;
1031 	codec->num_dai = 1;
1032 	codec->reg_cache_size = sizeof(aic3x_reg);
1033 	codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1034 	if (codec->reg_cache == NULL)
1035 		return -ENOMEM;
1036 
1037 	aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1038 	aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1039 
1040 	/* register pcms */
1041 	ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1042 	if (ret < 0) {
1043 		printk(KERN_ERR "aic3x: failed to create pcms\n");
1044 		goto pcm_err;
1045 	}
1046 
1047 	/* DAC default volume and mute */
1048 	aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1049 	aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1050 
1051 	/* DAC to HP default volume and route to Output mixer */
1052 	aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1053 	aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1054 	aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1055 	aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1056 	/* DAC to Line Out default volume and route to Output mixer */
1057 	aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1058 	aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1059 	/* DAC to Mono Line Out default volume and route to Output mixer */
1060 	aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1061 	aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1062 
1063 	/* unmute all outputs */
1064 	reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1065 	aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1066 	reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1067 	aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1068 	reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1069 	aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1070 	reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1071 	aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1072 	reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1073 	aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1074 	reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1075 	aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1076 	reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1077 	aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1078 
1079 	/* ADC default volume and unmute */
1080 	aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1081 	aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1082 	/* By default route Line1 to ADC PGA mixer */
1083 	aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1084 	aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1085 
1086 	/* PGA to HP Bypass default volume, disconnect from Output Mixer */
1087 	aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1088 	aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1089 	aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1090 	aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1091 	/* PGA to Line Out default volume, disconnect from Output Mixer */
1092 	aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1093 	aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1094 	/* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1095 	aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1096 	aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1097 
1098 	/* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1099 	aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1100 	aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1101 	aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1102 	aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1103 	/* Line2 Line Out default volume, disconnect from Output Mixer */
1104 	aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1105 	aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1106 	/* Line2 to Mono Out default volume, disconnect from Output Mixer */
1107 	aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1108 	aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1109 
1110 	/* off, with power on */
1111 	aic3x_dapm_event(codec, SNDRV_CTL_POWER_D3hot);
1112 
1113 	aic3x_add_controls(codec);
1114 	aic3x_add_widgets(codec);
1115 	ret = snd_soc_register_card(socdev);
1116 	if (ret < 0) {
1117 		printk(KERN_ERR "aic3x: failed to register card\n");
1118 		goto card_err;
1119 	}
1120 
1121 	return ret;
1122 
1123 card_err:
1124 	snd_soc_free_pcms(socdev);
1125 	snd_soc_dapm_free(socdev);
1126 pcm_err:
1127 	kfree(codec->reg_cache);
1128 	return ret;
1129 }
1130 
1131 static struct snd_soc_device *aic3x_socdev;
1132 
1133 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1134 /*
1135  * AIC3X 2 wire address can be up to 4 devices with device addresses
1136  * 0x18, 0x19, 0x1A, 0x1B
1137  */
1138 static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
1139 
1140 /* Magic definition of all other variables and things */
1141 I2C_CLIENT_INSMOD;
1142 
1143 static struct i2c_driver aic3x_i2c_driver;
1144 static struct i2c_client client_template;
1145 
1146 /*
1147  * If the i2c layer weren't so broken, we could pass this kind of data
1148  * around
1149  */
1150 static int aic3x_codec_probe(struct i2c_adapter *adap, int addr, int kind)
1151 {
1152 	struct snd_soc_device *socdev = aic3x_socdev;
1153 	struct aic3x_setup_data *setup = socdev->codec_data;
1154 	struct snd_soc_codec *codec = socdev->codec;
1155 	struct i2c_client *i2c;
1156 	int ret;
1157 
1158 	if (addr != setup->i2c_address)
1159 		return -ENODEV;
1160 
1161 	client_template.adapter = adap;
1162 	client_template.addr = addr;
1163 
1164 	i2c = kmemdup(&client_template, sizeof(client_template), GFP_KERNEL);
1165 	if (i2c == NULL) {
1166 		kfree(codec);
1167 		return -ENOMEM;
1168 	}
1169 	i2c_set_clientdata(i2c, codec);
1170 	codec->control_data = i2c;
1171 
1172 	ret = i2c_attach_client(i2c);
1173 	if (ret < 0) {
1174 		printk(KERN_ERR "aic3x: failed to attach codec at addr %x\n",
1175 		       addr);
1176 		goto err;
1177 	}
1178 
1179 	ret = aic3x_init(socdev);
1180 	if (ret < 0) {
1181 		printk(KERN_ERR "aic3x: failed to initialise AIC3X\n");
1182 		goto err;
1183 	}
1184 	return ret;
1185 
1186 err:
1187 	kfree(codec);
1188 	kfree(i2c);
1189 	return ret;
1190 }
1191 
1192 static int aic3x_i2c_detach(struct i2c_client *client)
1193 {
1194 	struct snd_soc_codec *codec = i2c_get_clientdata(client);
1195 	i2c_detach_client(client);
1196 	kfree(codec->reg_cache);
1197 	kfree(client);
1198 	return 0;
1199 }
1200 
1201 static int aic3x_i2c_attach(struct i2c_adapter *adap)
1202 {
1203 	return i2c_probe(adap, &addr_data, aic3x_codec_probe);
1204 }
1205 
1206 /* machine i2c codec control layer */
1207 static struct i2c_driver aic3x_i2c_driver = {
1208 	.driver = {
1209 		.name = "aic3x I2C Codec",
1210 		.owner = THIS_MODULE,
1211 	},
1212 	.attach_adapter = aic3x_i2c_attach,
1213 	.detach_client = aic3x_i2c_detach,
1214 };
1215 
1216 static struct i2c_client client_template = {
1217 	.name = "AIC3X",
1218 	.driver = &aic3x_i2c_driver,
1219 };
1220 #endif
1221 
1222 static int aic3x_probe(struct platform_device *pdev)
1223 {
1224 	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1225 	struct aic3x_setup_data *setup;
1226 	struct snd_soc_codec *codec;
1227 	struct aic3x_priv *aic3x;
1228 	int ret = 0;
1229 
1230 	printk(KERN_INFO "AIC3X Audio Codec %s\n", AIC3X_VERSION);
1231 
1232 	setup = socdev->codec_data;
1233 	codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1234 	if (codec == NULL)
1235 		return -ENOMEM;
1236 
1237 	aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1238 	if (aic3x == NULL) {
1239 		kfree(codec);
1240 		return -ENOMEM;
1241 	}
1242 
1243 	codec->private_data = aic3x;
1244 	socdev->codec = codec;
1245 	mutex_init(&codec->mutex);
1246 	INIT_LIST_HEAD(&codec->dapm_widgets);
1247 	INIT_LIST_HEAD(&codec->dapm_paths);
1248 
1249 	aic3x_socdev = socdev;
1250 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1251 	if (setup->i2c_address) {
1252 		normal_i2c[0] = setup->i2c_address;
1253 		codec->hw_write = (hw_write_t) i2c_master_send;
1254 		ret = i2c_add_driver(&aic3x_i2c_driver);
1255 		if (ret != 0)
1256 			printk(KERN_ERR "can't add i2c driver");
1257 	}
1258 #else
1259 	/* Add other interfaces here */
1260 #endif
1261 	return ret;
1262 }
1263 
1264 static int aic3x_remove(struct platform_device *pdev)
1265 {
1266 	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1267 	struct snd_soc_codec *codec = socdev->codec;
1268 
1269 	/* power down chip */
1270 	if (codec->control_data)
1271 		aic3x_dapm_event(codec, SNDRV_CTL_POWER_D3);
1272 
1273 	snd_soc_free_pcms(socdev);
1274 	snd_soc_dapm_free(socdev);
1275 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1276 	i2c_del_driver(&aic3x_i2c_driver);
1277 #endif
1278 	kfree(codec->private_data);
1279 	kfree(codec);
1280 
1281 	return 0;
1282 }
1283 
1284 struct snd_soc_codec_device soc_codec_dev_aic3x = {
1285 	.probe = aic3x_probe,
1286 	.remove = aic3x_remove,
1287 	.suspend = aic3x_suspend,
1288 	.resume = aic3x_resume,
1289 };
1290 EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1291 
1292 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1293 MODULE_AUTHOR("Vladimir Barinov");
1294 MODULE_LICENSE("GPL");
1295