1 /* 2 * ALSA SoC TLV320AIC3X codec driver 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * Notes: 14 * The AIC3X is a driver for a low power stereo audio 15 * codecs aic31, aic32, aic33, aic3007. 16 * 17 * It supports full aic33 codec functionality. 18 * The compatibility with aic32, aic31 and aic3007 is as follows: 19 * aic32/aic3007 | aic31 20 * --------------------------------------- 21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A 22 * | IN1L -> LINE1L 23 * | IN1R -> LINE1R 24 * | IN2L -> LINE2L 25 * | IN2R -> LINE2R 26 * | MIC3L/R -> N/A 27 * truncated internal functionality in 28 * accordance with documentation 29 * --------------------------------------- 30 * 31 * Hence the machine layer should disable unsupported inputs/outputs by 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/moduleparam.h> 37 #include <linux/init.h> 38 #include <linux/delay.h> 39 #include <linux/pm.h> 40 #include <linux/i2c.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/of_gpio.h> 44 #include <linux/slab.h> 45 #include <sound/core.h> 46 #include <sound/pcm.h> 47 #include <sound/pcm_params.h> 48 #include <sound/soc.h> 49 #include <sound/initval.h> 50 #include <sound/tlv.h> 51 #include <sound/tlv320aic3x.h> 52 53 #include "tlv320aic3x.h" 54 55 #define AIC3X_NUM_SUPPLIES 4 56 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { 57 "IOVDD", /* I/O Voltage */ 58 "DVDD", /* Digital Core Voltage */ 59 "AVDD", /* Analog DAC Voltage */ 60 "DRVDD", /* ADC Analog and Output Driver Voltage */ 61 }; 62 63 static LIST_HEAD(reset_list); 64 65 struct aic3x_priv; 66 67 struct aic3x_disable_nb { 68 struct notifier_block nb; 69 struct aic3x_priv *aic3x; 70 }; 71 72 /* codec private data */ 73 struct aic3x_priv { 74 struct snd_soc_codec *codec; 75 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; 76 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES]; 77 enum snd_soc_control_type control_type; 78 struct aic3x_setup_data *setup; 79 unsigned int sysclk; 80 struct list_head list; 81 int master; 82 int gpio_reset; 83 int power; 84 #define AIC3X_MODEL_3X 0 85 #define AIC3X_MODEL_33 1 86 #define AIC3X_MODEL_3007 2 87 u16 model; 88 89 /* Selects the micbias voltage */ 90 enum aic3x_micbias_voltage micbias_vg; 91 }; 92 93 /* 94 * AIC3X register cache 95 * We can't read the AIC3X register space when we are 96 * using 2 wire for device control, so we cache them instead. 97 * There is no point in caching the reset register 98 */ 99 static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { 100 0x00, 0x00, 0x00, 0x10, /* 0 */ 101 0x04, 0x00, 0x00, 0x00, /* 4 */ 102 0x00, 0x00, 0x00, 0x01, /* 8 */ 103 0x00, 0x00, 0x00, 0x80, /* 12 */ 104 0x80, 0xff, 0xff, 0x78, /* 16 */ 105 0x78, 0x78, 0x78, 0x78, /* 20 */ 106 0x78, 0x00, 0x00, 0xfe, /* 24 */ 107 0x00, 0x00, 0xfe, 0x00, /* 28 */ 108 0x18, 0x18, 0x00, 0x00, /* 32 */ 109 0x00, 0x00, 0x00, 0x00, /* 36 */ 110 0x00, 0x00, 0x00, 0x80, /* 40 */ 111 0x80, 0x00, 0x00, 0x00, /* 44 */ 112 0x00, 0x00, 0x00, 0x04, /* 48 */ 113 0x00, 0x00, 0x00, 0x00, /* 52 */ 114 0x00, 0x00, 0x04, 0x00, /* 56 */ 115 0x00, 0x00, 0x00, 0x00, /* 60 */ 116 0x00, 0x04, 0x00, 0x00, /* 64 */ 117 0x00, 0x00, 0x00, 0x00, /* 68 */ 118 0x04, 0x00, 0x00, 0x00, /* 72 */ 119 0x00, 0x00, 0x00, 0x00, /* 76 */ 120 0x00, 0x00, 0x00, 0x00, /* 80 */ 121 0x00, 0x00, 0x00, 0x00, /* 84 */ 122 0x00, 0x00, 0x00, 0x00, /* 88 */ 123 0x00, 0x00, 0x00, 0x00, /* 92 */ 124 0x00, 0x00, 0x00, 0x00, /* 96 */ 125 0x00, 0x00, 0x02, 0x00, /* 100 */ 126 0x00, 0x00, 0x00, 0x00, /* 104 */ 127 0x00, 0x00, /* 108 */ 128 }; 129 130 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ 131 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \ 132 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x) 133 134 /* 135 * All input lines are connected when !0xf and disconnected with 0xf bit field, 136 * so we have to use specific dapm_put call for input mixer 137 */ 138 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, 139 struct snd_ctl_elem_value *ucontrol) 140 { 141 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); 142 struct soc_mixer_control *mc = 143 (struct soc_mixer_control *)kcontrol->private_value; 144 unsigned int reg = mc->reg; 145 unsigned int shift = mc->shift; 146 int max = mc->max; 147 unsigned int mask = (1 << fls(max)) - 1; 148 unsigned int invert = mc->invert; 149 unsigned short val; 150 struct snd_soc_dapm_update update; 151 int connect, change; 152 153 val = (ucontrol->value.integer.value[0] & mask); 154 155 mask = 0xf; 156 if (val) 157 val = mask; 158 159 connect = !!val; 160 161 if (invert) 162 val = mask - val; 163 164 mask <<= shift; 165 val <<= shift; 166 167 change = snd_soc_test_bits(codec, val, mask, reg); 168 if (change) { 169 update.kcontrol = kcontrol; 170 update.reg = reg; 171 update.mask = mask; 172 update.val = val; 173 174 snd_soc_dapm_mixer_update_power(&codec->dapm, kcontrol, connect, 175 &update); 176 } 177 178 return change; 179 } 180 181 /* 182 * mic bias power on/off share the same register bits with 183 * output voltage of mic bias. when power on mic bias, we 184 * need reclaim it to voltage value. 185 * 0x0 = Powered off 186 * 0x1 = MICBIAS output is powered to 2.0V, 187 * 0x2 = MICBIAS output is powered to 2.5V 188 * 0x3 = MICBIAS output is connected to AVDD 189 */ 190 static int mic_bias_event(struct snd_soc_dapm_widget *w, 191 struct snd_kcontrol *kcontrol, int event) 192 { 193 struct snd_soc_codec *codec = w->codec; 194 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 195 196 switch (event) { 197 case SND_SOC_DAPM_POST_PMU: 198 /* change mic bias voltage to user defined */ 199 snd_soc_update_bits(codec, MICBIAS_CTRL, 200 MICBIAS_LEVEL_MASK, 201 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT); 202 break; 203 204 case SND_SOC_DAPM_PRE_PMD: 205 snd_soc_update_bits(codec, MICBIAS_CTRL, 206 MICBIAS_LEVEL_MASK, 0); 207 break; 208 } 209 return 0; 210 } 211 212 static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; 213 static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; 214 static const char *aic3x_left_hpcom_mux[] = 215 { "differential of HPLOUT", "constant VCM", "single-ended" }; 216 static const char *aic3x_right_hpcom_mux[] = 217 { "differential of HPROUT", "constant VCM", "single-ended", 218 "differential of HPLCOM", "external feedback" }; 219 static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; 220 static const char *aic3x_adc_hpf[] = 221 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; 222 223 #define LDAC_ENUM 0 224 #define RDAC_ENUM 1 225 #define LHPCOM_ENUM 2 226 #define RHPCOM_ENUM 3 227 #define LINE1L_2_L_ENUM 4 228 #define LINE1L_2_R_ENUM 5 229 #define LINE1R_2_L_ENUM 6 230 #define LINE1R_2_R_ENUM 7 231 #define LINE2L_ENUM 8 232 #define LINE2R_ENUM 9 233 #define ADC_HPF_ENUM 10 234 235 static const struct soc_enum aic3x_enum[] = { 236 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), 237 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), 238 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), 239 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), 240 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 241 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 242 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 243 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 244 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), 245 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), 246 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf), 247 }; 248 249 static const char *aic3x_agc_level[] = 250 { "-5.5dB", "-8dB", "-10dB", "-12dB", "-14dB", "-17dB", "-20dB", "-24dB" }; 251 static const struct soc_enum aic3x_agc_level_enum[] = { 252 SOC_ENUM_SINGLE(LAGC_CTRL_A, 4, 8, aic3x_agc_level), 253 SOC_ENUM_SINGLE(RAGC_CTRL_A, 4, 8, aic3x_agc_level), 254 }; 255 256 static const char *aic3x_agc_attack[] = { "8ms", "11ms", "16ms", "20ms" }; 257 static const struct soc_enum aic3x_agc_attack_enum[] = { 258 SOC_ENUM_SINGLE(LAGC_CTRL_A, 2, 4, aic3x_agc_attack), 259 SOC_ENUM_SINGLE(RAGC_CTRL_A, 2, 4, aic3x_agc_attack), 260 }; 261 262 static const char *aic3x_agc_decay[] = { "100ms", "200ms", "400ms", "500ms" }; 263 static const struct soc_enum aic3x_agc_decay_enum[] = { 264 SOC_ENUM_SINGLE(LAGC_CTRL_A, 0, 4, aic3x_agc_decay), 265 SOC_ENUM_SINGLE(RAGC_CTRL_A, 0, 4, aic3x_agc_decay), 266 }; 267 268 /* 269 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps 270 */ 271 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); 272 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ 273 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); 274 /* 275 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. 276 * Step size is approximately 0.5 dB over most of the scale but increasing 277 * near the very low levels. 278 * Define dB scale so that it is mostly correct for range about -55 to 0 dB 279 * but having increasing dB difference below that (and where it doesn't count 280 * so much). This setting shows -50 dB (actual is -50.3 dB) for register 281 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. 282 */ 283 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); 284 285 static const struct snd_kcontrol_new aic3x_snd_controls[] = { 286 /* Output */ 287 SOC_DOUBLE_R_TLV("PCM Playback Volume", 288 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), 289 290 /* 291 * Output controls that map to output mixer switches. Note these are 292 * only for swapped L-to-R and R-to-L routes. See below stereo controls 293 * for direct L-to-L and R-to-R routes. 294 */ 295 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", 296 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 297 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", 298 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 299 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", 300 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), 301 302 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", 303 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 304 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", 305 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 306 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", 307 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), 308 309 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", 310 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 311 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", 312 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 313 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", 314 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), 315 316 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", 317 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 318 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", 319 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 320 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", 321 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), 322 323 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", 324 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 325 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", 326 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 327 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", 328 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), 329 330 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", 331 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 332 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", 333 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 334 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", 335 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), 336 337 /* Stereo output controls for direct L-to-L and R-to-R routes */ 338 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", 339 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, 340 0, 118, 1, output_stage_tlv), 341 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", 342 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, 343 0, 118, 1, output_stage_tlv), 344 SOC_DOUBLE_R_TLV("Line DAC Playback Volume", 345 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 346 0, 118, 1, output_stage_tlv), 347 348 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", 349 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 350 0, 118, 1, output_stage_tlv), 351 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", 352 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 353 0, 118, 1, output_stage_tlv), 354 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", 355 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 356 0, 118, 1, output_stage_tlv), 357 358 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", 359 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 360 0, 118, 1, output_stage_tlv), 361 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", 362 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 363 0, 118, 1, output_stage_tlv), 364 SOC_DOUBLE_R_TLV("HP DAC Playback Volume", 365 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 366 0, 118, 1, output_stage_tlv), 367 368 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", 369 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 370 0, 118, 1, output_stage_tlv), 371 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", 372 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, 373 0, 118, 1, output_stage_tlv), 374 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", 375 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 376 0, 118, 1, output_stage_tlv), 377 378 /* Output pin mute controls */ 379 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, 380 0x01, 0), 381 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), 382 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 383 0x01, 0), 384 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 385 0x01, 0), 386 387 /* 388 * Note: enable Automatic input Gain Controller with care. It can 389 * adjust PGA to max value when ADC is on and will never go back. 390 */ 391 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), 392 SOC_ENUM("Left AGC Target level", aic3x_agc_level_enum[0]), 393 SOC_ENUM("Right AGC Target level", aic3x_agc_level_enum[1]), 394 SOC_ENUM("Left AGC Attack time", aic3x_agc_attack_enum[0]), 395 SOC_ENUM("Right AGC Attack time", aic3x_agc_attack_enum[1]), 396 SOC_ENUM("Left AGC Decay time", aic3x_agc_decay_enum[0]), 397 SOC_ENUM("Right AGC Decay time", aic3x_agc_decay_enum[1]), 398 399 /* De-emphasis */ 400 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0), 401 402 /* Input */ 403 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 404 0, 119, 0, adc_tlv), 405 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), 406 407 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]), 408 }; 409 410 /* 411 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps 412 */ 413 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0); 414 415 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl = 416 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv); 417 418 /* Left DAC Mux */ 419 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = 420 SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); 421 422 /* Right DAC Mux */ 423 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = 424 SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); 425 426 /* Left HPCOM Mux */ 427 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = 428 SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); 429 430 /* Right HPCOM Mux */ 431 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = 432 SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); 433 434 /* Left Line Mixer */ 435 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { 436 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), 437 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), 438 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), 439 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), 440 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), 441 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), 442 }; 443 444 /* Right Line Mixer */ 445 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { 446 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), 447 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), 448 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), 449 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), 450 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), 451 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), 452 }; 453 454 /* Mono Mixer */ 455 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { 456 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), 457 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), 458 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), 459 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), 460 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), 461 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), 462 }; 463 464 /* Left HP Mixer */ 465 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { 466 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), 467 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), 468 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), 469 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), 470 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), 471 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), 472 }; 473 474 /* Right HP Mixer */ 475 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { 476 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), 477 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), 478 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), 479 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), 480 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), 481 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), 482 }; 483 484 /* Left HPCOM Mixer */ 485 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { 486 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), 487 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), 488 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), 489 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), 490 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), 491 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), 492 }; 493 494 /* Right HPCOM Mixer */ 495 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { 496 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), 497 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), 498 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), 499 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), 500 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), 501 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), 502 }; 503 504 /* Left PGA Mixer */ 505 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { 506 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), 507 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), 508 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), 509 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), 510 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), 511 }; 512 513 /* Right PGA Mixer */ 514 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { 515 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), 516 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), 517 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), 518 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), 519 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), 520 }; 521 522 /* Left Line1 Mux */ 523 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls = 524 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]); 525 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls = 526 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]); 527 528 /* Right Line1 Mux */ 529 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls = 530 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]); 531 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls = 532 SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]); 533 534 /* Left Line2 Mux */ 535 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = 536 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); 537 538 /* Right Line2 Mux */ 539 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = 540 SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); 541 542 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { 543 /* Left DAC to Left Outputs */ 544 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), 545 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, 546 &aic3x_left_dac_mux_controls), 547 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, 548 &aic3x_left_hpcom_mux_controls), 549 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), 550 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), 551 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), 552 553 /* Right DAC to Right Outputs */ 554 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), 555 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, 556 &aic3x_right_dac_mux_controls), 557 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, 558 &aic3x_right_hpcom_mux_controls), 559 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), 560 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), 561 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), 562 563 /* Mono Output */ 564 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), 565 566 /* Inputs to Left ADC */ 567 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), 568 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, 569 &aic3x_left_pga_mixer_controls[0], 570 ARRAY_SIZE(aic3x_left_pga_mixer_controls)), 571 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, 572 &aic3x_left_line1l_mux_controls), 573 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, 574 &aic3x_left_line1r_mux_controls), 575 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, 576 &aic3x_left_line2_mux_controls), 577 578 /* Inputs to Right ADC */ 579 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", 580 LINE1R_2_RADC_CTRL, 2, 0), 581 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, 582 &aic3x_right_pga_mixer_controls[0], 583 ARRAY_SIZE(aic3x_right_pga_mixer_controls)), 584 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, 585 &aic3x_right_line1l_mux_controls), 586 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, 587 &aic3x_right_line1r_mux_controls), 588 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, 589 &aic3x_right_line2_mux_controls), 590 591 /* 592 * Not a real mic bias widget but similar function. This is for dynamic 593 * control of GPIO1 digital mic modulator clock output function when 594 * using digital mic. 595 */ 596 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", 597 AIC3X_GPIO1_REG, 4, 0xf, 598 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, 599 AIC3X_GPIO1_FUNC_DISABLED), 600 601 /* 602 * Also similar function like mic bias. Selects digital mic with 603 * configurable oversampling rate instead of ADC converter. 604 */ 605 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", 606 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), 607 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", 608 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), 609 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", 610 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), 611 612 /* Mic Bias */ 613 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0, 614 mic_bias_event, 615 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 616 617 /* Output mixers */ 618 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, 619 &aic3x_left_line_mixer_controls[0], 620 ARRAY_SIZE(aic3x_left_line_mixer_controls)), 621 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, 622 &aic3x_right_line_mixer_controls[0], 623 ARRAY_SIZE(aic3x_right_line_mixer_controls)), 624 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, 625 &aic3x_mono_mixer_controls[0], 626 ARRAY_SIZE(aic3x_mono_mixer_controls)), 627 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 628 &aic3x_left_hp_mixer_controls[0], 629 ARRAY_SIZE(aic3x_left_hp_mixer_controls)), 630 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 631 &aic3x_right_hp_mixer_controls[0], 632 ARRAY_SIZE(aic3x_right_hp_mixer_controls)), 633 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, 634 &aic3x_left_hpcom_mixer_controls[0], 635 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), 636 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, 637 &aic3x_right_hpcom_mixer_controls[0], 638 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), 639 640 SND_SOC_DAPM_OUTPUT("LLOUT"), 641 SND_SOC_DAPM_OUTPUT("RLOUT"), 642 SND_SOC_DAPM_OUTPUT("MONO_LOUT"), 643 SND_SOC_DAPM_OUTPUT("HPLOUT"), 644 SND_SOC_DAPM_OUTPUT("HPROUT"), 645 SND_SOC_DAPM_OUTPUT("HPLCOM"), 646 SND_SOC_DAPM_OUTPUT("HPRCOM"), 647 648 SND_SOC_DAPM_INPUT("MIC3L"), 649 SND_SOC_DAPM_INPUT("MIC3R"), 650 SND_SOC_DAPM_INPUT("LINE1L"), 651 SND_SOC_DAPM_INPUT("LINE1R"), 652 SND_SOC_DAPM_INPUT("LINE2L"), 653 SND_SOC_DAPM_INPUT("LINE2R"), 654 655 /* 656 * Virtual output pin to detection block inside codec. This can be 657 * used to keep codec bias on if gpio or detection features are needed. 658 * Force pin on or construct a path with an input jack and mic bias 659 * widgets. 660 */ 661 SND_SOC_DAPM_OUTPUT("Detection"), 662 }; 663 664 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { 665 /* Class-D outputs */ 666 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0), 667 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0), 668 669 SND_SOC_DAPM_OUTPUT("SPOP"), 670 SND_SOC_DAPM_OUTPUT("SPOM"), 671 }; 672 673 static const struct snd_soc_dapm_route intercon[] = { 674 /* Left Input */ 675 {"Left Line1L Mux", "single-ended", "LINE1L"}, 676 {"Left Line1L Mux", "differential", "LINE1L"}, 677 678 {"Left Line2L Mux", "single-ended", "LINE2L"}, 679 {"Left Line2L Mux", "differential", "LINE2L"}, 680 681 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, 682 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, 683 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, 684 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, 685 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, 686 687 {"Left ADC", NULL, "Left PGA Mixer"}, 688 {"Left ADC", NULL, "GPIO1 dmic modclk"}, 689 690 /* Right Input */ 691 {"Right Line1R Mux", "single-ended", "LINE1R"}, 692 {"Right Line1R Mux", "differential", "LINE1R"}, 693 694 {"Right Line2R Mux", "single-ended", "LINE2R"}, 695 {"Right Line2R Mux", "differential", "LINE2R"}, 696 697 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, 698 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, 699 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, 700 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, 701 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, 702 703 {"Right ADC", NULL, "Right PGA Mixer"}, 704 {"Right ADC", NULL, "GPIO1 dmic modclk"}, 705 706 /* 707 * Logical path between digital mic enable and GPIO1 modulator clock 708 * output function 709 */ 710 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, 711 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, 712 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, 713 714 /* Left DAC Output */ 715 {"Left DAC Mux", "DAC_L1", "Left DAC"}, 716 {"Left DAC Mux", "DAC_L2", "Left DAC"}, 717 {"Left DAC Mux", "DAC_L3", "Left DAC"}, 718 719 /* Right DAC Output */ 720 {"Right DAC Mux", "DAC_R1", "Right DAC"}, 721 {"Right DAC Mux", "DAC_R2", "Right DAC"}, 722 {"Right DAC Mux", "DAC_R3", "Right DAC"}, 723 724 /* Left Line Output */ 725 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 726 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 727 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 728 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 729 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 730 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 731 732 {"Left Line Out", NULL, "Left Line Mixer"}, 733 {"Left Line Out", NULL, "Left DAC Mux"}, 734 {"LLOUT", NULL, "Left Line Out"}, 735 736 /* Right Line Output */ 737 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 738 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 739 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, 740 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 741 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 742 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, 743 744 {"Right Line Out", NULL, "Right Line Mixer"}, 745 {"Right Line Out", NULL, "Right DAC Mux"}, 746 {"RLOUT", NULL, "Right Line Out"}, 747 748 /* Mono Output */ 749 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 750 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 751 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, 752 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 753 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 754 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, 755 756 {"Mono Out", NULL, "Mono Mixer"}, 757 {"MONO_LOUT", NULL, "Mono Out"}, 758 759 /* Left HP Output */ 760 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 761 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 762 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 763 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 764 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 765 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 766 767 {"Left HP Out", NULL, "Left HP Mixer"}, 768 {"Left HP Out", NULL, "Left DAC Mux"}, 769 {"HPLOUT", NULL, "Left HP Out"}, 770 771 /* Right HP Output */ 772 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 773 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 774 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, 775 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 776 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 777 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, 778 779 {"Right HP Out", NULL, "Right HP Mixer"}, 780 {"Right HP Out", NULL, "Right DAC Mux"}, 781 {"HPROUT", NULL, "Right HP Out"}, 782 783 /* Left HPCOM Output */ 784 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 785 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 786 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 787 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 788 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 789 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 790 791 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, 792 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, 793 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, 794 {"Left HP Com", NULL, "Left HPCOM Mux"}, 795 {"HPLCOM", NULL, "Left HP Com"}, 796 797 /* Right HPCOM Output */ 798 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, 799 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, 800 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, 801 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, 802 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, 803 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, 804 805 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, 806 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, 807 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, 808 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, 809 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, 810 {"Right HP Com", NULL, "Right HPCOM Mux"}, 811 {"HPRCOM", NULL, "Right HP Com"}, 812 }; 813 814 static const struct snd_soc_dapm_route intercon_3007[] = { 815 /* Class-D outputs */ 816 {"Left Class-D Out", NULL, "Left Line Out"}, 817 {"Right Class-D Out", NULL, "Left Line Out"}, 818 {"SPOP", NULL, "Left Class-D Out"}, 819 {"SPOM", NULL, "Right Class-D Out"}, 820 }; 821 822 static int aic3x_add_widgets(struct snd_soc_codec *codec) 823 { 824 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 825 struct snd_soc_dapm_context *dapm = &codec->dapm; 826 827 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets, 828 ARRAY_SIZE(aic3x_dapm_widgets)); 829 830 /* set up audio path interconnects */ 831 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); 832 833 if (aic3x->model == AIC3X_MODEL_3007) { 834 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, 835 ARRAY_SIZE(aic3007_dapm_widgets)); 836 snd_soc_dapm_add_routes(dapm, intercon_3007, 837 ARRAY_SIZE(intercon_3007)); 838 } 839 840 return 0; 841 } 842 843 static int aic3x_hw_params(struct snd_pcm_substream *substream, 844 struct snd_pcm_hw_params *params, 845 struct snd_soc_dai *dai) 846 { 847 struct snd_soc_codec *codec = dai->codec; 848 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 849 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 850 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 851 u16 d, pll_d = 1; 852 int clk; 853 854 /* select data word length */ 855 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); 856 switch (params_format(params)) { 857 case SNDRV_PCM_FORMAT_S16_LE: 858 break; 859 case SNDRV_PCM_FORMAT_S20_3LE: 860 data |= (0x01 << 4); 861 break; 862 case SNDRV_PCM_FORMAT_S24_LE: 863 data |= (0x02 << 4); 864 break; 865 case SNDRV_PCM_FORMAT_S32_LE: 866 data |= (0x03 << 4); 867 break; 868 } 869 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data); 870 871 /* Fsref can be 44100 or 48000 */ 872 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; 873 874 /* Try to find a value for Q which allows us to bypass the PLL and 875 * generate CODEC_CLK directly. */ 876 for (pll_q = 2; pll_q < 18; pll_q++) 877 if (aic3x->sysclk / (128 * pll_q) == fsref) { 878 bypass_pll = 1; 879 break; 880 } 881 882 if (bypass_pll) { 883 pll_q &= 0xf; 884 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 885 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 886 /* disable PLL if it is bypassed */ 887 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); 888 889 } else { 890 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 891 /* enable PLL when it is used */ 892 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 893 PLL_ENABLE, PLL_ENABLE); 894 } 895 896 /* Route Left DAC to left channel input and 897 * right DAC to right channel input */ 898 data = (LDAC2LCH | RDAC2RCH); 899 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; 900 if (params_rate(params) >= 64000) 901 data |= DUAL_RATE_MODE; 902 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data); 903 904 /* codec sample rate select */ 905 data = (fsref * 20) / params_rate(params); 906 if (params_rate(params) < 64000) 907 data /= 2; 908 data /= 5; 909 data -= 2; 910 data |= (data << 4); 911 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); 912 913 if (bypass_pll) 914 return 0; 915 916 /* Use PLL, compute appropriate setup for j, d, r and p, the closest 917 * one wins the game. Try with d==0 first, next with d!=0. 918 * Constraints for j are according to the datasheet. 919 * The sysclk is divided by 1000 to prevent integer overflows. 920 */ 921 922 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); 923 924 for (r = 1; r <= 16; r++) 925 for (p = 1; p <= 8; p++) { 926 for (j = 4; j <= 55; j++) { 927 /* This is actually 1000*((j+(d/10000))*r)/p 928 * The term had to be converted to get 929 * rid of the division by 10000; d = 0 here 930 */ 931 int tmp_clk = (1000 * j * r) / p; 932 933 /* Check whether this values get closer than 934 * the best ones we had before 935 */ 936 if (abs(codec_clk - tmp_clk) < 937 abs(codec_clk - last_clk)) { 938 pll_j = j; pll_d = 0; 939 pll_r = r; pll_p = p; 940 last_clk = tmp_clk; 941 } 942 943 /* Early exit for exact matches */ 944 if (tmp_clk == codec_clk) 945 goto found; 946 } 947 } 948 949 /* try with d != 0 */ 950 for (p = 1; p <= 8; p++) { 951 j = codec_clk * p / 1000; 952 953 if (j < 4 || j > 11) 954 continue; 955 956 /* do not use codec_clk here since we'd loose precision */ 957 d = ((2048 * p * fsref) - j * aic3x->sysclk) 958 * 100 / (aic3x->sysclk/100); 959 960 clk = (10000 * j + d) / (10 * p); 961 962 /* check whether this values get closer than the best 963 * ones we had before */ 964 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { 965 pll_j = j; pll_d = d; pll_r = 1; pll_p = p; 966 last_clk = clk; 967 } 968 969 /* Early exit for exact matches */ 970 if (clk == codec_clk) 971 goto found; 972 } 973 974 if (last_clk == 0) { 975 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); 976 return -EINVAL; 977 } 978 979 found: 980 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p); 981 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, 982 pll_r << PLLR_SHIFT); 983 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); 984 snd_soc_write(codec, AIC3X_PLL_PROGC_REG, 985 (pll_d >> 6) << PLLD_MSB_SHIFT); 986 snd_soc_write(codec, AIC3X_PLL_PROGD_REG, 987 (pll_d & 0x3F) << PLLD_LSB_SHIFT); 988 989 return 0; 990 } 991 992 static int aic3x_mute(struct snd_soc_dai *dai, int mute) 993 { 994 struct snd_soc_codec *codec = dai->codec; 995 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON; 996 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON; 997 998 if (mute) { 999 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); 1000 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); 1001 } else { 1002 snd_soc_write(codec, LDAC_VOL, ldac_reg); 1003 snd_soc_write(codec, RDAC_VOL, rdac_reg); 1004 } 1005 1006 return 0; 1007 } 1008 1009 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1010 int clk_id, unsigned int freq, int dir) 1011 { 1012 struct snd_soc_codec *codec = codec_dai->codec; 1013 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1014 1015 /* set clock on MCLK or GPIO2 or BCLK */ 1016 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, 1017 clk_id << PLLCLK_IN_SHIFT); 1018 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, 1019 clk_id << CLKDIV_IN_SHIFT); 1020 1021 aic3x->sysclk = freq; 1022 return 0; 1023 } 1024 1025 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, 1026 unsigned int fmt) 1027 { 1028 struct snd_soc_codec *codec = codec_dai->codec; 1029 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1030 u8 iface_areg, iface_breg; 1031 int delay = 0; 1032 1033 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; 1034 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; 1035 1036 /* set master/slave audio interface */ 1037 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1038 case SND_SOC_DAIFMT_CBM_CFM: 1039 aic3x->master = 1; 1040 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; 1041 break; 1042 case SND_SOC_DAIFMT_CBS_CFS: 1043 aic3x->master = 0; 1044 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER); 1045 break; 1046 default: 1047 return -EINVAL; 1048 } 1049 1050 /* 1051 * match both interface format and signal polarities since they 1052 * are fixed 1053 */ 1054 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | 1055 SND_SOC_DAIFMT_INV_MASK)) { 1056 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): 1057 break; 1058 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): 1059 delay = 1; 1060 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): 1061 iface_breg |= (0x01 << 6); 1062 break; 1063 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): 1064 iface_breg |= (0x02 << 6); 1065 break; 1066 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): 1067 iface_breg |= (0x03 << 6); 1068 break; 1069 default: 1070 return -EINVAL; 1071 } 1072 1073 /* set iface */ 1074 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); 1075 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); 1076 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay); 1077 1078 return 0; 1079 } 1080 1081 static int aic3x_init_3007(struct snd_soc_codec *codec) 1082 { 1083 u8 tmp1, tmp2, *cache = codec->reg_cache; 1084 1085 /* 1086 * There is no need to cache writes to undocumented page 0xD but 1087 * respective page 0 register cache entries must be preserved 1088 */ 1089 tmp1 = cache[0xD]; 1090 tmp2 = cache[0x8]; 1091 /* Class-D speaker driver init; datasheet p. 46 */ 1092 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D); 1093 snd_soc_write(codec, 0xD, 0x0D); 1094 snd_soc_write(codec, 0x8, 0x5C); 1095 snd_soc_write(codec, 0x8, 0x5D); 1096 snd_soc_write(codec, 0x8, 0x5C); 1097 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00); 1098 cache[0xD] = tmp1; 1099 cache[0x8] = tmp2; 1100 1101 return 0; 1102 } 1103 1104 static int aic3x_regulator_event(struct notifier_block *nb, 1105 unsigned long event, void *data) 1106 { 1107 struct aic3x_disable_nb *disable_nb = 1108 container_of(nb, struct aic3x_disable_nb, nb); 1109 struct aic3x_priv *aic3x = disable_nb->aic3x; 1110 1111 if (event & REGULATOR_EVENT_DISABLE) { 1112 /* 1113 * Put codec to reset and require cache sync as at least one 1114 * of the supplies was disabled 1115 */ 1116 if (gpio_is_valid(aic3x->gpio_reset)) 1117 gpio_set_value(aic3x->gpio_reset, 0); 1118 aic3x->codec->cache_sync = 1; 1119 } 1120 1121 return 0; 1122 } 1123 1124 static int aic3x_set_power(struct snd_soc_codec *codec, int power) 1125 { 1126 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1127 int i, ret; 1128 u8 *cache = codec->reg_cache; 1129 1130 if (power) { 1131 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), 1132 aic3x->supplies); 1133 if (ret) 1134 goto out; 1135 aic3x->power = 1; 1136 /* 1137 * Reset release and cache sync is necessary only if some 1138 * supply was off or if there were cached writes 1139 */ 1140 if (!codec->cache_sync) 1141 goto out; 1142 1143 if (gpio_is_valid(aic3x->gpio_reset)) { 1144 udelay(1); 1145 gpio_set_value(aic3x->gpio_reset, 1); 1146 } 1147 1148 /* Sync reg_cache with the hardware */ 1149 codec->cache_only = 0; 1150 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++) 1151 snd_soc_write(codec, i, cache[i]); 1152 if (aic3x->model == AIC3X_MODEL_3007) 1153 aic3x_init_3007(codec); 1154 codec->cache_sync = 0; 1155 } else { 1156 /* 1157 * Do soft reset to this codec instance in order to clear 1158 * possible VDD leakage currents in case the supply regulators 1159 * remain on 1160 */ 1161 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1162 codec->cache_sync = 1; 1163 aic3x->power = 0; 1164 /* HW writes are needless when bias is off */ 1165 codec->cache_only = 1; 1166 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), 1167 aic3x->supplies); 1168 } 1169 out: 1170 return ret; 1171 } 1172 1173 static int aic3x_set_bias_level(struct snd_soc_codec *codec, 1174 enum snd_soc_bias_level level) 1175 { 1176 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1177 1178 switch (level) { 1179 case SND_SOC_BIAS_ON: 1180 break; 1181 case SND_SOC_BIAS_PREPARE: 1182 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY && 1183 aic3x->master) { 1184 /* enable pll */ 1185 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1186 PLL_ENABLE, PLL_ENABLE); 1187 } 1188 break; 1189 case SND_SOC_BIAS_STANDBY: 1190 if (!aic3x->power) 1191 aic3x_set_power(codec, 1); 1192 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE && 1193 aic3x->master) { 1194 /* disable pll */ 1195 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, 1196 PLL_ENABLE, 0); 1197 } 1198 break; 1199 case SND_SOC_BIAS_OFF: 1200 if (aic3x->power) 1201 aic3x_set_power(codec, 0); 1202 break; 1203 } 1204 codec->dapm.bias_level = level; 1205 1206 return 0; 1207 } 1208 1209 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 1210 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1211 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 1212 1213 static const struct snd_soc_dai_ops aic3x_dai_ops = { 1214 .hw_params = aic3x_hw_params, 1215 .digital_mute = aic3x_mute, 1216 .set_sysclk = aic3x_set_dai_sysclk, 1217 .set_fmt = aic3x_set_dai_fmt, 1218 }; 1219 1220 static struct snd_soc_dai_driver aic3x_dai = { 1221 .name = "tlv320aic3x-hifi", 1222 .playback = { 1223 .stream_name = "Playback", 1224 .channels_min = 2, 1225 .channels_max = 2, 1226 .rates = AIC3X_RATES, 1227 .formats = AIC3X_FORMATS,}, 1228 .capture = { 1229 .stream_name = "Capture", 1230 .channels_min = 2, 1231 .channels_max = 2, 1232 .rates = AIC3X_RATES, 1233 .formats = AIC3X_FORMATS,}, 1234 .ops = &aic3x_dai_ops, 1235 .symmetric_rates = 1, 1236 }; 1237 1238 static int aic3x_suspend(struct snd_soc_codec *codec) 1239 { 1240 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1241 1242 return 0; 1243 } 1244 1245 static int aic3x_resume(struct snd_soc_codec *codec) 1246 { 1247 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1248 1249 return 0; 1250 } 1251 1252 /* 1253 * initialise the AIC3X driver 1254 * register the mixer and dsp interfaces with the kernel 1255 */ 1256 static int aic3x_init(struct snd_soc_codec *codec) 1257 { 1258 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1259 1260 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); 1261 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); 1262 1263 /* DAC default volume and mute */ 1264 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); 1265 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); 1266 1267 /* DAC to HP default volume and route to Output mixer */ 1268 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); 1269 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); 1270 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1271 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); 1272 /* DAC to Line Out default volume and route to Output mixer */ 1273 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1274 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1275 /* DAC to Mono Line Out default volume and route to Output mixer */ 1276 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1277 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); 1278 1279 /* unmute all outputs */ 1280 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE); 1281 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE); 1282 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE); 1283 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE); 1284 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE); 1285 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE); 1286 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE); 1287 1288 /* ADC default volume and unmute */ 1289 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN); 1290 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN); 1291 /* By default route Line1 to ADC PGA mixer */ 1292 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0); 1293 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0); 1294 1295 /* PGA to HP Bypass default volume, disconnect from Output Mixer */ 1296 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); 1297 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); 1298 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); 1299 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); 1300 /* PGA to Line Out default volume, disconnect from Output Mixer */ 1301 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); 1302 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); 1303 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ 1304 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); 1305 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); 1306 1307 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ 1308 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); 1309 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); 1310 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); 1311 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); 1312 /* Line2 Line Out default volume, disconnect from Output Mixer */ 1313 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); 1314 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); 1315 /* Line2 to Mono Out default volume, disconnect from Output Mixer */ 1316 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); 1317 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); 1318 1319 if (aic3x->model == AIC3X_MODEL_3007) { 1320 aic3x_init_3007(codec); 1321 snd_soc_write(codec, CLASSD_CTRL, 0); 1322 } 1323 1324 return 0; 1325 } 1326 1327 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x) 1328 { 1329 struct aic3x_priv *a; 1330 1331 list_for_each_entry(a, &reset_list, list) { 1332 if (gpio_is_valid(aic3x->gpio_reset) && 1333 aic3x->gpio_reset == a->gpio_reset) 1334 return true; 1335 } 1336 1337 return false; 1338 } 1339 1340 static int aic3x_probe(struct snd_soc_codec *codec) 1341 { 1342 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1343 int ret, i; 1344 1345 INIT_LIST_HEAD(&aic3x->list); 1346 aic3x->codec = codec; 1347 1348 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type); 1349 if (ret != 0) { 1350 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1351 return ret; 1352 } 1353 1354 if (gpio_is_valid(aic3x->gpio_reset) && 1355 !aic3x_is_shared_reset(aic3x)) { 1356 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); 1357 if (ret != 0) 1358 goto err_gpio; 1359 gpio_direction_output(aic3x->gpio_reset, 0); 1360 } 1361 1362 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1363 aic3x->supplies[i].supply = aic3x_supply_names[i]; 1364 1365 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies), 1366 aic3x->supplies); 1367 if (ret != 0) { 1368 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 1369 goto err_get; 1370 } 1371 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) { 1372 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; 1373 aic3x->disable_nb[i].aic3x = aic3x; 1374 ret = regulator_register_notifier(aic3x->supplies[i].consumer, 1375 &aic3x->disable_nb[i].nb); 1376 if (ret) { 1377 dev_err(codec->dev, 1378 "Failed to request regulator notifier: %d\n", 1379 ret); 1380 goto err_notif; 1381 } 1382 } 1383 1384 codec->cache_only = 1; 1385 aic3x_init(codec); 1386 1387 if (aic3x->setup) { 1388 /* setup GPIO functions */ 1389 snd_soc_write(codec, AIC3X_GPIO1_REG, 1390 (aic3x->setup->gpio_func[0] & 0xf) << 4); 1391 snd_soc_write(codec, AIC3X_GPIO2_REG, 1392 (aic3x->setup->gpio_func[1] & 0xf) << 4); 1393 } 1394 1395 snd_soc_add_codec_controls(codec, aic3x_snd_controls, 1396 ARRAY_SIZE(aic3x_snd_controls)); 1397 if (aic3x->model == AIC3X_MODEL_3007) 1398 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1); 1399 1400 /* set mic bias voltage */ 1401 switch (aic3x->micbias_vg) { 1402 case AIC3X_MICBIAS_2_0V: 1403 case AIC3X_MICBIAS_2_5V: 1404 case AIC3X_MICBIAS_AVDDV: 1405 snd_soc_update_bits(codec, MICBIAS_CTRL, 1406 MICBIAS_LEVEL_MASK, 1407 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT); 1408 break; 1409 case AIC3X_MICBIAS_OFF: 1410 /* 1411 * noting to do. target won't enter here. This is just to avoid 1412 * compile time warning "warning: enumeration value 1413 * 'AIC3X_MICBIAS_OFF' not handled in switch" 1414 */ 1415 break; 1416 } 1417 1418 aic3x_add_widgets(codec); 1419 list_add(&aic3x->list, &reset_list); 1420 1421 return 0; 1422 1423 err_notif: 1424 while (i--) 1425 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1426 &aic3x->disable_nb[i].nb); 1427 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1428 err_get: 1429 if (gpio_is_valid(aic3x->gpio_reset) && 1430 !aic3x_is_shared_reset(aic3x)) 1431 gpio_free(aic3x->gpio_reset); 1432 err_gpio: 1433 return ret; 1434 } 1435 1436 static int aic3x_remove(struct snd_soc_codec *codec) 1437 { 1438 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); 1439 int i; 1440 1441 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); 1442 list_del(&aic3x->list); 1443 if (gpio_is_valid(aic3x->gpio_reset) && 1444 !aic3x_is_shared_reset(aic3x)) { 1445 gpio_set_value(aic3x->gpio_reset, 0); 1446 gpio_free(aic3x->gpio_reset); 1447 } 1448 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) 1449 regulator_unregister_notifier(aic3x->supplies[i].consumer, 1450 &aic3x->disable_nb[i].nb); 1451 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); 1452 1453 return 0; 1454 } 1455 1456 static struct snd_soc_codec_driver soc_codec_dev_aic3x = { 1457 .set_bias_level = aic3x_set_bias_level, 1458 .idle_bias_off = true, 1459 .reg_cache_size = ARRAY_SIZE(aic3x_reg), 1460 .reg_word_size = sizeof(u8), 1461 .reg_cache_default = aic3x_reg, 1462 .probe = aic3x_probe, 1463 .remove = aic3x_remove, 1464 .suspend = aic3x_suspend, 1465 .resume = aic3x_resume, 1466 }; 1467 1468 /* 1469 * AIC3X 2 wire address can be up to 4 devices with device addresses 1470 * 0x18, 0x19, 0x1A, 0x1B 1471 */ 1472 1473 static const struct i2c_device_id aic3x_i2c_id[] = { 1474 { "tlv320aic3x", AIC3X_MODEL_3X }, 1475 { "tlv320aic33", AIC3X_MODEL_33 }, 1476 { "tlv320aic3007", AIC3X_MODEL_3007 }, 1477 { "tlv320aic3106", AIC3X_MODEL_3X }, 1478 { } 1479 }; 1480 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); 1481 1482 /* 1483 * If the i2c layer weren't so broken, we could pass this kind of data 1484 * around 1485 */ 1486 static int aic3x_i2c_probe(struct i2c_client *i2c, 1487 const struct i2c_device_id *id) 1488 { 1489 struct aic3x_pdata *pdata = i2c->dev.platform_data; 1490 struct aic3x_priv *aic3x; 1491 struct aic3x_setup_data *ai3x_setup; 1492 struct device_node *np = i2c->dev.of_node; 1493 int ret; 1494 u32 value; 1495 1496 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL); 1497 if (aic3x == NULL) { 1498 dev_err(&i2c->dev, "failed to create private data\n"); 1499 return -ENOMEM; 1500 } 1501 1502 aic3x->control_type = SND_SOC_I2C; 1503 1504 i2c_set_clientdata(i2c, aic3x); 1505 if (pdata) { 1506 aic3x->gpio_reset = pdata->gpio_reset; 1507 aic3x->setup = pdata->setup; 1508 aic3x->micbias_vg = pdata->micbias_vg; 1509 } else if (np) { 1510 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup), 1511 GFP_KERNEL); 1512 if (ai3x_setup == NULL) { 1513 dev_err(&i2c->dev, "failed to create private data\n"); 1514 return -ENOMEM; 1515 } 1516 1517 ret = of_get_named_gpio(np, "gpio-reset", 0); 1518 if (ret >= 0) 1519 aic3x->gpio_reset = ret; 1520 else 1521 aic3x->gpio_reset = -1; 1522 1523 if (of_property_read_u32_array(np, "ai3x-gpio-func", 1524 ai3x_setup->gpio_func, 2) >= 0) { 1525 aic3x->setup = ai3x_setup; 1526 } 1527 1528 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) { 1529 switch (value) { 1530 case 1 : 1531 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V; 1532 break; 1533 case 2 : 1534 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V; 1535 break; 1536 case 3 : 1537 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV; 1538 break; 1539 default : 1540 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; 1541 dev_err(&i2c->dev, "Unsuitable MicBias voltage " 1542 "found in DT\n"); 1543 } 1544 } else { 1545 aic3x->micbias_vg = AIC3X_MICBIAS_OFF; 1546 } 1547 1548 } else { 1549 aic3x->gpio_reset = -1; 1550 } 1551 1552 aic3x->model = id->driver_data; 1553 1554 ret = snd_soc_register_codec(&i2c->dev, 1555 &soc_codec_dev_aic3x, &aic3x_dai, 1); 1556 return ret; 1557 } 1558 1559 static int aic3x_i2c_remove(struct i2c_client *client) 1560 { 1561 snd_soc_unregister_codec(&client->dev); 1562 return 0; 1563 } 1564 1565 #if defined(CONFIG_OF) 1566 static const struct of_device_id tlv320aic3x_of_match[] = { 1567 { .compatible = "ti,tlv320aic3x", }, 1568 { .compatible = "ti,tlv320aic33" }, 1569 { .compatible = "ti,tlv320aic3007" }, 1570 { .compatible = "ti,tlv320aic3106" }, 1571 {}, 1572 }; 1573 MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match); 1574 #endif 1575 1576 /* machine i2c codec control layer */ 1577 static struct i2c_driver aic3x_i2c_driver = { 1578 .driver = { 1579 .name = "tlv320aic3x-codec", 1580 .owner = THIS_MODULE, 1581 .of_match_table = of_match_ptr(tlv320aic3x_of_match), 1582 }, 1583 .probe = aic3x_i2c_probe, 1584 .remove = aic3x_i2c_remove, 1585 .id_table = aic3x_i2c_id, 1586 }; 1587 1588 module_i2c_driver(aic3x_i2c_driver); 1589 1590 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); 1591 MODULE_AUTHOR("Vladimir Barinov"); 1592 MODULE_LICENSE("GPL"); 1593