1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * tlv320aic32x4.h 4 */ 5 6 7 #ifndef _TLV320AIC32X4_H 8 #define _TLV320AIC32X4_H 9 10 struct device; 11 struct regmap_config; 12 13 enum aic32x4_type { 14 AIC32X4_TYPE_AIC32X4 = 0, 15 AIC32X4_TYPE_AIC32X6, 16 AIC32X4_TYPE_TAS2505, 17 }; 18 19 extern const struct regmap_config aic32x4_regmap_config; 20 int aic32x4_probe(struct device *dev, struct regmap *regmap); 21 int aic32x4_remove(struct device *dev); 22 int aic32x4_register_clocks(struct device *dev, const char *mclk_name); 23 24 /* tlv320aic32x4 register space (in decimal to match datasheet) */ 25 26 #define AIC32X4_REG(page, reg) ((page * 128) + reg) 27 28 #define AIC32X4_PSEL AIC32X4_REG(0, 0) 29 30 #define AIC32X4_RESET AIC32X4_REG(0, 1) 31 #define AIC32X4_CLKMUX AIC32X4_REG(0, 4) 32 #define AIC32X4_PLLPR AIC32X4_REG(0, 5) 33 #define AIC32X4_PLLJ AIC32X4_REG(0, 6) 34 #define AIC32X4_PLLDMSB AIC32X4_REG(0, 7) 35 #define AIC32X4_PLLDLSB AIC32X4_REG(0, 8) 36 #define AIC32X4_NDAC AIC32X4_REG(0, 11) 37 #define AIC32X4_MDAC AIC32X4_REG(0, 12) 38 #define AIC32X4_DOSRMSB AIC32X4_REG(0, 13) 39 #define AIC32X4_DOSRLSB AIC32X4_REG(0, 14) 40 #define AIC32X4_NADC AIC32X4_REG(0, 18) 41 #define AIC32X4_MADC AIC32X4_REG(0, 19) 42 #define AIC32X4_AOSR AIC32X4_REG(0, 20) 43 #define AIC32X4_CLKMUX2 AIC32X4_REG(0, 25) 44 #define AIC32X4_CLKOUTM AIC32X4_REG(0, 26) 45 #define AIC32X4_IFACE1 AIC32X4_REG(0, 27) 46 #define AIC32X4_IFACE2 AIC32X4_REG(0, 28) 47 #define AIC32X4_IFACE3 AIC32X4_REG(0, 29) 48 #define AIC32X4_BCLKN AIC32X4_REG(0, 30) 49 #define AIC32X4_IFACE4 AIC32X4_REG(0, 31) 50 #define AIC32X4_IFACE5 AIC32X4_REG(0, 32) 51 #define AIC32X4_IFACE6 AIC32X4_REG(0, 33) 52 #define AIC32X4_GPIOCTL AIC32X4_REG(0, 52) 53 #define AIC32X4_DOUTCTL AIC32X4_REG(0, 53) 54 #define AIC32X4_DINCTL AIC32X4_REG(0, 54) 55 #define AIC32X4_MISOCTL AIC32X4_REG(0, 55) 56 #define AIC32X4_SCLKCTL AIC32X4_REG(0, 56) 57 #define AIC32X4_DACSPB AIC32X4_REG(0, 60) 58 #define AIC32X4_ADCSPB AIC32X4_REG(0, 61) 59 #define AIC32X4_DACSETUP AIC32X4_REG(0, 63) 60 #define AIC32X4_DACMUTE AIC32X4_REG(0, 64) 61 #define AIC32X4_LDACVOL AIC32X4_REG(0, 65) 62 #define AIC32X4_RDACVOL AIC32X4_REG(0, 66) 63 #define AIC32X4_ADCSETUP AIC32X4_REG(0, 81) 64 #define AIC32X4_ADCFGA AIC32X4_REG(0, 82) 65 #define AIC32X4_LADCVOL AIC32X4_REG(0, 83) 66 #define AIC32X4_RADCVOL AIC32X4_REG(0, 84) 67 #define AIC32X4_LAGC1 AIC32X4_REG(0, 86) 68 #define AIC32X4_LAGC2 AIC32X4_REG(0, 87) 69 #define AIC32X4_LAGC3 AIC32X4_REG(0, 88) 70 #define AIC32X4_LAGC4 AIC32X4_REG(0, 89) 71 #define AIC32X4_LAGC5 AIC32X4_REG(0, 90) 72 #define AIC32X4_LAGC6 AIC32X4_REG(0, 91) 73 #define AIC32X4_LAGC7 AIC32X4_REG(0, 92) 74 #define AIC32X4_RAGC1 AIC32X4_REG(0, 94) 75 #define AIC32X4_RAGC2 AIC32X4_REG(0, 95) 76 #define AIC32X4_RAGC3 AIC32X4_REG(0, 96) 77 #define AIC32X4_RAGC4 AIC32X4_REG(0, 97) 78 #define AIC32X4_RAGC5 AIC32X4_REG(0, 98) 79 #define AIC32X4_RAGC6 AIC32X4_REG(0, 99) 80 #define AIC32X4_RAGC7 AIC32X4_REG(0, 100) 81 82 #define AIC32X4_PWRCFG AIC32X4_REG(1, 1) 83 #define AIC32X4_LDOCTL AIC32X4_REG(1, 2) 84 #define AIC32X4_LPLAYBACK AIC32X4_REG(1, 3) 85 #define AIC32X4_RPLAYBACK AIC32X4_REG(1, 4) 86 #define AIC32X4_OUTPWRCTL AIC32X4_REG(1, 9) 87 #define AIC32X4_CMMODE AIC32X4_REG(1, 10) 88 #define AIC32X4_HPLROUTE AIC32X4_REG(1, 12) 89 #define AIC32X4_HPRROUTE AIC32X4_REG(1, 13) 90 #define AIC32X4_LOLROUTE AIC32X4_REG(1, 14) 91 #define AIC32X4_LORROUTE AIC32X4_REG(1, 15) 92 #define AIC32X4_HPLGAIN AIC32X4_REG(1, 16) 93 #define AIC32X4_HPRGAIN AIC32X4_REG(1, 17) 94 #define AIC32X4_LOLGAIN AIC32X4_REG(1, 18) 95 #define AIC32X4_LORGAIN AIC32X4_REG(1, 19) 96 #define AIC32X4_HEADSTART AIC32X4_REG(1, 20) 97 #define TAS2505_SPK AIC32X4_REG(1, 45) 98 #define TAS2505_SPKVOL1 AIC32X4_REG(1, 46) 99 #define TAS2505_SPKVOL2 AIC32X4_REG(1, 48) 100 #define AIC32X4_MICBIAS AIC32X4_REG(1, 51) 101 #define AIC32X4_LMICPGAPIN AIC32X4_REG(1, 52) 102 #define AIC32X4_LMICPGANIN AIC32X4_REG(1, 54) 103 #define AIC32X4_RMICPGAPIN AIC32X4_REG(1, 55) 104 #define AIC32X4_RMICPGANIN AIC32X4_REG(1, 57) 105 #define AIC32X4_FLOATINGINPUT AIC32X4_REG(1, 58) 106 #define AIC32X4_LMICPGAVOL AIC32X4_REG(1, 59) 107 #define AIC32X4_RMICPGAVOL AIC32X4_REG(1, 60) 108 #define TAS2505_REFPOWERUP AIC32X4_REG(1, 122) 109 #define AIC32X4_REFPOWERUP AIC32X4_REG(1, 123) 110 111 /* Bits, masks, and shifts */ 112 113 /* AIC32X4_CLKMUX */ 114 #define AIC32X4_PLL_CLKIN_MASK GENMASK(3, 2) 115 #define AIC32X4_PLL_CLKIN_SHIFT (2) 116 #define AIC32X4_PLL_CLKIN_MCLK (0x00) 117 #define AIC32X4_PLL_CLKIN_BCKL (0x01) 118 #define AIC32X4_PLL_CLKIN_GPIO1 (0x02) 119 #define AIC32X4_PLL_CLKIN_DIN (0x03) 120 #define AIC32X4_CODEC_CLKIN_MASK GENMASK(1, 0) 121 #define AIC32X4_CODEC_CLKIN_SHIFT (0) 122 #define AIC32X4_CODEC_CLKIN_MCLK (0x00) 123 #define AIC32X4_CODEC_CLKIN_BCLK (0x01) 124 #define AIC32X4_CODEC_CLKIN_GPIO1 (0x02) 125 #define AIC32X4_CODEC_CLKIN_PLL (0x03) 126 127 /* AIC32X4_PLLPR */ 128 #define AIC32X4_PLLEN BIT(7) 129 #define AIC32X4_PLL_P_MASK GENMASK(6, 4) 130 #define AIC32X4_PLL_P_SHIFT (4) 131 #define AIC32X4_PLL_R_MASK GENMASK(3, 0) 132 133 /* AIC32X4_NDAC */ 134 #define AIC32X4_NDACEN BIT(7) 135 #define AIC32X4_NDAC_MASK GENMASK(6, 0) 136 137 /* AIC32X4_MDAC */ 138 #define AIC32X4_MDACEN BIT(7) 139 #define AIC32X4_MDAC_MASK GENMASK(6, 0) 140 141 /* AIC32X4_NADC */ 142 #define AIC32X4_NADCEN BIT(7) 143 #define AIC32X4_NADC_MASK GENMASK(6, 0) 144 145 /* AIC32X4_MADC */ 146 #define AIC32X4_MADCEN BIT(7) 147 #define AIC32X4_MADC_MASK GENMASK(6, 0) 148 149 /* AIC32X4_BCLKN */ 150 #define AIC32X4_BCLKEN BIT(7) 151 #define AIC32X4_BCLK_MASK GENMASK(6, 0) 152 153 /* AIC32X4_IFACE1 */ 154 #define AIC32X4_IFACE1_DATATYPE_MASK GENMASK(7, 6) 155 #define AIC32X4_IFACE1_DATATYPE_SHIFT (6) 156 #define AIC32X4_I2S_MODE (0x00) 157 #define AIC32X4_DSP_MODE (0x01) 158 #define AIC32X4_RIGHT_JUSTIFIED_MODE (0x02) 159 #define AIC32X4_LEFT_JUSTIFIED_MODE (0x03) 160 #define AIC32X4_IFACE1_DATALEN_MASK GENMASK(5, 4) 161 #define AIC32X4_IFACE1_DATALEN_SHIFT (4) 162 #define AIC32X4_WORD_LEN_16BITS (0x00) 163 #define AIC32X4_WORD_LEN_20BITS (0x01) 164 #define AIC32X4_WORD_LEN_24BITS (0x02) 165 #define AIC32X4_WORD_LEN_32BITS (0x03) 166 #define AIC32X4_IFACE1_MASTER_MASK GENMASK(3, 2) 167 #define AIC32X4_BCLKMASTER BIT(2) 168 #define AIC32X4_WCLKMASTER BIT(3) 169 170 /* AIC32X4_IFACE2 */ 171 #define AIC32X4_DATA_OFFSET_MASK GENMASK(7, 0) 172 173 /* AIC32X4_IFACE3 */ 174 #define AIC32X4_BCLKINV_MASK BIT(3) 175 #define AIC32X4_BDIVCLK_MASK GENMASK(1, 0) 176 #define AIC32X4_BDIVCLK_SHIFT (0) 177 #define AIC32X4_DAC2BCLK (0x00) 178 #define AIC32X4_DACMOD2BCLK (0x01) 179 #define AIC32X4_ADC2BCLK (0x02) 180 #define AIC32X4_ADCMOD2BCLK (0x03) 181 182 /* AIC32X4_DACSETUP */ 183 #define AIC32X4_DAC_CHAN_MASK GENMASK(5, 2) 184 #define AIC32X4_LDAC2RCHN BIT(5) 185 #define AIC32X4_LDAC2LCHN BIT(4) 186 #define AIC32X4_RDAC2LCHN BIT(3) 187 #define AIC32X4_RDAC2RCHN BIT(2) 188 189 /* AIC32X4_DACMUTE */ 190 #define AIC32X4_MUTEON 0x0C 191 192 /* AIC32X4_ADCSETUP */ 193 #define AIC32X4_LADC_EN BIT(7) 194 #define AIC32X4_RADC_EN BIT(6) 195 196 /* AIC32X4_PWRCFG */ 197 #define AIC32X4_AVDDWEAKDISABLE BIT(3) 198 199 /* AIC32X4_LDOCTL */ 200 #define AIC32X4_LDOCTLEN BIT(0) 201 202 /* AIC32X4_CMMODE */ 203 #define AIC32X4_LDOIN_18_36 BIT(0) 204 #define AIC32X4_LDOIN2HP BIT(1) 205 206 /* AIC32X4_MICBIAS */ 207 #define AIC32X4_MICBIAS_LDOIN BIT(3) 208 #define AIC32X4_MICBIAS_2075V 0x60 209 #define AIC32x4_MICBIAS_MASK GENMASK(6, 3) 210 211 /* AIC32X4_LMICPGANIN */ 212 #define AIC32X4_LMICPGANIN_IN2R_10K 0x10 213 #define AIC32X4_LMICPGANIN_CM1L_10K 0x40 214 215 /* AIC32X4_RMICPGANIN */ 216 #define AIC32X4_RMICPGANIN_IN1L_10K 0x10 217 #define AIC32X4_RMICPGANIN_CM1R_10K 0x40 218 219 /* AIC32X4_REFPOWERUP */ 220 #define AIC32X4_REFPOWERUP_SLOW 0x04 221 #define AIC32X4_REFPOWERUP_40MS 0x05 222 #define AIC32X4_REFPOWERUP_80MS 0x06 223 #define AIC32X4_REFPOWERUP_120MS 0x07 224 225 /* Common mask and enable for all of the dividers */ 226 #define AIC32X4_DIVEN BIT(7) 227 #define AIC32X4_DIV_MASK GENMASK(6, 0) 228 229 /* Clock Limits */ 230 #define AIC32X4_MAX_DOSR_FREQ 6200000 231 #define AIC32X4_MIN_DOSR_FREQ 2800000 232 #define AIC32X4_MAX_CODEC_CLKIN_FREQ 110000000 233 #define AIC32X4_MAX_PLL_CLKIN 20000000 234 235 #endif /* _TLV320AIC32X4_H */ 236