11d471cd1SJavier Martin /* 21d471cd1SJavier Martin * tlv320aic32x4.h 31d471cd1SJavier Martin * 41d471cd1SJavier Martin * This program is free software; you can redistribute it and/or modify 51d471cd1SJavier Martin * it under the terms of the GNU General Public License version 2 as 61d471cd1SJavier Martin * published by the Free Software Foundation. 71d471cd1SJavier Martin */ 81d471cd1SJavier Martin 91d471cd1SJavier Martin 101d471cd1SJavier Martin #ifndef _TLV320AIC32X4_H 111d471cd1SJavier Martin #define _TLV320AIC32X4_H 121d471cd1SJavier Martin 131d471cd1SJavier Martin /* tlv320aic32x4 register space (in decimal to match datasheet) */ 141d471cd1SJavier Martin 151d471cd1SJavier Martin #define AIC32X4_PAGE1 128 161d471cd1SJavier Martin 171d471cd1SJavier Martin #define AIC32X4_PSEL 0 181d471cd1SJavier Martin #define AIC32X4_RESET 1 191d471cd1SJavier Martin #define AIC32X4_CLKMUX 4 201d471cd1SJavier Martin #define AIC32X4_PLLPR 5 211d471cd1SJavier Martin #define AIC32X4_PLLJ 6 221d471cd1SJavier Martin #define AIC32X4_PLLDMSB 7 231d471cd1SJavier Martin #define AIC32X4_PLLDLSB 8 241d471cd1SJavier Martin #define AIC32X4_NDAC 11 251d471cd1SJavier Martin #define AIC32X4_MDAC 12 261d471cd1SJavier Martin #define AIC32X4_DOSRMSB 13 271d471cd1SJavier Martin #define AIC32X4_DOSRLSB 14 281d471cd1SJavier Martin #define AIC32X4_NADC 18 291d471cd1SJavier Martin #define AIC32X4_MADC 19 301d471cd1SJavier Martin #define AIC32X4_AOSR 20 311d471cd1SJavier Martin #define AIC32X4_CLKMUX2 25 321d471cd1SJavier Martin #define AIC32X4_CLKOUTM 26 331d471cd1SJavier Martin #define AIC32X4_IFACE1 27 341d471cd1SJavier Martin #define AIC32X4_IFACE2 28 351d471cd1SJavier Martin #define AIC32X4_IFACE3 29 361d471cd1SJavier Martin #define AIC32X4_BCLKN 30 371d471cd1SJavier Martin #define AIC32X4_IFACE4 31 381d471cd1SJavier Martin #define AIC32X4_IFACE5 32 391d471cd1SJavier Martin #define AIC32X4_IFACE6 33 401d471cd1SJavier Martin #define AIC32X4_DOUTCTL 53 411d471cd1SJavier Martin #define AIC32X4_DINCTL 54 421d471cd1SJavier Martin #define AIC32X4_DACSPB 60 431d471cd1SJavier Martin #define AIC32X4_ADCSPB 61 441d471cd1SJavier Martin #define AIC32X4_DACSETUP 63 451d471cd1SJavier Martin #define AIC32X4_DACMUTE 64 461d471cd1SJavier Martin #define AIC32X4_LDACVOL 65 471d471cd1SJavier Martin #define AIC32X4_RDACVOL 66 481d471cd1SJavier Martin #define AIC32X4_ADCSETUP 81 491d471cd1SJavier Martin #define AIC32X4_ADCFGA 82 501d471cd1SJavier Martin #define AIC32X4_LADCVOL 83 511d471cd1SJavier Martin #define AIC32X4_RADCVOL 84 521d471cd1SJavier Martin #define AIC32X4_LAGC1 86 531d471cd1SJavier Martin #define AIC32X4_LAGC2 87 541d471cd1SJavier Martin #define AIC32X4_LAGC3 88 551d471cd1SJavier Martin #define AIC32X4_LAGC4 89 561d471cd1SJavier Martin #define AIC32X4_LAGC5 90 571d471cd1SJavier Martin #define AIC32X4_LAGC6 91 581d471cd1SJavier Martin #define AIC32X4_LAGC7 92 591d471cd1SJavier Martin #define AIC32X4_RAGC1 94 601d471cd1SJavier Martin #define AIC32X4_RAGC2 95 611d471cd1SJavier Martin #define AIC32X4_RAGC3 96 621d471cd1SJavier Martin #define AIC32X4_RAGC4 97 631d471cd1SJavier Martin #define AIC32X4_RAGC5 98 641d471cd1SJavier Martin #define AIC32X4_RAGC6 99 651d471cd1SJavier Martin #define AIC32X4_RAGC7 100 661d471cd1SJavier Martin #define AIC32X4_PWRCFG (AIC32X4_PAGE1 + 1) 671d471cd1SJavier Martin #define AIC32X4_LDOCTL (AIC32X4_PAGE1 + 2) 681d471cd1SJavier Martin #define AIC32X4_OUTPWRCTL (AIC32X4_PAGE1 + 9) 691d471cd1SJavier Martin #define AIC32X4_CMMODE (AIC32X4_PAGE1 + 10) 701d471cd1SJavier Martin #define AIC32X4_HPLROUTE (AIC32X4_PAGE1 + 12) 711d471cd1SJavier Martin #define AIC32X4_HPRROUTE (AIC32X4_PAGE1 + 13) 721d471cd1SJavier Martin #define AIC32X4_LOLROUTE (AIC32X4_PAGE1 + 14) 731d471cd1SJavier Martin #define AIC32X4_LORROUTE (AIC32X4_PAGE1 + 15) 741d471cd1SJavier Martin #define AIC32X4_HPLGAIN (AIC32X4_PAGE1 + 16) 751d471cd1SJavier Martin #define AIC32X4_HPRGAIN (AIC32X4_PAGE1 + 17) 761d471cd1SJavier Martin #define AIC32X4_LOLGAIN (AIC32X4_PAGE1 + 18) 771d471cd1SJavier Martin #define AIC32X4_LORGAIN (AIC32X4_PAGE1 + 19) 781d471cd1SJavier Martin #define AIC32X4_HEADSTART (AIC32X4_PAGE1 + 20) 791d471cd1SJavier Martin #define AIC32X4_MICBIAS (AIC32X4_PAGE1 + 51) 801d471cd1SJavier Martin #define AIC32X4_LMICPGAPIN (AIC32X4_PAGE1 + 52) 811d471cd1SJavier Martin #define AIC32X4_LMICPGANIN (AIC32X4_PAGE1 + 54) 821d471cd1SJavier Martin #define AIC32X4_RMICPGAPIN (AIC32X4_PAGE1 + 55) 831d471cd1SJavier Martin #define AIC32X4_RMICPGANIN (AIC32X4_PAGE1 + 57) 841d471cd1SJavier Martin #define AIC32X4_FLOATINGINPUT (AIC32X4_PAGE1 + 58) 851d471cd1SJavier Martin #define AIC32X4_LMICPGAVOL (AIC32X4_PAGE1 + 59) 861d471cd1SJavier Martin #define AIC32X4_RMICPGAVOL (AIC32X4_PAGE1 + 60) 871d471cd1SJavier Martin 881d471cd1SJavier Martin #define AIC32X4_FREQ_12000000 12000000 891d471cd1SJavier Martin #define AIC32X4_FREQ_24000000 24000000 901d471cd1SJavier Martin #define AIC32X4_FREQ_25000000 25000000 911d471cd1SJavier Martin 921d471cd1SJavier Martin #define AIC32X4_WORD_LEN_16BITS 0x00 931d471cd1SJavier Martin #define AIC32X4_WORD_LEN_20BITS 0x01 941d471cd1SJavier Martin #define AIC32X4_WORD_LEN_24BITS 0x02 951d471cd1SJavier Martin #define AIC32X4_WORD_LEN_32BITS 0x03 961d471cd1SJavier Martin 97a405387cSJavier Martin #define AIC32X4_LADC_EN (1 << 7) 98a405387cSJavier Martin #define AIC32X4_RADC_EN (1 << 6) 99a405387cSJavier Martin 1001d471cd1SJavier Martin #define AIC32X4_I2S_MODE 0x00 1011d471cd1SJavier Martin #define AIC32X4_DSP_MODE 0x01 1021d471cd1SJavier Martin #define AIC32X4_RIGHT_JUSTIFIED_MODE 0x02 1031d471cd1SJavier Martin #define AIC32X4_LEFT_JUSTIFIED_MODE 0x03 1041d471cd1SJavier Martin 1051d471cd1SJavier Martin #define AIC32X4_AVDDWEAKDISABLE 0x08 1061d471cd1SJavier Martin #define AIC32X4_LDOCTLEN 0x01 1071d471cd1SJavier Martin 1081d471cd1SJavier Martin #define AIC32X4_LDOIN_18_36 0x01 1091d471cd1SJavier Martin #define AIC32X4_LDOIN2HP 0x02 1101d471cd1SJavier Martin 1111d471cd1SJavier Martin #define AIC32X4_DACSPBLOCK_MASK 0x1f 1121d471cd1SJavier Martin #define AIC32X4_ADCSPBLOCK_MASK 0x1f 1131d471cd1SJavier Martin 1141d471cd1SJavier Martin #define AIC32X4_PLLJ_SHIFT 6 1151d471cd1SJavier Martin #define AIC32X4_DOSRMSB_SHIFT 4 1161d471cd1SJavier Martin 1171d471cd1SJavier Martin #define AIC32X4_PLLCLKIN 0x03 1181d471cd1SJavier Martin 1191d471cd1SJavier Martin #define AIC32X4_MICBIAS_LDOIN 0x08 1201d471cd1SJavier Martin #define AIC32X4_MICBIAS_2075V 0x60 1211d471cd1SJavier Martin 1221d471cd1SJavier Martin #define AIC32X4_LMICPGANIN_IN2R_10K 0x10 1231d471cd1SJavier Martin #define AIC32X4_RMICPGANIN_IN1L_10K 0x10 1241d471cd1SJavier Martin 1251d471cd1SJavier Martin #define AIC32X4_LMICPGAVOL_NOGAIN 0x80 1261d471cd1SJavier Martin #define AIC32X4_RMICPGAVOL_NOGAIN 0x80 1271d471cd1SJavier Martin 1281d471cd1SJavier Martin #define AIC32X4_BCLKMASTER 0x08 1291d471cd1SJavier Martin #define AIC32X4_WCLKMASTER 0x04 1301d471cd1SJavier Martin #define AIC32X4_PLLEN (0x01 << 7) 1311d471cd1SJavier Martin #define AIC32X4_NDACEN (0x01 << 7) 1321d471cd1SJavier Martin #define AIC32X4_MDACEN (0x01 << 7) 1331d471cd1SJavier Martin #define AIC32X4_NADCEN (0x01 << 7) 1341d471cd1SJavier Martin #define AIC32X4_MADCEN (0x01 << 7) 1351d471cd1SJavier Martin #define AIC32X4_BCLKEN (0x01 << 7) 1361d471cd1SJavier Martin #define AIC32X4_DACEN (0x03 << 6) 1371d471cd1SJavier Martin #define AIC32X4_RDAC2LCHN (0x02 << 2) 1381d471cd1SJavier Martin #define AIC32X4_LDAC2RCHN (0x02 << 4) 1391d471cd1SJavier Martin #define AIC32X4_LDAC2LCHN (0x01 << 4) 1401d471cd1SJavier Martin #define AIC32X4_RDAC2RCHN (0x01 << 2) 1411d471cd1SJavier Martin 1421d471cd1SJavier Martin #define AIC32X4_SSTEP2WCLK 0x01 1431d471cd1SJavier Martin #define AIC32X4_MUTEON 0x0C 1441d471cd1SJavier Martin #define AIC32X4_DACMOD2BCLK 0x01 1451d471cd1SJavier Martin 1461d471cd1SJavier Martin #endif /* _TLV320AIC32X4_H */ 147