1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 21d471cd1SJavier Martin /* 31d471cd1SJavier Martin * tlv320aic32x4.h 41d471cd1SJavier Martin */ 51d471cd1SJavier Martin 61d471cd1SJavier Martin 71d471cd1SJavier Martin #ifndef _TLV320AIC32X4_H 81d471cd1SJavier Martin #define _TLV320AIC32X4_H 91d471cd1SJavier Martin 103bcfd222SJeremy McDermond struct device; 113bcfd222SJeremy McDermond struct regmap_config; 123bcfd222SJeremy McDermond 13*688d47cdSClaudius Heine enum aic32x4_type { 14*688d47cdSClaudius Heine AIC32X4_TYPE_AIC32X4 = 0, 15*688d47cdSClaudius Heine AIC32X4_TYPE_AIC32X6, 16*688d47cdSClaudius Heine }; 17*688d47cdSClaudius Heine 183bcfd222SJeremy McDermond extern const struct regmap_config aic32x4_regmap_config; 193bcfd222SJeremy McDermond int aic32x4_probe(struct device *dev, struct regmap *regmap); 203bcfd222SJeremy McDermond int aic32x4_remove(struct device *dev); 21514b044cSAnnaliese McDermond int aic32x4_register_clocks(struct device *dev, const char *mclk_name); 223bcfd222SJeremy McDermond 231d471cd1SJavier Martin /* tlv320aic32x4 register space (in decimal to match datasheet) */ 241d471cd1SJavier Martin 251714196cSAndrew F. Davis #define AIC32X4_REG(page, reg) ((page * 128) + reg) 261d471cd1SJavier Martin 271714196cSAndrew F. Davis #define AIC32X4_PSEL AIC32X4_REG(0, 0) 281714196cSAndrew F. Davis 291714196cSAndrew F. Davis #define AIC32X4_RESET AIC32X4_REG(0, 1) 301714196cSAndrew F. Davis #define AIC32X4_CLKMUX AIC32X4_REG(0, 4) 311714196cSAndrew F. Davis #define AIC32X4_PLLPR AIC32X4_REG(0, 5) 321714196cSAndrew F. Davis #define AIC32X4_PLLJ AIC32X4_REG(0, 6) 331714196cSAndrew F. Davis #define AIC32X4_PLLDMSB AIC32X4_REG(0, 7) 341714196cSAndrew F. Davis #define AIC32X4_PLLDLSB AIC32X4_REG(0, 8) 351714196cSAndrew F. Davis #define AIC32X4_NDAC AIC32X4_REG(0, 11) 361714196cSAndrew F. Davis #define AIC32X4_MDAC AIC32X4_REG(0, 12) 371714196cSAndrew F. Davis #define AIC32X4_DOSRMSB AIC32X4_REG(0, 13) 381714196cSAndrew F. Davis #define AIC32X4_DOSRLSB AIC32X4_REG(0, 14) 391714196cSAndrew F. Davis #define AIC32X4_NADC AIC32X4_REG(0, 18) 401714196cSAndrew F. Davis #define AIC32X4_MADC AIC32X4_REG(0, 19) 411714196cSAndrew F. Davis #define AIC32X4_AOSR AIC32X4_REG(0, 20) 421714196cSAndrew F. Davis #define AIC32X4_CLKMUX2 AIC32X4_REG(0, 25) 431714196cSAndrew F. Davis #define AIC32X4_CLKOUTM AIC32X4_REG(0, 26) 441714196cSAndrew F. Davis #define AIC32X4_IFACE1 AIC32X4_REG(0, 27) 451714196cSAndrew F. Davis #define AIC32X4_IFACE2 AIC32X4_REG(0, 28) 461714196cSAndrew F. Davis #define AIC32X4_IFACE3 AIC32X4_REG(0, 29) 471714196cSAndrew F. Davis #define AIC32X4_BCLKN AIC32X4_REG(0, 30) 481714196cSAndrew F. Davis #define AIC32X4_IFACE4 AIC32X4_REG(0, 31) 491714196cSAndrew F. Davis #define AIC32X4_IFACE5 AIC32X4_REG(0, 32) 501714196cSAndrew F. Davis #define AIC32X4_IFACE6 AIC32X4_REG(0, 33) 511714196cSAndrew F. Davis #define AIC32X4_GPIOCTL AIC32X4_REG(0, 52) 521714196cSAndrew F. Davis #define AIC32X4_DOUTCTL AIC32X4_REG(0, 53) 531714196cSAndrew F. Davis #define AIC32X4_DINCTL AIC32X4_REG(0, 54) 541714196cSAndrew F. Davis #define AIC32X4_MISOCTL AIC32X4_REG(0, 55) 551714196cSAndrew F. Davis #define AIC32X4_SCLKCTL AIC32X4_REG(0, 56) 561714196cSAndrew F. Davis #define AIC32X4_DACSPB AIC32X4_REG(0, 60) 571714196cSAndrew F. Davis #define AIC32X4_ADCSPB AIC32X4_REG(0, 61) 581714196cSAndrew F. Davis #define AIC32X4_DACSETUP AIC32X4_REG(0, 63) 591714196cSAndrew F. Davis #define AIC32X4_DACMUTE AIC32X4_REG(0, 64) 601714196cSAndrew F. Davis #define AIC32X4_LDACVOL AIC32X4_REG(0, 65) 611714196cSAndrew F. Davis #define AIC32X4_RDACVOL AIC32X4_REG(0, 66) 621714196cSAndrew F. Davis #define AIC32X4_ADCSETUP AIC32X4_REG(0, 81) 631714196cSAndrew F. Davis #define AIC32X4_ADCFGA AIC32X4_REG(0, 82) 641714196cSAndrew F. Davis #define AIC32X4_LADCVOL AIC32X4_REG(0, 83) 651714196cSAndrew F. Davis #define AIC32X4_RADCVOL AIC32X4_REG(0, 84) 661714196cSAndrew F. Davis #define AIC32X4_LAGC1 AIC32X4_REG(0, 86) 671714196cSAndrew F. Davis #define AIC32X4_LAGC2 AIC32X4_REG(0, 87) 681714196cSAndrew F. Davis #define AIC32X4_LAGC3 AIC32X4_REG(0, 88) 691714196cSAndrew F. Davis #define AIC32X4_LAGC4 AIC32X4_REG(0, 89) 701714196cSAndrew F. Davis #define AIC32X4_LAGC5 AIC32X4_REG(0, 90) 711714196cSAndrew F. Davis #define AIC32X4_LAGC6 AIC32X4_REG(0, 91) 721714196cSAndrew F. Davis #define AIC32X4_LAGC7 AIC32X4_REG(0, 92) 731714196cSAndrew F. Davis #define AIC32X4_RAGC1 AIC32X4_REG(0, 94) 741714196cSAndrew F. Davis #define AIC32X4_RAGC2 AIC32X4_REG(0, 95) 751714196cSAndrew F. Davis #define AIC32X4_RAGC3 AIC32X4_REG(0, 96) 761714196cSAndrew F. Davis #define AIC32X4_RAGC4 AIC32X4_REG(0, 97) 771714196cSAndrew F. Davis #define AIC32X4_RAGC5 AIC32X4_REG(0, 98) 781714196cSAndrew F. Davis #define AIC32X4_RAGC6 AIC32X4_REG(0, 99) 791714196cSAndrew F. Davis #define AIC32X4_RAGC7 AIC32X4_REG(0, 100) 801714196cSAndrew F. Davis 811714196cSAndrew F. Davis #define AIC32X4_PWRCFG AIC32X4_REG(1, 1) 821714196cSAndrew F. Davis #define AIC32X4_LDOCTL AIC32X4_REG(1, 2) 83d3e6e374SAnnaliese McDermond #define AIC32X4_LPLAYBACK AIC32X4_REG(1, 3) 84d3e6e374SAnnaliese McDermond #define AIC32X4_RPLAYBACK AIC32X4_REG(1, 4) 851714196cSAndrew F. Davis #define AIC32X4_OUTPWRCTL AIC32X4_REG(1, 9) 861714196cSAndrew F. Davis #define AIC32X4_CMMODE AIC32X4_REG(1, 10) 871714196cSAndrew F. Davis #define AIC32X4_HPLROUTE AIC32X4_REG(1, 12) 881714196cSAndrew F. Davis #define AIC32X4_HPRROUTE AIC32X4_REG(1, 13) 891714196cSAndrew F. Davis #define AIC32X4_LOLROUTE AIC32X4_REG(1, 14) 901714196cSAndrew F. Davis #define AIC32X4_LORROUTE AIC32X4_REG(1, 15) 911714196cSAndrew F. Davis #define AIC32X4_HPLGAIN AIC32X4_REG(1, 16) 921714196cSAndrew F. Davis #define AIC32X4_HPRGAIN AIC32X4_REG(1, 17) 931714196cSAndrew F. Davis #define AIC32X4_LOLGAIN AIC32X4_REG(1, 18) 941714196cSAndrew F. Davis #define AIC32X4_LORGAIN AIC32X4_REG(1, 19) 951714196cSAndrew F. Davis #define AIC32X4_HEADSTART AIC32X4_REG(1, 20) 961714196cSAndrew F. Davis #define AIC32X4_MICBIAS AIC32X4_REG(1, 51) 971714196cSAndrew F. Davis #define AIC32X4_LMICPGAPIN AIC32X4_REG(1, 52) 981714196cSAndrew F. Davis #define AIC32X4_LMICPGANIN AIC32X4_REG(1, 54) 991714196cSAndrew F. Davis #define AIC32X4_RMICPGAPIN AIC32X4_REG(1, 55) 1001714196cSAndrew F. Davis #define AIC32X4_RMICPGANIN AIC32X4_REG(1, 57) 1011714196cSAndrew F. Davis #define AIC32X4_FLOATINGINPUT AIC32X4_REG(1, 58) 1021714196cSAndrew F. Davis #define AIC32X4_LMICPGAVOL AIC32X4_REG(1, 59) 1031714196cSAndrew F. Davis #define AIC32X4_RMICPGAVOL AIC32X4_REG(1, 60) 104ec96690dSMiquel Raynal #define AIC32X4_REFPOWERUP AIC32X4_REG(1, 123) 1051d471cd1SJavier Martin 1060fe7aa39SAndrew F. Davis /* Bits, masks, and shifts */ 1071d471cd1SJavier Martin 1080fe7aa39SAndrew F. Davis /* AIC32X4_CLKMUX */ 1090fe7aa39SAndrew F. Davis #define AIC32X4_PLL_CLKIN_MASK GENMASK(3, 2) 1100fe7aa39SAndrew F. Davis #define AIC32X4_PLL_CLKIN_SHIFT (2) 1110fe7aa39SAndrew F. Davis #define AIC32X4_PLL_CLKIN_MCLK (0x00) 1120fe7aa39SAndrew F. Davis #define AIC32X4_PLL_CLKIN_BCKL (0x01) 1130fe7aa39SAndrew F. Davis #define AIC32X4_PLL_CLKIN_GPIO1 (0x02) 1140fe7aa39SAndrew F. Davis #define AIC32X4_PLL_CLKIN_DIN (0x03) 1150fe7aa39SAndrew F. Davis #define AIC32X4_CODEC_CLKIN_MASK GENMASK(1, 0) 1160fe7aa39SAndrew F. Davis #define AIC32X4_CODEC_CLKIN_SHIFT (0) 1170fe7aa39SAndrew F. Davis #define AIC32X4_CODEC_CLKIN_MCLK (0x00) 1180fe7aa39SAndrew F. Davis #define AIC32X4_CODEC_CLKIN_BCLK (0x01) 1190fe7aa39SAndrew F. Davis #define AIC32X4_CODEC_CLKIN_GPIO1 (0x02) 1200fe7aa39SAndrew F. Davis #define AIC32X4_CODEC_CLKIN_PLL (0x03) 121a405387cSJavier Martin 1220fe7aa39SAndrew F. Davis /* AIC32X4_PLLPR */ 1230fe7aa39SAndrew F. Davis #define AIC32X4_PLLEN BIT(7) 12464aab899SAndrew F. Davis #define AIC32X4_PLL_P_MASK GENMASK(6, 4) 12564aab899SAndrew F. Davis #define AIC32X4_PLL_P_SHIFT (4) 12664aab899SAndrew F. Davis #define AIC32X4_PLL_R_MASK GENMASK(3, 0) 1271d471cd1SJavier Martin 1280fe7aa39SAndrew F. Davis /* AIC32X4_NDAC */ 1290fe7aa39SAndrew F. Davis #define AIC32X4_NDACEN BIT(7) 13064aab899SAndrew F. Davis #define AIC32X4_NDAC_MASK GENMASK(6, 0) 1311d471cd1SJavier Martin 1320fe7aa39SAndrew F. Davis /* AIC32X4_MDAC */ 1330fe7aa39SAndrew F. Davis #define AIC32X4_MDACEN BIT(7) 13464aab899SAndrew F. Davis #define AIC32X4_MDAC_MASK GENMASK(6, 0) 1351d471cd1SJavier Martin 1360fe7aa39SAndrew F. Davis /* AIC32X4_NADC */ 1370fe7aa39SAndrew F. Davis #define AIC32X4_NADCEN BIT(7) 13864aab899SAndrew F. Davis #define AIC32X4_NADC_MASK GENMASK(6, 0) 1391d471cd1SJavier Martin 1400fe7aa39SAndrew F. Davis /* AIC32X4_MADC */ 1410fe7aa39SAndrew F. Davis #define AIC32X4_MADCEN BIT(7) 14264aab899SAndrew F. Davis #define AIC32X4_MADC_MASK GENMASK(6, 0) 1431d471cd1SJavier Martin 1440fe7aa39SAndrew F. Davis /* AIC32X4_BCLKN */ 1450fe7aa39SAndrew F. Davis #define AIC32X4_BCLKEN BIT(7) 14664aab899SAndrew F. Davis #define AIC32X4_BCLK_MASK GENMASK(6, 0) 1471d471cd1SJavier Martin 1480fe7aa39SAndrew F. Davis /* AIC32X4_IFACE1 */ 1490fe7aa39SAndrew F. Davis #define AIC32X4_IFACE1_DATATYPE_MASK GENMASK(7, 6) 1500fe7aa39SAndrew F. Davis #define AIC32X4_IFACE1_DATATYPE_SHIFT (6) 1510fe7aa39SAndrew F. Davis #define AIC32X4_I2S_MODE (0x00) 1520fe7aa39SAndrew F. Davis #define AIC32X4_DSP_MODE (0x01) 1530fe7aa39SAndrew F. Davis #define AIC32X4_RIGHT_JUSTIFIED_MODE (0x02) 1540fe7aa39SAndrew F. Davis #define AIC32X4_LEFT_JUSTIFIED_MODE (0x03) 1550fe7aa39SAndrew F. Davis #define AIC32X4_IFACE1_DATALEN_MASK GENMASK(5, 4) 1560fe7aa39SAndrew F. Davis #define AIC32X4_IFACE1_DATALEN_SHIFT (4) 1570fe7aa39SAndrew F. Davis #define AIC32X4_WORD_LEN_16BITS (0x00) 1580fe7aa39SAndrew F. Davis #define AIC32X4_WORD_LEN_20BITS (0x01) 1590fe7aa39SAndrew F. Davis #define AIC32X4_WORD_LEN_24BITS (0x02) 1600fe7aa39SAndrew F. Davis #define AIC32X4_WORD_LEN_32BITS (0x03) 1610fe7aa39SAndrew F. Davis #define AIC32X4_IFACE1_MASTER_MASK GENMASK(3, 2) 1620fe7aa39SAndrew F. Davis #define AIC32X4_BCLKMASTER BIT(2) 1630fe7aa39SAndrew F. Davis #define AIC32X4_WCLKMASTER BIT(3) 1640fe7aa39SAndrew F. Davis 1650fe7aa39SAndrew F. Davis /* AIC32X4_IFACE2 */ 1660fe7aa39SAndrew F. Davis #define AIC32X4_DATA_OFFSET_MASK GENMASK(7, 0) 1670fe7aa39SAndrew F. Davis 1680fe7aa39SAndrew F. Davis /* AIC32X4_IFACE3 */ 1690fe7aa39SAndrew F. Davis #define AIC32X4_BCLKINV_MASK BIT(3) 1700fe7aa39SAndrew F. Davis #define AIC32X4_BDIVCLK_MASK GENMASK(1, 0) 1710fe7aa39SAndrew F. Davis #define AIC32X4_BDIVCLK_SHIFT (0) 1720fe7aa39SAndrew F. Davis #define AIC32X4_DAC2BCLK (0x00) 1730fe7aa39SAndrew F. Davis #define AIC32X4_DACMOD2BCLK (0x01) 1740fe7aa39SAndrew F. Davis #define AIC32X4_ADC2BCLK (0x02) 1750fe7aa39SAndrew F. Davis #define AIC32X4_ADCMOD2BCLK (0x03) 1760fe7aa39SAndrew F. Davis 1770fe7aa39SAndrew F. Davis /* AIC32X4_DACSETUP */ 1780fe7aa39SAndrew F. Davis #define AIC32X4_DAC_CHAN_MASK GENMASK(5, 2) 1790fe7aa39SAndrew F. Davis #define AIC32X4_LDAC2RCHN BIT(5) 1800fe7aa39SAndrew F. Davis #define AIC32X4_LDAC2LCHN BIT(4) 1810fe7aa39SAndrew F. Davis #define AIC32X4_RDAC2LCHN BIT(3) 1820fe7aa39SAndrew F. Davis #define AIC32X4_RDAC2RCHN BIT(2) 1830fe7aa39SAndrew F. Davis 1840fe7aa39SAndrew F. Davis /* AIC32X4_DACMUTE */ 1850fe7aa39SAndrew F. Davis #define AIC32X4_MUTEON 0x0C 1860fe7aa39SAndrew F. Davis 1870fe7aa39SAndrew F. Davis /* AIC32X4_ADCSETUP */ 1880fe7aa39SAndrew F. Davis #define AIC32X4_LADC_EN BIT(7) 1890fe7aa39SAndrew F. Davis #define AIC32X4_RADC_EN BIT(6) 1900fe7aa39SAndrew F. Davis 1910fe7aa39SAndrew F. Davis /* AIC32X4_PWRCFG */ 1920fe7aa39SAndrew F. Davis #define AIC32X4_AVDDWEAKDISABLE BIT(3) 1930fe7aa39SAndrew F. Davis 1940fe7aa39SAndrew F. Davis /* AIC32X4_LDOCTL */ 1950fe7aa39SAndrew F. Davis #define AIC32X4_LDOCTLEN BIT(0) 1960fe7aa39SAndrew F. Davis 1970fe7aa39SAndrew F. Davis /* AIC32X4_CMMODE */ 1980fe7aa39SAndrew F. Davis #define AIC32X4_LDOIN_18_36 BIT(0) 1990fe7aa39SAndrew F. Davis #define AIC32X4_LDOIN2HP BIT(1) 2000fe7aa39SAndrew F. Davis 2010fe7aa39SAndrew F. Davis /* AIC32X4_MICBIAS */ 2020fe7aa39SAndrew F. Davis #define AIC32X4_MICBIAS_LDOIN BIT(3) 2031d471cd1SJavier Martin #define AIC32X4_MICBIAS_2075V 0x60 20404d979d7Sb-ak #define AIC32x4_MICBIAS_MASK GENMASK(6, 3) 2051d471cd1SJavier Martin 2060fe7aa39SAndrew F. Davis /* AIC32X4_LMICPGANIN */ 2071d471cd1SJavier Martin #define AIC32X4_LMICPGANIN_IN2R_10K 0x10 208609e6025SMarkus Pargmann #define AIC32X4_LMICPGANIN_CM1L_10K 0x40 2090fe7aa39SAndrew F. Davis 2100fe7aa39SAndrew F. Davis /* AIC32X4_RMICPGANIN */ 2111d471cd1SJavier Martin #define AIC32X4_RMICPGANIN_IN1L_10K 0x10 212609e6025SMarkus Pargmann #define AIC32X4_RMICPGANIN_CM1R_10K 0x40 2131d471cd1SJavier Martin 214ec96690dSMiquel Raynal /* AIC32X4_REFPOWERUP */ 215ec96690dSMiquel Raynal #define AIC32X4_REFPOWERUP_SLOW 0x04 216ec96690dSMiquel Raynal #define AIC32X4_REFPOWERUP_40MS 0x05 217ec96690dSMiquel Raynal #define AIC32X4_REFPOWERUP_80MS 0x06 218ec96690dSMiquel Raynal #define AIC32X4_REFPOWERUP_120MS 0x07 219ec96690dSMiquel Raynal 220a51b5006SAnnaliese McDermond /* Common mask and enable for all of the dividers */ 221a51b5006SAnnaliese McDermond #define AIC32X4_DIVEN BIT(7) 222a51b5006SAnnaliese McDermond #define AIC32X4_DIV_MASK GENMASK(6, 0) 223a51b5006SAnnaliese McDermond 224514b044cSAnnaliese McDermond /* Clock Limits */ 22596c3bb00SAnnaliese McDermond #define AIC32X4_MAX_DOSR_FREQ 6200000 22696c3bb00SAnnaliese McDermond #define AIC32X4_MIN_DOSR_FREQ 2800000 22796c3bb00SAnnaliese McDermond #define AIC32X4_MAX_CODEC_CLKIN_FREQ 110000000 228514b044cSAnnaliese McDermond #define AIC32X4_MAX_PLL_CLKIN 20000000 229514b044cSAnnaliese McDermond 2301d471cd1SJavier Martin #endif /* _TLV320AIC32X4_H */ 231