xref: /openbmc/linux/sound/soc/codecs/tlv320aic32x4.h (revision 1714196c)
11d471cd1SJavier Martin /*
21d471cd1SJavier Martin  * tlv320aic32x4.h
31d471cd1SJavier Martin  *
41d471cd1SJavier Martin  * This program is free software; you can redistribute it and/or modify
51d471cd1SJavier Martin  * it under the terms of the GNU General Public License version 2 as
61d471cd1SJavier Martin  * published by the Free Software Foundation.
71d471cd1SJavier Martin  */
81d471cd1SJavier Martin 
91d471cd1SJavier Martin 
101d471cd1SJavier Martin #ifndef _TLV320AIC32X4_H
111d471cd1SJavier Martin #define _TLV320AIC32X4_H
121d471cd1SJavier Martin 
133bcfd222SJeremy McDermond struct device;
143bcfd222SJeremy McDermond struct regmap_config;
153bcfd222SJeremy McDermond 
163bcfd222SJeremy McDermond extern const struct regmap_config aic32x4_regmap_config;
173bcfd222SJeremy McDermond int aic32x4_probe(struct device *dev, struct regmap *regmap);
183bcfd222SJeremy McDermond int aic32x4_remove(struct device *dev);
193bcfd222SJeremy McDermond 
201d471cd1SJavier Martin /* tlv320aic32x4 register space (in decimal to match datasheet) */
211d471cd1SJavier Martin 
221714196cSAndrew F. Davis #define AIC32X4_REG(page, reg)	((page * 128) + reg)
231d471cd1SJavier Martin 
241714196cSAndrew F. Davis #define	AIC32X4_PSEL		AIC32X4_REG(0, 0)
251714196cSAndrew F. Davis 
261714196cSAndrew F. Davis #define	AIC32X4_RESET		AIC32X4_REG(0, 1)
271714196cSAndrew F. Davis #define	AIC32X4_CLKMUX		AIC32X4_REG(0, 4)
281714196cSAndrew F. Davis #define	AIC32X4_PLLPR		AIC32X4_REG(0, 5)
291714196cSAndrew F. Davis #define	AIC32X4_PLLJ		AIC32X4_REG(0, 6)
301714196cSAndrew F. Davis #define	AIC32X4_PLLDMSB		AIC32X4_REG(0, 7)
311714196cSAndrew F. Davis #define	AIC32X4_PLLDLSB		AIC32X4_REG(0, 8)
321714196cSAndrew F. Davis #define	AIC32X4_NDAC		AIC32X4_REG(0, 11)
331714196cSAndrew F. Davis #define	AIC32X4_MDAC		AIC32X4_REG(0, 12)
341714196cSAndrew F. Davis #define AIC32X4_DOSRMSB		AIC32X4_REG(0, 13)
351714196cSAndrew F. Davis #define AIC32X4_DOSRLSB		AIC32X4_REG(0, 14)
361714196cSAndrew F. Davis #define	AIC32X4_NADC		AIC32X4_REG(0, 18)
371714196cSAndrew F. Davis #define	AIC32X4_MADC		AIC32X4_REG(0, 19)
381714196cSAndrew F. Davis #define AIC32X4_AOSR		AIC32X4_REG(0, 20)
391714196cSAndrew F. Davis #define AIC32X4_CLKMUX2		AIC32X4_REG(0, 25)
401714196cSAndrew F. Davis #define AIC32X4_CLKOUTM		AIC32X4_REG(0, 26)
411714196cSAndrew F. Davis #define AIC32X4_IFACE1		AIC32X4_REG(0, 27)
421714196cSAndrew F. Davis #define AIC32X4_IFACE2		AIC32X4_REG(0, 28)
431714196cSAndrew F. Davis #define AIC32X4_IFACE3		AIC32X4_REG(0, 29)
441714196cSAndrew F. Davis #define AIC32X4_BCLKN		AIC32X4_REG(0, 30)
451714196cSAndrew F. Davis #define AIC32X4_IFACE4		AIC32X4_REG(0, 31)
461714196cSAndrew F. Davis #define AIC32X4_IFACE5		AIC32X4_REG(0, 32)
471714196cSAndrew F. Davis #define AIC32X4_IFACE6		AIC32X4_REG(0, 33)
481714196cSAndrew F. Davis #define AIC32X4_GPIOCTL		AIC32X4_REG(0, 52)
491714196cSAndrew F. Davis #define AIC32X4_DOUTCTL		AIC32X4_REG(0, 53)
501714196cSAndrew F. Davis #define AIC32X4_DINCTL		AIC32X4_REG(0, 54)
511714196cSAndrew F. Davis #define AIC32X4_MISOCTL		AIC32X4_REG(0, 55)
521714196cSAndrew F. Davis #define AIC32X4_SCLKCTL		AIC32X4_REG(0, 56)
531714196cSAndrew F. Davis #define AIC32X4_DACSPB		AIC32X4_REG(0, 60)
541714196cSAndrew F. Davis #define AIC32X4_ADCSPB		AIC32X4_REG(0, 61)
551714196cSAndrew F. Davis #define AIC32X4_DACSETUP	AIC32X4_REG(0, 63)
561714196cSAndrew F. Davis #define AIC32X4_DACMUTE		AIC32X4_REG(0, 64)
571714196cSAndrew F. Davis #define AIC32X4_LDACVOL		AIC32X4_REG(0, 65)
581714196cSAndrew F. Davis #define AIC32X4_RDACVOL		AIC32X4_REG(0, 66)
591714196cSAndrew F. Davis #define AIC32X4_ADCSETUP	AIC32X4_REG(0, 81)
601714196cSAndrew F. Davis #define	AIC32X4_ADCFGA		AIC32X4_REG(0, 82)
611714196cSAndrew F. Davis #define AIC32X4_LADCVOL		AIC32X4_REG(0, 83)
621714196cSAndrew F. Davis #define AIC32X4_RADCVOL		AIC32X4_REG(0, 84)
631714196cSAndrew F. Davis #define AIC32X4_LAGC1		AIC32X4_REG(0, 86)
641714196cSAndrew F. Davis #define AIC32X4_LAGC2		AIC32X4_REG(0, 87)
651714196cSAndrew F. Davis #define AIC32X4_LAGC3		AIC32X4_REG(0, 88)
661714196cSAndrew F. Davis #define AIC32X4_LAGC4		AIC32X4_REG(0, 89)
671714196cSAndrew F. Davis #define AIC32X4_LAGC5		AIC32X4_REG(0, 90)
681714196cSAndrew F. Davis #define AIC32X4_LAGC6		AIC32X4_REG(0, 91)
691714196cSAndrew F. Davis #define AIC32X4_LAGC7		AIC32X4_REG(0, 92)
701714196cSAndrew F. Davis #define AIC32X4_RAGC1		AIC32X4_REG(0, 94)
711714196cSAndrew F. Davis #define AIC32X4_RAGC2		AIC32X4_REG(0, 95)
721714196cSAndrew F. Davis #define AIC32X4_RAGC3		AIC32X4_REG(0, 96)
731714196cSAndrew F. Davis #define AIC32X4_RAGC4		AIC32X4_REG(0, 97)
741714196cSAndrew F. Davis #define AIC32X4_RAGC5		AIC32X4_REG(0, 98)
751714196cSAndrew F. Davis #define AIC32X4_RAGC6		AIC32X4_REG(0, 99)
761714196cSAndrew F. Davis #define AIC32X4_RAGC7		AIC32X4_REG(0, 100)
771714196cSAndrew F. Davis 
781714196cSAndrew F. Davis #define AIC32X4_PWRCFG		AIC32X4_REG(1, 1)
791714196cSAndrew F. Davis #define AIC32X4_LDOCTL		AIC32X4_REG(1, 2)
801714196cSAndrew F. Davis #define AIC32X4_OUTPWRCTL	AIC32X4_REG(1, 9)
811714196cSAndrew F. Davis #define AIC32X4_CMMODE		AIC32X4_REG(1, 10)
821714196cSAndrew F. Davis #define AIC32X4_HPLROUTE	AIC32X4_REG(1, 12)
831714196cSAndrew F. Davis #define AIC32X4_HPRROUTE	AIC32X4_REG(1, 13)
841714196cSAndrew F. Davis #define AIC32X4_LOLROUTE	AIC32X4_REG(1, 14)
851714196cSAndrew F. Davis #define AIC32X4_LORROUTE	AIC32X4_REG(1, 15)
861714196cSAndrew F. Davis #define	AIC32X4_HPLGAIN		AIC32X4_REG(1, 16)
871714196cSAndrew F. Davis #define	AIC32X4_HPRGAIN		AIC32X4_REG(1, 17)
881714196cSAndrew F. Davis #define	AIC32X4_LOLGAIN		AIC32X4_REG(1, 18)
891714196cSAndrew F. Davis #define	AIC32X4_LORGAIN		AIC32X4_REG(1, 19)
901714196cSAndrew F. Davis #define AIC32X4_HEADSTART	AIC32X4_REG(1, 20)
911714196cSAndrew F. Davis #define AIC32X4_MICBIAS		AIC32X4_REG(1, 51)
921714196cSAndrew F. Davis #define AIC32X4_LMICPGAPIN	AIC32X4_REG(1, 52)
931714196cSAndrew F. Davis #define AIC32X4_LMICPGANIN	AIC32X4_REG(1, 54)
941714196cSAndrew F. Davis #define AIC32X4_RMICPGAPIN	AIC32X4_REG(1, 55)
951714196cSAndrew F. Davis #define AIC32X4_RMICPGANIN	AIC32X4_REG(1, 57)
961714196cSAndrew F. Davis #define AIC32X4_FLOATINGINPUT	AIC32X4_REG(1, 58)
971714196cSAndrew F. Davis #define AIC32X4_LMICPGAVOL	AIC32X4_REG(1, 59)
981714196cSAndrew F. Davis #define AIC32X4_RMICPGAVOL	AIC32X4_REG(1, 60)
991d471cd1SJavier Martin 
1001d471cd1SJavier Martin #define AIC32X4_FREQ_12000000 12000000
1011d471cd1SJavier Martin #define AIC32X4_FREQ_24000000 24000000
1021d471cd1SJavier Martin #define AIC32X4_FREQ_25000000 25000000
1031d471cd1SJavier Martin 
1041d471cd1SJavier Martin #define AIC32X4_WORD_LEN_16BITS		0x00
1051d471cd1SJavier Martin #define AIC32X4_WORD_LEN_20BITS		0x01
1061d471cd1SJavier Martin #define AIC32X4_WORD_LEN_24BITS		0x02
1071d471cd1SJavier Martin #define AIC32X4_WORD_LEN_32BITS		0x03
1081d471cd1SJavier Martin 
109a405387cSJavier Martin #define AIC32X4_LADC_EN			(1 << 7)
110a405387cSJavier Martin #define AIC32X4_RADC_EN			(1 << 6)
111a405387cSJavier Martin 
1121d471cd1SJavier Martin #define AIC32X4_I2S_MODE		0x00
1131d471cd1SJavier Martin #define AIC32X4_DSP_MODE		0x01
1141d471cd1SJavier Martin #define AIC32X4_RIGHT_JUSTIFIED_MODE	0x02
1151d471cd1SJavier Martin #define AIC32X4_LEFT_JUSTIFIED_MODE	0x03
1161d471cd1SJavier Martin 
1171d471cd1SJavier Martin #define AIC32X4_AVDDWEAKDISABLE		0x08
1181d471cd1SJavier Martin #define AIC32X4_LDOCTLEN		0x01
1191d471cd1SJavier Martin 
1201d471cd1SJavier Martin #define AIC32X4_LDOIN_18_36		0x01
1211d471cd1SJavier Martin #define AIC32X4_LDOIN2HP		0x02
1221d471cd1SJavier Martin 
1231d471cd1SJavier Martin #define AIC32X4_DACSPBLOCK_MASK		0x1f
1241d471cd1SJavier Martin #define AIC32X4_ADCSPBLOCK_MASK		0x1f
1251d471cd1SJavier Martin 
1261d471cd1SJavier Martin #define AIC32X4_PLLJ_SHIFT		6
1271d471cd1SJavier Martin #define AIC32X4_DOSRMSB_SHIFT		4
1281d471cd1SJavier Martin 
1291d471cd1SJavier Martin #define AIC32X4_PLLCLKIN		0x03
1301d471cd1SJavier Martin 
1311d471cd1SJavier Martin #define AIC32X4_MICBIAS_LDOIN		0x08
1321d471cd1SJavier Martin #define AIC32X4_MICBIAS_2075V		0x60
1331d471cd1SJavier Martin 
1341d471cd1SJavier Martin #define AIC32X4_LMICPGANIN_IN2R_10K	0x10
135609e6025SMarkus Pargmann #define AIC32X4_LMICPGANIN_CM1L_10K	0x40
1361d471cd1SJavier Martin #define AIC32X4_RMICPGANIN_IN1L_10K	0x10
137609e6025SMarkus Pargmann #define AIC32X4_RMICPGANIN_CM1R_10K	0x40
1381d471cd1SJavier Martin 
1391d471cd1SJavier Martin #define AIC32X4_LMICPGAVOL_NOGAIN	0x80
1401d471cd1SJavier Martin #define AIC32X4_RMICPGAVOL_NOGAIN	0x80
1411d471cd1SJavier Martin 
1421d471cd1SJavier Martin #define AIC32X4_BCLKMASTER		0x08
1431d471cd1SJavier Martin #define AIC32X4_WCLKMASTER		0x04
1441d471cd1SJavier Martin #define AIC32X4_PLLEN			(0x01 << 7)
1451d471cd1SJavier Martin #define AIC32X4_NDACEN			(0x01 << 7)
1461d471cd1SJavier Martin #define AIC32X4_MDACEN			(0x01 << 7)
1471d471cd1SJavier Martin #define AIC32X4_NADCEN			(0x01 << 7)
1481d471cd1SJavier Martin #define AIC32X4_MADCEN			(0x01 << 7)
1491d471cd1SJavier Martin #define AIC32X4_BCLKEN			(0x01 << 7)
1501d471cd1SJavier Martin #define AIC32X4_DACEN			(0x03 << 6)
1511d471cd1SJavier Martin #define AIC32X4_RDAC2LCHN		(0x02 << 2)
1521d471cd1SJavier Martin #define AIC32X4_LDAC2RCHN		(0x02 << 4)
1531d471cd1SJavier Martin #define AIC32X4_LDAC2LCHN		(0x01 << 4)
1541d471cd1SJavier Martin #define AIC32X4_RDAC2RCHN		(0x01 << 2)
155b44aa40fSMarkus Pargmann #define AIC32X4_DAC_CHAN_MASK		0x3c
1561d471cd1SJavier Martin 
1571d471cd1SJavier Martin #define AIC32X4_SSTEP2WCLK		0x01
1581d471cd1SJavier Martin #define AIC32X4_MUTEON			0x0C
1591d471cd1SJavier Martin #define	AIC32X4_DACMOD2BCLK		0x01
1601d471cd1SJavier Martin 
1611d471cd1SJavier Martin #endif				/* _TLV320AIC32X4_H */
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