1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 21d471cd1SJavier Martin /* 31d471cd1SJavier Martin * tlv320aic32x4.h 41d471cd1SJavier Martin */ 51d471cd1SJavier Martin 61d471cd1SJavier Martin 71d471cd1SJavier Martin #ifndef _TLV320AIC32X4_H 81d471cd1SJavier Martin #define _TLV320AIC32X4_H 91d471cd1SJavier Martin 103bcfd222SJeremy McDermond struct device; 113bcfd222SJeremy McDermond struct regmap_config; 123bcfd222SJeremy McDermond 13688d47cdSClaudius Heine enum aic32x4_type { 14688d47cdSClaudius Heine AIC32X4_TYPE_AIC32X4 = 0, 15688d47cdSClaudius Heine AIC32X4_TYPE_AIC32X6, 16b4525b61SClaudius Heine AIC32X4_TYPE_TAS2505, 17688d47cdSClaudius Heine }; 18688d47cdSClaudius Heine 193bcfd222SJeremy McDermond extern const struct regmap_config aic32x4_regmap_config; 203bcfd222SJeremy McDermond int aic32x4_probe(struct device *dev, struct regmap *regmap); 210f884099SUwe Kleine-König void aic32x4_remove(struct device *dev); 22514b044cSAnnaliese McDermond int aic32x4_register_clocks(struct device *dev, const char *mclk_name); 233bcfd222SJeremy McDermond 241d471cd1SJavier Martin /* tlv320aic32x4 register space (in decimal to match datasheet) */ 251d471cd1SJavier Martin 261714196cSAndrew F. Davis #define AIC32X4_REG(page, reg) ((page * 128) + reg) 271d471cd1SJavier Martin 281714196cSAndrew F. Davis #define AIC32X4_PSEL AIC32X4_REG(0, 0) 291714196cSAndrew F. Davis 301714196cSAndrew F. Davis #define AIC32X4_RESET AIC32X4_REG(0, 1) 311714196cSAndrew F. Davis #define AIC32X4_CLKMUX AIC32X4_REG(0, 4) 321714196cSAndrew F. Davis #define AIC32X4_PLLPR AIC32X4_REG(0, 5) 331714196cSAndrew F. Davis #define AIC32X4_PLLJ AIC32X4_REG(0, 6) 341714196cSAndrew F. Davis #define AIC32X4_PLLDMSB AIC32X4_REG(0, 7) 351714196cSAndrew F. Davis #define AIC32X4_PLLDLSB AIC32X4_REG(0, 8) 361714196cSAndrew F. Davis #define AIC32X4_NDAC AIC32X4_REG(0, 11) 371714196cSAndrew F. Davis #define AIC32X4_MDAC AIC32X4_REG(0, 12) 381714196cSAndrew F. Davis #define AIC32X4_DOSRMSB AIC32X4_REG(0, 13) 391714196cSAndrew F. Davis #define AIC32X4_DOSRLSB AIC32X4_REG(0, 14) 401714196cSAndrew F. Davis #define AIC32X4_NADC AIC32X4_REG(0, 18) 411714196cSAndrew F. Davis #define AIC32X4_MADC AIC32X4_REG(0, 19) 421714196cSAndrew F. Davis #define AIC32X4_AOSR AIC32X4_REG(0, 20) 431714196cSAndrew F. Davis #define AIC32X4_CLKMUX2 AIC32X4_REG(0, 25) 441714196cSAndrew F. Davis #define AIC32X4_CLKOUTM AIC32X4_REG(0, 26) 451714196cSAndrew F. Davis #define AIC32X4_IFACE1 AIC32X4_REG(0, 27) 461714196cSAndrew F. Davis #define AIC32X4_IFACE2 AIC32X4_REG(0, 28) 471714196cSAndrew F. Davis #define AIC32X4_IFACE3 AIC32X4_REG(0, 29) 481714196cSAndrew F. Davis #define AIC32X4_BCLKN AIC32X4_REG(0, 30) 491714196cSAndrew F. Davis #define AIC32X4_IFACE4 AIC32X4_REG(0, 31) 501714196cSAndrew F. Davis #define AIC32X4_IFACE5 AIC32X4_REG(0, 32) 511714196cSAndrew F. Davis #define AIC32X4_IFACE6 AIC32X4_REG(0, 33) 521714196cSAndrew F. Davis #define AIC32X4_GPIOCTL AIC32X4_REG(0, 52) 531714196cSAndrew F. Davis #define AIC32X4_DOUTCTL AIC32X4_REG(0, 53) 541714196cSAndrew F. Davis #define AIC32X4_DINCTL AIC32X4_REG(0, 54) 551714196cSAndrew F. Davis #define AIC32X4_MISOCTL AIC32X4_REG(0, 55) 561714196cSAndrew F. Davis #define AIC32X4_SCLKCTL AIC32X4_REG(0, 56) 571714196cSAndrew F. Davis #define AIC32X4_DACSPB AIC32X4_REG(0, 60) 581714196cSAndrew F. Davis #define AIC32X4_ADCSPB AIC32X4_REG(0, 61) 591714196cSAndrew F. Davis #define AIC32X4_DACSETUP AIC32X4_REG(0, 63) 601714196cSAndrew F. Davis #define AIC32X4_DACMUTE AIC32X4_REG(0, 64) 611714196cSAndrew F. Davis #define AIC32X4_LDACVOL AIC32X4_REG(0, 65) 621714196cSAndrew F. Davis #define AIC32X4_RDACVOL AIC32X4_REG(0, 66) 631714196cSAndrew F. Davis #define AIC32X4_ADCSETUP AIC32X4_REG(0, 81) 641714196cSAndrew F. Davis #define AIC32X4_ADCFGA AIC32X4_REG(0, 82) 651714196cSAndrew F. Davis #define AIC32X4_LADCVOL AIC32X4_REG(0, 83) 661714196cSAndrew F. Davis #define AIC32X4_RADCVOL AIC32X4_REG(0, 84) 671714196cSAndrew F. Davis #define AIC32X4_LAGC1 AIC32X4_REG(0, 86) 681714196cSAndrew F. Davis #define AIC32X4_LAGC2 AIC32X4_REG(0, 87) 691714196cSAndrew F. Davis #define AIC32X4_LAGC3 AIC32X4_REG(0, 88) 701714196cSAndrew F. Davis #define AIC32X4_LAGC4 AIC32X4_REG(0, 89) 711714196cSAndrew F. Davis #define AIC32X4_LAGC5 AIC32X4_REG(0, 90) 721714196cSAndrew F. Davis #define AIC32X4_LAGC6 AIC32X4_REG(0, 91) 731714196cSAndrew F. Davis #define AIC32X4_LAGC7 AIC32X4_REG(0, 92) 741714196cSAndrew F. Davis #define AIC32X4_RAGC1 AIC32X4_REG(0, 94) 751714196cSAndrew F. Davis #define AIC32X4_RAGC2 AIC32X4_REG(0, 95) 761714196cSAndrew F. Davis #define AIC32X4_RAGC3 AIC32X4_REG(0, 96) 771714196cSAndrew F. Davis #define AIC32X4_RAGC4 AIC32X4_REG(0, 97) 781714196cSAndrew F. Davis #define AIC32X4_RAGC5 AIC32X4_REG(0, 98) 791714196cSAndrew F. Davis #define AIC32X4_RAGC6 AIC32X4_REG(0, 99) 801714196cSAndrew F. Davis #define AIC32X4_RAGC7 AIC32X4_REG(0, 100) 811714196cSAndrew F. Davis 821714196cSAndrew F. Davis #define AIC32X4_PWRCFG AIC32X4_REG(1, 1) 831714196cSAndrew F. Davis #define AIC32X4_LDOCTL AIC32X4_REG(1, 2) 84d3e6e374SAnnaliese McDermond #define AIC32X4_LPLAYBACK AIC32X4_REG(1, 3) 85d3e6e374SAnnaliese McDermond #define AIC32X4_RPLAYBACK AIC32X4_REG(1, 4) 861714196cSAndrew F. Davis #define AIC32X4_OUTPWRCTL AIC32X4_REG(1, 9) 871714196cSAndrew F. Davis #define AIC32X4_CMMODE AIC32X4_REG(1, 10) 881714196cSAndrew F. Davis #define AIC32X4_HPLROUTE AIC32X4_REG(1, 12) 891714196cSAndrew F. Davis #define AIC32X4_HPRROUTE AIC32X4_REG(1, 13) 901714196cSAndrew F. Davis #define AIC32X4_LOLROUTE AIC32X4_REG(1, 14) 911714196cSAndrew F. Davis #define AIC32X4_LORROUTE AIC32X4_REG(1, 15) 921714196cSAndrew F. Davis #define AIC32X4_HPLGAIN AIC32X4_REG(1, 16) 931714196cSAndrew F. Davis #define AIC32X4_HPRGAIN AIC32X4_REG(1, 17) 941714196cSAndrew F. Davis #define AIC32X4_LOLGAIN AIC32X4_REG(1, 18) 951714196cSAndrew F. Davis #define AIC32X4_LORGAIN AIC32X4_REG(1, 19) 961714196cSAndrew F. Davis #define AIC32X4_HEADSTART AIC32X4_REG(1, 20) 97b4525b61SClaudius Heine #define TAS2505_SPK AIC32X4_REG(1, 45) 98b4525b61SClaudius Heine #define TAS2505_SPKVOL1 AIC32X4_REG(1, 46) 99b4525b61SClaudius Heine #define TAS2505_SPKVOL2 AIC32X4_REG(1, 48) 1001714196cSAndrew F. Davis #define AIC32X4_MICBIAS AIC32X4_REG(1, 51) 1011714196cSAndrew F. Davis #define AIC32X4_LMICPGAPIN AIC32X4_REG(1, 52) 1021714196cSAndrew F. Davis #define AIC32X4_LMICPGANIN AIC32X4_REG(1, 54) 1031714196cSAndrew F. Davis #define AIC32X4_RMICPGAPIN AIC32X4_REG(1, 55) 1041714196cSAndrew F. Davis #define AIC32X4_RMICPGANIN AIC32X4_REG(1, 57) 1051714196cSAndrew F. Davis #define AIC32X4_FLOATINGINPUT AIC32X4_REG(1, 58) 1061714196cSAndrew F. Davis #define AIC32X4_LMICPGAVOL AIC32X4_REG(1, 59) 1071714196cSAndrew F. Davis #define AIC32X4_RMICPGAVOL AIC32X4_REG(1, 60) 108b4525b61SClaudius Heine #define TAS2505_REFPOWERUP AIC32X4_REG(1, 122) 109ec96690dSMiquel Raynal #define AIC32X4_REFPOWERUP AIC32X4_REG(1, 123) 1101d471cd1SJavier Martin 1110fe7aa39SAndrew F. Davis /* Bits, masks, and shifts */ 1121d471cd1SJavier Martin 1130fe7aa39SAndrew F. Davis /* AIC32X4_CLKMUX */ 1140fe7aa39SAndrew F. Davis #define AIC32X4_PLL_CLKIN_MASK GENMASK(3, 2) 1150fe7aa39SAndrew F. Davis #define AIC32X4_PLL_CLKIN_SHIFT (2) 1160fe7aa39SAndrew F. Davis #define AIC32X4_PLL_CLKIN_MCLK (0x00) 1170fe7aa39SAndrew F. Davis #define AIC32X4_PLL_CLKIN_BCKL (0x01) 1180fe7aa39SAndrew F. Davis #define AIC32X4_PLL_CLKIN_GPIO1 (0x02) 1190fe7aa39SAndrew F. Davis #define AIC32X4_PLL_CLKIN_DIN (0x03) 1200fe7aa39SAndrew F. Davis #define AIC32X4_CODEC_CLKIN_MASK GENMASK(1, 0) 1210fe7aa39SAndrew F. Davis #define AIC32X4_CODEC_CLKIN_SHIFT (0) 1220fe7aa39SAndrew F. Davis #define AIC32X4_CODEC_CLKIN_MCLK (0x00) 1230fe7aa39SAndrew F. Davis #define AIC32X4_CODEC_CLKIN_BCLK (0x01) 1240fe7aa39SAndrew F. Davis #define AIC32X4_CODEC_CLKIN_GPIO1 (0x02) 1250fe7aa39SAndrew F. Davis #define AIC32X4_CODEC_CLKIN_PLL (0x03) 126a405387cSJavier Martin 1270fe7aa39SAndrew F. Davis /* AIC32X4_PLLPR */ 1280fe7aa39SAndrew F. Davis #define AIC32X4_PLLEN BIT(7) 12964aab899SAndrew F. Davis #define AIC32X4_PLL_P_MASK GENMASK(6, 4) 13064aab899SAndrew F. Davis #define AIC32X4_PLL_P_SHIFT (4) 13164aab899SAndrew F. Davis #define AIC32X4_PLL_R_MASK GENMASK(3, 0) 1321d471cd1SJavier Martin 1330fe7aa39SAndrew F. Davis /* AIC32X4_NDAC */ 1340fe7aa39SAndrew F. Davis #define AIC32X4_NDACEN BIT(7) 13564aab899SAndrew F. Davis #define AIC32X4_NDAC_MASK GENMASK(6, 0) 1361d471cd1SJavier Martin 1370fe7aa39SAndrew F. Davis /* AIC32X4_MDAC */ 1380fe7aa39SAndrew F. Davis #define AIC32X4_MDACEN BIT(7) 13964aab899SAndrew F. Davis #define AIC32X4_MDAC_MASK GENMASK(6, 0) 1401d471cd1SJavier Martin 1410fe7aa39SAndrew F. Davis /* AIC32X4_NADC */ 1420fe7aa39SAndrew F. Davis #define AIC32X4_NADCEN BIT(7) 14364aab899SAndrew F. Davis #define AIC32X4_NADC_MASK GENMASK(6, 0) 1441d471cd1SJavier Martin 1450fe7aa39SAndrew F. Davis /* AIC32X4_MADC */ 1460fe7aa39SAndrew F. Davis #define AIC32X4_MADCEN BIT(7) 14764aab899SAndrew F. Davis #define AIC32X4_MADC_MASK GENMASK(6, 0) 1481d471cd1SJavier Martin 1490fe7aa39SAndrew F. Davis /* AIC32X4_BCLKN */ 1500fe7aa39SAndrew F. Davis #define AIC32X4_BCLKEN BIT(7) 15164aab899SAndrew F. Davis #define AIC32X4_BCLK_MASK GENMASK(6, 0) 1521d471cd1SJavier Martin 1530fe7aa39SAndrew F. Davis /* AIC32X4_IFACE1 */ 1540fe7aa39SAndrew F. Davis #define AIC32X4_IFACE1_DATATYPE_MASK GENMASK(7, 6) 1550fe7aa39SAndrew F. Davis #define AIC32X4_IFACE1_DATATYPE_SHIFT (6) 1560fe7aa39SAndrew F. Davis #define AIC32X4_I2S_MODE (0x00) 1570fe7aa39SAndrew F. Davis #define AIC32X4_DSP_MODE (0x01) 1580fe7aa39SAndrew F. Davis #define AIC32X4_RIGHT_JUSTIFIED_MODE (0x02) 1590fe7aa39SAndrew F. Davis #define AIC32X4_LEFT_JUSTIFIED_MODE (0x03) 1600fe7aa39SAndrew F. Davis #define AIC32X4_IFACE1_DATALEN_MASK GENMASK(5, 4) 1610fe7aa39SAndrew F. Davis #define AIC32X4_IFACE1_DATALEN_SHIFT (4) 1620fe7aa39SAndrew F. Davis #define AIC32X4_WORD_LEN_16BITS (0x00) 1630fe7aa39SAndrew F. Davis #define AIC32X4_WORD_LEN_20BITS (0x01) 1640fe7aa39SAndrew F. Davis #define AIC32X4_WORD_LEN_24BITS (0x02) 1650fe7aa39SAndrew F. Davis #define AIC32X4_WORD_LEN_32BITS (0x03) 1660fe7aa39SAndrew F. Davis #define AIC32X4_IFACE1_MASTER_MASK GENMASK(3, 2) 1670fe7aa39SAndrew F. Davis #define AIC32X4_BCLKMASTER BIT(2) 1680fe7aa39SAndrew F. Davis #define AIC32X4_WCLKMASTER BIT(3) 1690fe7aa39SAndrew F. Davis 1700fe7aa39SAndrew F. Davis /* AIC32X4_IFACE2 */ 1710fe7aa39SAndrew F. Davis #define AIC32X4_DATA_OFFSET_MASK GENMASK(7, 0) 1720fe7aa39SAndrew F. Davis 1730fe7aa39SAndrew F. Davis /* AIC32X4_IFACE3 */ 1740fe7aa39SAndrew F. Davis #define AIC32X4_BCLKINV_MASK BIT(3) 1750fe7aa39SAndrew F. Davis #define AIC32X4_BDIVCLK_MASK GENMASK(1, 0) 1760fe7aa39SAndrew F. Davis #define AIC32X4_BDIVCLK_SHIFT (0) 1770fe7aa39SAndrew F. Davis #define AIC32X4_DAC2BCLK (0x00) 1780fe7aa39SAndrew F. Davis #define AIC32X4_DACMOD2BCLK (0x01) 1790fe7aa39SAndrew F. Davis #define AIC32X4_ADC2BCLK (0x02) 1800fe7aa39SAndrew F. Davis #define AIC32X4_ADCMOD2BCLK (0x03) 1810fe7aa39SAndrew F. Davis 1820fe7aa39SAndrew F. Davis /* AIC32X4_DACSETUP */ 1830fe7aa39SAndrew F. Davis #define AIC32X4_DAC_CHAN_MASK GENMASK(5, 2) 1840fe7aa39SAndrew F. Davis #define AIC32X4_LDAC2RCHN BIT(5) 1850fe7aa39SAndrew F. Davis #define AIC32X4_LDAC2LCHN BIT(4) 1860fe7aa39SAndrew F. Davis #define AIC32X4_RDAC2LCHN BIT(3) 1870fe7aa39SAndrew F. Davis #define AIC32X4_RDAC2RCHN BIT(2) 1880fe7aa39SAndrew F. Davis 1890fe7aa39SAndrew F. Davis /* AIC32X4_DACMUTE */ 1900fe7aa39SAndrew F. Davis #define AIC32X4_MUTEON 0x0C 1910fe7aa39SAndrew F. Davis 1920fe7aa39SAndrew F. Davis /* AIC32X4_ADCSETUP */ 1930fe7aa39SAndrew F. Davis #define AIC32X4_LADC_EN BIT(7) 1940fe7aa39SAndrew F. Davis #define AIC32X4_RADC_EN BIT(6) 1950fe7aa39SAndrew F. Davis 1960fe7aa39SAndrew F. Davis /* AIC32X4_PWRCFG */ 1970fe7aa39SAndrew F. Davis #define AIC32X4_AVDDWEAKDISABLE BIT(3) 1980fe7aa39SAndrew F. Davis 1990fe7aa39SAndrew F. Davis /* AIC32X4_LDOCTL */ 2000fe7aa39SAndrew F. Davis #define AIC32X4_LDOCTLEN BIT(0) 2010fe7aa39SAndrew F. Davis 2020fe7aa39SAndrew F. Davis /* AIC32X4_CMMODE */ 2030fe7aa39SAndrew F. Davis #define AIC32X4_LDOIN_18_36 BIT(0) 2040fe7aa39SAndrew F. Davis #define AIC32X4_LDOIN2HP BIT(1) 2050fe7aa39SAndrew F. Davis 2060fe7aa39SAndrew F. Davis /* AIC32X4_MICBIAS */ 2070fe7aa39SAndrew F. Davis #define AIC32X4_MICBIAS_LDOIN BIT(3) 2081d471cd1SJavier Martin #define AIC32X4_MICBIAS_2075V 0x60 20904d979d7Sb-ak #define AIC32x4_MICBIAS_MASK GENMASK(6, 3) 2101d471cd1SJavier Martin 2110fe7aa39SAndrew F. Davis /* AIC32X4_LMICPGANIN */ 2121d471cd1SJavier Martin #define AIC32X4_LMICPGANIN_IN2R_10K 0x10 213609e6025SMarkus Pargmann #define AIC32X4_LMICPGANIN_CM1L_10K 0x40 2140fe7aa39SAndrew F. Davis 2150fe7aa39SAndrew F. Davis /* AIC32X4_RMICPGANIN */ 2161d471cd1SJavier Martin #define AIC32X4_RMICPGANIN_IN1L_10K 0x10 217609e6025SMarkus Pargmann #define AIC32X4_RMICPGANIN_CM1R_10K 0x40 2181d471cd1SJavier Martin 219ec96690dSMiquel Raynal /* AIC32X4_REFPOWERUP */ 220ec96690dSMiquel Raynal #define AIC32X4_REFPOWERUP_SLOW 0x04 221ec96690dSMiquel Raynal #define AIC32X4_REFPOWERUP_40MS 0x05 222ec96690dSMiquel Raynal #define AIC32X4_REFPOWERUP_80MS 0x06 223ec96690dSMiquel Raynal #define AIC32X4_REFPOWERUP_120MS 0x07 224ec96690dSMiquel Raynal 225a51b5006SAnnaliese McDermond /* Common mask and enable for all of the dividers */ 226a51b5006SAnnaliese McDermond #define AIC32X4_DIVEN BIT(7) 227a51b5006SAnnaliese McDermond #define AIC32X4_DIV_MASK GENMASK(6, 0) 228*11e756ccSGuiting Shen #define AIC32X4_DIV_MAX 128 229a51b5006SAnnaliese McDermond 230514b044cSAnnaliese McDermond /* Clock Limits */ 23196c3bb00SAnnaliese McDermond #define AIC32X4_MAX_DOSR_FREQ 6200000 23296c3bb00SAnnaliese McDermond #define AIC32X4_MIN_DOSR_FREQ 2800000 23396c3bb00SAnnaliese McDermond #define AIC32X4_MAX_CODEC_CLKIN_FREQ 110000000 234514b044cSAnnaliese McDermond #define AIC32X4_MAX_PLL_CLKIN 20000000 235514b044cSAnnaliese McDermond 2361d471cd1SJavier Martin #endif /* _TLV320AIC32X4_H */ 237