1 /* 2 * linux/sound/soc/codecs/tlv320aic32x4.c 3 * 4 * Copyright 2011 Vista Silicon S.L. 5 * 6 * Author: Javier Martin <javier.martin@vista-silicon.com> 7 * 8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 23 * MA 02110-1301, USA. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/moduleparam.h> 28 #include <linux/init.h> 29 #include <linux/delay.h> 30 #include <linux/pm.h> 31 #include <linux/gpio.h> 32 #include <linux/i2c.h> 33 #include <linux/cdev.h> 34 #include <linux/slab.h> 35 36 #include <sound/tlv320aic32x4.h> 37 #include <sound/core.h> 38 #include <sound/pcm.h> 39 #include <sound/pcm_params.h> 40 #include <sound/soc.h> 41 #include <sound/soc-dapm.h> 42 #include <sound/initval.h> 43 #include <sound/tlv.h> 44 45 #include "tlv320aic32x4.h" 46 47 struct aic32x4_rate_divs { 48 u32 mclk; 49 u32 rate; 50 u8 p_val; 51 u8 pll_j; 52 u16 pll_d; 53 u16 dosr; 54 u8 ndac; 55 u8 mdac; 56 u8 aosr; 57 u8 nadc; 58 u8 madc; 59 u8 blck_N; 60 }; 61 62 struct aic32x4_priv { 63 u32 sysclk; 64 u8 page_no; 65 void *control_data; 66 u32 power_cfg; 67 u32 micpga_routing; 68 bool swapdacs; 69 int rstn_gpio; 70 }; 71 72 /* 0dB min, 1dB steps */ 73 static DECLARE_TLV_DB_SCALE(tlv_step_1, 0, 100, 0); 74 /* 0dB min, 0.5dB steps */ 75 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 76 77 static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 78 SOC_DOUBLE_R_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 79 AIC32X4_RDACVOL, 0, 0x30, 0, tlv_step_0_5), 80 SOC_DOUBLE_R_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 81 AIC32X4_HPRGAIN, 0, 0x1D, 0, tlv_step_1), 82 SOC_DOUBLE_R_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 83 AIC32X4_LORGAIN, 0, 0x1D, 0, tlv_step_1), 84 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 85 AIC32X4_HPRGAIN, 6, 0x01, 1), 86 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 87 AIC32X4_LORGAIN, 6, 0x01, 1), 88 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 89 AIC32X4_RMICPGAVOL, 7, 0x01, 1), 90 91 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 92 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 93 94 SOC_DOUBLE_R_TLV("ADC Level Volume", AIC32X4_LADCVOL, 95 AIC32X4_RADCVOL, 0, 0x28, 0, tlv_step_0_5), 96 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 97 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 98 99 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 100 101 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 102 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 103 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 104 4, 0x07, 0), 105 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 106 0, 0x03, 0), 107 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 108 6, 0x03, 0), 109 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 110 1, 0x1F, 0), 111 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 112 0, 0x7F, 0), 113 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 114 3, 0x1F, 0), 115 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 116 3, 0x1F, 0), 117 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 118 0, 0x1F, 0), 119 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 120 0, 0x0F, 0), 121 }; 122 123 static const struct aic32x4_rate_divs aic32x4_divs[] = { 124 /* 8k rate */ 125 {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24}, 126 {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24}, 127 {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24}, 128 /* 11.025k rate */ 129 {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16}, 130 {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16}, 131 /* 16k rate */ 132 {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12}, 133 {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12}, 134 {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12}, 135 /* 22.05k rate */ 136 {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8}, 137 {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8}, 138 {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8}, 139 /* 32k rate */ 140 {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6}, 141 {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6}, 142 /* 44.1k rate */ 143 {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4}, 144 {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4}, 145 {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4}, 146 /* 48k rate */ 147 {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4}, 148 {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4}, 149 {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4} 150 }; 151 152 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 153 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 154 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 155 }; 156 157 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 158 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 159 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 160 }; 161 162 static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 163 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 164 }; 165 166 static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 167 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 168 }; 169 170 static const struct snd_kcontrol_new left_input_mixer_controls[] = { 171 SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0), 172 SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0), 173 SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0), 174 }; 175 176 static const struct snd_kcontrol_new right_input_mixer_controls[] = { 177 SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0), 178 SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0), 179 SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0), 180 }; 181 182 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 183 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 184 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 185 &hpl_output_mixer_controls[0], 186 ARRAY_SIZE(hpl_output_mixer_controls)), 187 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 188 189 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 190 &lol_output_mixer_controls[0], 191 ARRAY_SIZE(lol_output_mixer_controls)), 192 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 193 194 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 195 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 196 &hpr_output_mixer_controls[0], 197 ARRAY_SIZE(hpr_output_mixer_controls)), 198 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 199 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 200 &lor_output_mixer_controls[0], 201 ARRAY_SIZE(lor_output_mixer_controls)), 202 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 203 SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0, 204 &left_input_mixer_controls[0], 205 ARRAY_SIZE(left_input_mixer_controls)), 206 SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0, 207 &right_input_mixer_controls[0], 208 ARRAY_SIZE(right_input_mixer_controls)), 209 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 210 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 211 SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0), 212 213 SND_SOC_DAPM_OUTPUT("HPL"), 214 SND_SOC_DAPM_OUTPUT("HPR"), 215 SND_SOC_DAPM_OUTPUT("LOL"), 216 SND_SOC_DAPM_OUTPUT("LOR"), 217 SND_SOC_DAPM_INPUT("IN1_L"), 218 SND_SOC_DAPM_INPUT("IN1_R"), 219 SND_SOC_DAPM_INPUT("IN2_L"), 220 SND_SOC_DAPM_INPUT("IN2_R"), 221 SND_SOC_DAPM_INPUT("IN3_L"), 222 SND_SOC_DAPM_INPUT("IN3_R"), 223 }; 224 225 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 226 /* Left Output */ 227 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 228 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 229 230 {"HPL Power", NULL, "HPL Output Mixer"}, 231 {"HPL", NULL, "HPL Power"}, 232 233 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 234 235 {"LOL Power", NULL, "LOL Output Mixer"}, 236 {"LOL", NULL, "LOL Power"}, 237 238 /* Right Output */ 239 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 240 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 241 242 {"HPR Power", NULL, "HPR Output Mixer"}, 243 {"HPR", NULL, "HPR Power"}, 244 245 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 246 247 {"LOR Power", NULL, "LOR Output Mixer"}, 248 {"LOR", NULL, "LOR Power"}, 249 250 /* Left input */ 251 {"Left Input Mixer", "IN1_L P Switch", "IN1_L"}, 252 {"Left Input Mixer", "IN2_L P Switch", "IN2_L"}, 253 {"Left Input Mixer", "IN3_L P Switch", "IN3_L"}, 254 255 {"Left ADC", NULL, "Left Input Mixer"}, 256 257 /* Right Input */ 258 {"Right Input Mixer", "IN1_R P Switch", "IN1_R"}, 259 {"Right Input Mixer", "IN2_R P Switch", "IN2_R"}, 260 {"Right Input Mixer", "IN3_R P Switch", "IN3_R"}, 261 262 {"Right ADC", NULL, "Right Input Mixer"}, 263 }; 264 265 static inline int aic32x4_change_page(struct snd_soc_codec *codec, 266 unsigned int new_page) 267 { 268 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 269 u8 data[2]; 270 int ret; 271 272 data[0] = 0x00; 273 data[1] = new_page & 0xff; 274 275 ret = codec->hw_write(codec->control_data, data, 2); 276 if (ret == 2) { 277 aic32x4->page_no = new_page; 278 return 0; 279 } else { 280 return ret; 281 } 282 } 283 284 static int aic32x4_write(struct snd_soc_codec *codec, unsigned int reg, 285 unsigned int val) 286 { 287 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 288 unsigned int page = reg / 128; 289 unsigned int fixed_reg = reg % 128; 290 u8 data[2]; 291 int ret; 292 293 /* A write to AIC32X4_PSEL is really a non-explicit page change */ 294 if (reg == AIC32X4_PSEL) 295 return aic32x4_change_page(codec, val); 296 297 if (aic32x4->page_no != page) { 298 ret = aic32x4_change_page(codec, page); 299 if (ret != 0) 300 return ret; 301 } 302 303 data[0] = fixed_reg & 0xff; 304 data[1] = val & 0xff; 305 306 if (codec->hw_write(codec->control_data, data, 2) == 2) 307 return 0; 308 else 309 return -EIO; 310 } 311 312 static unsigned int aic32x4_read(struct snd_soc_codec *codec, unsigned int reg) 313 { 314 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 315 unsigned int page = reg / 128; 316 unsigned int fixed_reg = reg % 128; 317 int ret; 318 319 if (aic32x4->page_no != page) { 320 ret = aic32x4_change_page(codec, page); 321 if (ret != 0) 322 return ret; 323 } 324 return i2c_smbus_read_byte_data(codec->control_data, fixed_reg & 0xff); 325 } 326 327 static inline int aic32x4_get_divs(int mclk, int rate) 328 { 329 int i; 330 331 for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) { 332 if ((aic32x4_divs[i].rate == rate) 333 && (aic32x4_divs[i].mclk == mclk)) { 334 return i; 335 } 336 } 337 printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n"); 338 return -EINVAL; 339 } 340 341 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 342 int clk_id, unsigned int freq, int dir) 343 { 344 struct snd_soc_codec *codec = codec_dai->codec; 345 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 346 347 switch (freq) { 348 case AIC32X4_FREQ_12000000: 349 case AIC32X4_FREQ_24000000: 350 case AIC32X4_FREQ_25000000: 351 aic32x4->sysclk = freq; 352 return 0; 353 } 354 printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n"); 355 return -EINVAL; 356 } 357 358 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 359 { 360 struct snd_soc_codec *codec = codec_dai->codec; 361 u8 iface_reg_1; 362 u8 iface_reg_2; 363 u8 iface_reg_3; 364 365 iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1); 366 iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2); 367 iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2); 368 iface_reg_2 = 0; 369 iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3); 370 iface_reg_3 = iface_reg_3 & ~(1 << 3); 371 372 /* set master/slave audio interface */ 373 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 374 case SND_SOC_DAIFMT_CBM_CFM: 375 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 376 break; 377 case SND_SOC_DAIFMT_CBS_CFS: 378 break; 379 default: 380 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 381 return -EINVAL; 382 } 383 384 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 385 case SND_SOC_DAIFMT_I2S: 386 break; 387 case SND_SOC_DAIFMT_DSP_A: 388 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT); 389 iface_reg_3 |= (1 << 3); /* invert bit clock */ 390 iface_reg_2 = 0x01; /* add offset 1 */ 391 break; 392 case SND_SOC_DAIFMT_DSP_B: 393 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT); 394 iface_reg_3 |= (1 << 3); /* invert bit clock */ 395 break; 396 case SND_SOC_DAIFMT_RIGHT_J: 397 iface_reg_1 |= 398 (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT); 399 break; 400 case SND_SOC_DAIFMT_LEFT_J: 401 iface_reg_1 |= 402 (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT); 403 break; 404 default: 405 printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 406 return -EINVAL; 407 } 408 409 snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1); 410 snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2); 411 snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3); 412 return 0; 413 } 414 415 static int aic32x4_hw_params(struct snd_pcm_substream *substream, 416 struct snd_pcm_hw_params *params, 417 struct snd_soc_dai *dai) 418 { 419 struct snd_soc_codec *codec = dai->codec; 420 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 421 u8 data; 422 int i; 423 424 i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params)); 425 if (i < 0) { 426 printk(KERN_ERR "aic32x4: sampling rate not supported\n"); 427 return i; 428 } 429 430 /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */ 431 snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN); 432 snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK); 433 434 /* We will fix R value to 1 and will make P & J=K.D as varialble */ 435 data = snd_soc_read(codec, AIC32X4_PLLPR); 436 data &= ~(7 << 4); 437 snd_soc_write(codec, AIC32X4_PLLPR, 438 (data | (aic32x4_divs[i].p_val << 4) | 0x01)); 439 440 snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j); 441 442 snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8)); 443 snd_soc_write(codec, AIC32X4_PLLDLSB, 444 (aic32x4_divs[i].pll_d & 0xff)); 445 446 /* NDAC divider value */ 447 data = snd_soc_read(codec, AIC32X4_NDAC); 448 data &= ~(0x7f); 449 snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac); 450 451 /* MDAC divider value */ 452 data = snd_soc_read(codec, AIC32X4_MDAC); 453 data &= ~(0x7f); 454 snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac); 455 456 /* DOSR MSB & LSB values */ 457 snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); 458 snd_soc_write(codec, AIC32X4_DOSRLSB, 459 (aic32x4_divs[i].dosr & 0xff)); 460 461 /* NADC divider value */ 462 data = snd_soc_read(codec, AIC32X4_NADC); 463 data &= ~(0x7f); 464 snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc); 465 466 /* MADC divider value */ 467 data = snd_soc_read(codec, AIC32X4_MADC); 468 data &= ~(0x7f); 469 snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc); 470 471 /* AOSR value */ 472 snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr); 473 474 /* BCLK N divider */ 475 data = snd_soc_read(codec, AIC32X4_BCLKN); 476 data &= ~(0x7f); 477 snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N); 478 479 data = snd_soc_read(codec, AIC32X4_IFACE1); 480 data = data & ~(3 << 4); 481 switch (params_format(params)) { 482 case SNDRV_PCM_FORMAT_S16_LE: 483 break; 484 case SNDRV_PCM_FORMAT_S20_3LE: 485 data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT); 486 break; 487 case SNDRV_PCM_FORMAT_S24_LE: 488 data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT); 489 break; 490 case SNDRV_PCM_FORMAT_S32_LE: 491 data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT); 492 break; 493 } 494 snd_soc_write(codec, AIC32X4_IFACE1, data); 495 496 return 0; 497 } 498 499 static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 500 { 501 struct snd_soc_codec *codec = dai->codec; 502 u8 dac_reg; 503 504 dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON; 505 if (mute) 506 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON); 507 else 508 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg); 509 return 0; 510 } 511 512 static int aic32x4_set_bias_level(struct snd_soc_codec *codec, 513 enum snd_soc_bias_level level) 514 { 515 switch (level) { 516 case SND_SOC_BIAS_ON: 517 /* Switch on PLL */ 518 snd_soc_update_bits(codec, AIC32X4_PLLPR, 519 AIC32X4_PLLEN, AIC32X4_PLLEN); 520 521 /* Switch on NDAC Divider */ 522 snd_soc_update_bits(codec, AIC32X4_NDAC, 523 AIC32X4_NDACEN, AIC32X4_NDACEN); 524 525 /* Switch on MDAC Divider */ 526 snd_soc_update_bits(codec, AIC32X4_MDAC, 527 AIC32X4_MDACEN, AIC32X4_MDACEN); 528 529 /* Switch on NADC Divider */ 530 snd_soc_update_bits(codec, AIC32X4_NADC, 531 AIC32X4_NADCEN, AIC32X4_NADCEN); 532 533 /* Switch on MADC Divider */ 534 snd_soc_update_bits(codec, AIC32X4_MADC, 535 AIC32X4_MADCEN, AIC32X4_MADCEN); 536 537 /* Switch on BCLK_N Divider */ 538 snd_soc_update_bits(codec, AIC32X4_BCLKN, 539 AIC32X4_BCLKEN, AIC32X4_BCLKEN); 540 break; 541 case SND_SOC_BIAS_PREPARE: 542 break; 543 case SND_SOC_BIAS_STANDBY: 544 /* Switch off PLL */ 545 snd_soc_update_bits(codec, AIC32X4_PLLPR, 546 AIC32X4_PLLEN, 0); 547 548 /* Switch off NDAC Divider */ 549 snd_soc_update_bits(codec, AIC32X4_NDAC, 550 AIC32X4_NDACEN, 0); 551 552 /* Switch off MDAC Divider */ 553 snd_soc_update_bits(codec, AIC32X4_MDAC, 554 AIC32X4_MDACEN, 0); 555 556 /* Switch off NADC Divider */ 557 snd_soc_update_bits(codec, AIC32X4_NADC, 558 AIC32X4_NADCEN, 0); 559 560 /* Switch off MADC Divider */ 561 snd_soc_update_bits(codec, AIC32X4_MADC, 562 AIC32X4_MADCEN, 0); 563 564 /* Switch off BCLK_N Divider */ 565 snd_soc_update_bits(codec, AIC32X4_BCLKN, 566 AIC32X4_BCLKEN, 0); 567 break; 568 case SND_SOC_BIAS_OFF: 569 break; 570 } 571 codec->dapm.bias_level = level; 572 return 0; 573 } 574 575 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_48000 576 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 577 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 578 579 static const struct snd_soc_dai_ops aic32x4_ops = { 580 .hw_params = aic32x4_hw_params, 581 .digital_mute = aic32x4_mute, 582 .set_fmt = aic32x4_set_dai_fmt, 583 .set_sysclk = aic32x4_set_dai_sysclk, 584 }; 585 586 static struct snd_soc_dai_driver aic32x4_dai = { 587 .name = "tlv320aic32x4-hifi", 588 .playback = { 589 .stream_name = "Playback", 590 .channels_min = 1, 591 .channels_max = 2, 592 .rates = AIC32X4_RATES, 593 .formats = AIC32X4_FORMATS,}, 594 .capture = { 595 .stream_name = "Capture", 596 .channels_min = 1, 597 .channels_max = 2, 598 .rates = AIC32X4_RATES, 599 .formats = AIC32X4_FORMATS,}, 600 .ops = &aic32x4_ops, 601 .symmetric_rates = 1, 602 }; 603 604 static int aic32x4_suspend(struct snd_soc_codec *codec) 605 { 606 aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF); 607 return 0; 608 } 609 610 static int aic32x4_resume(struct snd_soc_codec *codec) 611 { 612 aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 613 return 0; 614 } 615 616 static int aic32x4_probe(struct snd_soc_codec *codec) 617 { 618 struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec); 619 u32 tmp_reg; 620 int ret; 621 622 codec->hw_write = (hw_write_t) i2c_master_send; 623 codec->control_data = aic32x4->control_data; 624 625 if (aic32x4->rstn_gpio >= 0) { 626 ret = devm_gpio_request_one(codec->dev, aic32x4->rstn_gpio, 627 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 628 if (ret != 0) 629 return ret; 630 ndelay(10); 631 gpio_set_value(aic32x4->rstn_gpio, 1); 632 } 633 634 snd_soc_write(codec, AIC32X4_RESET, 0x01); 635 636 /* Power platform configuration */ 637 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 638 snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN | 639 AIC32X4_MICBIAS_2075V); 640 } 641 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) { 642 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 643 } 644 645 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 646 AIC32X4_LDOCTLEN : 0; 647 snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg); 648 649 tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE); 650 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) { 651 tmp_reg |= AIC32X4_LDOIN_18_36; 652 } 653 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) { 654 tmp_reg |= AIC32X4_LDOIN2HP; 655 } 656 snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg); 657 658 /* Do DACs need to be swapped? */ 659 if (aic32x4->swapdacs) { 660 snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2RCHN | AIC32X4_RDAC2LCHN); 661 } else { 662 snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN); 663 } 664 665 /* Mic PGA routing */ 666 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) { 667 snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K); 668 } 669 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) { 670 snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K); 671 } 672 673 aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 674 675 /* 676 * Workaround: for an unknown reason, the ADC needs to be powered up 677 * and down for the first capture to work properly. It seems related to 678 * a HW BUG or some kind of behavior not documented in the datasheet. 679 */ 680 tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP); 681 snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg | 682 AIC32X4_LADC_EN | AIC32X4_RADC_EN); 683 snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg); 684 685 return 0; 686 } 687 688 static int aic32x4_remove(struct snd_soc_codec *codec) 689 { 690 aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF); 691 return 0; 692 } 693 694 static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = { 695 .read = aic32x4_read, 696 .write = aic32x4_write, 697 .probe = aic32x4_probe, 698 .remove = aic32x4_remove, 699 .suspend = aic32x4_suspend, 700 .resume = aic32x4_resume, 701 .set_bias_level = aic32x4_set_bias_level, 702 703 .controls = aic32x4_snd_controls, 704 .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 705 .dapm_widgets = aic32x4_dapm_widgets, 706 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 707 .dapm_routes = aic32x4_dapm_routes, 708 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 709 }; 710 711 static int aic32x4_i2c_probe(struct i2c_client *i2c, 712 const struct i2c_device_id *id) 713 { 714 struct aic32x4_pdata *pdata = i2c->dev.platform_data; 715 struct aic32x4_priv *aic32x4; 716 int ret; 717 718 aic32x4 = devm_kzalloc(&i2c->dev, sizeof(struct aic32x4_priv), 719 GFP_KERNEL); 720 if (aic32x4 == NULL) 721 return -ENOMEM; 722 723 aic32x4->control_data = i2c; 724 i2c_set_clientdata(i2c, aic32x4); 725 726 if (pdata) { 727 aic32x4->power_cfg = pdata->power_cfg; 728 aic32x4->swapdacs = pdata->swapdacs; 729 aic32x4->micpga_routing = pdata->micpga_routing; 730 aic32x4->rstn_gpio = pdata->rstn_gpio; 731 } else { 732 aic32x4->power_cfg = 0; 733 aic32x4->swapdacs = false; 734 aic32x4->micpga_routing = 0; 735 aic32x4->rstn_gpio = -1; 736 } 737 738 ret = snd_soc_register_codec(&i2c->dev, 739 &soc_codec_dev_aic32x4, &aic32x4_dai, 1); 740 return ret; 741 } 742 743 static int aic32x4_i2c_remove(struct i2c_client *client) 744 { 745 snd_soc_unregister_codec(&client->dev); 746 return 0; 747 } 748 749 static const struct i2c_device_id aic32x4_i2c_id[] = { 750 { "tlv320aic32x4", 0 }, 751 { } 752 }; 753 MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id); 754 755 static struct i2c_driver aic32x4_i2c_driver = { 756 .driver = { 757 .name = "tlv320aic32x4", 758 .owner = THIS_MODULE, 759 }, 760 .probe = aic32x4_i2c_probe, 761 .remove = aic32x4_i2c_remove, 762 .id_table = aic32x4_i2c_id, 763 }; 764 765 module_i2c_driver(aic32x4_i2c_driver); 766 767 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 768 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 769 MODULE_LICENSE("GPL"); 770