1 /* 2 * linux/sound/soc/codecs/tlv320aic32x4.c 3 * 4 * Copyright 2011 Vista Silicon S.L. 5 * 6 * Author: Javier Martin <javier.martin@vista-silicon.com> 7 * 8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 23 * MA 02110-1301, USA. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/moduleparam.h> 28 #include <linux/init.h> 29 #include <linux/delay.h> 30 #include <linux/pm.h> 31 #include <linux/gpio.h> 32 #include <linux/of_gpio.h> 33 #include <linux/cdev.h> 34 #include <linux/slab.h> 35 #include <linux/clk.h> 36 #include <linux/regulator/consumer.h> 37 38 #include <sound/tlv320aic32x4.h> 39 #include <sound/core.h> 40 #include <sound/pcm.h> 41 #include <sound/pcm_params.h> 42 #include <sound/soc.h> 43 #include <sound/soc-dapm.h> 44 #include <sound/initval.h> 45 #include <sound/tlv.h> 46 47 #include "tlv320aic32x4.h" 48 49 struct aic32x4_rate_divs { 50 u32 mclk; 51 u32 rate; 52 u8 p_val; 53 u8 pll_j; 54 u16 pll_d; 55 u16 dosr; 56 u8 ndac; 57 u8 mdac; 58 u8 aosr; 59 u8 nadc; 60 u8 madc; 61 u8 blck_N; 62 }; 63 64 struct aic32x4_priv { 65 struct regmap *regmap; 66 u32 sysclk; 67 u32 power_cfg; 68 u32 micpga_routing; 69 bool swapdacs; 70 int rstn_gpio; 71 struct clk *mclk; 72 73 struct regulator *supply_ldo; 74 struct regulator *supply_iov; 75 struct regulator *supply_dv; 76 struct regulator *supply_av; 77 78 struct aic32x4_setup_data *setup; 79 struct device *dev; 80 }; 81 82 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol, 83 struct snd_ctl_elem_value *ucontrol) 84 { 85 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 86 u8 val; 87 88 val = snd_soc_component_read32(component, AIC32X4_DINCTL); 89 90 ucontrol->value.integer.value[0] = (val & 0x01); 91 92 return 0; 93 }; 94 95 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol, 96 struct snd_ctl_elem_value *ucontrol) 97 { 98 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 99 u8 val; 100 u8 gpio_check; 101 102 val = snd_soc_component_read32(component, AIC32X4_DOUTCTL); 103 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 104 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 105 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n", 106 __func__); 107 return -EINVAL; 108 } 109 110 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH)) 111 return 0; 112 113 if (ucontrol->value.integer.value[0]) 114 val |= ucontrol->value.integer.value[0]; 115 else 116 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH; 117 118 snd_soc_component_write(component, AIC32X4_DOUTCTL, val); 119 120 return 0; 121 }; 122 123 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol, 124 struct snd_ctl_elem_value *ucontrol) 125 { 126 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 127 u8 val; 128 129 val = snd_soc_component_read32(component, AIC32X4_SCLKCTL); 130 131 ucontrol->value.integer.value[0] = (val & 0x01); 132 133 return 0; 134 }; 135 136 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol, 137 struct snd_ctl_elem_value *ucontrol) 138 { 139 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 140 u8 val; 141 u8 gpio_check; 142 143 val = snd_soc_component_read32(component, AIC32X4_MISOCTL); 144 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 145 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 146 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n", 147 __func__); 148 return -EINVAL; 149 } 150 151 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH)) 152 return 0; 153 154 if (ucontrol->value.integer.value[0]) 155 val |= ucontrol->value.integer.value[0]; 156 else 157 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH; 158 159 snd_soc_component_write(component, AIC32X4_MISOCTL, val); 160 161 return 0; 162 }; 163 164 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol, 165 struct snd_ctl_elem_value *ucontrol) 166 { 167 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 168 u8 val; 169 170 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 171 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1); 172 173 return 0; 174 }; 175 176 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol, 177 struct snd_ctl_elem_value *ucontrol) 178 { 179 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 180 u8 val; 181 u8 gpio_check; 182 183 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 184 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT); 185 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) { 186 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n", 187 __func__); 188 return -EINVAL; 189 } 190 191 if (ucontrol->value.integer.value[0] == (val & 0x1)) 192 return 0; 193 194 if (ucontrol->value.integer.value[0]) 195 val |= ucontrol->value.integer.value[0]; 196 else 197 val &= 0xfe; 198 199 snd_soc_component_write(component, AIC32X4_GPIOCTL, val); 200 201 return 0; 202 }; 203 204 static const struct snd_kcontrol_new aic32x4_mfp1[] = { 205 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL), 206 }; 207 208 static const struct snd_kcontrol_new aic32x4_mfp2[] = { 209 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio), 210 }; 211 212 static const struct snd_kcontrol_new aic32x4_mfp3[] = { 213 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL), 214 }; 215 216 static const struct snd_kcontrol_new aic32x4_mfp4[] = { 217 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio), 218 }; 219 220 static const struct snd_kcontrol_new aic32x4_mfp5[] = { 221 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio, 222 aic32x4_set_mfp5_gpio), 223 }; 224 225 /* 0dB min, 0.5dB steps */ 226 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 227 /* -63.5dB min, 0.5dB steps */ 228 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0); 229 /* -6dB min, 1dB steps */ 230 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0); 231 /* -12dB min, 0.5dB steps */ 232 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0); 233 234 static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 235 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 236 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm), 237 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 238 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, 239 tlv_driver_gain), 240 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 241 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, 242 tlv_driver_gain), 243 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 244 AIC32X4_HPRGAIN, 6, 0x01, 1), 245 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 246 AIC32X4_LORGAIN, 6, 0x01, 1), 247 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 248 AIC32X4_RMICPGAVOL, 7, 0x01, 1), 249 250 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 251 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 252 253 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL, 254 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol), 255 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 256 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 257 258 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 259 260 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 261 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 262 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 263 4, 0x07, 0), 264 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 265 0, 0x03, 0), 266 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 267 6, 0x03, 0), 268 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 269 1, 0x1F, 0), 270 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 271 0, 0x7F, 0), 272 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 273 3, 0x1F, 0), 274 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 275 3, 0x1F, 0), 276 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 277 0, 0x1F, 0), 278 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 279 0, 0x0F, 0), 280 }; 281 282 static const struct aic32x4_rate_divs aic32x4_divs[] = { 283 /* 8k rate */ 284 {12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24}, 285 {24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24}, 286 {25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24}, 287 /* 11.025k rate */ 288 {12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16}, 289 {24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16}, 290 /* 16k rate */ 291 {12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12}, 292 {24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12}, 293 {25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12}, 294 /* 22.05k rate */ 295 {12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8}, 296 {24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8}, 297 {25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8}, 298 /* 32k rate */ 299 {12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6}, 300 {24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6}, 301 /* 44.1k rate */ 302 {12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4}, 303 {24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4}, 304 {25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4}, 305 /* 48k rate */ 306 {12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4}, 307 {24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4}, 308 {25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}, 309 310 /* 96k rate */ 311 {25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1}, 312 }; 313 314 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 315 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 316 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 317 }; 318 319 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 320 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 321 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 322 }; 323 324 static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 325 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 326 }; 327 328 static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 329 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 330 }; 331 332 static const char * const resistor_text[] = { 333 "Off", "10 kOhm", "20 kOhm", "40 kOhm", 334 }; 335 336 /* Left mixer pins */ 337 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text); 338 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text); 339 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text); 340 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text); 341 342 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text); 343 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text); 344 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text); 345 346 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = { 347 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum), 348 }; 349 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = { 350 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum), 351 }; 352 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = { 353 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum), 354 }; 355 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = { 356 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum), 357 }; 358 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = { 359 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum), 360 }; 361 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = { 362 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum), 363 }; 364 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = { 365 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum), 366 }; 367 368 /* Right mixer pins */ 369 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text); 370 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text); 371 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text); 372 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text); 373 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text); 374 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text); 375 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text); 376 377 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = { 378 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum), 379 }; 380 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = { 381 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum), 382 }; 383 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = { 384 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum), 385 }; 386 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = { 387 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum), 388 }; 389 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = { 390 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum), 391 }; 392 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = { 393 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum), 394 }; 395 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = { 396 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum), 397 }; 398 399 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 400 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 401 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 402 &hpl_output_mixer_controls[0], 403 ARRAY_SIZE(hpl_output_mixer_controls)), 404 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 405 406 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 407 &lol_output_mixer_controls[0], 408 ARRAY_SIZE(lol_output_mixer_controls)), 409 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 410 411 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 412 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 413 &hpr_output_mixer_controls[0], 414 ARRAY_SIZE(hpr_output_mixer_controls)), 415 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 416 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 417 &lor_output_mixer_controls[0], 418 ARRAY_SIZE(lor_output_mixer_controls)), 419 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 420 421 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 422 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 423 in1r_to_rmixer_controls), 424 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 425 in2r_to_rmixer_controls), 426 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 427 in3r_to_rmixer_controls), 428 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 429 in2l_to_rmixer_controls), 430 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 431 cmr_to_rmixer_controls), 432 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 433 in1l_to_rmixer_controls), 434 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 435 in3l_to_rmixer_controls), 436 437 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 438 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 439 in1l_to_lmixer_controls), 440 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 441 in2l_to_lmixer_controls), 442 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 443 in3l_to_lmixer_controls), 444 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 445 in1r_to_lmixer_controls), 446 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 447 cml_to_lmixer_controls), 448 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 449 in2r_to_lmixer_controls), 450 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 451 in3r_to_lmixer_controls), 452 453 SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0), 454 455 SND_SOC_DAPM_OUTPUT("HPL"), 456 SND_SOC_DAPM_OUTPUT("HPR"), 457 SND_SOC_DAPM_OUTPUT("LOL"), 458 SND_SOC_DAPM_OUTPUT("LOR"), 459 SND_SOC_DAPM_INPUT("IN1_L"), 460 SND_SOC_DAPM_INPUT("IN1_R"), 461 SND_SOC_DAPM_INPUT("IN2_L"), 462 SND_SOC_DAPM_INPUT("IN2_R"), 463 SND_SOC_DAPM_INPUT("IN3_L"), 464 SND_SOC_DAPM_INPUT("IN3_R"), 465 }; 466 467 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 468 /* Left Output */ 469 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 470 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 471 472 {"HPL Power", NULL, "HPL Output Mixer"}, 473 {"HPL", NULL, "HPL Power"}, 474 475 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 476 477 {"LOL Power", NULL, "LOL Output Mixer"}, 478 {"LOL", NULL, "LOL Power"}, 479 480 /* Right Output */ 481 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 482 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 483 484 {"HPR Power", NULL, "HPR Output Mixer"}, 485 {"HPR", NULL, "HPR Power"}, 486 487 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 488 489 {"LOR Power", NULL, "LOR Output Mixer"}, 490 {"LOR", NULL, "LOR Power"}, 491 492 /* Right Input */ 493 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"}, 494 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 495 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 496 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 497 498 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"}, 499 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"}, 500 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"}, 501 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"}, 502 503 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"}, 504 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"}, 505 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"}, 506 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"}, 507 508 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"}, 509 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 510 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 511 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 512 513 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"}, 514 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"}, 515 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"}, 516 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"}, 517 518 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"}, 519 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"}, 520 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"}, 521 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"}, 522 523 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"}, 524 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"}, 525 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"}, 526 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"}, 527 528 /* Left Input */ 529 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"}, 530 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"}, 531 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"}, 532 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"}, 533 534 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"}, 535 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 536 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 537 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 538 539 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"}, 540 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"}, 541 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"}, 542 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"}, 543 544 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"}, 545 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 546 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 547 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 548 549 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"}, 550 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"}, 551 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"}, 552 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"}, 553 554 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"}, 555 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"}, 556 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"}, 557 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"}, 558 559 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"}, 560 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"}, 561 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"}, 562 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"}, 563 }; 564 565 static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 566 { 567 .selector_reg = 0, 568 .selector_mask = 0xff, 569 .window_start = 0, 570 .window_len = 128, 571 .range_min = 0, 572 .range_max = AIC32X4_RMICPGAVOL, 573 }, 574 }; 575 576 const struct regmap_config aic32x4_regmap_config = { 577 .max_register = AIC32X4_RMICPGAVOL, 578 .ranges = aic32x4_regmap_pages, 579 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 580 }; 581 EXPORT_SYMBOL(aic32x4_regmap_config); 582 583 static inline int aic32x4_get_divs(int mclk, int rate) 584 { 585 int i; 586 587 for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) { 588 if ((aic32x4_divs[i].rate == rate) 589 && (aic32x4_divs[i].mclk == mclk)) { 590 return i; 591 } 592 } 593 printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n"); 594 return -EINVAL; 595 } 596 597 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 598 int clk_id, unsigned int freq, int dir) 599 { 600 struct snd_soc_component *component = codec_dai->component; 601 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 602 603 switch (freq) { 604 case 12000000: 605 case 24000000: 606 case 25000000: 607 aic32x4->sysclk = freq; 608 return 0; 609 } 610 printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n"); 611 return -EINVAL; 612 } 613 614 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 615 { 616 struct snd_soc_component *component = codec_dai->component; 617 u8 iface_reg_1 = 0; 618 u8 iface_reg_2 = 0; 619 u8 iface_reg_3 = 0; 620 621 /* set master/slave audio interface */ 622 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 623 case SND_SOC_DAIFMT_CBM_CFM: 624 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 625 break; 626 case SND_SOC_DAIFMT_CBS_CFS: 627 break; 628 default: 629 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 630 return -EINVAL; 631 } 632 633 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 634 case SND_SOC_DAIFMT_I2S: 635 break; 636 case SND_SOC_DAIFMT_DSP_A: 637 iface_reg_1 |= (AIC32X4_DSP_MODE << 638 AIC32X4_IFACE1_DATATYPE_SHIFT); 639 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 640 iface_reg_2 = 0x01; /* add offset 1 */ 641 break; 642 case SND_SOC_DAIFMT_DSP_B: 643 iface_reg_1 |= (AIC32X4_DSP_MODE << 644 AIC32X4_IFACE1_DATATYPE_SHIFT); 645 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 646 break; 647 case SND_SOC_DAIFMT_RIGHT_J: 648 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE << 649 AIC32X4_IFACE1_DATATYPE_SHIFT); 650 break; 651 case SND_SOC_DAIFMT_LEFT_J: 652 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE << 653 AIC32X4_IFACE1_DATATYPE_SHIFT); 654 break; 655 default: 656 printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 657 return -EINVAL; 658 } 659 660 snd_soc_component_update_bits(component, AIC32X4_IFACE1, 661 AIC32X4_IFACE1_DATATYPE_MASK | 662 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1); 663 snd_soc_component_update_bits(component, AIC32X4_IFACE2, 664 AIC32X4_DATA_OFFSET_MASK, iface_reg_2); 665 snd_soc_component_update_bits(component, AIC32X4_IFACE3, 666 AIC32X4_BCLKINV_MASK, iface_reg_3); 667 668 return 0; 669 } 670 671 static int aic32x4_hw_params(struct snd_pcm_substream *substream, 672 struct snd_pcm_hw_params *params, 673 struct snd_soc_dai *dai) 674 { 675 struct snd_soc_component *component = dai->component; 676 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 677 u8 iface1_reg = 0; 678 u8 dacsetup_reg = 0; 679 int i; 680 681 i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params)); 682 if (i < 0) { 683 printk(KERN_ERR "aic32x4: sampling rate not supported\n"); 684 return i; 685 } 686 687 /* MCLK as PLL_CLKIN */ 688 snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_PLL_CLKIN_MASK, 689 AIC32X4_PLL_CLKIN_MCLK << AIC32X4_PLL_CLKIN_SHIFT); 690 /* PLL as CODEC_CLKIN */ 691 snd_soc_component_update_bits(component, AIC32X4_CLKMUX, AIC32X4_CODEC_CLKIN_MASK, 692 AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT); 693 /* DAC_MOD_CLK as BDIV_CLKIN */ 694 snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK, 695 AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT); 696 697 /* We will fix R value to 1 and will make P & J=K.D as variable */ 698 snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_R_MASK, 0x01); 699 700 /* PLL P value */ 701 snd_soc_component_update_bits(component, AIC32X4_PLLPR, AIC32X4_PLL_P_MASK, 702 aic32x4_divs[i].p_val << AIC32X4_PLL_P_SHIFT); 703 704 /* PLL J value */ 705 snd_soc_component_write(component, AIC32X4_PLLJ, aic32x4_divs[i].pll_j); 706 707 /* PLL D value */ 708 snd_soc_component_write(component, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8)); 709 snd_soc_component_write(component, AIC32X4_PLLDLSB, (aic32x4_divs[i].pll_d & 0xff)); 710 711 /* NDAC divider value */ 712 snd_soc_component_update_bits(component, AIC32X4_NDAC, 713 AIC32X4_NDAC_MASK, aic32x4_divs[i].ndac); 714 715 /* MDAC divider value */ 716 snd_soc_component_update_bits(component, AIC32X4_MDAC, 717 AIC32X4_MDAC_MASK, aic32x4_divs[i].mdac); 718 719 /* DOSR MSB & LSB values */ 720 snd_soc_component_write(component, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8); 721 snd_soc_component_write(component, AIC32X4_DOSRLSB, (aic32x4_divs[i].dosr & 0xff)); 722 723 /* NADC divider value */ 724 snd_soc_component_update_bits(component, AIC32X4_NADC, 725 AIC32X4_NADC_MASK, aic32x4_divs[i].nadc); 726 727 /* MADC divider value */ 728 snd_soc_component_update_bits(component, AIC32X4_MADC, 729 AIC32X4_MADC_MASK, aic32x4_divs[i].madc); 730 731 /* AOSR value */ 732 snd_soc_component_write(component, AIC32X4_AOSR, aic32x4_divs[i].aosr); 733 734 /* BCLK N divider */ 735 snd_soc_component_update_bits(component, AIC32X4_BCLKN, 736 AIC32X4_BCLK_MASK, aic32x4_divs[i].blck_N); 737 738 switch (params_width(params)) { 739 case 16: 740 iface1_reg |= (AIC32X4_WORD_LEN_16BITS << 741 AIC32X4_IFACE1_DATALEN_SHIFT); 742 break; 743 case 20: 744 iface1_reg |= (AIC32X4_WORD_LEN_20BITS << 745 AIC32X4_IFACE1_DATALEN_SHIFT); 746 break; 747 case 24: 748 iface1_reg |= (AIC32X4_WORD_LEN_24BITS << 749 AIC32X4_IFACE1_DATALEN_SHIFT); 750 break; 751 case 32: 752 iface1_reg |= (AIC32X4_WORD_LEN_32BITS << 753 AIC32X4_IFACE1_DATALEN_SHIFT); 754 break; 755 } 756 snd_soc_component_update_bits(component, AIC32X4_IFACE1, 757 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg); 758 759 if (params_channels(params) == 1) { 760 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 761 } else { 762 if (aic32x4->swapdacs) 763 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 764 else 765 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 766 } 767 snd_soc_component_update_bits(component, AIC32X4_DACSETUP, 768 AIC32X4_DAC_CHAN_MASK, dacsetup_reg); 769 770 return 0; 771 } 772 773 static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 774 { 775 struct snd_soc_component *component = dai->component; 776 777 snd_soc_component_update_bits(component, AIC32X4_DACMUTE, 778 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0); 779 780 return 0; 781 } 782 783 static int aic32x4_set_bias_level(struct snd_soc_component *component, 784 enum snd_soc_bias_level level) 785 { 786 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 787 int ret; 788 789 switch (level) { 790 case SND_SOC_BIAS_ON: 791 /* Switch on master clock */ 792 ret = clk_prepare_enable(aic32x4->mclk); 793 if (ret) { 794 dev_err(component->dev, "Failed to enable master clock\n"); 795 return ret; 796 } 797 798 /* Switch on PLL */ 799 snd_soc_component_update_bits(component, AIC32X4_PLLPR, 800 AIC32X4_PLLEN, AIC32X4_PLLEN); 801 802 /* Switch on NDAC Divider */ 803 snd_soc_component_update_bits(component, AIC32X4_NDAC, 804 AIC32X4_NDACEN, AIC32X4_NDACEN); 805 806 /* Switch on MDAC Divider */ 807 snd_soc_component_update_bits(component, AIC32X4_MDAC, 808 AIC32X4_MDACEN, AIC32X4_MDACEN); 809 810 /* Switch on NADC Divider */ 811 snd_soc_component_update_bits(component, AIC32X4_NADC, 812 AIC32X4_NADCEN, AIC32X4_NADCEN); 813 814 /* Switch on MADC Divider */ 815 snd_soc_component_update_bits(component, AIC32X4_MADC, 816 AIC32X4_MADCEN, AIC32X4_MADCEN); 817 818 /* Switch on BCLK_N Divider */ 819 snd_soc_component_update_bits(component, AIC32X4_BCLKN, 820 AIC32X4_BCLKEN, AIC32X4_BCLKEN); 821 break; 822 case SND_SOC_BIAS_PREPARE: 823 break; 824 case SND_SOC_BIAS_STANDBY: 825 /* Switch off BCLK_N Divider */ 826 snd_soc_component_update_bits(component, AIC32X4_BCLKN, 827 AIC32X4_BCLKEN, 0); 828 829 /* Switch off MADC Divider */ 830 snd_soc_component_update_bits(component, AIC32X4_MADC, 831 AIC32X4_MADCEN, 0); 832 833 /* Switch off NADC Divider */ 834 snd_soc_component_update_bits(component, AIC32X4_NADC, 835 AIC32X4_NADCEN, 0); 836 837 /* Switch off MDAC Divider */ 838 snd_soc_component_update_bits(component, AIC32X4_MDAC, 839 AIC32X4_MDACEN, 0); 840 841 /* Switch off NDAC Divider */ 842 snd_soc_component_update_bits(component, AIC32X4_NDAC, 843 AIC32X4_NDACEN, 0); 844 845 /* Switch off PLL */ 846 snd_soc_component_update_bits(component, AIC32X4_PLLPR, 847 AIC32X4_PLLEN, 0); 848 849 /* Switch off master clock */ 850 clk_disable_unprepare(aic32x4->mclk); 851 break; 852 case SND_SOC_BIAS_OFF: 853 break; 854 } 855 return 0; 856 } 857 858 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000 859 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 860 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 861 862 static const struct snd_soc_dai_ops aic32x4_ops = { 863 .hw_params = aic32x4_hw_params, 864 .digital_mute = aic32x4_mute, 865 .set_fmt = aic32x4_set_dai_fmt, 866 .set_sysclk = aic32x4_set_dai_sysclk, 867 }; 868 869 static struct snd_soc_dai_driver aic32x4_dai = { 870 .name = "tlv320aic32x4-hifi", 871 .playback = { 872 .stream_name = "Playback", 873 .channels_min = 1, 874 .channels_max = 2, 875 .rates = AIC32X4_RATES, 876 .formats = AIC32X4_FORMATS,}, 877 .capture = { 878 .stream_name = "Capture", 879 .channels_min = 1, 880 .channels_max = 2, 881 .rates = AIC32X4_RATES, 882 .formats = AIC32X4_FORMATS,}, 883 .ops = &aic32x4_ops, 884 .symmetric_rates = 1, 885 }; 886 887 static void aic32x4_setup_gpios(struct snd_soc_component *component) 888 { 889 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 890 891 /* setup GPIO functions */ 892 /* MFP1 */ 893 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) { 894 snd_soc_component_write(component, AIC32X4_DINCTL, 895 aic32x4->setup->gpio_func[0]); 896 snd_soc_add_component_controls(component, aic32x4_mfp1, 897 ARRAY_SIZE(aic32x4_mfp1)); 898 } 899 900 /* MFP2 */ 901 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) { 902 snd_soc_component_write(component, AIC32X4_DOUTCTL, 903 aic32x4->setup->gpio_func[1]); 904 snd_soc_add_component_controls(component, aic32x4_mfp2, 905 ARRAY_SIZE(aic32x4_mfp2)); 906 } 907 908 /* MFP3 */ 909 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) { 910 snd_soc_component_write(component, AIC32X4_SCLKCTL, 911 aic32x4->setup->gpio_func[2]); 912 snd_soc_add_component_controls(component, aic32x4_mfp3, 913 ARRAY_SIZE(aic32x4_mfp3)); 914 } 915 916 /* MFP4 */ 917 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) { 918 snd_soc_component_write(component, AIC32X4_MISOCTL, 919 aic32x4->setup->gpio_func[3]); 920 snd_soc_add_component_controls(component, aic32x4_mfp4, 921 ARRAY_SIZE(aic32x4_mfp4)); 922 } 923 924 /* MFP5 */ 925 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) { 926 snd_soc_component_write(component, AIC32X4_GPIOCTL, 927 aic32x4->setup->gpio_func[4]); 928 snd_soc_add_component_controls(component, aic32x4_mfp5, 929 ARRAY_SIZE(aic32x4_mfp5)); 930 } 931 } 932 933 static int aic32x4_component_probe(struct snd_soc_component *component) 934 { 935 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 936 u32 tmp_reg; 937 938 if (gpio_is_valid(aic32x4->rstn_gpio)) { 939 ndelay(10); 940 gpio_set_value(aic32x4->rstn_gpio, 1); 941 } 942 943 snd_soc_component_write(component, AIC32X4_RESET, 0x01); 944 945 if (aic32x4->setup) 946 aic32x4_setup_gpios(component); 947 948 /* Power platform configuration */ 949 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 950 snd_soc_component_write(component, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN | 951 AIC32X4_MICBIAS_2075V); 952 } 953 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) 954 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 955 956 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 957 AIC32X4_LDOCTLEN : 0; 958 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg); 959 960 tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE); 961 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) 962 tmp_reg |= AIC32X4_LDOIN_18_36; 963 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) 964 tmp_reg |= AIC32X4_LDOIN2HP; 965 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg); 966 967 /* Mic PGA routing */ 968 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) 969 snd_soc_component_write(component, AIC32X4_LMICPGANIN, 970 AIC32X4_LMICPGANIN_IN2R_10K); 971 else 972 snd_soc_component_write(component, AIC32X4_LMICPGANIN, 973 AIC32X4_LMICPGANIN_CM1L_10K); 974 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) 975 snd_soc_component_write(component, AIC32X4_RMICPGANIN, 976 AIC32X4_RMICPGANIN_IN1L_10K); 977 else 978 snd_soc_component_write(component, AIC32X4_RMICPGANIN, 979 AIC32X4_RMICPGANIN_CM1R_10K); 980 981 /* 982 * Workaround: for an unknown reason, the ADC needs to be powered up 983 * and down for the first capture to work properly. It seems related to 984 * a HW BUG or some kind of behavior not documented in the datasheet. 985 */ 986 tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); 987 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg | 988 AIC32X4_LADC_EN | AIC32X4_RADC_EN); 989 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg); 990 991 return 0; 992 } 993 994 static const struct snd_soc_component_driver soc_component_dev_aic32x4 = { 995 .probe = aic32x4_component_probe, 996 .set_bias_level = aic32x4_set_bias_level, 997 .controls = aic32x4_snd_controls, 998 .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 999 .dapm_widgets = aic32x4_dapm_widgets, 1000 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 1001 .dapm_routes = aic32x4_dapm_routes, 1002 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 1003 .suspend_bias_off = 1, 1004 .idle_bias_on = 1, 1005 .use_pmdown_time = 1, 1006 .endianness = 1, 1007 .non_legacy_dai_naming = 1, 1008 }; 1009 1010 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, 1011 struct device_node *np) 1012 { 1013 struct aic32x4_setup_data *aic32x4_setup; 1014 1015 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup), 1016 GFP_KERNEL); 1017 if (!aic32x4_setup) 1018 return -ENOMEM; 1019 1020 aic32x4->swapdacs = false; 1021 aic32x4->micpga_routing = 0; 1022 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); 1023 1024 if (of_property_read_u32_array(np, "aic32x4-gpio-func", 1025 aic32x4_setup->gpio_func, 5) >= 0) 1026 aic32x4->setup = aic32x4_setup; 1027 return 0; 1028 } 1029 1030 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4) 1031 { 1032 regulator_disable(aic32x4->supply_iov); 1033 1034 if (!IS_ERR(aic32x4->supply_ldo)) 1035 regulator_disable(aic32x4->supply_ldo); 1036 1037 if (!IS_ERR(aic32x4->supply_dv)) 1038 regulator_disable(aic32x4->supply_dv); 1039 1040 if (!IS_ERR(aic32x4->supply_av)) 1041 regulator_disable(aic32x4->supply_av); 1042 } 1043 1044 static int aic32x4_setup_regulators(struct device *dev, 1045 struct aic32x4_priv *aic32x4) 1046 { 1047 int ret = 0; 1048 1049 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin"); 1050 aic32x4->supply_iov = devm_regulator_get(dev, "iov"); 1051 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv"); 1052 aic32x4->supply_av = devm_regulator_get_optional(dev, "av"); 1053 1054 /* Check if the regulator requirements are fulfilled */ 1055 1056 if (IS_ERR(aic32x4->supply_iov)) { 1057 dev_err(dev, "Missing supply 'iov'\n"); 1058 return PTR_ERR(aic32x4->supply_iov); 1059 } 1060 1061 if (IS_ERR(aic32x4->supply_ldo)) { 1062 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER) 1063 return -EPROBE_DEFER; 1064 1065 if (IS_ERR(aic32x4->supply_dv)) { 1066 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n"); 1067 return PTR_ERR(aic32x4->supply_dv); 1068 } 1069 if (IS_ERR(aic32x4->supply_av)) { 1070 dev_err(dev, "Missing supply 'av' or 'ldoin'\n"); 1071 return PTR_ERR(aic32x4->supply_av); 1072 } 1073 } else { 1074 if (IS_ERR(aic32x4->supply_dv) && 1075 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER) 1076 return -EPROBE_DEFER; 1077 if (IS_ERR(aic32x4->supply_av) && 1078 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER) 1079 return -EPROBE_DEFER; 1080 } 1081 1082 ret = regulator_enable(aic32x4->supply_iov); 1083 if (ret) { 1084 dev_err(dev, "Failed to enable regulator iov\n"); 1085 return ret; 1086 } 1087 1088 if (!IS_ERR(aic32x4->supply_ldo)) { 1089 ret = regulator_enable(aic32x4->supply_ldo); 1090 if (ret) { 1091 dev_err(dev, "Failed to enable regulator ldo\n"); 1092 goto error_ldo; 1093 } 1094 } 1095 1096 if (!IS_ERR(aic32x4->supply_dv)) { 1097 ret = regulator_enable(aic32x4->supply_dv); 1098 if (ret) { 1099 dev_err(dev, "Failed to enable regulator dv\n"); 1100 goto error_dv; 1101 } 1102 } 1103 1104 if (!IS_ERR(aic32x4->supply_av)) { 1105 ret = regulator_enable(aic32x4->supply_av); 1106 if (ret) { 1107 dev_err(dev, "Failed to enable regulator av\n"); 1108 goto error_av; 1109 } 1110 } 1111 1112 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av)) 1113 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE; 1114 1115 return 0; 1116 1117 error_av: 1118 if (!IS_ERR(aic32x4->supply_dv)) 1119 regulator_disable(aic32x4->supply_dv); 1120 1121 error_dv: 1122 if (!IS_ERR(aic32x4->supply_ldo)) 1123 regulator_disable(aic32x4->supply_ldo); 1124 1125 error_ldo: 1126 regulator_disable(aic32x4->supply_iov); 1127 return ret; 1128 } 1129 1130 int aic32x4_probe(struct device *dev, struct regmap *regmap) 1131 { 1132 struct aic32x4_priv *aic32x4; 1133 struct aic32x4_pdata *pdata = dev->platform_data; 1134 struct device_node *np = dev->of_node; 1135 int ret; 1136 1137 if (IS_ERR(regmap)) 1138 return PTR_ERR(regmap); 1139 1140 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), 1141 GFP_KERNEL); 1142 if (aic32x4 == NULL) 1143 return -ENOMEM; 1144 1145 aic32x4->dev = dev; 1146 dev_set_drvdata(dev, aic32x4); 1147 1148 if (pdata) { 1149 aic32x4->power_cfg = pdata->power_cfg; 1150 aic32x4->swapdacs = pdata->swapdacs; 1151 aic32x4->micpga_routing = pdata->micpga_routing; 1152 aic32x4->rstn_gpio = pdata->rstn_gpio; 1153 } else if (np) { 1154 ret = aic32x4_parse_dt(aic32x4, np); 1155 if (ret) { 1156 dev_err(dev, "Failed to parse DT node\n"); 1157 return ret; 1158 } 1159 } else { 1160 aic32x4->power_cfg = 0; 1161 aic32x4->swapdacs = false; 1162 aic32x4->micpga_routing = 0; 1163 aic32x4->rstn_gpio = -1; 1164 } 1165 1166 aic32x4->mclk = devm_clk_get(dev, "mclk"); 1167 if (IS_ERR(aic32x4->mclk)) { 1168 dev_err(dev, "Failed getting the mclk. The current implementation does not support the usage of this codec without mclk\n"); 1169 return PTR_ERR(aic32x4->mclk); 1170 } 1171 1172 if (gpio_is_valid(aic32x4->rstn_gpio)) { 1173 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, 1174 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 1175 if (ret != 0) 1176 return ret; 1177 } 1178 1179 ret = aic32x4_setup_regulators(dev, aic32x4); 1180 if (ret) { 1181 dev_err(dev, "Failed to setup regulators\n"); 1182 return ret; 1183 } 1184 1185 ret = devm_snd_soc_register_component(dev, 1186 &soc_component_dev_aic32x4, &aic32x4_dai, 1); 1187 if (ret) { 1188 dev_err(dev, "Failed to register component\n"); 1189 aic32x4_disable_regulators(aic32x4); 1190 return ret; 1191 } 1192 1193 return 0; 1194 } 1195 EXPORT_SYMBOL(aic32x4_probe); 1196 1197 int aic32x4_remove(struct device *dev) 1198 { 1199 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev); 1200 1201 aic32x4_disable_regulators(aic32x4); 1202 1203 return 0; 1204 } 1205 EXPORT_SYMBOL(aic32x4_remove); 1206 1207 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 1208 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 1209 MODULE_LICENSE("GPL"); 1210