1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * linux/sound/soc/codecs/tlv320aic32x4.c 4 * 5 * Copyright 2011 Vista Silicon S.L. 6 * 7 * Author: Javier Martin <javier.martin@vista-silicon.com> 8 * 9 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/moduleparam.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/gpio.h> 18 #include <linux/of_gpio.h> 19 #include <linux/cdev.h> 20 #include <linux/slab.h> 21 #include <linux/clk.h> 22 #include <linux/of_clk.h> 23 #include <linux/regulator/consumer.h> 24 25 #include <sound/tlv320aic32x4.h> 26 #include <sound/core.h> 27 #include <sound/pcm.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/soc-dapm.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 34 #include "tlv320aic32x4.h" 35 36 struct aic32x4_priv { 37 struct regmap *regmap; 38 u32 power_cfg; 39 u32 micpga_routing; 40 bool swapdacs; 41 int rstn_gpio; 42 const char *mclk_name; 43 44 struct regulator *supply_ldo; 45 struct regulator *supply_iov; 46 struct regulator *supply_dv; 47 struct regulator *supply_av; 48 49 struct aic32x4_setup_data *setup; 50 struct device *dev; 51 }; 52 53 static int mic_bias_event(struct snd_soc_dapm_widget *w, 54 struct snd_kcontrol *kcontrol, int event) 55 { 56 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 57 58 switch (event) { 59 case SND_SOC_DAPM_POST_PMU: 60 /* Change Mic Bias Registor */ 61 snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 62 AIC32x4_MICBIAS_MASK, 63 AIC32X4_MICBIAS_LDOIN | 64 AIC32X4_MICBIAS_2075V); 65 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__); 66 break; 67 case SND_SOC_DAPM_PRE_PMD: 68 snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 69 AIC32x4_MICBIAS_MASK, 0); 70 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n", 71 __func__); 72 break; 73 } 74 75 return 0; 76 } 77 78 79 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol, 80 struct snd_ctl_elem_value *ucontrol) 81 { 82 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 83 u8 val; 84 85 val = snd_soc_component_read32(component, AIC32X4_DINCTL); 86 87 ucontrol->value.integer.value[0] = (val & 0x01); 88 89 return 0; 90 }; 91 92 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol, 93 struct snd_ctl_elem_value *ucontrol) 94 { 95 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 96 u8 val; 97 u8 gpio_check; 98 99 val = snd_soc_component_read32(component, AIC32X4_DOUTCTL); 100 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 101 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 102 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n", 103 __func__); 104 return -EINVAL; 105 } 106 107 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH)) 108 return 0; 109 110 if (ucontrol->value.integer.value[0]) 111 val |= ucontrol->value.integer.value[0]; 112 else 113 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH; 114 115 snd_soc_component_write(component, AIC32X4_DOUTCTL, val); 116 117 return 0; 118 }; 119 120 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol, 121 struct snd_ctl_elem_value *ucontrol) 122 { 123 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 124 u8 val; 125 126 val = snd_soc_component_read32(component, AIC32X4_SCLKCTL); 127 128 ucontrol->value.integer.value[0] = (val & 0x01); 129 130 return 0; 131 }; 132 133 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol, 134 struct snd_ctl_elem_value *ucontrol) 135 { 136 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 137 u8 val; 138 u8 gpio_check; 139 140 val = snd_soc_component_read32(component, AIC32X4_MISOCTL); 141 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 142 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 143 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n", 144 __func__); 145 return -EINVAL; 146 } 147 148 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH)) 149 return 0; 150 151 if (ucontrol->value.integer.value[0]) 152 val |= ucontrol->value.integer.value[0]; 153 else 154 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH; 155 156 snd_soc_component_write(component, AIC32X4_MISOCTL, val); 157 158 return 0; 159 }; 160 161 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol, 162 struct snd_ctl_elem_value *ucontrol) 163 { 164 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 165 u8 val; 166 167 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 168 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1); 169 170 return 0; 171 }; 172 173 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol, 174 struct snd_ctl_elem_value *ucontrol) 175 { 176 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 177 u8 val; 178 u8 gpio_check; 179 180 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 181 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT); 182 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) { 183 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n", 184 __func__); 185 return -EINVAL; 186 } 187 188 if (ucontrol->value.integer.value[0] == (val & 0x1)) 189 return 0; 190 191 if (ucontrol->value.integer.value[0]) 192 val |= ucontrol->value.integer.value[0]; 193 else 194 val &= 0xfe; 195 196 snd_soc_component_write(component, AIC32X4_GPIOCTL, val); 197 198 return 0; 199 }; 200 201 static const struct snd_kcontrol_new aic32x4_mfp1[] = { 202 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL), 203 }; 204 205 static const struct snd_kcontrol_new aic32x4_mfp2[] = { 206 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio), 207 }; 208 209 static const struct snd_kcontrol_new aic32x4_mfp3[] = { 210 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL), 211 }; 212 213 static const struct snd_kcontrol_new aic32x4_mfp4[] = { 214 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio), 215 }; 216 217 static const struct snd_kcontrol_new aic32x4_mfp5[] = { 218 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio, 219 aic32x4_set_mfp5_gpio), 220 }; 221 222 /* 0dB min, 0.5dB steps */ 223 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 224 /* -63.5dB min, 0.5dB steps */ 225 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0); 226 /* -6dB min, 1dB steps */ 227 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0); 228 /* -12dB min, 0.5dB steps */ 229 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0); 230 231 static const char * const lo_cm_text[] = { 232 "Full Chip", "1.65V", 233 }; 234 235 static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text); 236 237 static const char * const ptm_text[] = { 238 "P3", "P2", "P1", 239 }; 240 241 static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text); 242 static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text); 243 244 static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 245 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 246 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm), 247 SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum), 248 SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum), 249 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 250 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, 251 tlv_driver_gain), 252 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 253 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, 254 tlv_driver_gain), 255 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 256 AIC32X4_HPRGAIN, 6, 0x01, 1), 257 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 258 AIC32X4_LORGAIN, 6, 0x01, 1), 259 SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum), 260 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 261 AIC32X4_RMICPGAVOL, 7, 0x01, 1), 262 263 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 264 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 265 266 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL, 267 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol), 268 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 269 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 270 271 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 272 273 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 274 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 275 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 276 4, 0x07, 0), 277 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 278 0, 0x03, 0), 279 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 280 6, 0x03, 0), 281 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 282 1, 0x1F, 0), 283 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 284 0, 0x7F, 0), 285 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 286 3, 0x1F, 0), 287 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 288 3, 0x1F, 0), 289 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 290 0, 0x1F, 0), 291 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 292 0, 0x0F, 0), 293 }; 294 295 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 296 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 297 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 298 }; 299 300 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 301 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 302 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 303 }; 304 305 static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 306 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 307 }; 308 309 static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 310 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 311 }; 312 313 static const char * const resistor_text[] = { 314 "Off", "10 kOhm", "20 kOhm", "40 kOhm", 315 }; 316 317 /* Left mixer pins */ 318 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text); 319 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text); 320 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text); 321 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text); 322 323 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text); 324 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text); 325 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text); 326 327 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = { 328 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum), 329 }; 330 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = { 331 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum), 332 }; 333 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = { 334 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum), 335 }; 336 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = { 337 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum), 338 }; 339 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = { 340 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum), 341 }; 342 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = { 343 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum), 344 }; 345 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = { 346 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum), 347 }; 348 349 /* Right mixer pins */ 350 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text); 351 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text); 352 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text); 353 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text); 354 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text); 355 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text); 356 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text); 357 358 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = { 359 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum), 360 }; 361 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = { 362 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum), 363 }; 364 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = { 365 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum), 366 }; 367 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = { 368 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum), 369 }; 370 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = { 371 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum), 372 }; 373 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = { 374 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum), 375 }; 376 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = { 377 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum), 378 }; 379 380 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 381 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 382 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 383 &hpl_output_mixer_controls[0], 384 ARRAY_SIZE(hpl_output_mixer_controls)), 385 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 386 387 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 388 &lol_output_mixer_controls[0], 389 ARRAY_SIZE(lol_output_mixer_controls)), 390 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 391 392 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 393 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 394 &hpr_output_mixer_controls[0], 395 ARRAY_SIZE(hpr_output_mixer_controls)), 396 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 397 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 398 &lor_output_mixer_controls[0], 399 ARRAY_SIZE(lor_output_mixer_controls)), 400 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 401 402 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 403 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 404 in1r_to_rmixer_controls), 405 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 406 in2r_to_rmixer_controls), 407 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 408 in3r_to_rmixer_controls), 409 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 410 in2l_to_rmixer_controls), 411 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 412 cmr_to_rmixer_controls), 413 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 414 in1l_to_rmixer_controls), 415 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 416 in3l_to_rmixer_controls), 417 418 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 419 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 420 in1l_to_lmixer_controls), 421 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 422 in2l_to_lmixer_controls), 423 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 424 in3l_to_lmixer_controls), 425 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 426 in1r_to_lmixer_controls), 427 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 428 cml_to_lmixer_controls), 429 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 430 in2r_to_lmixer_controls), 431 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 432 in3r_to_lmixer_controls), 433 434 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event, 435 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 436 437 438 SND_SOC_DAPM_OUTPUT("HPL"), 439 SND_SOC_DAPM_OUTPUT("HPR"), 440 SND_SOC_DAPM_OUTPUT("LOL"), 441 SND_SOC_DAPM_OUTPUT("LOR"), 442 SND_SOC_DAPM_INPUT("IN1_L"), 443 SND_SOC_DAPM_INPUT("IN1_R"), 444 SND_SOC_DAPM_INPUT("IN2_L"), 445 SND_SOC_DAPM_INPUT("IN2_R"), 446 SND_SOC_DAPM_INPUT("IN3_L"), 447 SND_SOC_DAPM_INPUT("IN3_R"), 448 SND_SOC_DAPM_INPUT("CM_L"), 449 SND_SOC_DAPM_INPUT("CM_R"), 450 }; 451 452 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 453 /* Left Output */ 454 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 455 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 456 457 {"HPL Power", NULL, "HPL Output Mixer"}, 458 {"HPL", NULL, "HPL Power"}, 459 460 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 461 462 {"LOL Power", NULL, "LOL Output Mixer"}, 463 {"LOL", NULL, "LOL Power"}, 464 465 /* Right Output */ 466 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 467 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 468 469 {"HPR Power", NULL, "HPR Output Mixer"}, 470 {"HPR", NULL, "HPR Power"}, 471 472 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 473 474 {"LOR Power", NULL, "LOR Output Mixer"}, 475 {"LOR", NULL, "LOR Power"}, 476 477 /* Right Input */ 478 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"}, 479 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 480 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 481 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 482 483 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"}, 484 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"}, 485 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"}, 486 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"}, 487 488 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"}, 489 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"}, 490 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"}, 491 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"}, 492 493 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"}, 494 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 495 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 496 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 497 498 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"}, 499 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"}, 500 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"}, 501 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"}, 502 503 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"}, 504 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"}, 505 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"}, 506 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"}, 507 508 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"}, 509 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"}, 510 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"}, 511 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"}, 512 513 /* Left Input */ 514 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"}, 515 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"}, 516 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"}, 517 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"}, 518 519 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"}, 520 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 521 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 522 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 523 524 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"}, 525 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"}, 526 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"}, 527 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"}, 528 529 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"}, 530 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 531 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 532 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 533 534 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"}, 535 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"}, 536 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"}, 537 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"}, 538 539 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"}, 540 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"}, 541 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"}, 542 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"}, 543 544 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"}, 545 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"}, 546 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"}, 547 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"}, 548 }; 549 550 static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 551 { 552 .selector_reg = 0, 553 .selector_mask = 0xff, 554 .window_start = 0, 555 .window_len = 128, 556 .range_min = 0, 557 .range_max = AIC32X4_RMICPGAVOL, 558 }, 559 }; 560 561 const struct regmap_config aic32x4_regmap_config = { 562 .max_register = AIC32X4_RMICPGAVOL, 563 .ranges = aic32x4_regmap_pages, 564 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 565 }; 566 EXPORT_SYMBOL(aic32x4_regmap_config); 567 568 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 569 int clk_id, unsigned int freq, int dir) 570 { 571 struct snd_soc_component *component = codec_dai->component; 572 struct clk *mclk; 573 struct clk *pll; 574 575 pll = devm_clk_get(component->dev, "pll"); 576 if (IS_ERR(pll)) 577 return PTR_ERR(pll); 578 579 mclk = clk_get_parent(pll); 580 581 return clk_set_rate(mclk, freq); 582 } 583 584 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 585 { 586 struct snd_soc_component *component = codec_dai->component; 587 u8 iface_reg_1 = 0; 588 u8 iface_reg_2 = 0; 589 u8 iface_reg_3 = 0; 590 591 /* set master/slave audio interface */ 592 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 593 case SND_SOC_DAIFMT_CBM_CFM: 594 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 595 break; 596 case SND_SOC_DAIFMT_CBS_CFS: 597 break; 598 default: 599 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 600 return -EINVAL; 601 } 602 603 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 604 case SND_SOC_DAIFMT_I2S: 605 break; 606 case SND_SOC_DAIFMT_DSP_A: 607 iface_reg_1 |= (AIC32X4_DSP_MODE << 608 AIC32X4_IFACE1_DATATYPE_SHIFT); 609 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 610 iface_reg_2 = 0x01; /* add offset 1 */ 611 break; 612 case SND_SOC_DAIFMT_DSP_B: 613 iface_reg_1 |= (AIC32X4_DSP_MODE << 614 AIC32X4_IFACE1_DATATYPE_SHIFT); 615 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 616 break; 617 case SND_SOC_DAIFMT_RIGHT_J: 618 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE << 619 AIC32X4_IFACE1_DATATYPE_SHIFT); 620 break; 621 case SND_SOC_DAIFMT_LEFT_J: 622 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE << 623 AIC32X4_IFACE1_DATATYPE_SHIFT); 624 break; 625 default: 626 printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 627 return -EINVAL; 628 } 629 630 snd_soc_component_update_bits(component, AIC32X4_IFACE1, 631 AIC32X4_IFACE1_DATATYPE_MASK | 632 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1); 633 snd_soc_component_update_bits(component, AIC32X4_IFACE2, 634 AIC32X4_DATA_OFFSET_MASK, iface_reg_2); 635 snd_soc_component_update_bits(component, AIC32X4_IFACE3, 636 AIC32X4_BCLKINV_MASK, iface_reg_3); 637 638 return 0; 639 } 640 641 static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr) 642 { 643 return snd_soc_component_write(component, AIC32X4_AOSR, aosr); 644 } 645 646 static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr) 647 { 648 snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8); 649 snd_soc_component_write(component, AIC32X4_DOSRLSB, 650 (dosr & 0xff)); 651 652 return 0; 653 } 654 655 static int aic32x4_set_processing_blocks(struct snd_soc_component *component, 656 u8 r_block, u8 p_block) 657 { 658 if (r_block > 18 || p_block > 25) 659 return -EINVAL; 660 661 snd_soc_component_write(component, AIC32X4_ADCSPB, r_block); 662 snd_soc_component_write(component, AIC32X4_DACSPB, p_block); 663 664 return 0; 665 } 666 667 static int aic32x4_setup_clocks(struct snd_soc_component *component, 668 unsigned int sample_rate) 669 { 670 u8 aosr; 671 u16 dosr; 672 u8 adc_resource_class, dac_resource_class; 673 u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac; 674 u8 dosr_increment; 675 u16 max_dosr, min_dosr; 676 unsigned long adc_clock_rate, dac_clock_rate; 677 int ret; 678 679 struct clk_bulk_data clocks[] = { 680 { .id = "pll" }, 681 { .id = "nadc" }, 682 { .id = "madc" }, 683 { .id = "ndac" }, 684 { .id = "mdac" }, 685 { .id = "bdiv" }, 686 }; 687 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 688 if (ret) 689 return ret; 690 691 if (sample_rate <= 48000) { 692 aosr = 128; 693 adc_resource_class = 6; 694 dac_resource_class = 8; 695 dosr_increment = 8; 696 aic32x4_set_processing_blocks(component, 1, 1); 697 } else if (sample_rate <= 96000) { 698 aosr = 64; 699 adc_resource_class = 6; 700 dac_resource_class = 8; 701 dosr_increment = 4; 702 aic32x4_set_processing_blocks(component, 1, 9); 703 } else if (sample_rate == 192000) { 704 aosr = 32; 705 adc_resource_class = 3; 706 dac_resource_class = 4; 707 dosr_increment = 2; 708 aic32x4_set_processing_blocks(component, 13, 19); 709 } else { 710 dev_err(component->dev, "Sampling rate not supported\n"); 711 return -EINVAL; 712 } 713 714 madc = DIV_ROUND_UP((32 * adc_resource_class), aosr); 715 max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) * 716 dosr_increment; 717 min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) * 718 dosr_increment; 719 max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate); 720 721 for (nadc = max_nadc; nadc > 0; --nadc) { 722 adc_clock_rate = nadc * madc * aosr * sample_rate; 723 for (dosr = max_dosr; dosr >= min_dosr; 724 dosr -= dosr_increment) { 725 min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr); 726 max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ / 727 (min_mdac * dosr * sample_rate); 728 for (mdac = min_mdac; mdac <= 128; ++mdac) { 729 for (ndac = max_ndac; ndac > 0; --ndac) { 730 dac_clock_rate = ndac * mdac * dosr * 731 sample_rate; 732 if (dac_clock_rate == adc_clock_rate) { 733 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0) 734 continue; 735 736 clk_set_rate(clocks[0].clk, 737 dac_clock_rate); 738 739 clk_set_rate(clocks[1].clk, 740 sample_rate * aosr * 741 madc); 742 clk_set_rate(clocks[2].clk, 743 sample_rate * aosr); 744 aic32x4_set_aosr(component, 745 aosr); 746 747 clk_set_rate(clocks[3].clk, 748 sample_rate * dosr * 749 mdac); 750 clk_set_rate(clocks[4].clk, 751 sample_rate * dosr); 752 aic32x4_set_dosr(component, 753 dosr); 754 755 clk_set_rate(clocks[5].clk, 756 sample_rate * 32); 757 return 0; 758 } 759 } 760 } 761 } 762 } 763 764 dev_err(component->dev, 765 "Could not set clocks to support sample rate.\n"); 766 return -EINVAL; 767 } 768 769 static int aic32x4_hw_params(struct snd_pcm_substream *substream, 770 struct snd_pcm_hw_params *params, 771 struct snd_soc_dai *dai) 772 { 773 struct snd_soc_component *component = dai->component; 774 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 775 u8 iface1_reg = 0; 776 u8 dacsetup_reg = 0; 777 778 aic32x4_setup_clocks(component, params_rate(params)); 779 780 switch (params_width(params)) { 781 case 16: 782 iface1_reg |= (AIC32X4_WORD_LEN_16BITS << 783 AIC32X4_IFACE1_DATALEN_SHIFT); 784 break; 785 case 20: 786 iface1_reg |= (AIC32X4_WORD_LEN_20BITS << 787 AIC32X4_IFACE1_DATALEN_SHIFT); 788 break; 789 case 24: 790 iface1_reg |= (AIC32X4_WORD_LEN_24BITS << 791 AIC32X4_IFACE1_DATALEN_SHIFT); 792 break; 793 case 32: 794 iface1_reg |= (AIC32X4_WORD_LEN_32BITS << 795 AIC32X4_IFACE1_DATALEN_SHIFT); 796 break; 797 } 798 snd_soc_component_update_bits(component, AIC32X4_IFACE1, 799 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg); 800 801 if (params_channels(params) == 1) { 802 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 803 } else { 804 if (aic32x4->swapdacs) 805 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 806 else 807 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 808 } 809 snd_soc_component_update_bits(component, AIC32X4_DACSETUP, 810 AIC32X4_DAC_CHAN_MASK, dacsetup_reg); 811 812 return 0; 813 } 814 815 static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 816 { 817 struct snd_soc_component *component = dai->component; 818 819 snd_soc_component_update_bits(component, AIC32X4_DACMUTE, 820 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0); 821 822 return 0; 823 } 824 825 static int aic32x4_set_bias_level(struct snd_soc_component *component, 826 enum snd_soc_bias_level level) 827 { 828 int ret; 829 830 struct clk_bulk_data clocks[] = { 831 { .id = "madc" }, 832 { .id = "mdac" }, 833 { .id = "bdiv" }, 834 }; 835 836 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 837 if (ret) 838 return ret; 839 840 switch (level) { 841 case SND_SOC_BIAS_ON: 842 ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); 843 if (ret) { 844 dev_err(component->dev, "Failed to enable clocks\n"); 845 return ret; 846 } 847 break; 848 case SND_SOC_BIAS_PREPARE: 849 break; 850 case SND_SOC_BIAS_STANDBY: 851 /* Initial cold start */ 852 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 853 break; 854 855 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); 856 break; 857 case SND_SOC_BIAS_OFF: 858 break; 859 } 860 return 0; 861 } 862 863 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000 864 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 865 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 866 867 static const struct snd_soc_dai_ops aic32x4_ops = { 868 .hw_params = aic32x4_hw_params, 869 .digital_mute = aic32x4_mute, 870 .set_fmt = aic32x4_set_dai_fmt, 871 .set_sysclk = aic32x4_set_dai_sysclk, 872 }; 873 874 static struct snd_soc_dai_driver aic32x4_dai = { 875 .name = "tlv320aic32x4-hifi", 876 .playback = { 877 .stream_name = "Playback", 878 .channels_min = 1, 879 .channels_max = 2, 880 .rates = AIC32X4_RATES, 881 .formats = AIC32X4_FORMATS,}, 882 .capture = { 883 .stream_name = "Capture", 884 .channels_min = 1, 885 .channels_max = 2, 886 .rates = AIC32X4_RATES, 887 .formats = AIC32X4_FORMATS,}, 888 .ops = &aic32x4_ops, 889 .symmetric_rates = 1, 890 }; 891 892 static void aic32x4_setup_gpios(struct snd_soc_component *component) 893 { 894 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 895 896 /* setup GPIO functions */ 897 /* MFP1 */ 898 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) { 899 snd_soc_component_write(component, AIC32X4_DINCTL, 900 aic32x4->setup->gpio_func[0]); 901 snd_soc_add_component_controls(component, aic32x4_mfp1, 902 ARRAY_SIZE(aic32x4_mfp1)); 903 } 904 905 /* MFP2 */ 906 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) { 907 snd_soc_component_write(component, AIC32X4_DOUTCTL, 908 aic32x4->setup->gpio_func[1]); 909 snd_soc_add_component_controls(component, aic32x4_mfp2, 910 ARRAY_SIZE(aic32x4_mfp2)); 911 } 912 913 /* MFP3 */ 914 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) { 915 snd_soc_component_write(component, AIC32X4_SCLKCTL, 916 aic32x4->setup->gpio_func[2]); 917 snd_soc_add_component_controls(component, aic32x4_mfp3, 918 ARRAY_SIZE(aic32x4_mfp3)); 919 } 920 921 /* MFP4 */ 922 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) { 923 snd_soc_component_write(component, AIC32X4_MISOCTL, 924 aic32x4->setup->gpio_func[3]); 925 snd_soc_add_component_controls(component, aic32x4_mfp4, 926 ARRAY_SIZE(aic32x4_mfp4)); 927 } 928 929 /* MFP5 */ 930 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) { 931 snd_soc_component_write(component, AIC32X4_GPIOCTL, 932 aic32x4->setup->gpio_func[4]); 933 snd_soc_add_component_controls(component, aic32x4_mfp5, 934 ARRAY_SIZE(aic32x4_mfp5)); 935 } 936 } 937 938 static int aic32x4_component_probe(struct snd_soc_component *component) 939 { 940 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 941 u32 tmp_reg; 942 int ret; 943 944 struct clk_bulk_data clocks[] = { 945 { .id = "codec_clkin" }, 946 { .id = "pll" }, 947 { .id = "bdiv" }, 948 { .id = "mdac" }, 949 }; 950 951 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 952 if (ret) 953 return ret; 954 955 if (gpio_is_valid(aic32x4->rstn_gpio)) { 956 ndelay(10); 957 gpio_set_value(aic32x4->rstn_gpio, 1); 958 mdelay(1); 959 } 960 961 snd_soc_component_write(component, AIC32X4_RESET, 0x01); 962 963 if (aic32x4->setup) 964 aic32x4_setup_gpios(component); 965 966 clk_set_parent(clocks[0].clk, clocks[1].clk); 967 clk_set_parent(clocks[2].clk, clocks[3].clk); 968 969 /* Power platform configuration */ 970 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 971 snd_soc_component_write(component, AIC32X4_MICBIAS, 972 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V); 973 } 974 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) 975 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 976 977 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 978 AIC32X4_LDOCTLEN : 0; 979 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg); 980 981 tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE); 982 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) 983 tmp_reg |= AIC32X4_LDOIN_18_36; 984 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) 985 tmp_reg |= AIC32X4_LDOIN2HP; 986 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg); 987 988 /* Mic PGA routing */ 989 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) 990 snd_soc_component_write(component, AIC32X4_LMICPGANIN, 991 AIC32X4_LMICPGANIN_IN2R_10K); 992 else 993 snd_soc_component_write(component, AIC32X4_LMICPGANIN, 994 AIC32X4_LMICPGANIN_CM1L_10K); 995 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) 996 snd_soc_component_write(component, AIC32X4_RMICPGANIN, 997 AIC32X4_RMICPGANIN_IN1L_10K); 998 else 999 snd_soc_component_write(component, AIC32X4_RMICPGANIN, 1000 AIC32X4_RMICPGANIN_CM1R_10K); 1001 1002 /* 1003 * Workaround: for an unknown reason, the ADC needs to be powered up 1004 * and down for the first capture to work properly. It seems related to 1005 * a HW BUG or some kind of behavior not documented in the datasheet. 1006 */ 1007 tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); 1008 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg | 1009 AIC32X4_LADC_EN | AIC32X4_RADC_EN); 1010 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg); 1011 1012 return 0; 1013 } 1014 1015 static const struct snd_soc_component_driver soc_component_dev_aic32x4 = { 1016 .probe = aic32x4_component_probe, 1017 .set_bias_level = aic32x4_set_bias_level, 1018 .controls = aic32x4_snd_controls, 1019 .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 1020 .dapm_widgets = aic32x4_dapm_widgets, 1021 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 1022 .dapm_routes = aic32x4_dapm_routes, 1023 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 1024 .suspend_bias_off = 1, 1025 .idle_bias_on = 1, 1026 .use_pmdown_time = 1, 1027 .endianness = 1, 1028 .non_legacy_dai_naming = 1, 1029 }; 1030 1031 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, 1032 struct device_node *np) 1033 { 1034 struct aic32x4_setup_data *aic32x4_setup; 1035 int ret; 1036 1037 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup), 1038 GFP_KERNEL); 1039 if (!aic32x4_setup) 1040 return -ENOMEM; 1041 1042 ret = of_property_match_string(np, "clock-names", "mclk"); 1043 if (ret < 0) 1044 return -EINVAL; 1045 aic32x4->mclk_name = of_clk_get_parent_name(np, ret); 1046 1047 aic32x4->swapdacs = false; 1048 aic32x4->micpga_routing = 0; 1049 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); 1050 1051 if (of_property_read_u32_array(np, "aic32x4-gpio-func", 1052 aic32x4_setup->gpio_func, 5) >= 0) 1053 aic32x4->setup = aic32x4_setup; 1054 return 0; 1055 } 1056 1057 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4) 1058 { 1059 regulator_disable(aic32x4->supply_iov); 1060 1061 if (!IS_ERR(aic32x4->supply_ldo)) 1062 regulator_disable(aic32x4->supply_ldo); 1063 1064 if (!IS_ERR(aic32x4->supply_dv)) 1065 regulator_disable(aic32x4->supply_dv); 1066 1067 if (!IS_ERR(aic32x4->supply_av)) 1068 regulator_disable(aic32x4->supply_av); 1069 } 1070 1071 static int aic32x4_setup_regulators(struct device *dev, 1072 struct aic32x4_priv *aic32x4) 1073 { 1074 int ret = 0; 1075 1076 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin"); 1077 aic32x4->supply_iov = devm_regulator_get(dev, "iov"); 1078 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv"); 1079 aic32x4->supply_av = devm_regulator_get_optional(dev, "av"); 1080 1081 /* Check if the regulator requirements are fulfilled */ 1082 1083 if (IS_ERR(aic32x4->supply_iov)) { 1084 dev_err(dev, "Missing supply 'iov'\n"); 1085 return PTR_ERR(aic32x4->supply_iov); 1086 } 1087 1088 if (IS_ERR(aic32x4->supply_ldo)) { 1089 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER) 1090 return -EPROBE_DEFER; 1091 1092 if (IS_ERR(aic32x4->supply_dv)) { 1093 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n"); 1094 return PTR_ERR(aic32x4->supply_dv); 1095 } 1096 if (IS_ERR(aic32x4->supply_av)) { 1097 dev_err(dev, "Missing supply 'av' or 'ldoin'\n"); 1098 return PTR_ERR(aic32x4->supply_av); 1099 } 1100 } else { 1101 if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER) 1102 return -EPROBE_DEFER; 1103 if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER) 1104 return -EPROBE_DEFER; 1105 } 1106 1107 ret = regulator_enable(aic32x4->supply_iov); 1108 if (ret) { 1109 dev_err(dev, "Failed to enable regulator iov\n"); 1110 return ret; 1111 } 1112 1113 if (!IS_ERR(aic32x4->supply_ldo)) { 1114 ret = regulator_enable(aic32x4->supply_ldo); 1115 if (ret) { 1116 dev_err(dev, "Failed to enable regulator ldo\n"); 1117 goto error_ldo; 1118 } 1119 } 1120 1121 if (!IS_ERR(aic32x4->supply_dv)) { 1122 ret = regulator_enable(aic32x4->supply_dv); 1123 if (ret) { 1124 dev_err(dev, "Failed to enable regulator dv\n"); 1125 goto error_dv; 1126 } 1127 } 1128 1129 if (!IS_ERR(aic32x4->supply_av)) { 1130 ret = regulator_enable(aic32x4->supply_av); 1131 if (ret) { 1132 dev_err(dev, "Failed to enable regulator av\n"); 1133 goto error_av; 1134 } 1135 } 1136 1137 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av)) 1138 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE; 1139 1140 return 0; 1141 1142 error_av: 1143 if (!IS_ERR(aic32x4->supply_dv)) 1144 regulator_disable(aic32x4->supply_dv); 1145 1146 error_dv: 1147 if (!IS_ERR(aic32x4->supply_ldo)) 1148 regulator_disable(aic32x4->supply_ldo); 1149 1150 error_ldo: 1151 regulator_disable(aic32x4->supply_iov); 1152 return ret; 1153 } 1154 1155 int aic32x4_probe(struct device *dev, struct regmap *regmap) 1156 { 1157 struct aic32x4_priv *aic32x4; 1158 struct aic32x4_pdata *pdata = dev->platform_data; 1159 struct device_node *np = dev->of_node; 1160 int ret; 1161 1162 if (IS_ERR(regmap)) 1163 return PTR_ERR(regmap); 1164 1165 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), 1166 GFP_KERNEL); 1167 if (aic32x4 == NULL) 1168 return -ENOMEM; 1169 1170 aic32x4->dev = dev; 1171 dev_set_drvdata(dev, aic32x4); 1172 1173 if (pdata) { 1174 aic32x4->power_cfg = pdata->power_cfg; 1175 aic32x4->swapdacs = pdata->swapdacs; 1176 aic32x4->micpga_routing = pdata->micpga_routing; 1177 aic32x4->rstn_gpio = pdata->rstn_gpio; 1178 aic32x4->mclk_name = "mclk"; 1179 } else if (np) { 1180 ret = aic32x4_parse_dt(aic32x4, np); 1181 if (ret) { 1182 dev_err(dev, "Failed to parse DT node\n"); 1183 return ret; 1184 } 1185 } else { 1186 aic32x4->power_cfg = 0; 1187 aic32x4->swapdacs = false; 1188 aic32x4->micpga_routing = 0; 1189 aic32x4->rstn_gpio = -1; 1190 aic32x4->mclk_name = "mclk"; 1191 } 1192 1193 ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); 1194 if (ret) 1195 return ret; 1196 1197 if (gpio_is_valid(aic32x4->rstn_gpio)) { 1198 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, 1199 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 1200 if (ret != 0) 1201 return ret; 1202 } 1203 1204 ret = aic32x4_setup_regulators(dev, aic32x4); 1205 if (ret) { 1206 dev_err(dev, "Failed to setup regulators\n"); 1207 return ret; 1208 } 1209 1210 ret = devm_snd_soc_register_component(dev, 1211 &soc_component_dev_aic32x4, &aic32x4_dai, 1); 1212 if (ret) { 1213 dev_err(dev, "Failed to register component\n"); 1214 aic32x4_disable_regulators(aic32x4); 1215 return ret; 1216 } 1217 1218 return 0; 1219 } 1220 EXPORT_SYMBOL(aic32x4_probe); 1221 1222 int aic32x4_remove(struct device *dev) 1223 { 1224 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev); 1225 1226 aic32x4_disable_regulators(aic32x4); 1227 1228 return 0; 1229 } 1230 EXPORT_SYMBOL(aic32x4_remove); 1231 1232 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 1233 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 1234 MODULE_LICENSE("GPL"); 1235