1 /* 2 * linux/sound/soc/codecs/tlv320aic32x4.c 3 * 4 * Copyright 2011 Vista Silicon S.L. 5 * 6 * Author: Javier Martin <javier.martin@vista-silicon.com> 7 * 8 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 23 * MA 02110-1301, USA. 24 */ 25 26 #include <linux/module.h> 27 #include <linux/moduleparam.h> 28 #include <linux/init.h> 29 #include <linux/delay.h> 30 #include <linux/pm.h> 31 #include <linux/gpio.h> 32 #include <linux/of_gpio.h> 33 #include <linux/cdev.h> 34 #include <linux/slab.h> 35 #include <linux/clk.h> 36 #include <linux/of_clk.h> 37 #include <linux/regulator/consumer.h> 38 39 #include <sound/tlv320aic32x4.h> 40 #include <sound/core.h> 41 #include <sound/pcm.h> 42 #include <sound/pcm_params.h> 43 #include <sound/soc.h> 44 #include <sound/soc-dapm.h> 45 #include <sound/initval.h> 46 #include <sound/tlv.h> 47 48 #include "tlv320aic32x4.h" 49 50 struct aic32x4_priv { 51 struct regmap *regmap; 52 u32 power_cfg; 53 u32 micpga_routing; 54 bool swapdacs; 55 int rstn_gpio; 56 const char *mclk_name; 57 58 struct regulator *supply_ldo; 59 struct regulator *supply_iov; 60 struct regulator *supply_dv; 61 struct regulator *supply_av; 62 63 struct aic32x4_setup_data *setup; 64 struct device *dev; 65 }; 66 67 static int mic_bias_event(struct snd_soc_dapm_widget *w, 68 struct snd_kcontrol *kcontrol, int event) 69 { 70 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 71 72 switch (event) { 73 case SND_SOC_DAPM_POST_PMU: 74 /* Change Mic Bias Registor */ 75 snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 76 AIC32x4_MICBIAS_MASK, 77 AIC32X4_MICBIAS_LDOIN | 78 AIC32X4_MICBIAS_2075V); 79 printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__); 80 break; 81 case SND_SOC_DAPM_PRE_PMD: 82 snd_soc_component_update_bits(component, AIC32X4_MICBIAS, 83 AIC32x4_MICBIAS_MASK, 0); 84 printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n", 85 __func__); 86 break; 87 } 88 89 return 0; 90 } 91 92 93 static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol, 94 struct snd_ctl_elem_value *ucontrol) 95 { 96 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 97 u8 val; 98 99 val = snd_soc_component_read32(component, AIC32X4_DINCTL); 100 101 ucontrol->value.integer.value[0] = (val & 0x01); 102 103 return 0; 104 }; 105 106 static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol, 107 struct snd_ctl_elem_value *ucontrol) 108 { 109 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 110 u8 val; 111 u8 gpio_check; 112 113 val = snd_soc_component_read32(component, AIC32X4_DOUTCTL); 114 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 115 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 116 printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n", 117 __func__); 118 return -EINVAL; 119 } 120 121 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH)) 122 return 0; 123 124 if (ucontrol->value.integer.value[0]) 125 val |= ucontrol->value.integer.value[0]; 126 else 127 val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH; 128 129 snd_soc_component_write(component, AIC32X4_DOUTCTL, val); 130 131 return 0; 132 }; 133 134 static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol, 135 struct snd_ctl_elem_value *ucontrol) 136 { 137 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 138 u8 val; 139 140 val = snd_soc_component_read32(component, AIC32X4_SCLKCTL); 141 142 ucontrol->value.integer.value[0] = (val & 0x01); 143 144 return 0; 145 }; 146 147 static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol, 148 struct snd_ctl_elem_value *ucontrol) 149 { 150 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 151 u8 val; 152 u8 gpio_check; 153 154 val = snd_soc_component_read32(component, AIC32X4_MISOCTL); 155 gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED); 156 if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) { 157 printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n", 158 __func__); 159 return -EINVAL; 160 } 161 162 if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH)) 163 return 0; 164 165 if (ucontrol->value.integer.value[0]) 166 val |= ucontrol->value.integer.value[0]; 167 else 168 val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH; 169 170 snd_soc_component_write(component, AIC32X4_MISOCTL, val); 171 172 return 0; 173 }; 174 175 static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol, 176 struct snd_ctl_elem_value *ucontrol) 177 { 178 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 179 u8 val; 180 181 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 182 ucontrol->value.integer.value[0] = ((val & 0x2) >> 1); 183 184 return 0; 185 }; 186 187 static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol, 188 struct snd_ctl_elem_value *ucontrol) 189 { 190 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 191 u8 val; 192 u8 gpio_check; 193 194 val = snd_soc_component_read32(component, AIC32X4_GPIOCTL); 195 gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT); 196 if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) { 197 printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n", 198 __func__); 199 return -EINVAL; 200 } 201 202 if (ucontrol->value.integer.value[0] == (val & 0x1)) 203 return 0; 204 205 if (ucontrol->value.integer.value[0]) 206 val |= ucontrol->value.integer.value[0]; 207 else 208 val &= 0xfe; 209 210 snd_soc_component_write(component, AIC32X4_GPIOCTL, val); 211 212 return 0; 213 }; 214 215 static const struct snd_kcontrol_new aic32x4_mfp1[] = { 216 SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL), 217 }; 218 219 static const struct snd_kcontrol_new aic32x4_mfp2[] = { 220 SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio), 221 }; 222 223 static const struct snd_kcontrol_new aic32x4_mfp3[] = { 224 SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL), 225 }; 226 227 static const struct snd_kcontrol_new aic32x4_mfp4[] = { 228 SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio), 229 }; 230 231 static const struct snd_kcontrol_new aic32x4_mfp5[] = { 232 SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio, 233 aic32x4_set_mfp5_gpio), 234 }; 235 236 /* 0dB min, 0.5dB steps */ 237 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0); 238 /* -63.5dB min, 0.5dB steps */ 239 static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0); 240 /* -6dB min, 1dB steps */ 241 static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0); 242 /* -12dB min, 0.5dB steps */ 243 static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0); 244 245 static const char * const lo_cm_text[] = { 246 "Full Chip", "1.65V", 247 }; 248 249 static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text); 250 251 static const char * const ptm_text[] = { 252 "P3", "P2", "P1", 253 }; 254 255 static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text); 256 static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text); 257 258 static const struct snd_kcontrol_new aic32x4_snd_controls[] = { 259 SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL, 260 AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm), 261 SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum), 262 SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum), 263 SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN, 264 AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0, 265 tlv_driver_gain), 266 SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN, 267 AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0, 268 tlv_driver_gain), 269 SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN, 270 AIC32X4_HPRGAIN, 6, 0x01, 1), 271 SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN, 272 AIC32X4_LORGAIN, 6, 0x01, 1), 273 SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum), 274 SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL, 275 AIC32X4_RMICPGAVOL, 7, 0x01, 1), 276 277 SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0), 278 SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0), 279 280 SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL, 281 AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol), 282 SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL, 283 AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5), 284 285 SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0), 286 287 SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0), 288 SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0), 289 SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1, 290 4, 0x07, 0), 291 SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1, 292 0, 0x03, 0), 293 SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2, 294 6, 0x03, 0), 295 SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2, 296 1, 0x1F, 0), 297 SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3, 298 0, 0x7F, 0), 299 SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4, 300 3, 0x1F, 0), 301 SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5, 302 3, 0x1F, 0), 303 SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6, 304 0, 0x1F, 0), 305 SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7, 306 0, 0x0F, 0), 307 }; 308 309 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = { 310 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0), 311 SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0), 312 }; 313 314 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = { 315 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0), 316 SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0), 317 }; 318 319 static const struct snd_kcontrol_new lol_output_mixer_controls[] = { 320 SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0), 321 }; 322 323 static const struct snd_kcontrol_new lor_output_mixer_controls[] = { 324 SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0), 325 }; 326 327 static const char * const resistor_text[] = { 328 "Off", "10 kOhm", "20 kOhm", "40 kOhm", 329 }; 330 331 /* Left mixer pins */ 332 static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text); 333 static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text); 334 static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text); 335 static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text); 336 337 static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text); 338 static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text); 339 static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text); 340 341 static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = { 342 SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum), 343 }; 344 static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = { 345 SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum), 346 }; 347 static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = { 348 SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum), 349 }; 350 static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = { 351 SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum), 352 }; 353 static const struct snd_kcontrol_new cml_to_lmixer_controls[] = { 354 SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum), 355 }; 356 static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = { 357 SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum), 358 }; 359 static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = { 360 SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum), 361 }; 362 363 /* Right mixer pins */ 364 static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text); 365 static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text); 366 static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text); 367 static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text); 368 static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text); 369 static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text); 370 static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text); 371 372 static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = { 373 SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum), 374 }; 375 static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = { 376 SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum), 377 }; 378 static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = { 379 SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum), 380 }; 381 static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = { 382 SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum), 383 }; 384 static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = { 385 SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum), 386 }; 387 static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = { 388 SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum), 389 }; 390 static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = { 391 SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum), 392 }; 393 394 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { 395 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0), 396 SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0, 397 &hpl_output_mixer_controls[0], 398 ARRAY_SIZE(hpl_output_mixer_controls)), 399 SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0), 400 401 SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0, 402 &lol_output_mixer_controls[0], 403 ARRAY_SIZE(lol_output_mixer_controls)), 404 SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0), 405 406 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0), 407 SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0, 408 &hpr_output_mixer_controls[0], 409 ARRAY_SIZE(hpr_output_mixer_controls)), 410 SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0), 411 SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0, 412 &lor_output_mixer_controls[0], 413 ARRAY_SIZE(lor_output_mixer_controls)), 414 SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0), 415 416 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0), 417 SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 418 in1r_to_rmixer_controls), 419 SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 420 in2r_to_rmixer_controls), 421 SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 422 in3r_to_rmixer_controls), 423 SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 424 in2l_to_rmixer_controls), 425 SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 426 cmr_to_rmixer_controls), 427 SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 428 in1l_to_rmixer_controls), 429 SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 430 in3l_to_rmixer_controls), 431 432 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0), 433 SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 434 in1l_to_lmixer_controls), 435 SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 436 in2l_to_lmixer_controls), 437 SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 438 in3l_to_lmixer_controls), 439 SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0, 440 in1r_to_lmixer_controls), 441 SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 442 cml_to_lmixer_controls), 443 SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 444 in2r_to_lmixer_controls), 445 SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0, 446 in3r_to_lmixer_controls), 447 448 SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event, 449 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 450 451 452 SND_SOC_DAPM_OUTPUT("HPL"), 453 SND_SOC_DAPM_OUTPUT("HPR"), 454 SND_SOC_DAPM_OUTPUT("LOL"), 455 SND_SOC_DAPM_OUTPUT("LOR"), 456 SND_SOC_DAPM_INPUT("IN1_L"), 457 SND_SOC_DAPM_INPUT("IN1_R"), 458 SND_SOC_DAPM_INPUT("IN2_L"), 459 SND_SOC_DAPM_INPUT("IN2_R"), 460 SND_SOC_DAPM_INPUT("IN3_L"), 461 SND_SOC_DAPM_INPUT("IN3_R"), 462 SND_SOC_DAPM_INPUT("CM_L"), 463 SND_SOC_DAPM_INPUT("CM_R"), 464 }; 465 466 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = { 467 /* Left Output */ 468 {"HPL Output Mixer", "L_DAC Switch", "Left DAC"}, 469 {"HPL Output Mixer", "IN1_L Switch", "IN1_L"}, 470 471 {"HPL Power", NULL, "HPL Output Mixer"}, 472 {"HPL", NULL, "HPL Power"}, 473 474 {"LOL Output Mixer", "L_DAC Switch", "Left DAC"}, 475 476 {"LOL Power", NULL, "LOL Output Mixer"}, 477 {"LOL", NULL, "LOL Power"}, 478 479 /* Right Output */ 480 {"HPR Output Mixer", "R_DAC Switch", "Right DAC"}, 481 {"HPR Output Mixer", "IN1_R Switch", "IN1_R"}, 482 483 {"HPR Power", NULL, "HPR Output Mixer"}, 484 {"HPR", NULL, "HPR Power"}, 485 486 {"LOR Output Mixer", "R_DAC Switch", "Right DAC"}, 487 488 {"LOR Power", NULL, "LOR Output Mixer"}, 489 {"LOR", NULL, "LOR Power"}, 490 491 /* Right Input */ 492 {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"}, 493 {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 494 {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 495 {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 496 497 {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"}, 498 {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"}, 499 {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"}, 500 {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"}, 501 502 {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"}, 503 {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"}, 504 {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"}, 505 {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"}, 506 507 {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"}, 508 {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 509 {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 510 {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 511 512 {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"}, 513 {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"}, 514 {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"}, 515 {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"}, 516 517 {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"}, 518 {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"}, 519 {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"}, 520 {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"}, 521 522 {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"}, 523 {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"}, 524 {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"}, 525 {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"}, 526 527 /* Left Input */ 528 {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"}, 529 {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"}, 530 {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"}, 531 {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"}, 532 533 {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"}, 534 {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"}, 535 {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"}, 536 {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"}, 537 538 {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"}, 539 {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"}, 540 {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"}, 541 {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"}, 542 543 {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"}, 544 {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"}, 545 {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"}, 546 {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"}, 547 548 {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"}, 549 {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"}, 550 {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"}, 551 {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"}, 552 553 {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"}, 554 {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"}, 555 {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"}, 556 {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"}, 557 558 {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"}, 559 {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"}, 560 {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"}, 561 {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"}, 562 }; 563 564 static const struct regmap_range_cfg aic32x4_regmap_pages[] = { 565 { 566 .selector_reg = 0, 567 .selector_mask = 0xff, 568 .window_start = 0, 569 .window_len = 128, 570 .range_min = 0, 571 .range_max = AIC32X4_RMICPGAVOL, 572 }, 573 }; 574 575 const struct regmap_config aic32x4_regmap_config = { 576 .max_register = AIC32X4_RMICPGAVOL, 577 .ranges = aic32x4_regmap_pages, 578 .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages), 579 }; 580 EXPORT_SYMBOL(aic32x4_regmap_config); 581 582 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai, 583 int clk_id, unsigned int freq, int dir) 584 { 585 struct snd_soc_component *component = codec_dai->component; 586 struct clk *mclk; 587 struct clk *pll; 588 589 pll = devm_clk_get(component->dev, "pll"); 590 mclk = clk_get_parent(pll); 591 592 return clk_set_rate(mclk, freq); 593 } 594 595 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 596 { 597 struct snd_soc_component *component = codec_dai->component; 598 u8 iface_reg_1 = 0; 599 u8 iface_reg_2 = 0; 600 u8 iface_reg_3 = 0; 601 602 /* set master/slave audio interface */ 603 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 604 case SND_SOC_DAIFMT_CBM_CFM: 605 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER; 606 break; 607 case SND_SOC_DAIFMT_CBS_CFS: 608 break; 609 default: 610 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n"); 611 return -EINVAL; 612 } 613 614 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 615 case SND_SOC_DAIFMT_I2S: 616 break; 617 case SND_SOC_DAIFMT_DSP_A: 618 iface_reg_1 |= (AIC32X4_DSP_MODE << 619 AIC32X4_IFACE1_DATATYPE_SHIFT); 620 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 621 iface_reg_2 = 0x01; /* add offset 1 */ 622 break; 623 case SND_SOC_DAIFMT_DSP_B: 624 iface_reg_1 |= (AIC32X4_DSP_MODE << 625 AIC32X4_IFACE1_DATATYPE_SHIFT); 626 iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */ 627 break; 628 case SND_SOC_DAIFMT_RIGHT_J: 629 iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE << 630 AIC32X4_IFACE1_DATATYPE_SHIFT); 631 break; 632 case SND_SOC_DAIFMT_LEFT_J: 633 iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE << 634 AIC32X4_IFACE1_DATATYPE_SHIFT); 635 break; 636 default: 637 printk(KERN_ERR "aic32x4: invalid DAI interface format\n"); 638 return -EINVAL; 639 } 640 641 snd_soc_component_update_bits(component, AIC32X4_IFACE1, 642 AIC32X4_IFACE1_DATATYPE_MASK | 643 AIC32X4_IFACE1_MASTER_MASK, iface_reg_1); 644 snd_soc_component_update_bits(component, AIC32X4_IFACE2, 645 AIC32X4_DATA_OFFSET_MASK, iface_reg_2); 646 snd_soc_component_update_bits(component, AIC32X4_IFACE3, 647 AIC32X4_BCLKINV_MASK, iface_reg_3); 648 649 return 0; 650 } 651 652 static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr) 653 { 654 return snd_soc_component_write(component, AIC32X4_AOSR, aosr); 655 } 656 657 static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr) 658 { 659 snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8); 660 snd_soc_component_write(component, AIC32X4_DOSRLSB, 661 (dosr & 0xff)); 662 663 return 0; 664 } 665 666 static int aic32x4_set_processing_blocks(struct snd_soc_component *component, 667 u8 r_block, u8 p_block) 668 { 669 if (r_block > 18 || p_block > 25) 670 return -EINVAL; 671 672 snd_soc_component_write(component, AIC32X4_ADCSPB, r_block); 673 snd_soc_component_write(component, AIC32X4_DACSPB, p_block); 674 675 return 0; 676 } 677 678 static int aic32x4_setup_clocks(struct snd_soc_component *component, 679 unsigned int sample_rate) 680 { 681 u8 aosr; 682 u16 dosr; 683 u8 adc_resource_class, dac_resource_class; 684 u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac; 685 u8 dosr_increment; 686 u16 max_dosr, min_dosr; 687 unsigned long adc_clock_rate, dac_clock_rate; 688 int ret; 689 690 struct clk_bulk_data clocks[] = { 691 { .id = "pll" }, 692 { .id = "nadc" }, 693 { .id = "madc" }, 694 { .id = "ndac" }, 695 { .id = "mdac" }, 696 { .id = "bdiv" }, 697 }; 698 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 699 if (ret) 700 return ret; 701 702 if (sample_rate <= 48000) { 703 aosr = 128; 704 adc_resource_class = 6; 705 dac_resource_class = 8; 706 dosr_increment = 8; 707 aic32x4_set_processing_blocks(component, 1, 1); 708 } else if (sample_rate <= 96000) { 709 aosr = 64; 710 adc_resource_class = 6; 711 dac_resource_class = 8; 712 dosr_increment = 4; 713 aic32x4_set_processing_blocks(component, 1, 9); 714 } else if (sample_rate == 192000) { 715 aosr = 32; 716 adc_resource_class = 3; 717 dac_resource_class = 4; 718 dosr_increment = 2; 719 aic32x4_set_processing_blocks(component, 13, 19); 720 } else { 721 dev_err(component->dev, "Sampling rate not supported\n"); 722 return -EINVAL; 723 } 724 725 madc = DIV_ROUND_UP((32 * adc_resource_class), aosr); 726 max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) * 727 dosr_increment; 728 min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) * 729 dosr_increment; 730 max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate); 731 732 for (nadc = max_nadc; nadc > 0; --nadc) { 733 adc_clock_rate = nadc * madc * aosr * sample_rate; 734 for (dosr = max_dosr; dosr >= min_dosr; 735 dosr -= dosr_increment) { 736 min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr); 737 max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ / 738 (min_mdac * dosr * sample_rate); 739 for (mdac = min_mdac; mdac <= 128; ++mdac) { 740 for (ndac = max_ndac; ndac > 0; --ndac) { 741 dac_clock_rate = ndac * mdac * dosr * 742 sample_rate; 743 if (dac_clock_rate == adc_clock_rate) { 744 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0) 745 continue; 746 747 clk_set_rate(clocks[0].clk, 748 dac_clock_rate); 749 750 clk_set_rate(clocks[1].clk, 751 sample_rate * aosr * 752 madc); 753 clk_set_rate(clocks[2].clk, 754 sample_rate * aosr); 755 aic32x4_set_aosr(component, 756 aosr); 757 758 clk_set_rate(clocks[3].clk, 759 sample_rate * dosr * 760 mdac); 761 clk_set_rate(clocks[4].clk, 762 sample_rate * dosr); 763 aic32x4_set_dosr(component, 764 dosr); 765 766 clk_set_rate(clocks[5].clk, 767 sample_rate * 32); 768 return 0; 769 } 770 } 771 } 772 } 773 } 774 775 dev_err(component->dev, 776 "Could not set clocks to support sample rate.\n"); 777 return -EINVAL; 778 } 779 780 static int aic32x4_hw_params(struct snd_pcm_substream *substream, 781 struct snd_pcm_hw_params *params, 782 struct snd_soc_dai *dai) 783 { 784 struct snd_soc_component *component = dai->component; 785 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 786 u8 iface1_reg = 0; 787 u8 dacsetup_reg = 0; 788 789 aic32x4_setup_clocks(component, params_rate(params)); 790 791 switch (params_width(params)) { 792 case 16: 793 iface1_reg |= (AIC32X4_WORD_LEN_16BITS << 794 AIC32X4_IFACE1_DATALEN_SHIFT); 795 break; 796 case 20: 797 iface1_reg |= (AIC32X4_WORD_LEN_20BITS << 798 AIC32X4_IFACE1_DATALEN_SHIFT); 799 break; 800 case 24: 801 iface1_reg |= (AIC32X4_WORD_LEN_24BITS << 802 AIC32X4_IFACE1_DATALEN_SHIFT); 803 break; 804 case 32: 805 iface1_reg |= (AIC32X4_WORD_LEN_32BITS << 806 AIC32X4_IFACE1_DATALEN_SHIFT); 807 break; 808 } 809 snd_soc_component_update_bits(component, AIC32X4_IFACE1, 810 AIC32X4_IFACE1_DATALEN_MASK, iface1_reg); 811 812 if (params_channels(params) == 1) { 813 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN; 814 } else { 815 if (aic32x4->swapdacs) 816 dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN; 817 else 818 dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN; 819 } 820 snd_soc_component_update_bits(component, AIC32X4_DACSETUP, 821 AIC32X4_DAC_CHAN_MASK, dacsetup_reg); 822 823 return 0; 824 } 825 826 static int aic32x4_mute(struct snd_soc_dai *dai, int mute) 827 { 828 struct snd_soc_component *component = dai->component; 829 830 snd_soc_component_update_bits(component, AIC32X4_DACMUTE, 831 AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0); 832 833 return 0; 834 } 835 836 static int aic32x4_set_bias_level(struct snd_soc_component *component, 837 enum snd_soc_bias_level level) 838 { 839 int ret; 840 841 struct clk_bulk_data clocks[] = { 842 { .id = "madc" }, 843 { .id = "mdac" }, 844 { .id = "bdiv" }, 845 }; 846 847 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 848 if (ret) 849 return ret; 850 851 switch (level) { 852 case SND_SOC_BIAS_ON: 853 ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks); 854 if (ret) { 855 dev_err(component->dev, "Failed to enable clocks\n"); 856 return ret; 857 } 858 break; 859 case SND_SOC_BIAS_PREPARE: 860 break; 861 case SND_SOC_BIAS_STANDBY: 862 /* Initial cold start */ 863 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 864 break; 865 866 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); 867 break; 868 case SND_SOC_BIAS_OFF: 869 break; 870 } 871 return 0; 872 } 873 874 #define AIC32X4_RATES SNDRV_PCM_RATE_8000_192000 875 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 876 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 877 878 static const struct snd_soc_dai_ops aic32x4_ops = { 879 .hw_params = aic32x4_hw_params, 880 .digital_mute = aic32x4_mute, 881 .set_fmt = aic32x4_set_dai_fmt, 882 .set_sysclk = aic32x4_set_dai_sysclk, 883 }; 884 885 static struct snd_soc_dai_driver aic32x4_dai = { 886 .name = "tlv320aic32x4-hifi", 887 .playback = { 888 .stream_name = "Playback", 889 .channels_min = 1, 890 .channels_max = 2, 891 .rates = AIC32X4_RATES, 892 .formats = AIC32X4_FORMATS,}, 893 .capture = { 894 .stream_name = "Capture", 895 .channels_min = 1, 896 .channels_max = 2, 897 .rates = AIC32X4_RATES, 898 .formats = AIC32X4_FORMATS,}, 899 .ops = &aic32x4_ops, 900 .symmetric_rates = 1, 901 }; 902 903 static void aic32x4_setup_gpios(struct snd_soc_component *component) 904 { 905 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 906 907 /* setup GPIO functions */ 908 /* MFP1 */ 909 if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) { 910 snd_soc_component_write(component, AIC32X4_DINCTL, 911 aic32x4->setup->gpio_func[0]); 912 snd_soc_add_component_controls(component, aic32x4_mfp1, 913 ARRAY_SIZE(aic32x4_mfp1)); 914 } 915 916 /* MFP2 */ 917 if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) { 918 snd_soc_component_write(component, AIC32X4_DOUTCTL, 919 aic32x4->setup->gpio_func[1]); 920 snd_soc_add_component_controls(component, aic32x4_mfp2, 921 ARRAY_SIZE(aic32x4_mfp2)); 922 } 923 924 /* MFP3 */ 925 if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) { 926 snd_soc_component_write(component, AIC32X4_SCLKCTL, 927 aic32x4->setup->gpio_func[2]); 928 snd_soc_add_component_controls(component, aic32x4_mfp3, 929 ARRAY_SIZE(aic32x4_mfp3)); 930 } 931 932 /* MFP4 */ 933 if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) { 934 snd_soc_component_write(component, AIC32X4_MISOCTL, 935 aic32x4->setup->gpio_func[3]); 936 snd_soc_add_component_controls(component, aic32x4_mfp4, 937 ARRAY_SIZE(aic32x4_mfp4)); 938 } 939 940 /* MFP5 */ 941 if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) { 942 snd_soc_component_write(component, AIC32X4_GPIOCTL, 943 aic32x4->setup->gpio_func[4]); 944 snd_soc_add_component_controls(component, aic32x4_mfp5, 945 ARRAY_SIZE(aic32x4_mfp5)); 946 } 947 } 948 949 static int aic32x4_component_probe(struct snd_soc_component *component) 950 { 951 struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component); 952 u32 tmp_reg; 953 int ret; 954 955 struct clk_bulk_data clocks[] = { 956 { .id = "codec_clkin" }, 957 { .id = "pll" }, 958 { .id = "bdiv" }, 959 { .id = "mdac" }, 960 }; 961 962 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 963 if (ret) 964 return ret; 965 966 if (gpio_is_valid(aic32x4->rstn_gpio)) { 967 ndelay(10); 968 gpio_set_value(aic32x4->rstn_gpio, 1); 969 mdelay(1); 970 } 971 972 snd_soc_component_write(component, AIC32X4_RESET, 0x01); 973 974 if (aic32x4->setup) 975 aic32x4_setup_gpios(component); 976 977 clk_set_parent(clocks[0].clk, clocks[1].clk); 978 clk_set_parent(clocks[2].clk, clocks[3].clk); 979 980 /* Power platform configuration */ 981 if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) { 982 snd_soc_component_write(component, AIC32X4_MICBIAS, 983 AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V); 984 } 985 if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) 986 snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE); 987 988 tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ? 989 AIC32X4_LDOCTLEN : 0; 990 snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg); 991 992 tmp_reg = snd_soc_component_read32(component, AIC32X4_CMMODE); 993 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) 994 tmp_reg |= AIC32X4_LDOIN_18_36; 995 if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) 996 tmp_reg |= AIC32X4_LDOIN2HP; 997 snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg); 998 999 /* Mic PGA routing */ 1000 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) 1001 snd_soc_component_write(component, AIC32X4_LMICPGANIN, 1002 AIC32X4_LMICPGANIN_IN2R_10K); 1003 else 1004 snd_soc_component_write(component, AIC32X4_LMICPGANIN, 1005 AIC32X4_LMICPGANIN_CM1L_10K); 1006 if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) 1007 snd_soc_component_write(component, AIC32X4_RMICPGANIN, 1008 AIC32X4_RMICPGANIN_IN1L_10K); 1009 else 1010 snd_soc_component_write(component, AIC32X4_RMICPGANIN, 1011 AIC32X4_RMICPGANIN_CM1R_10K); 1012 1013 /* 1014 * Workaround: for an unknown reason, the ADC needs to be powered up 1015 * and down for the first capture to work properly. It seems related to 1016 * a HW BUG or some kind of behavior not documented in the datasheet. 1017 */ 1018 tmp_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); 1019 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg | 1020 AIC32X4_LADC_EN | AIC32X4_RADC_EN); 1021 snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg); 1022 1023 return 0; 1024 } 1025 1026 static const struct snd_soc_component_driver soc_component_dev_aic32x4 = { 1027 .probe = aic32x4_component_probe, 1028 .set_bias_level = aic32x4_set_bias_level, 1029 .controls = aic32x4_snd_controls, 1030 .num_controls = ARRAY_SIZE(aic32x4_snd_controls), 1031 .dapm_widgets = aic32x4_dapm_widgets, 1032 .num_dapm_widgets = ARRAY_SIZE(aic32x4_dapm_widgets), 1033 .dapm_routes = aic32x4_dapm_routes, 1034 .num_dapm_routes = ARRAY_SIZE(aic32x4_dapm_routes), 1035 .suspend_bias_off = 1, 1036 .idle_bias_on = 1, 1037 .use_pmdown_time = 1, 1038 .endianness = 1, 1039 .non_legacy_dai_naming = 1, 1040 }; 1041 1042 static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4, 1043 struct device_node *np) 1044 { 1045 struct aic32x4_setup_data *aic32x4_setup; 1046 int ret; 1047 1048 aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup), 1049 GFP_KERNEL); 1050 if (!aic32x4_setup) 1051 return -ENOMEM; 1052 1053 ret = of_property_match_string(np, "clock-names", "mclk"); 1054 if (ret < 0) 1055 return -EINVAL; 1056 aic32x4->mclk_name = of_clk_get_parent_name(np, ret); 1057 1058 aic32x4->swapdacs = false; 1059 aic32x4->micpga_routing = 0; 1060 aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0); 1061 1062 if (of_property_read_u32_array(np, "aic32x4-gpio-func", 1063 aic32x4_setup->gpio_func, 5) >= 0) 1064 aic32x4->setup = aic32x4_setup; 1065 return 0; 1066 } 1067 1068 static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4) 1069 { 1070 regulator_disable(aic32x4->supply_iov); 1071 1072 if (!IS_ERR(aic32x4->supply_ldo)) 1073 regulator_disable(aic32x4->supply_ldo); 1074 1075 if (!IS_ERR(aic32x4->supply_dv)) 1076 regulator_disable(aic32x4->supply_dv); 1077 1078 if (!IS_ERR(aic32x4->supply_av)) 1079 regulator_disable(aic32x4->supply_av); 1080 } 1081 1082 static int aic32x4_setup_regulators(struct device *dev, 1083 struct aic32x4_priv *aic32x4) 1084 { 1085 int ret = 0; 1086 1087 aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin"); 1088 aic32x4->supply_iov = devm_regulator_get(dev, "iov"); 1089 aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv"); 1090 aic32x4->supply_av = devm_regulator_get_optional(dev, "av"); 1091 1092 /* Check if the regulator requirements are fulfilled */ 1093 1094 if (IS_ERR(aic32x4->supply_iov)) { 1095 dev_err(dev, "Missing supply 'iov'\n"); 1096 return PTR_ERR(aic32x4->supply_iov); 1097 } 1098 1099 if (IS_ERR(aic32x4->supply_ldo)) { 1100 if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER) 1101 return -EPROBE_DEFER; 1102 1103 if (IS_ERR(aic32x4->supply_dv)) { 1104 dev_err(dev, "Missing supply 'dv' or 'ldoin'\n"); 1105 return PTR_ERR(aic32x4->supply_dv); 1106 } 1107 if (IS_ERR(aic32x4->supply_av)) { 1108 dev_err(dev, "Missing supply 'av' or 'ldoin'\n"); 1109 return PTR_ERR(aic32x4->supply_av); 1110 } 1111 } else { 1112 if (IS_ERR(aic32x4->supply_dv) && 1113 PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER) 1114 return -EPROBE_DEFER; 1115 if (IS_ERR(aic32x4->supply_av) && 1116 PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER) 1117 return -EPROBE_DEFER; 1118 } 1119 1120 ret = regulator_enable(aic32x4->supply_iov); 1121 if (ret) { 1122 dev_err(dev, "Failed to enable regulator iov\n"); 1123 return ret; 1124 } 1125 1126 if (!IS_ERR(aic32x4->supply_ldo)) { 1127 ret = regulator_enable(aic32x4->supply_ldo); 1128 if (ret) { 1129 dev_err(dev, "Failed to enable regulator ldo\n"); 1130 goto error_ldo; 1131 } 1132 } 1133 1134 if (!IS_ERR(aic32x4->supply_dv)) { 1135 ret = regulator_enable(aic32x4->supply_dv); 1136 if (ret) { 1137 dev_err(dev, "Failed to enable regulator dv\n"); 1138 goto error_dv; 1139 } 1140 } 1141 1142 if (!IS_ERR(aic32x4->supply_av)) { 1143 ret = regulator_enable(aic32x4->supply_av); 1144 if (ret) { 1145 dev_err(dev, "Failed to enable regulator av\n"); 1146 goto error_av; 1147 } 1148 } 1149 1150 if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av)) 1151 aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE; 1152 1153 return 0; 1154 1155 error_av: 1156 if (!IS_ERR(aic32x4->supply_dv)) 1157 regulator_disable(aic32x4->supply_dv); 1158 1159 error_dv: 1160 if (!IS_ERR(aic32x4->supply_ldo)) 1161 regulator_disable(aic32x4->supply_ldo); 1162 1163 error_ldo: 1164 regulator_disable(aic32x4->supply_iov); 1165 return ret; 1166 } 1167 1168 int aic32x4_probe(struct device *dev, struct regmap *regmap) 1169 { 1170 struct aic32x4_priv *aic32x4; 1171 struct aic32x4_pdata *pdata = dev->platform_data; 1172 struct device_node *np = dev->of_node; 1173 int ret; 1174 1175 if (IS_ERR(regmap)) 1176 return PTR_ERR(regmap); 1177 1178 aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv), 1179 GFP_KERNEL); 1180 if (aic32x4 == NULL) 1181 return -ENOMEM; 1182 1183 aic32x4->dev = dev; 1184 dev_set_drvdata(dev, aic32x4); 1185 1186 if (pdata) { 1187 aic32x4->power_cfg = pdata->power_cfg; 1188 aic32x4->swapdacs = pdata->swapdacs; 1189 aic32x4->micpga_routing = pdata->micpga_routing; 1190 aic32x4->rstn_gpio = pdata->rstn_gpio; 1191 aic32x4->mclk_name = "mclk"; 1192 } else if (np) { 1193 ret = aic32x4_parse_dt(aic32x4, np); 1194 if (ret) { 1195 dev_err(dev, "Failed to parse DT node\n"); 1196 return ret; 1197 } 1198 } else { 1199 aic32x4->power_cfg = 0; 1200 aic32x4->swapdacs = false; 1201 aic32x4->micpga_routing = 0; 1202 aic32x4->rstn_gpio = -1; 1203 aic32x4->mclk_name = "mclk"; 1204 } 1205 1206 ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); 1207 if (ret) 1208 return ret; 1209 1210 if (gpio_is_valid(aic32x4->rstn_gpio)) { 1211 ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, 1212 GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); 1213 if (ret != 0) 1214 return ret; 1215 } 1216 1217 ret = aic32x4_setup_regulators(dev, aic32x4); 1218 if (ret) { 1219 dev_err(dev, "Failed to setup regulators\n"); 1220 return ret; 1221 } 1222 1223 ret = devm_snd_soc_register_component(dev, 1224 &soc_component_dev_aic32x4, &aic32x4_dai, 1); 1225 if (ret) { 1226 dev_err(dev, "Failed to register component\n"); 1227 aic32x4_disable_regulators(aic32x4); 1228 return ret; 1229 } 1230 1231 return 0; 1232 } 1233 EXPORT_SYMBOL(aic32x4_probe); 1234 1235 int aic32x4_remove(struct device *dev) 1236 { 1237 struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev); 1238 1239 aic32x4_disable_regulators(aic32x4); 1240 1241 return 0; 1242 } 1243 EXPORT_SYMBOL(aic32x4_remove); 1244 1245 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver"); 1246 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>"); 1247 MODULE_LICENSE("GPL"); 1248