1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ALSA SoC TLV320AIC31xx CODEC Driver Definitions 4 * 5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8 #ifndef _TLV320AIC31XX_H 9 #define _TLV320AIC31XX_H 10 11 #define AIC31XX_RATES SNDRV_PCM_RATE_8000_192000 12 13 #define AIC31XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 14 SNDRV_PCM_FMTBIT_S20_3LE | \ 15 SNDRV_PCM_FMTBIT_S24_3LE | \ 16 SNDRV_PCM_FMTBIT_S24_LE | \ 17 SNDRV_PCM_FMTBIT_S32_LE) 18 19 #define AIC31XX_STEREO_CLASS_D_BIT BIT(1) 20 #define AIC31XX_MINIDSP_BIT BIT(2) 21 #define DAC31XX_BIT BIT(3) 22 23 #define AIC31XX_JACK_MASK (SND_JACK_HEADPHONE | \ 24 SND_JACK_HEADSET | \ 25 SND_JACK_BTN_0) 26 27 enum aic31xx_type { 28 AIC3100 = 0, 29 AIC3110 = AIC31XX_STEREO_CLASS_D_BIT, 30 AIC3120 = AIC31XX_MINIDSP_BIT, 31 AIC3111 = AIC31XX_STEREO_CLASS_D_BIT | AIC31XX_MINIDSP_BIT, 32 DAC3100 = DAC31XX_BIT, 33 DAC3101 = DAC31XX_BIT | AIC31XX_STEREO_CLASS_D_BIT, 34 }; 35 36 struct aic31xx_pdata { 37 enum aic31xx_type codec_type; 38 unsigned int gpio_reset; 39 int micbias_vg; 40 }; 41 42 #define AIC31XX_REG(page, reg) ((page * 128) + reg) 43 44 #define AIC31XX_PAGECTL AIC31XX_REG(0, 0) /* Page Control Register */ 45 46 /* Page 0 Registers */ 47 #define AIC31XX_RESET AIC31XX_REG(0, 1) /* Software reset register */ 48 #define AIC31XX_OT_FLAG AIC31XX_REG(0, 3) /* OT FLAG register */ 49 #define AIC31XX_CLKMUX AIC31XX_REG(0, 4) /* Clock clock Gen muxing, Multiplexers*/ 50 #define AIC31XX_PLLPR AIC31XX_REG(0, 5) /* PLL P and R-VAL register */ 51 #define AIC31XX_PLLJ AIC31XX_REG(0, 6) /* PLL J-VAL register */ 52 #define AIC31XX_PLLDMSB AIC31XX_REG(0, 7) /* PLL D-VAL MSB register */ 53 #define AIC31XX_PLLDLSB AIC31XX_REG(0, 8) /* PLL D-VAL LSB register */ 54 #define AIC31XX_NDAC AIC31XX_REG(0, 11) /* DAC NDAC_VAL register*/ 55 #define AIC31XX_MDAC AIC31XX_REG(0, 12) /* DAC MDAC_VAL register */ 56 #define AIC31XX_DOSRMSB AIC31XX_REG(0, 13) /* DAC OSR setting register 1, MSB value */ 57 #define AIC31XX_DOSRLSB AIC31XX_REG(0, 14) /* DAC OSR setting register 2, LSB value */ 58 #define AIC31XX_MINI_DSP_INPOL AIC31XX_REG(0, 16) 59 #define AIC31XX_NADC AIC31XX_REG(0, 18) /* Clock setting register 8, PLL */ 60 #define AIC31XX_MADC AIC31XX_REG(0, 19) /* Clock setting register 9, PLL */ 61 #define AIC31XX_AOSR AIC31XX_REG(0, 20) /* ADC Oversampling (AOSR) Register */ 62 #define AIC31XX_CLKOUTMUX AIC31XX_REG(0, 25) /* Clock setting register 9, Multiplexers */ 63 #define AIC31XX_CLKOUTMVAL AIC31XX_REG(0, 26) /* Clock setting register 10, CLOCKOUT M divider value */ 64 #define AIC31XX_IFACE1 AIC31XX_REG(0, 27) /* Audio Interface Setting Register 1 */ 65 #define AIC31XX_DATA_OFFSET AIC31XX_REG(0, 28) /* Audio Data Slot Offset Programming */ 66 #define AIC31XX_IFACE2 AIC31XX_REG(0, 29) /* Audio Interface Setting Register 2 */ 67 #define AIC31XX_BCLKN AIC31XX_REG(0, 30) /* Clock setting register 11, BCLK N Divider */ 68 #define AIC31XX_IFACESEC1 AIC31XX_REG(0, 31) /* Audio Interface Setting Register 3, Secondary Audio Interface */ 69 #define AIC31XX_IFACESEC2 AIC31XX_REG(0, 32) /* Audio Interface Setting Register 4 */ 70 #define AIC31XX_IFACESEC3 AIC31XX_REG(0, 33) /* Audio Interface Setting Register 5 */ 71 #define AIC31XX_I2C AIC31XX_REG(0, 34) /* I2C Bus Condition */ 72 #define AIC31XX_ADCFLAG AIC31XX_REG(0, 36) /* ADC FLAG */ 73 #define AIC31XX_DACFLAG1 AIC31XX_REG(0, 37) /* DAC Flag Registers */ 74 #define AIC31XX_DACFLAG2 AIC31XX_REG(0, 38) 75 #define AIC31XX_OFFLAG AIC31XX_REG(0, 39) /* Sticky Interrupt flag (overflow) */ 76 #define AIC31XX_INTRDACFLAG AIC31XX_REG(0, 44) /* Sticy DAC Interrupt flags */ 77 #define AIC31XX_INTRADCFLAG AIC31XX_REG(0, 45) /* Sticy ADC Interrupt flags */ 78 #define AIC31XX_INTRDACFLAG2 AIC31XX_REG(0, 46) /* DAC Interrupt flags 2 */ 79 #define AIC31XX_INTRADCFLAG2 AIC31XX_REG(0, 47) /* ADC Interrupt flags 2 */ 80 #define AIC31XX_INT1CTRL AIC31XX_REG(0, 48) /* INT1 interrupt control */ 81 #define AIC31XX_INT2CTRL AIC31XX_REG(0, 49) /* INT2 interrupt control */ 82 #define AIC31XX_GPIO1 AIC31XX_REG(0, 51) /* GPIO1 control */ 83 #define AIC31XX_DACPRB AIC31XX_REG(0, 60) 84 #define AIC31XX_ADCPRB AIC31XX_REG(0, 61) /* ADC Instruction Set Register */ 85 #define AIC31XX_DACSETUP AIC31XX_REG(0, 63) /* DAC channel setup register */ 86 #define AIC31XX_DACMUTE AIC31XX_REG(0, 64) /* DAC Mute and volume control register */ 87 #define AIC31XX_LDACVOL AIC31XX_REG(0, 65) /* Left DAC channel digital volume control */ 88 #define AIC31XX_RDACVOL AIC31XX_REG(0, 66) /* Right DAC channel digital volume control */ 89 #define AIC31XX_HSDETECT AIC31XX_REG(0, 67) /* Headset detection */ 90 #define AIC31XX_ADCSETUP AIC31XX_REG(0, 81) /* ADC Digital Mic */ 91 #define AIC31XX_ADCFGA AIC31XX_REG(0, 82) /* ADC Digital Volume Control Fine Adjust */ 92 #define AIC31XX_ADCVOL AIC31XX_REG(0, 83) /* ADC Digital Volume Control Coarse Adjust */ 93 94 /* Page 1 Registers */ 95 #define AIC31XX_HPDRIVER AIC31XX_REG(1, 31) /* Headphone drivers */ 96 #define AIC31XX_SPKAMP AIC31XX_REG(1, 32) /* Class-D Speakear Amplifier */ 97 #define AIC31XX_HPPOP AIC31XX_REG(1, 33) /* HP Output Drivers POP Removal Settings */ 98 #define AIC31XX_SPPGARAMP AIC31XX_REG(1, 34) /* Output Driver PGA Ramp-Down Period Control */ 99 #define AIC31XX_DACMIXERROUTE AIC31XX_REG(1, 35) /* DAC_L and DAC_R Output Mixer Routing */ 100 #define AIC31XX_LANALOGHPL AIC31XX_REG(1, 36) /* Left Analog Vol to HPL */ 101 #define AIC31XX_RANALOGHPR AIC31XX_REG(1, 37) /* Right Analog Vol to HPR */ 102 #define AIC31XX_LANALOGSPL AIC31XX_REG(1, 38) /* Left Analog Vol to SPL */ 103 #define AIC31XX_RANALOGSPR AIC31XX_REG(1, 39) /* Right Analog Vol to SPR */ 104 #define AIC31XX_HPLGAIN AIC31XX_REG(1, 40) /* HPL Driver */ 105 #define AIC31XX_HPRGAIN AIC31XX_REG(1, 41) /* HPR Driver */ 106 #define AIC31XX_SPLGAIN AIC31XX_REG(1, 42) /* SPL Driver */ 107 #define AIC31XX_SPRGAIN AIC31XX_REG(1, 43) /* SPR Driver */ 108 #define AIC31XX_HPCONTROL AIC31XX_REG(1, 44) /* HP Driver Control */ 109 #define AIC31XX_MICBIAS AIC31XX_REG(1, 46) /* MIC Bias Control */ 110 #define AIC31XX_MICPGA AIC31XX_REG(1, 47) /* MIC PGA*/ 111 #define AIC31XX_MICPGAPI AIC31XX_REG(1, 48) /* Delta-Sigma Mono ADC Channel Fine-Gain Input Selection for P-Terminal */ 112 #define AIC31XX_MICPGAMI AIC31XX_REG(1, 49) /* ADC Input Selection for M-Terminal */ 113 #define AIC31XX_MICPGACM AIC31XX_REG(1, 50) /* Input CM Settings */ 114 115 /* Bits, masks, and shifts */ 116 117 /* AIC31XX_CLKMUX */ 118 #define AIC31XX_PLL_CLKIN_MASK GENMASK(3, 2) 119 #define AIC31XX_PLL_CLKIN_SHIFT (2) 120 #define AIC31XX_PLL_CLKIN_MCLK 0x00 121 #define AIC31XX_PLL_CLKIN_BCKL 0x01 122 #define AIC31XX_PLL_CLKIN_GPIO1 0x02 123 #define AIC31XX_PLL_CLKIN_DIN 0x03 124 #define AIC31XX_CODEC_CLKIN_MASK GENMASK(1, 0) 125 #define AIC31XX_CODEC_CLKIN_SHIFT (0) 126 #define AIC31XX_CODEC_CLKIN_MCLK 0x00 127 #define AIC31XX_CODEC_CLKIN_BCLK 0x01 128 #define AIC31XX_CODEC_CLKIN_GPIO1 0x02 129 #define AIC31XX_CODEC_CLKIN_PLL 0x03 130 131 /* AIC31XX_PLLPR */ 132 /* AIC31XX_NDAC */ 133 /* AIC31XX_MDAC */ 134 /* AIC31XX_NADC */ 135 /* AIC31XX_MADC */ 136 /* AIC31XX_BCLKN */ 137 #define AIC31XX_PLL_MASK GENMASK(6, 0) 138 #define AIC31XX_PM_MASK BIT(7) 139 140 /* AIC31XX_IFACE1 */ 141 #define AIC31XX_IFACE1_DATATYPE_MASK GENMASK(7, 6) 142 #define AIC31XX_IFACE1_DATATYPE_SHIFT (6) 143 #define AIC31XX_I2S_MODE 0x00 144 #define AIC31XX_DSP_MODE 0x01 145 #define AIC31XX_RIGHT_JUSTIFIED_MODE 0x02 146 #define AIC31XX_LEFT_JUSTIFIED_MODE 0x03 147 #define AIC31XX_IFACE1_DATALEN_MASK GENMASK(5, 4) 148 #define AIC31XX_IFACE1_DATALEN_SHIFT (4) 149 #define AIC31XX_WORD_LEN_16BITS 0x00 150 #define AIC31XX_WORD_LEN_20BITS 0x01 151 #define AIC31XX_WORD_LEN_24BITS 0x02 152 #define AIC31XX_WORD_LEN_32BITS 0x03 153 #define AIC31XX_IFACE1_MASTER_MASK GENMASK(3, 2) 154 #define AIC31XX_BCLK_MASTER BIT(3) 155 #define AIC31XX_WCLK_MASTER BIT(2) 156 157 /* AIC31XX_DATA_OFFSET */ 158 #define AIC31XX_DATA_OFFSET_MASK GENMASK(7, 0) 159 160 /* AIC31XX_IFACE2 */ 161 #define AIC31XX_BCLKINV_MASK BIT(3) 162 #define AIC31XX_BDIVCLK_MASK GENMASK(1, 0) 163 #define AIC31XX_DAC2BCLK 0x00 164 #define AIC31XX_DACMOD2BCLK 0x01 165 #define AIC31XX_ADC2BCLK 0x02 166 #define AIC31XX_ADCMOD2BCLK 0x03 167 #define AIC31XX_KEEP_I2SCLK BIT(2) 168 169 /* AIC31XX_ADCFLAG */ 170 #define AIC31XX_ADCPWRSTATUS_MASK BIT(6) 171 172 /* AIC31XX_DACFLAG1 */ 173 #define AIC31XX_LDACPWRSTATUS_MASK BIT(7) 174 #define AIC31XX_HPLDRVPWRSTATUS_MASK BIT(5) 175 #define AIC31XX_SPLDRVPWRSTATUS_MASK BIT(4) 176 #define AIC31XX_RDACPWRSTATUS_MASK BIT(3) 177 #define AIC31XX_HPRDRVPWRSTATUS_MASK BIT(1) 178 #define AIC31XX_SPRDRVPWRSTATUS_MASK BIT(0) 179 180 /* AIC31XX_OFFLAG */ 181 #define AIC31XX_DAC_OF_LEFT BIT(7) 182 #define AIC31XX_DAC_OF_RIGHT BIT(6) 183 #define AIC31XX_DAC_OF_SHIFTER BIT(5) 184 #define AIC31XX_ADC_OF BIT(3) 185 #define AIC31XX_ADC_OF_SHIFTER BIT(1) 186 187 /* AIC31XX_INTRDACFLAG */ 188 #define AIC31XX_HPLSCDETECT BIT(7) 189 #define AIC31XX_HPRSCDETECT BIT(6) 190 #define AIC31XX_BUTTONPRESS BIT(5) 191 #define AIC31XX_HSPLUG BIT(4) 192 #define AIC31XX_LDRCTHRES BIT(3) 193 #define AIC31XX_RDRCTHRES BIT(2) 194 #define AIC31XX_DACSINT BIT(1) 195 #define AIC31XX_DACAINT BIT(0) 196 197 /* AIC31XX_INT1CTRL */ 198 #define AIC31XX_HSPLUGDET BIT(7) 199 #define AIC31XX_BUTTONPRESSDET BIT(6) 200 #define AIC31XX_DRCTHRES BIT(5) 201 #define AIC31XX_AGCNOISE BIT(4) 202 #define AIC31XX_SC BIT(3) 203 #define AIC31XX_ENGINE BIT(2) 204 205 /* AIC31XX_GPIO1 */ 206 #define AIC31XX_GPIO1_FUNC_MASK GENMASK(5, 2) 207 #define AIC31XX_GPIO1_FUNC_SHIFT 2 208 #define AIC31XX_GPIO1_DISABLED 0x00 209 #define AIC31XX_GPIO1_INPUT 0x01 210 #define AIC31XX_GPIO1_GPI 0x02 211 #define AIC31XX_GPIO1_GPO 0x03 212 #define AIC31XX_GPIO1_CLKOUT 0x04 213 #define AIC31XX_GPIO1_INT1 0x05 214 #define AIC31XX_GPIO1_INT2 0x06 215 #define AIC31XX_GPIO1_ADC_WCLK 0x07 216 #define AIC31XX_GPIO1_SBCLK 0x08 217 #define AIC31XX_GPIO1_SWCLK 0x09 218 #define AIC31XX_GPIO1_ADC_MOD_CLK 0x10 219 #define AIC31XX_GPIO1_SDOUT 0x11 220 221 /* AIC31XX_DACMUTE */ 222 #define AIC31XX_DACMUTE_MASK GENMASK(3, 2) 223 224 /* AIC31XX_HSDETECT */ 225 #define AIC31XX_HSD_ENABLE BIT(7) 226 #define AIC31XX_HSD_TYPE_MASK GENMASK(6, 5) 227 #define AIC31XX_HSD_TYPE_SHIFT 5 228 #define AIC31XX_HSD_NONE 0x00 229 #define AIC31XX_HSD_HP 0x01 230 #define AIC31XX_HSD_HS 0x03 231 232 /* AIC31XX_HPDRIVER */ 233 #define AIC31XX_HPD_OCMV_MASK GENMASK(4, 3) 234 #define AIC31XX_HPD_OCMV_SHIFT 3 235 #define AIC31XX_HPD_OCMV_1_35V 0x0 236 #define AIC31XX_HPD_OCMV_1_5V 0x1 237 #define AIC31XX_HPD_OCMV_1_65V 0x2 238 #define AIC31XX_HPD_OCMV_1_8V 0x3 239 240 /* AIC31XX_MICBIAS */ 241 #define AIC31XX_MICBIAS_MASK GENMASK(1, 0) 242 #define AIC31XX_MICBIAS_SHIFT 0 243 244 #endif /* _TLV320AIC31XX_H */ 245