1 /* 2 * ALSA SoC TLV320AIC31XX codec driver 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * This package is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 13 * 14 */ 15 #ifndef _TLV320AIC31XX_H 16 #define _TLV320AIC31XX_H 17 18 #define AIC31XX_RATES SNDRV_PCM_RATE_8000_192000 19 20 #define AIC31XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 21 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \ 22 | SNDRV_PCM_FMTBIT_S32_LE) 23 24 25 #define AIC31XX_STEREO_CLASS_D_BIT 0x1 26 #define AIC31XX_MINIDSP_BIT 0x2 27 28 enum aic31xx_type { 29 AIC3100 = 0, 30 AIC3110 = AIC31XX_STEREO_CLASS_D_BIT, 31 AIC3120 = AIC31XX_MINIDSP_BIT, 32 AIC3111 = (AIC31XX_STEREO_CLASS_D_BIT | AIC31XX_MINIDSP_BIT), 33 }; 34 35 struct aic31xx_pdata { 36 enum aic31xx_type codec_type; 37 unsigned int gpio_reset; 38 int micbias_vg; 39 }; 40 41 #define AIC31XX_REG(page, reg) ((page * 128) + reg) 42 43 /* Page Control Register */ 44 #define AIC31XX_PAGECTL AIC31XX_REG(0, 0) 45 46 /* Page 0 Registers */ 47 /* Software reset register */ 48 #define AIC31XX_RESET AIC31XX_REG(0, 1) 49 /* OT FLAG register */ 50 #define AIC31XX_OT_FLAG AIC31XX_REG(0, 3) 51 /* Clock clock Gen muxing, Multiplexers*/ 52 #define AIC31XX_CLKMUX AIC31XX_REG(0, 4) 53 /* PLL P and R-VAL register */ 54 #define AIC31XX_PLLPR AIC31XX_REG(0, 5) 55 /* PLL J-VAL register */ 56 #define AIC31XX_PLLJ AIC31XX_REG(0, 6) 57 /* PLL D-VAL MSB register */ 58 #define AIC31XX_PLLDMSB AIC31XX_REG(0, 7) 59 /* PLL D-VAL LSB register */ 60 #define AIC31XX_PLLDLSB AIC31XX_REG(0, 8) 61 /* DAC NDAC_VAL register*/ 62 #define AIC31XX_NDAC AIC31XX_REG(0, 11) 63 /* DAC MDAC_VAL register */ 64 #define AIC31XX_MDAC AIC31XX_REG(0, 12) 65 /* DAC OSR setting register 1, MSB value */ 66 #define AIC31XX_DOSRMSB AIC31XX_REG(0, 13) 67 /* DAC OSR setting register 2, LSB value */ 68 #define AIC31XX_DOSRLSB AIC31XX_REG(0, 14) 69 #define AIC31XX_MINI_DSP_INPOL AIC31XX_REG(0, 16) 70 /* Clock setting register 8, PLL */ 71 #define AIC31XX_NADC AIC31XX_REG(0, 18) 72 /* Clock setting register 9, PLL */ 73 #define AIC31XX_MADC AIC31XX_REG(0, 19) 74 /* ADC Oversampling (AOSR) Register */ 75 #define AIC31XX_AOSR AIC31XX_REG(0, 20) 76 /* Clock setting register 9, Multiplexers */ 77 #define AIC31XX_CLKOUTMUX AIC31XX_REG(0, 25) 78 /* Clock setting register 10, CLOCKOUT M divider value */ 79 #define AIC31XX_CLKOUTMVAL AIC31XX_REG(0, 26) 80 /* Audio Interface Setting Register 1 */ 81 #define AIC31XX_IFACE1 AIC31XX_REG(0, 27) 82 /* Audio Data Slot Offset Programming */ 83 #define AIC31XX_DATA_OFFSET AIC31XX_REG(0, 28) 84 /* Audio Interface Setting Register 2 */ 85 #define AIC31XX_IFACE2 AIC31XX_REG(0, 29) 86 /* Clock setting register 11, BCLK N Divider */ 87 #define AIC31XX_BCLKN AIC31XX_REG(0, 30) 88 /* Audio Interface Setting Register 3, Secondary Audio Interface */ 89 #define AIC31XX_IFACESEC1 AIC31XX_REG(0, 31) 90 /* Audio Interface Setting Register 4 */ 91 #define AIC31XX_IFACESEC2 AIC31XX_REG(0, 32) 92 /* Audio Interface Setting Register 5 */ 93 #define AIC31XX_IFACESEC3 AIC31XX_REG(0, 33) 94 /* I2C Bus Condition */ 95 #define AIC31XX_I2C AIC31XX_REG(0, 34) 96 /* ADC FLAG */ 97 #define AIC31XX_ADCFLAG AIC31XX_REG(0, 36) 98 /* DAC Flag Registers */ 99 #define AIC31XX_DACFLAG1 AIC31XX_REG(0, 37) 100 #define AIC31XX_DACFLAG2 AIC31XX_REG(0, 38) 101 /* Sticky Interrupt flag (overflow) */ 102 #define AIC31XX_OFFLAG AIC31XX_REG(0, 39) 103 /* Sticy DAC Interrupt flags */ 104 #define AIC31XX_INTRDACFLAG AIC31XX_REG(0, 44) 105 /* Sticy ADC Interrupt flags */ 106 #define AIC31XX_INTRADCFLAG AIC31XX_REG(0, 45) 107 /* DAC Interrupt flags 2 */ 108 #define AIC31XX_INTRDACFLAG2 AIC31XX_REG(0, 46) 109 /* ADC Interrupt flags 2 */ 110 #define AIC31XX_INTRADCFLAG2 AIC31XX_REG(0, 47) 111 /* INT1 interrupt control */ 112 #define AIC31XX_INT1CTRL AIC31XX_REG(0, 48) 113 /* INT2 interrupt control */ 114 #define AIC31XX_INT2CTRL AIC31XX_REG(0, 49) 115 /* GPIO1 control */ 116 #define AIC31XX_GPIO1 AIC31XX_REG(0, 50) 117 118 #define AIC31XX_DACPRB AIC31XX_REG(0, 60) 119 /* ADC Instruction Set Register */ 120 #define AIC31XX_ADCPRB AIC31XX_REG(0, 61) 121 /* DAC channel setup register */ 122 #define AIC31XX_DACSETUP AIC31XX_REG(0, 63) 123 /* DAC Mute and volume control register */ 124 #define AIC31XX_DACMUTE AIC31XX_REG(0, 64) 125 /* Left DAC channel digital volume control */ 126 #define AIC31XX_LDACVOL AIC31XX_REG(0, 65) 127 /* Right DAC channel digital volume control */ 128 #define AIC31XX_RDACVOL AIC31XX_REG(0, 66) 129 /* Headset detection */ 130 #define AIC31XX_HSDETECT AIC31XX_REG(0, 67) 131 /* ADC Digital Mic */ 132 #define AIC31XX_ADCSETUP AIC31XX_REG(0, 81) 133 /* ADC Digital Volume Control Fine Adjust */ 134 #define AIC31XX_ADCFGA AIC31XX_REG(0, 82) 135 /* ADC Digital Volume Control Coarse Adjust */ 136 #define AIC31XX_ADCVOL AIC31XX_REG(0, 83) 137 138 139 /* Page 1 Registers */ 140 /* Headphone drivers */ 141 #define AIC31XX_HPDRIVER AIC31XX_REG(1, 31) 142 /* Class-D Speakear Amplifier */ 143 #define AIC31XX_SPKAMP AIC31XX_REG(1, 32) 144 /* HP Output Drivers POP Removal Settings */ 145 #define AIC31XX_HPPOP AIC31XX_REG(1, 33) 146 /* Output Driver PGA Ramp-Down Period Control */ 147 #define AIC31XX_SPPGARAMP AIC31XX_REG(1, 34) 148 /* DAC_L and DAC_R Output Mixer Routing */ 149 #define AIC31XX_DACMIXERROUTE AIC31XX_REG(1, 35) 150 /* Left Analog Vol to HPL */ 151 #define AIC31XX_LANALOGHPL AIC31XX_REG(1, 36) 152 /* Right Analog Vol to HPR */ 153 #define AIC31XX_RANALOGHPR AIC31XX_REG(1, 37) 154 /* Left Analog Vol to SPL */ 155 #define AIC31XX_LANALOGSPL AIC31XX_REG(1, 38) 156 /* Right Analog Vol to SPR */ 157 #define AIC31XX_RANALOGSPR AIC31XX_REG(1, 39) 158 /* HPL Driver */ 159 #define AIC31XX_HPLGAIN AIC31XX_REG(1, 40) 160 /* HPR Driver */ 161 #define AIC31XX_HPRGAIN AIC31XX_REG(1, 41) 162 /* SPL Driver */ 163 #define AIC31XX_SPLGAIN AIC31XX_REG(1, 42) 164 /* SPR Driver */ 165 #define AIC31XX_SPRGAIN AIC31XX_REG(1, 43) 166 /* HP Driver Control */ 167 #define AIC31XX_HPCONTROL AIC31XX_REG(1, 44) 168 /* MIC Bias Control */ 169 #define AIC31XX_MICBIAS AIC31XX_REG(1, 46) 170 /* MIC PGA*/ 171 #define AIC31XX_MICPGA AIC31XX_REG(1, 47) 172 /* Delta-Sigma Mono ADC Channel Fine-Gain Input Selection for P-Terminal */ 173 #define AIC31XX_MICPGAPI AIC31XX_REG(1, 48) 174 /* ADC Input Selection for M-Terminal */ 175 #define AIC31XX_MICPGAMI AIC31XX_REG(1, 49) 176 /* Input CM Settings */ 177 #define AIC31XX_MICPGACM AIC31XX_REG(1, 50) 178 179 /* Bits, masks and shifts */ 180 181 /* AIC31XX_CLKMUX */ 182 #define AIC31XX_PLL_CLKIN_MASK 0x0c 183 #define AIC31XX_PLL_CLKIN_SHIFT 2 184 #define AIC31XX_PLL_CLKIN_MCLK 0 185 #define AIC31XX_CODEC_CLKIN_MASK 0x03 186 #define AIC31XX_CODEC_CLKIN_SHIFT 0 187 #define AIC31XX_CODEC_CLKIN_PLL 3 188 #define AIC31XX_CODEC_CLKIN_BCLK 1 189 190 /* AIC31XX_PLLPR, AIC31XX_NDAC, AIC31XX_MDAC, AIC31XX_NADC, AIC31XX_MADC, 191 AIC31XX_BCLKN */ 192 #define AIC31XX_PLL_MASK 0x7f 193 #define AIC31XX_PM_MASK 0x80 194 195 /* AIC31XX_IFACE1 */ 196 #define AIC31XX_WORD_LEN_16BITS 0x00 197 #define AIC31XX_WORD_LEN_20BITS 0x01 198 #define AIC31XX_WORD_LEN_24BITS 0x02 199 #define AIC31XX_WORD_LEN_32BITS 0x03 200 #define AIC31XX_IFACE1_DATALEN_MASK 0x30 201 #define AIC31XX_IFACE1_DATALEN_SHIFT (4) 202 #define AIC31XX_IFACE1_DATATYPE_MASK 0xC0 203 #define AIC31XX_IFACE1_DATATYPE_SHIFT (6) 204 #define AIC31XX_I2S_MODE 0x00 205 #define AIC31XX_DSP_MODE 0x01 206 #define AIC31XX_RIGHT_JUSTIFIED_MODE 0x02 207 #define AIC31XX_LEFT_JUSTIFIED_MODE 0x03 208 #define AIC31XX_IFACE1_MASTER_MASK 0x0C 209 #define AIC31XX_BCLK_MASTER 0x08 210 #define AIC31XX_WCLK_MASTER 0x04 211 212 /* AIC31XX_DATA_OFFSET */ 213 #define AIC31XX_DATA_OFFSET_MASK 0xFF 214 215 /* AIC31XX_IFACE2 */ 216 #define AIC31XX_BCLKINV_MASK 0x08 217 #define AIC31XX_BDIVCLK_MASK 0x03 218 #define AIC31XX_DAC2BCLK 0x00 219 #define AIC31XX_DACMOD2BCLK 0x01 220 #define AIC31XX_ADC2BCLK 0x02 221 #define AIC31XX_ADCMOD2BCLK 0x03 222 223 /* AIC31XX_ADCFLAG */ 224 #define AIC31XX_ADCPWRSTATUS_MASK 0x40 225 226 /* AIC31XX_DACFLAG1 */ 227 #define AIC31XX_LDACPWRSTATUS_MASK 0x80 228 #define AIC31XX_RDACPWRSTATUS_MASK 0x08 229 #define AIC31XX_HPLDRVPWRSTATUS_MASK 0x20 230 #define AIC31XX_HPRDRVPWRSTATUS_MASK 0x02 231 #define AIC31XX_SPLDRVPWRSTATUS_MASK 0x10 232 #define AIC31XX_SPRDRVPWRSTATUS_MASK 0x01 233 234 /* AIC31XX_INTRDACFLAG */ 235 #define AIC31XX_HPSCDETECT_MASK 0x80 236 #define AIC31XX_BUTTONPRESS_MASK 0x20 237 #define AIC31XX_HSPLUG_MASK 0x10 238 #define AIC31XX_LDRCTHRES_MASK 0x08 239 #define AIC31XX_RDRCTHRES_MASK 0x04 240 #define AIC31XX_DACSINT_MASK 0x02 241 #define AIC31XX_DACAINT_MASK 0x01 242 243 /* AIC31XX_INT1CTRL */ 244 #define AIC31XX_HSPLUGDET_MASK 0x80 245 #define AIC31XX_BUTTONPRESSDET_MASK 0x40 246 #define AIC31XX_DRCTHRES_MASK 0x20 247 #define AIC31XX_AGCNOISE_MASK 0x10 248 #define AIC31XX_OC_MASK 0x08 249 #define AIC31XX_ENGINE_MASK 0x04 250 251 /* AIC31XX_DACSETUP */ 252 #define AIC31XX_SOFTSTEP_MASK 0x03 253 254 /* AIC31XX_DACMUTE */ 255 #define AIC31XX_DACMUTE_MASK 0x0C 256 257 /* AIC31XX_MICBIAS */ 258 #define AIC31XX_MICBIAS_MASK 0x03 259 #define AIC31XX_MICBIAS_SHIFT 0 260 261 #endif /* _TLV320AIC31XX_H */ 262