1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ALSA SoC TLV320AIC31xx CODEC Driver 4 * 5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ 6 * Jyri Sarha <jsarha@ti.com> 7 * 8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com> 9 * 10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated 11 * high performance codecs which provides a stereo DAC, a mono ADC, 12 * and mono/stereo Class-D speaker driver. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/init.h> 18 #include <linux/delay.h> 19 #include <linux/pm.h> 20 #include <linux/i2c.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/acpi.h> 24 #include <linux/of.h> 25 #include <linux/of_gpio.h> 26 #include <linux/slab.h> 27 #include <sound/core.h> 28 #include <sound/jack.h> 29 #include <sound/pcm.h> 30 #include <sound/pcm_params.h> 31 #include <sound/soc.h> 32 #include <sound/initval.h> 33 #include <sound/tlv.h> 34 #include <dt-bindings/sound/tlv320aic31xx-micbias.h> 35 36 #include "tlv320aic31xx.h" 37 38 static const struct reg_default aic31xx_reg_defaults[] = { 39 { AIC31XX_CLKMUX, 0x00 }, 40 { AIC31XX_PLLPR, 0x11 }, 41 { AIC31XX_PLLJ, 0x04 }, 42 { AIC31XX_PLLDMSB, 0x00 }, 43 { AIC31XX_PLLDLSB, 0x00 }, 44 { AIC31XX_NDAC, 0x01 }, 45 { AIC31XX_MDAC, 0x01 }, 46 { AIC31XX_DOSRMSB, 0x00 }, 47 { AIC31XX_DOSRLSB, 0x80 }, 48 { AIC31XX_NADC, 0x01 }, 49 { AIC31XX_MADC, 0x01 }, 50 { AIC31XX_AOSR, 0x80 }, 51 { AIC31XX_IFACE1, 0x00 }, 52 { AIC31XX_DATA_OFFSET, 0x00 }, 53 { AIC31XX_IFACE2, 0x00 }, 54 { AIC31XX_BCLKN, 0x01 }, 55 { AIC31XX_DACSETUP, 0x14 }, 56 { AIC31XX_DACMUTE, 0x0c }, 57 { AIC31XX_LDACVOL, 0x00 }, 58 { AIC31XX_RDACVOL, 0x00 }, 59 { AIC31XX_ADCSETUP, 0x00 }, 60 { AIC31XX_ADCFGA, 0x80 }, 61 { AIC31XX_ADCVOL, 0x00 }, 62 { AIC31XX_HPDRIVER, 0x04 }, 63 { AIC31XX_SPKAMP, 0x06 }, 64 { AIC31XX_DACMIXERROUTE, 0x00 }, 65 { AIC31XX_LANALOGHPL, 0x7f }, 66 { AIC31XX_RANALOGHPR, 0x7f }, 67 { AIC31XX_LANALOGSPL, 0x7f }, 68 { AIC31XX_RANALOGSPR, 0x7f }, 69 { AIC31XX_HPLGAIN, 0x02 }, 70 { AIC31XX_HPRGAIN, 0x02 }, 71 { AIC31XX_SPLGAIN, 0x00 }, 72 { AIC31XX_SPRGAIN, 0x00 }, 73 { AIC31XX_MICBIAS, 0x00 }, 74 { AIC31XX_MICPGA, 0x80 }, 75 { AIC31XX_MICPGAPI, 0x00 }, 76 { AIC31XX_MICPGAMI, 0x00 }, 77 }; 78 79 static bool aic31xx_volatile(struct device *dev, unsigned int reg) 80 { 81 switch (reg) { 82 case AIC31XX_PAGECTL: /* regmap implementation requires this */ 83 case AIC31XX_RESET: /* always clears after write */ 84 case AIC31XX_OT_FLAG: 85 case AIC31XX_ADCFLAG: 86 case AIC31XX_DACFLAG1: 87 case AIC31XX_DACFLAG2: 88 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 89 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 90 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 91 case AIC31XX_INTRDACFLAG2: 92 case AIC31XX_INTRADCFLAG2: 93 case AIC31XX_HSDETECT: 94 return true; 95 } 96 return false; 97 } 98 99 static bool aic31xx_writeable(struct device *dev, unsigned int reg) 100 { 101 switch (reg) { 102 case AIC31XX_OT_FLAG: 103 case AIC31XX_ADCFLAG: 104 case AIC31XX_DACFLAG1: 105 case AIC31XX_DACFLAG2: 106 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 107 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 108 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 109 case AIC31XX_INTRDACFLAG2: 110 case AIC31XX_INTRADCFLAG2: 111 return false; 112 } 113 return true; 114 } 115 116 static const struct regmap_range_cfg aic31xx_ranges[] = { 117 { 118 .range_min = 0, 119 .range_max = 12 * 128, 120 .selector_reg = AIC31XX_PAGECTL, 121 .selector_mask = 0xff, 122 .selector_shift = 0, 123 .window_start = 0, 124 .window_len = 128, 125 }, 126 }; 127 128 static const struct regmap_config aic31xx_i2c_regmap = { 129 .reg_bits = 8, 130 .val_bits = 8, 131 .writeable_reg = aic31xx_writeable, 132 .volatile_reg = aic31xx_volatile, 133 .reg_defaults = aic31xx_reg_defaults, 134 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults), 135 .cache_type = REGCACHE_RBTREE, 136 .ranges = aic31xx_ranges, 137 .num_ranges = ARRAY_SIZE(aic31xx_ranges), 138 .max_register = 12 * 128, 139 }; 140 141 static const char * const aic31xx_supply_names[] = { 142 "HPVDD", 143 "SPRVDD", 144 "SPLVDD", 145 "AVDD", 146 "IOVDD", 147 "DVDD", 148 }; 149 150 #define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names) 151 152 struct aic31xx_disable_nb { 153 struct notifier_block nb; 154 struct aic31xx_priv *aic31xx; 155 }; 156 157 struct aic31xx_priv { 158 struct snd_soc_component *component; 159 u8 i2c_regs_status; 160 struct device *dev; 161 struct regmap *regmap; 162 enum aic31xx_type codec_type; 163 struct gpio_desc *gpio_reset; 164 int micbias_vg; 165 struct aic31xx_pdata pdata; 166 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES]; 167 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES]; 168 struct snd_soc_jack *jack; 169 unsigned int sysclk; 170 u8 p_div; 171 int rate_div_line; 172 bool master_dapm_route_applied; 173 int irq; 174 u8 ocmv; /* output common-mode voltage */ 175 }; 176 177 struct aic31xx_rate_divs { 178 u32 mclk_p; 179 u32 rate; 180 u8 pll_j; 181 u16 pll_d; 182 u16 dosr; 183 u8 ndac; 184 u8 mdac; 185 u8 aosr; 186 u8 nadc; 187 u8 madc; 188 }; 189 190 /* ADC dividers can be disabled by configuring them to 0 */ 191 static const struct aic31xx_rate_divs aic31xx_divs[] = { 192 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */ 193 /* 8k rate */ 194 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2}, 195 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3}, 196 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2}, 197 /* 11.025k rate */ 198 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2}, 199 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3}, 200 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2}, 201 /* 16k rate */ 202 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2}, 203 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3}, 204 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2}, 205 /* 22.05k rate */ 206 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2}, 207 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3}, 208 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2}, 209 /* 32k rate */ 210 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2}, 211 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3}, 212 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2}, 213 /* 44.1k rate */ 214 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2}, 215 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3}, 216 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2}, 217 /* 48k rate */ 218 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2}, 219 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4}, 220 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2}, 221 /* 88.2k rate */ 222 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2}, 223 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3}, 224 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2}, 225 /* 96k rate */ 226 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2}, 227 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4}, 228 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2}, 229 /* 176.4k rate */ 230 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2}, 231 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3}, 232 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2}, 233 /* 192k rate */ 234 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2}, 235 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4}, 236 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2}, 237 }; 238 239 static const char * const ldac_in_text[] = { 240 "Off", "Left Data", "Right Data", "Mono" 241 }; 242 243 static const char * const rdac_in_text[] = { 244 "Off", "Right Data", "Left Data", "Mono" 245 }; 246 247 static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text); 248 249 static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text); 250 251 static const char * const mic_select_text[] = { 252 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm" 253 }; 254 255 static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6, 256 mic_select_text); 257 static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4, 258 mic_select_text); 259 static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2, 260 mic_select_text); 261 262 static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4, 263 mic_select_text); 264 265 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0); 266 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0); 267 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0); 268 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0); 269 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0); 270 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0); 271 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0); 272 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0); 273 274 /* 275 * controls to be exported to the user space 276 */ 277 static const struct snd_kcontrol_new common31xx_snd_controls[] = { 278 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL, 279 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv), 280 281 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN, 282 AIC31XX_HPRGAIN, 2, 1, 0), 283 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN, 284 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv), 285 286 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL, 287 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv), 288 }; 289 290 static const struct snd_kcontrol_new aic31xx_snd_controls[] = { 291 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1, 292 adc_fgain_tlv), 293 294 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1), 295 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL, 296 0, -24, 40, 6, 0, adc_cgain_tlv), 297 298 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0, 299 119, 0, mic_pga_tlv), 300 }; 301 302 static const struct snd_kcontrol_new aic311x_snd_controls[] = { 303 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 304 AIC31XX_SPRGAIN, 2, 1, 0), 305 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 306 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv), 307 308 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 309 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv), 310 }; 311 312 static const struct snd_kcontrol_new aic310x_snd_controls[] = { 313 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 314 2, 1, 0), 315 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 316 3, 3, 0, class_D_drv_tlv), 317 318 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 319 0, 0x7F, 1, sp_vol_tlv), 320 }; 321 322 static const struct snd_kcontrol_new ldac_in_control = 323 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum); 324 325 static const struct snd_kcontrol_new rdac_in_control = 326 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum); 327 328 static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg, 329 unsigned int mask, unsigned int wbits, int sleep, 330 int count) 331 { 332 unsigned int bits; 333 int counter = count; 334 int ret = regmap_read(aic31xx->regmap, reg, &bits); 335 336 while ((bits & mask) != wbits && counter && !ret) { 337 usleep_range(sleep, sleep * 2); 338 ret = regmap_read(aic31xx->regmap, reg, &bits); 339 counter--; 340 } 341 if ((bits & mask) != wbits) { 342 dev_err(aic31xx->dev, 343 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n", 344 __func__, reg, bits, wbits, ret, mask, 345 (count - counter) * sleep); 346 ret = -1; 347 } 348 return ret; 349 } 350 351 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg)) 352 353 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w, 354 struct snd_kcontrol *kcontrol, int event) 355 { 356 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 357 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 358 unsigned int reg = AIC31XX_DACFLAG1; 359 unsigned int mask; 360 361 switch (WIDGET_BIT(w->reg, w->shift)) { 362 case WIDGET_BIT(AIC31XX_DACSETUP, 7): 363 mask = AIC31XX_LDACPWRSTATUS_MASK; 364 break; 365 case WIDGET_BIT(AIC31XX_DACSETUP, 6): 366 mask = AIC31XX_RDACPWRSTATUS_MASK; 367 break; 368 case WIDGET_BIT(AIC31XX_HPDRIVER, 7): 369 mask = AIC31XX_HPLDRVPWRSTATUS_MASK; 370 break; 371 case WIDGET_BIT(AIC31XX_HPDRIVER, 6): 372 mask = AIC31XX_HPRDRVPWRSTATUS_MASK; 373 break; 374 case WIDGET_BIT(AIC31XX_SPKAMP, 7): 375 mask = AIC31XX_SPLDRVPWRSTATUS_MASK; 376 break; 377 case WIDGET_BIT(AIC31XX_SPKAMP, 6): 378 mask = AIC31XX_SPRDRVPWRSTATUS_MASK; 379 break; 380 case WIDGET_BIT(AIC31XX_ADCSETUP, 7): 381 mask = AIC31XX_ADCPWRSTATUS_MASK; 382 reg = AIC31XX_ADCFLAG; 383 break; 384 default: 385 dev_err(component->dev, "Unknown widget '%s' calling %s\n", 386 w->name, __func__); 387 return -EINVAL; 388 } 389 390 switch (event) { 391 case SND_SOC_DAPM_POST_PMU: 392 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100); 393 case SND_SOC_DAPM_POST_PMD: 394 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100); 395 default: 396 dev_dbg(component->dev, 397 "Unhandled dapm widget event %d from %s\n", 398 event, w->name); 399 } 400 return 0; 401 } 402 403 static const struct snd_kcontrol_new aic31xx_left_output_switches[] = { 404 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 405 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0), 406 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0), 407 }; 408 409 static const struct snd_kcontrol_new aic31xx_right_output_switches[] = { 410 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 411 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0), 412 }; 413 414 static const struct snd_kcontrol_new dac31xx_left_output_switches[] = { 415 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 416 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0), 417 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0), 418 }; 419 420 static const struct snd_kcontrol_new dac31xx_right_output_switches[] = { 421 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 422 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0), 423 }; 424 425 static const struct snd_kcontrol_new p_term_mic1lp = 426 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum); 427 428 static const struct snd_kcontrol_new p_term_mic1rp = 429 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum); 430 431 static const struct snd_kcontrol_new p_term_mic1lm = 432 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum); 433 434 static const struct snd_kcontrol_new m_term_mic1lm = 435 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum); 436 437 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch = 438 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0); 439 440 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch = 441 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0); 442 443 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch = 444 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0); 445 446 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch = 447 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0); 448 449 static int mic_bias_event(struct snd_soc_dapm_widget *w, 450 struct snd_kcontrol *kcontrol, int event) 451 { 452 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 453 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 454 455 switch (event) { 456 case SND_SOC_DAPM_POST_PMU: 457 /* change mic bias voltage to user defined */ 458 snd_soc_component_update_bits(component, AIC31XX_MICBIAS, 459 AIC31XX_MICBIAS_MASK, 460 aic31xx->micbias_vg << 461 AIC31XX_MICBIAS_SHIFT); 462 dev_dbg(component->dev, "%s: turned on\n", __func__); 463 break; 464 case SND_SOC_DAPM_PRE_PMD: 465 /* turn mic bias off */ 466 snd_soc_component_update_bits(component, AIC31XX_MICBIAS, 467 AIC31XX_MICBIAS_MASK, 0); 468 dev_dbg(component->dev, "%s: turned off\n", __func__); 469 break; 470 } 471 return 0; 472 } 473 474 static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = { 475 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0), 476 477 SND_SOC_DAPM_MUX("DAC Left Input", 478 SND_SOC_NOPM, 0, 0, &ldac_in_control), 479 SND_SOC_DAPM_MUX("DAC Right Input", 480 SND_SOC_NOPM, 0, 0, &rdac_in_control), 481 /* DACs */ 482 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback", 483 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event, 484 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 485 486 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback", 487 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event, 488 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 489 490 /* HP */ 491 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0, 492 &aic31xx_dapm_hpl_switch), 493 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0, 494 &aic31xx_dapm_hpr_switch), 495 496 /* Output drivers */ 497 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0, 498 NULL, 0, aic31xx_dapm_power_event, 499 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 500 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0, 501 NULL, 0, aic31xx_dapm_power_event, 502 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 503 504 /* Mic Bias */ 505 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event, 506 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 507 508 /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */ 509 SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0, 510 NULL, 0), 511 512 /* Outputs */ 513 SND_SOC_DAPM_OUTPUT("HPL"), 514 SND_SOC_DAPM_OUTPUT("HPR"), 515 }; 516 517 static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = { 518 /* Inputs */ 519 SND_SOC_DAPM_INPUT("AIN1"), 520 SND_SOC_DAPM_INPUT("AIN2"), 521 522 /* Output Mixers */ 523 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 524 dac31xx_left_output_switches, 525 ARRAY_SIZE(dac31xx_left_output_switches)), 526 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 527 dac31xx_right_output_switches, 528 ARRAY_SIZE(dac31xx_right_output_switches)), 529 }; 530 531 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = { 532 /* Inputs */ 533 SND_SOC_DAPM_INPUT("MIC1LP"), 534 SND_SOC_DAPM_INPUT("MIC1RP"), 535 SND_SOC_DAPM_INPUT("MIC1LM"), 536 537 /* Input Selection to MIC_PGA */ 538 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0, 539 &p_term_mic1lp), 540 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0, 541 &p_term_mic1rp), 542 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0, 543 &p_term_mic1lm), 544 545 /* ADC */ 546 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0, 547 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 548 SND_SOC_DAPM_POST_PMD), 549 550 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0, 551 &m_term_mic1lm), 552 553 /* Enabling & Disabling MIC Gain Ctl */ 554 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA, 555 7, 1, NULL, 0), 556 557 /* Output Mixers */ 558 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 559 aic31xx_left_output_switches, 560 ARRAY_SIZE(aic31xx_left_output_switches)), 561 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 562 aic31xx_right_output_switches, 563 ARRAY_SIZE(aic31xx_right_output_switches)), 564 565 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 566 }; 567 568 static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = { 569 /* AIC3111 and AIC3110 have stereo class-D amplifier */ 570 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 571 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 572 SND_SOC_DAPM_POST_PMD), 573 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0, 574 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 575 SND_SOC_DAPM_POST_PMD), 576 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0, 577 &aic31xx_dapm_spl_switch), 578 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0, 579 &aic31xx_dapm_spr_switch), 580 SND_SOC_DAPM_OUTPUT("SPL"), 581 SND_SOC_DAPM_OUTPUT("SPR"), 582 }; 583 584 /* AIC3100 and AIC3120 have only mono class-D amplifier */ 585 static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = { 586 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 587 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 588 SND_SOC_DAPM_POST_PMD), 589 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0, 590 &aic31xx_dapm_spl_switch), 591 SND_SOC_DAPM_OUTPUT("SPK"), 592 }; 593 594 static const struct snd_soc_dapm_route 595 common31xx_audio_map[] = { 596 /* DAC Input Routing */ 597 {"DAC Left Input", "Left Data", "AIF IN"}, 598 {"DAC Left Input", "Right Data", "AIF IN"}, 599 {"DAC Left Input", "Mono", "AIF IN"}, 600 {"DAC Right Input", "Left Data", "AIF IN"}, 601 {"DAC Right Input", "Right Data", "AIF IN"}, 602 {"DAC Right Input", "Mono", "AIF IN"}, 603 {"DAC Left", NULL, "DAC Left Input"}, 604 {"DAC Right", NULL, "DAC Right Input"}, 605 606 /* HPL path */ 607 {"HP Left", "Switch", "Output Left"}, 608 {"HPL Driver", NULL, "HP Left"}, 609 {"HPL", NULL, "HPL Driver"}, 610 611 /* HPR path */ 612 {"HP Right", "Switch", "Output Right"}, 613 {"HPR Driver", NULL, "HP Right"}, 614 {"HPR", NULL, "HPR Driver"}, 615 }; 616 617 static const struct snd_soc_dapm_route 618 dac31xx_audio_map[] = { 619 /* Left Output */ 620 {"Output Left", "From Left DAC", "DAC Left"}, 621 {"Output Left", "From AIN1", "AIN1"}, 622 {"Output Left", "From AIN2", "AIN2"}, 623 624 /* Right Output */ 625 {"Output Right", "From Right DAC", "DAC Right"}, 626 {"Output Right", "From AIN2", "AIN2"}, 627 }; 628 629 static const struct snd_soc_dapm_route 630 aic31xx_audio_map[] = { 631 /* Mic input */ 632 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"}, 633 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"}, 634 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"}, 635 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"}, 636 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"}, 637 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"}, 638 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"}, 639 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"}, 640 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"}, 641 642 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"}, 643 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"}, 644 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"}, 645 646 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"}, 647 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"}, 648 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"}, 649 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"}, 650 651 {"ADC", NULL, "MIC_GAIN_CTL"}, 652 653 {"AIF OUT", NULL, "ADC"}, 654 655 /* Left Output */ 656 {"Output Left", "From Left DAC", "DAC Left"}, 657 {"Output Left", "From MIC1LP", "MIC1LP"}, 658 {"Output Left", "From MIC1RP", "MIC1RP"}, 659 660 /* Right Output */ 661 {"Output Right", "From Right DAC", "DAC Right"}, 662 {"Output Right", "From MIC1RP", "MIC1RP"}, 663 }; 664 665 static const struct snd_soc_dapm_route 666 aic311x_audio_map[] = { 667 /* SP L path */ 668 {"Speaker Left", "Switch", "Output Left"}, 669 {"SPL ClassD", NULL, "Speaker Left"}, 670 {"SPL", NULL, "SPL ClassD"}, 671 672 /* SP R path */ 673 {"Speaker Right", "Switch", "Output Right"}, 674 {"SPR ClassD", NULL, "Speaker Right"}, 675 {"SPR", NULL, "SPR ClassD"}, 676 }; 677 678 static const struct snd_soc_dapm_route 679 aic310x_audio_map[] = { 680 /* SP L path */ 681 {"Speaker", "Switch", "Output Left"}, 682 {"SPK ClassD", NULL, "Speaker"}, 683 {"SPK", NULL, "SPK ClassD"}, 684 }; 685 686 /* 687 * Always connected DAPM routes for codec clock master modes. 688 * If the codec is the master on the I2S bus, we need to power up components 689 * to have valid DAC_CLK. 690 * 691 * In order to have the I2S clocks on the bus either the DACs/ADC need to be 692 * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set. 693 * 694 * Otherwise the codec will not generate clocks on the bus. 695 */ 696 static const struct snd_soc_dapm_route 697 common31xx_cm_audio_map[] = { 698 {"HPL", NULL, "AIF IN"}, 699 {"HPR", NULL, "AIF IN"}, 700 701 {"AIF IN", NULL, "Activate I2S clocks"}, 702 }; 703 704 static const struct snd_soc_dapm_route 705 aic31xx_cm_audio_map[] = { 706 {"AIF OUT", NULL, "MIC1LP"}, 707 {"AIF OUT", NULL, "MIC1RP"}, 708 {"AIF OUT", NULL, "MIC1LM"}, 709 710 {"AIF OUT", NULL, "Activate I2S clocks"}, 711 }; 712 713 static int aic31xx_add_controls(struct snd_soc_component *component) 714 { 715 int ret = 0; 716 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 717 718 if (!(aic31xx->codec_type & DAC31XX_BIT)) 719 ret = snd_soc_add_component_controls( 720 component, aic31xx_snd_controls, 721 ARRAY_SIZE(aic31xx_snd_controls)); 722 if (ret) 723 return ret; 724 725 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) 726 ret = snd_soc_add_component_controls( 727 component, aic311x_snd_controls, 728 ARRAY_SIZE(aic311x_snd_controls)); 729 else 730 ret = snd_soc_add_component_controls( 731 component, aic310x_snd_controls, 732 ARRAY_SIZE(aic310x_snd_controls)); 733 734 return ret; 735 } 736 737 static int aic31xx_add_widgets(struct snd_soc_component *component) 738 { 739 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 740 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 741 int ret = 0; 742 743 if (aic31xx->codec_type & DAC31XX_BIT) { 744 ret = snd_soc_dapm_new_controls( 745 dapm, dac31xx_dapm_widgets, 746 ARRAY_SIZE(dac31xx_dapm_widgets)); 747 if (ret) 748 return ret; 749 750 ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map, 751 ARRAY_SIZE(dac31xx_audio_map)); 752 if (ret) 753 return ret; 754 } else { 755 ret = snd_soc_dapm_new_controls( 756 dapm, aic31xx_dapm_widgets, 757 ARRAY_SIZE(aic31xx_dapm_widgets)); 758 if (ret) 759 return ret; 760 761 ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map, 762 ARRAY_SIZE(aic31xx_audio_map)); 763 if (ret) 764 return ret; 765 } 766 767 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) { 768 ret = snd_soc_dapm_new_controls( 769 dapm, aic311x_dapm_widgets, 770 ARRAY_SIZE(aic311x_dapm_widgets)); 771 if (ret) 772 return ret; 773 774 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map, 775 ARRAY_SIZE(aic311x_audio_map)); 776 if (ret) 777 return ret; 778 } else { 779 ret = snd_soc_dapm_new_controls( 780 dapm, aic310x_dapm_widgets, 781 ARRAY_SIZE(aic310x_dapm_widgets)); 782 if (ret) 783 return ret; 784 785 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map, 786 ARRAY_SIZE(aic310x_audio_map)); 787 if (ret) 788 return ret; 789 } 790 791 return 0; 792 } 793 794 static int aic31xx_setup_pll(struct snd_soc_component *component, 795 struct snd_pcm_hw_params *params) 796 { 797 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 798 int bclk_score = snd_soc_params_to_frame_size(params); 799 int mclk_p; 800 int bclk_n = 0; 801 int match = -1; 802 int i; 803 804 if (!aic31xx->sysclk || !aic31xx->p_div) { 805 dev_err(component->dev, "Master clock not supplied\n"); 806 return -EINVAL; 807 } 808 mclk_p = aic31xx->sysclk / aic31xx->p_div; 809 810 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */ 811 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, 812 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL); 813 snd_soc_component_update_bits(component, AIC31XX_IFACE2, 814 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK); 815 816 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { 817 if (aic31xx_divs[i].rate == params_rate(params) && 818 aic31xx_divs[i].mclk_p == mclk_p) { 819 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) % 820 snd_soc_params_to_frame_size(params); 821 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) / 822 snd_soc_params_to_frame_size(params); 823 if (s < bclk_score && bn > 0) { 824 match = i; 825 bclk_n = bn; 826 bclk_score = s; 827 } 828 } 829 } 830 831 if (match == -1) { 832 dev_err(component->dev, 833 "%s: Sample rate (%u) and format not supported\n", 834 __func__, params_rate(params)); 835 /* See bellow for details how fix this. */ 836 return -EINVAL; 837 } 838 if (bclk_score != 0) { 839 dev_warn(component->dev, "Can not produce exact bitclock"); 840 /* This is fine if using dsp format, but if using i2s 841 there may be trouble. To fix the issue edit the 842 aic31xx_divs table for your mclk and sample 843 rate. Details can be found from: 844 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf 845 Section: 5.6 CLOCK Generation and PLL 846 */ 847 } 848 i = match; 849 850 /* PLL configuration */ 851 snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK, 852 (aic31xx->p_div << 4) | 0x01); 853 snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j); 854 855 snd_soc_component_write(component, AIC31XX_PLLDMSB, 856 aic31xx_divs[i].pll_d >> 8); 857 snd_soc_component_write(component, AIC31XX_PLLDLSB, 858 aic31xx_divs[i].pll_d & 0xff); 859 860 /* DAC dividers configuration */ 861 snd_soc_component_update_bits(component, AIC31XX_NDAC, AIC31XX_PLL_MASK, 862 aic31xx_divs[i].ndac); 863 snd_soc_component_update_bits(component, AIC31XX_MDAC, AIC31XX_PLL_MASK, 864 aic31xx_divs[i].mdac); 865 866 snd_soc_component_write(component, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8); 867 snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff); 868 869 /* ADC dividers configuration. Write reset value 1 if not used. */ 870 snd_soc_component_update_bits(component, AIC31XX_NADC, AIC31XX_PLL_MASK, 871 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1); 872 snd_soc_component_update_bits(component, AIC31XX_MADC, AIC31XX_PLL_MASK, 873 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1); 874 875 snd_soc_component_write(component, AIC31XX_AOSR, aic31xx_divs[i].aosr); 876 877 /* Bit clock divider configuration. */ 878 snd_soc_component_update_bits(component, AIC31XX_BCLKN, 879 AIC31XX_PLL_MASK, bclk_n); 880 881 aic31xx->rate_div_line = i; 882 883 dev_dbg(component->dev, 884 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n", 885 aic31xx_divs[i].pll_j, 886 aic31xx_divs[i].pll_d, 887 aic31xx->p_div, 888 aic31xx_divs[i].dosr, 889 aic31xx_divs[i].ndac, 890 aic31xx_divs[i].mdac, 891 aic31xx_divs[i].aosr, 892 aic31xx_divs[i].nadc, 893 aic31xx_divs[i].madc, 894 bclk_n 895 ); 896 897 return 0; 898 } 899 900 static int aic31xx_hw_params(struct snd_pcm_substream *substream, 901 struct snd_pcm_hw_params *params, 902 struct snd_soc_dai *dai) 903 { 904 struct snd_soc_component *component = dai->component; 905 u8 data = 0; 906 907 dev_dbg(component->dev, "## %s: width %d rate %d\n", 908 __func__, params_width(params), 909 params_rate(params)); 910 911 switch (params_width(params)) { 912 case 16: 913 break; 914 case 20: 915 data = (AIC31XX_WORD_LEN_20BITS << 916 AIC31XX_IFACE1_DATALEN_SHIFT); 917 break; 918 case 24: 919 data = (AIC31XX_WORD_LEN_24BITS << 920 AIC31XX_IFACE1_DATALEN_SHIFT); 921 break; 922 case 32: 923 data = (AIC31XX_WORD_LEN_32BITS << 924 AIC31XX_IFACE1_DATALEN_SHIFT); 925 break; 926 default: 927 dev_err(component->dev, "%s: Unsupported width %d\n", 928 __func__, params_width(params)); 929 return -EINVAL; 930 } 931 932 snd_soc_component_update_bits(component, AIC31XX_IFACE1, 933 AIC31XX_IFACE1_DATALEN_MASK, 934 data); 935 936 return aic31xx_setup_pll(component, params); 937 } 938 939 static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute) 940 { 941 struct snd_soc_component *component = codec_dai->component; 942 943 if (mute) { 944 snd_soc_component_update_bits(component, AIC31XX_DACMUTE, 945 AIC31XX_DACMUTE_MASK, 946 AIC31XX_DACMUTE_MASK); 947 } else { 948 snd_soc_component_update_bits(component, AIC31XX_DACMUTE, 949 AIC31XX_DACMUTE_MASK, 0x0); 950 } 951 952 return 0; 953 } 954 955 static int aic31xx_clock_master_routes(struct snd_soc_component *component, 956 unsigned int fmt) 957 { 958 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 959 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 960 int ret; 961 962 fmt &= SND_SOC_DAIFMT_MASTER_MASK; 963 if (fmt == SND_SOC_DAIFMT_CBS_CFS && 964 aic31xx->master_dapm_route_applied) { 965 /* 966 * Remove the DAPM route(s) for codec clock master modes, 967 * if applied 968 */ 969 ret = snd_soc_dapm_del_routes(dapm, common31xx_cm_audio_map, 970 ARRAY_SIZE(common31xx_cm_audio_map)); 971 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT)) 972 ret = snd_soc_dapm_del_routes(dapm, 973 aic31xx_cm_audio_map, 974 ARRAY_SIZE(aic31xx_cm_audio_map)); 975 976 if (ret) 977 return ret; 978 979 aic31xx->master_dapm_route_applied = false; 980 } else if (fmt != SND_SOC_DAIFMT_CBS_CFS && 981 !aic31xx->master_dapm_route_applied) { 982 /* 983 * Add the needed DAPM route(s) for codec clock master modes, 984 * if it is not done already 985 */ 986 ret = snd_soc_dapm_add_routes(dapm, common31xx_cm_audio_map, 987 ARRAY_SIZE(common31xx_cm_audio_map)); 988 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT)) 989 ret = snd_soc_dapm_add_routes(dapm, 990 aic31xx_cm_audio_map, 991 ARRAY_SIZE(aic31xx_cm_audio_map)); 992 993 if (ret) 994 return ret; 995 996 aic31xx->master_dapm_route_applied = true; 997 } 998 999 return 0; 1000 } 1001 1002 static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 1003 unsigned int fmt) 1004 { 1005 struct snd_soc_component *component = codec_dai->component; 1006 u8 iface_reg1 = 0; 1007 u8 iface_reg2 = 0; 1008 u8 dsp_a_val = 0; 1009 1010 dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt); 1011 1012 /* set master/slave audio interface */ 1013 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1014 case SND_SOC_DAIFMT_CBM_CFM: 1015 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER; 1016 break; 1017 case SND_SOC_DAIFMT_CBS_CFM: 1018 iface_reg1 |= AIC31XX_WCLK_MASTER; 1019 break; 1020 case SND_SOC_DAIFMT_CBM_CFS: 1021 iface_reg1 |= AIC31XX_BCLK_MASTER; 1022 break; 1023 case SND_SOC_DAIFMT_CBS_CFS: 1024 break; 1025 default: 1026 dev_err(component->dev, "Invalid DAI master/slave interface\n"); 1027 return -EINVAL; 1028 } 1029 1030 /* signal polarity */ 1031 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1032 case SND_SOC_DAIFMT_NB_NF: 1033 break; 1034 case SND_SOC_DAIFMT_IB_NF: 1035 iface_reg2 |= AIC31XX_BCLKINV_MASK; 1036 break; 1037 default: 1038 dev_err(component->dev, "Invalid DAI clock signal polarity\n"); 1039 return -EINVAL; 1040 } 1041 1042 /* interface format */ 1043 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1044 case SND_SOC_DAIFMT_I2S: 1045 break; 1046 case SND_SOC_DAIFMT_DSP_A: 1047 dsp_a_val = 0x1; /* fall through */ 1048 case SND_SOC_DAIFMT_DSP_B: 1049 /* 1050 * NOTE: This CODEC samples on the falling edge of BCLK in 1051 * DSP mode, this is inverted compared to what most DAIs 1052 * expect, so we invert for this mode 1053 */ 1054 iface_reg2 ^= AIC31XX_BCLKINV_MASK; 1055 iface_reg1 |= (AIC31XX_DSP_MODE << 1056 AIC31XX_IFACE1_DATATYPE_SHIFT); 1057 break; 1058 case SND_SOC_DAIFMT_RIGHT_J: 1059 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE << 1060 AIC31XX_IFACE1_DATATYPE_SHIFT); 1061 break; 1062 case SND_SOC_DAIFMT_LEFT_J: 1063 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE << 1064 AIC31XX_IFACE1_DATATYPE_SHIFT); 1065 break; 1066 default: 1067 dev_err(component->dev, "Invalid DAI interface format\n"); 1068 return -EINVAL; 1069 } 1070 1071 snd_soc_component_update_bits(component, AIC31XX_IFACE1, 1072 AIC31XX_IFACE1_DATATYPE_MASK | 1073 AIC31XX_IFACE1_MASTER_MASK, 1074 iface_reg1); 1075 snd_soc_component_update_bits(component, AIC31XX_DATA_OFFSET, 1076 AIC31XX_DATA_OFFSET_MASK, 1077 dsp_a_val); 1078 snd_soc_component_update_bits(component, AIC31XX_IFACE2, 1079 AIC31XX_BCLKINV_MASK, 1080 iface_reg2); 1081 1082 return aic31xx_clock_master_routes(component, fmt); 1083 } 1084 1085 static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1086 int clk_id, unsigned int freq, int dir) 1087 { 1088 struct snd_soc_component *component = codec_dai->component; 1089 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1090 int i; 1091 1092 dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n", 1093 __func__, clk_id, freq, dir); 1094 1095 for (i = 1; i < 8; i++) 1096 if (freq / i <= 20000000) 1097 break; 1098 if (freq/i > 20000000) { 1099 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n", 1100 __func__, freq); 1101 return -EINVAL; 1102 } 1103 aic31xx->p_div = i; 1104 1105 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) 1106 if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div) 1107 break; 1108 if (i == ARRAY_SIZE(aic31xx_divs)) { 1109 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n", 1110 __func__, freq); 1111 return -EINVAL; 1112 } 1113 1114 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */ 1115 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK, 1116 clk_id << AIC31XX_PLL_CLKIN_SHIFT); 1117 1118 aic31xx->sysclk = freq; 1119 1120 return 0; 1121 } 1122 1123 static int aic31xx_regulator_event(struct notifier_block *nb, 1124 unsigned long event, void *data) 1125 { 1126 struct aic31xx_disable_nb *disable_nb = 1127 container_of(nb, struct aic31xx_disable_nb, nb); 1128 struct aic31xx_priv *aic31xx = disable_nb->aic31xx; 1129 1130 if (event & REGULATOR_EVENT_DISABLE) { 1131 /* 1132 * Put codec to reset and as at least one of the 1133 * supplies was disabled. 1134 */ 1135 if (aic31xx->gpio_reset) 1136 gpiod_set_value(aic31xx->gpio_reset, 1); 1137 1138 regcache_mark_dirty(aic31xx->regmap); 1139 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__); 1140 } 1141 1142 return 0; 1143 } 1144 1145 static int aic31xx_reset(struct aic31xx_priv *aic31xx) 1146 { 1147 int ret = 0; 1148 1149 if (aic31xx->gpio_reset) { 1150 gpiod_set_value(aic31xx->gpio_reset, 1); 1151 ndelay(10); /* At least 10ns */ 1152 gpiod_set_value(aic31xx->gpio_reset, 0); 1153 } else { 1154 ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1); 1155 } 1156 mdelay(1); /* At least 1ms */ 1157 1158 return ret; 1159 } 1160 1161 static void aic31xx_clk_on(struct snd_soc_component *component) 1162 { 1163 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1164 u8 mask = AIC31XX_PM_MASK; 1165 u8 on = AIC31XX_PM_MASK; 1166 1167 dev_dbg(component->dev, "codec clock -> on (rate %d)\n", 1168 aic31xx_divs[aic31xx->rate_div_line].rate); 1169 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on); 1170 mdelay(10); 1171 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on); 1172 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on); 1173 if (aic31xx_divs[aic31xx->rate_div_line].nadc) 1174 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on); 1175 if (aic31xx_divs[aic31xx->rate_div_line].madc) 1176 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on); 1177 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on); 1178 } 1179 1180 static void aic31xx_clk_off(struct snd_soc_component *component) 1181 { 1182 u8 mask = AIC31XX_PM_MASK; 1183 u8 off = 0; 1184 1185 dev_dbg(component->dev, "codec clock -> off\n"); 1186 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off); 1187 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off); 1188 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off); 1189 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off); 1190 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off); 1191 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off); 1192 } 1193 1194 static int aic31xx_power_on(struct snd_soc_component *component) 1195 { 1196 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1197 int ret; 1198 1199 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies), 1200 aic31xx->supplies); 1201 if (ret) 1202 return ret; 1203 1204 regcache_cache_only(aic31xx->regmap, false); 1205 1206 /* Reset device registers for a consistent power-on like state */ 1207 ret = aic31xx_reset(aic31xx); 1208 if (ret < 0) 1209 dev_err(aic31xx->dev, "Could not reset device: %d\n", ret); 1210 1211 ret = regcache_sync(aic31xx->regmap); 1212 if (ret) { 1213 dev_err(component->dev, 1214 "Failed to restore cache: %d\n", ret); 1215 regcache_cache_only(aic31xx->regmap, true); 1216 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1217 aic31xx->supplies); 1218 return ret; 1219 } 1220 1221 return 0; 1222 } 1223 1224 static void aic31xx_power_off(struct snd_soc_component *component) 1225 { 1226 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1227 1228 regcache_cache_only(aic31xx->regmap, true); 1229 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1230 aic31xx->supplies); 1231 } 1232 1233 static int aic31xx_set_bias_level(struct snd_soc_component *component, 1234 enum snd_soc_bias_level level) 1235 { 1236 dev_dbg(component->dev, "## %s: %d -> %d\n", __func__, 1237 snd_soc_component_get_bias_level(component), level); 1238 1239 switch (level) { 1240 case SND_SOC_BIAS_ON: 1241 break; 1242 case SND_SOC_BIAS_PREPARE: 1243 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 1244 aic31xx_clk_on(component); 1245 break; 1246 case SND_SOC_BIAS_STANDBY: 1247 switch (snd_soc_component_get_bias_level(component)) { 1248 case SND_SOC_BIAS_OFF: 1249 aic31xx_power_on(component); 1250 break; 1251 case SND_SOC_BIAS_PREPARE: 1252 aic31xx_clk_off(component); 1253 break; 1254 default: 1255 BUG(); 1256 } 1257 break; 1258 case SND_SOC_BIAS_OFF: 1259 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 1260 aic31xx_power_off(component); 1261 break; 1262 } 1263 1264 return 0; 1265 } 1266 1267 static int aic31xx_set_jack(struct snd_soc_component *component, 1268 struct snd_soc_jack *jack, void *data) 1269 { 1270 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1271 1272 aic31xx->jack = jack; 1273 1274 /* Enable/Disable jack detection */ 1275 regmap_write(aic31xx->regmap, AIC31XX_HSDETECT, 1276 jack ? AIC31XX_HSD_ENABLE : 0); 1277 1278 return 0; 1279 } 1280 1281 static int aic31xx_codec_probe(struct snd_soc_component *component) 1282 { 1283 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1284 int i, ret; 1285 1286 dev_dbg(aic31xx->dev, "## %s\n", __func__); 1287 1288 aic31xx->component = component; 1289 1290 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) { 1291 aic31xx->disable_nb[i].nb.notifier_call = 1292 aic31xx_regulator_event; 1293 aic31xx->disable_nb[i].aic31xx = aic31xx; 1294 ret = devm_regulator_register_notifier( 1295 aic31xx->supplies[i].consumer, 1296 &aic31xx->disable_nb[i].nb); 1297 if (ret) { 1298 dev_err(component->dev, 1299 "Failed to request regulator notifier: %d\n", 1300 ret); 1301 return ret; 1302 } 1303 } 1304 1305 regcache_cache_only(aic31xx->regmap, true); 1306 regcache_mark_dirty(aic31xx->regmap); 1307 1308 ret = aic31xx_add_controls(component); 1309 if (ret) 1310 return ret; 1311 1312 ret = aic31xx_add_widgets(component); 1313 if (ret) 1314 return ret; 1315 1316 /* set output common-mode voltage */ 1317 snd_soc_component_update_bits(component, AIC31XX_HPDRIVER, 1318 AIC31XX_HPD_OCMV_MASK, 1319 aic31xx->ocmv << AIC31XX_HPD_OCMV_SHIFT); 1320 1321 return 0; 1322 } 1323 1324 static const struct snd_soc_component_driver soc_codec_driver_aic31xx = { 1325 .probe = aic31xx_codec_probe, 1326 .set_jack = aic31xx_set_jack, 1327 .set_bias_level = aic31xx_set_bias_level, 1328 .controls = common31xx_snd_controls, 1329 .num_controls = ARRAY_SIZE(common31xx_snd_controls), 1330 .dapm_widgets = common31xx_dapm_widgets, 1331 .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets), 1332 .dapm_routes = common31xx_audio_map, 1333 .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map), 1334 .suspend_bias_off = 1, 1335 .idle_bias_on = 1, 1336 .use_pmdown_time = 1, 1337 .endianness = 1, 1338 .non_legacy_dai_naming = 1, 1339 }; 1340 1341 static const struct snd_soc_dai_ops aic31xx_dai_ops = { 1342 .hw_params = aic31xx_hw_params, 1343 .set_sysclk = aic31xx_set_dai_sysclk, 1344 .set_fmt = aic31xx_set_dai_fmt, 1345 .digital_mute = aic31xx_dac_mute, 1346 }; 1347 1348 static struct snd_soc_dai_driver dac31xx_dai_driver[] = { 1349 { 1350 .name = "tlv320dac31xx-hifi", 1351 .playback = { 1352 .stream_name = "Playback", 1353 .channels_min = 2, 1354 .channels_max = 2, 1355 .rates = AIC31XX_RATES, 1356 .formats = AIC31XX_FORMATS, 1357 }, 1358 .ops = &aic31xx_dai_ops, 1359 .symmetric_rates = 1, 1360 } 1361 }; 1362 1363 static struct snd_soc_dai_driver aic31xx_dai_driver[] = { 1364 { 1365 .name = "tlv320aic31xx-hifi", 1366 .playback = { 1367 .stream_name = "Playback", 1368 .channels_min = 2, 1369 .channels_max = 2, 1370 .rates = AIC31XX_RATES, 1371 .formats = AIC31XX_FORMATS, 1372 }, 1373 .capture = { 1374 .stream_name = "Capture", 1375 .channels_min = 2, 1376 .channels_max = 2, 1377 .rates = AIC31XX_RATES, 1378 .formats = AIC31XX_FORMATS, 1379 }, 1380 .ops = &aic31xx_dai_ops, 1381 .symmetric_rates = 1, 1382 } 1383 }; 1384 1385 #if defined(CONFIG_OF) 1386 static const struct of_device_id tlv320aic31xx_of_match[] = { 1387 { .compatible = "ti,tlv320aic310x" }, 1388 { .compatible = "ti,tlv320aic311x" }, 1389 { .compatible = "ti,tlv320aic3100" }, 1390 { .compatible = "ti,tlv320aic3110" }, 1391 { .compatible = "ti,tlv320aic3120" }, 1392 { .compatible = "ti,tlv320aic3111" }, 1393 { .compatible = "ti,tlv320dac3100" }, 1394 { .compatible = "ti,tlv320dac3101" }, 1395 {}, 1396 }; 1397 MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match); 1398 #endif /* CONFIG_OF */ 1399 1400 #ifdef CONFIG_ACPI 1401 static const struct acpi_device_id aic31xx_acpi_match[] = { 1402 { "10TI3100", 0 }, 1403 { } 1404 }; 1405 MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match); 1406 #endif 1407 1408 static irqreturn_t aic31xx_irq(int irq, void *data) 1409 { 1410 struct aic31xx_priv *aic31xx = data; 1411 struct device *dev = aic31xx->dev; 1412 unsigned int value; 1413 bool handled = false; 1414 int ret; 1415 1416 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG, &value); 1417 if (ret) { 1418 dev_err(dev, "Failed to read interrupt mask: %d\n", ret); 1419 goto exit; 1420 } 1421 1422 if (value) 1423 handled = true; 1424 else 1425 goto read_overflow; 1426 1427 if (value & AIC31XX_HPLSCDETECT) 1428 dev_err(dev, "Short circuit on Left output is detected\n"); 1429 if (value & AIC31XX_HPRSCDETECT) 1430 dev_err(dev, "Short circuit on Right output is detected\n"); 1431 if (value & (AIC31XX_HSPLUG | AIC31XX_BUTTONPRESS)) { 1432 unsigned int val; 1433 int status = 0; 1434 1435 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG2, 1436 &val); 1437 if (ret) { 1438 dev_err(dev, "Failed to read interrupt mask: %d\n", 1439 ret); 1440 goto exit; 1441 } 1442 1443 if (val & AIC31XX_BUTTONPRESS) 1444 status |= SND_JACK_BTN_0; 1445 1446 ret = regmap_read(aic31xx->regmap, AIC31XX_HSDETECT, &val); 1447 if (ret) { 1448 dev_err(dev, "Failed to read headset type: %d\n", ret); 1449 goto exit; 1450 } 1451 1452 switch ((val & AIC31XX_HSD_TYPE_MASK) >> 1453 AIC31XX_HSD_TYPE_SHIFT) { 1454 case AIC31XX_HSD_HP: 1455 status |= SND_JACK_HEADPHONE; 1456 break; 1457 case AIC31XX_HSD_HS: 1458 status |= SND_JACK_HEADSET; 1459 break; 1460 default: 1461 break; 1462 } 1463 1464 if (aic31xx->jack) 1465 snd_soc_jack_report(aic31xx->jack, status, 1466 AIC31XX_JACK_MASK); 1467 } 1468 if (value & ~(AIC31XX_HPLSCDETECT | 1469 AIC31XX_HPRSCDETECT | 1470 AIC31XX_HSPLUG | 1471 AIC31XX_BUTTONPRESS)) 1472 dev_err(dev, "Unknown DAC interrupt flags: 0x%08x\n", value); 1473 1474 read_overflow: 1475 ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value); 1476 if (ret) { 1477 dev_err(dev, "Failed to read overflow flag: %d\n", ret); 1478 goto exit; 1479 } 1480 1481 if (value) 1482 handled = true; 1483 else 1484 goto exit; 1485 1486 if (value & AIC31XX_DAC_OF_LEFT) 1487 dev_warn(dev, "Left-channel DAC overflow has occurred\n"); 1488 if (value & AIC31XX_DAC_OF_RIGHT) 1489 dev_warn(dev, "Right-channel DAC overflow has occurred\n"); 1490 if (value & AIC31XX_DAC_OF_SHIFTER) 1491 dev_warn(dev, "DAC barrel shifter overflow has occurred\n"); 1492 if (value & AIC31XX_ADC_OF) 1493 dev_warn(dev, "ADC overflow has occurred\n"); 1494 if (value & AIC31XX_ADC_OF_SHIFTER) 1495 dev_warn(dev, "ADC barrel shifter overflow has occurred\n"); 1496 if (value & ~(AIC31XX_DAC_OF_LEFT | 1497 AIC31XX_DAC_OF_RIGHT | 1498 AIC31XX_DAC_OF_SHIFTER | 1499 AIC31XX_ADC_OF | 1500 AIC31XX_ADC_OF_SHIFTER)) 1501 dev_warn(dev, "Unknown overflow interrupt flags: 0x%08x\n", value); 1502 1503 exit: 1504 if (handled) 1505 return IRQ_HANDLED; 1506 else 1507 return IRQ_NONE; 1508 } 1509 1510 static void aic31xx_configure_ocmv(struct aic31xx_priv *priv) 1511 { 1512 struct device *dev = priv->dev; 1513 int dvdd, avdd; 1514 u32 value; 1515 1516 if (dev->fwnode && 1517 fwnode_property_read_u32(dev->fwnode, "ai31xx-ocmv", &value)) { 1518 /* OCMV setting is forced by DT */ 1519 if (value <= 3) { 1520 priv->ocmv = value; 1521 return; 1522 } 1523 } 1524 1525 avdd = regulator_get_voltage(priv->supplies[3].consumer); 1526 dvdd = regulator_get_voltage(priv->supplies[5].consumer); 1527 1528 if (avdd > 3600000 || dvdd > 1950000) { 1529 dev_warn(dev, 1530 "Too high supply voltage(s) AVDD: %d, DVDD: %d\n", 1531 avdd, dvdd); 1532 } else if (avdd == 3600000 && dvdd == 1950000) { 1533 priv->ocmv = AIC31XX_HPD_OCMV_1_8V; 1534 } else if (avdd >= 3300000 && dvdd >= 1800000) { 1535 priv->ocmv = AIC31XX_HPD_OCMV_1_65V; 1536 } else if (avdd >= 3000000 && dvdd >= 1650000) { 1537 priv->ocmv = AIC31XX_HPD_OCMV_1_5V; 1538 } else if (avdd >= 2700000 && dvdd >= 1525000) { 1539 priv->ocmv = AIC31XX_HPD_OCMV_1_35V; 1540 } else { 1541 dev_warn(dev, 1542 "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n", 1543 avdd, dvdd); 1544 } 1545 } 1546 1547 static int aic31xx_i2c_probe(struct i2c_client *i2c, 1548 const struct i2c_device_id *id) 1549 { 1550 struct aic31xx_priv *aic31xx; 1551 unsigned int micbias_value = MICBIAS_2_0V; 1552 int i, ret; 1553 1554 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__, 1555 id->name, (int)id->driver_data); 1556 1557 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL); 1558 if (!aic31xx) 1559 return -ENOMEM; 1560 1561 aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap); 1562 if (IS_ERR(aic31xx->regmap)) { 1563 ret = PTR_ERR(aic31xx->regmap); 1564 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1565 ret); 1566 return ret; 1567 } 1568 aic31xx->dev = &i2c->dev; 1569 aic31xx->irq = i2c->irq; 1570 1571 aic31xx->codec_type = id->driver_data; 1572 1573 dev_set_drvdata(aic31xx->dev, aic31xx); 1574 1575 fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg", 1576 &micbias_value); 1577 switch (micbias_value) { 1578 case MICBIAS_2_0V: 1579 case MICBIAS_2_5V: 1580 case MICBIAS_AVDDV: 1581 aic31xx->micbias_vg = micbias_value; 1582 break; 1583 default: 1584 dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n", 1585 micbias_value); 1586 aic31xx->micbias_vg = MICBIAS_2_0V; 1587 } 1588 1589 if (dev_get_platdata(aic31xx->dev)) { 1590 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata)); 1591 aic31xx->codec_type = aic31xx->pdata.codec_type; 1592 aic31xx->micbias_vg = aic31xx->pdata.micbias_vg; 1593 } 1594 1595 aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset", 1596 GPIOD_OUT_LOW); 1597 if (IS_ERR(aic31xx->gpio_reset)) { 1598 if (PTR_ERR(aic31xx->gpio_reset) != -EPROBE_DEFER) 1599 dev_err(aic31xx->dev, "not able to acquire gpio\n"); 1600 return PTR_ERR(aic31xx->gpio_reset); 1601 } 1602 1603 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) 1604 aic31xx->supplies[i].supply = aic31xx_supply_names[i]; 1605 1606 ret = devm_regulator_bulk_get(aic31xx->dev, 1607 ARRAY_SIZE(aic31xx->supplies), 1608 aic31xx->supplies); 1609 if (ret) { 1610 if (ret != -EPROBE_DEFER) 1611 dev_err(aic31xx->dev, 1612 "Failed to request supplies: %d\n", ret); 1613 return ret; 1614 } 1615 1616 aic31xx_configure_ocmv(aic31xx); 1617 1618 if (aic31xx->irq > 0) { 1619 regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1, 1620 AIC31XX_GPIO1_FUNC_MASK, 1621 AIC31XX_GPIO1_INT1 << 1622 AIC31XX_GPIO1_FUNC_SHIFT); 1623 1624 regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL, 1625 AIC31XX_HSPLUGDET | 1626 AIC31XX_BUTTONPRESSDET | 1627 AIC31XX_SC | 1628 AIC31XX_ENGINE); 1629 1630 ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq, 1631 NULL, aic31xx_irq, 1632 IRQF_ONESHOT, "aic31xx-irq", 1633 aic31xx); 1634 if (ret) { 1635 dev_err(aic31xx->dev, "Unable to request IRQ\n"); 1636 return ret; 1637 } 1638 } 1639 1640 if (aic31xx->codec_type & DAC31XX_BIT) 1641 return devm_snd_soc_register_component(&i2c->dev, 1642 &soc_codec_driver_aic31xx, 1643 dac31xx_dai_driver, 1644 ARRAY_SIZE(dac31xx_dai_driver)); 1645 else 1646 return devm_snd_soc_register_component(&i2c->dev, 1647 &soc_codec_driver_aic31xx, 1648 aic31xx_dai_driver, 1649 ARRAY_SIZE(aic31xx_dai_driver)); 1650 } 1651 1652 static const struct i2c_device_id aic31xx_i2c_id[] = { 1653 { "tlv320aic310x", AIC3100 }, 1654 { "tlv320aic311x", AIC3110 }, 1655 { "tlv320aic3100", AIC3100 }, 1656 { "tlv320aic3110", AIC3110 }, 1657 { "tlv320aic3120", AIC3120 }, 1658 { "tlv320aic3111", AIC3111 }, 1659 { "tlv320dac3100", DAC3100 }, 1660 { "tlv320dac3101", DAC3101 }, 1661 { } 1662 }; 1663 MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id); 1664 1665 static struct i2c_driver aic31xx_i2c_driver = { 1666 .driver = { 1667 .name = "tlv320aic31xx-codec", 1668 .of_match_table = of_match_ptr(tlv320aic31xx_of_match), 1669 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match), 1670 }, 1671 .probe = aic31xx_i2c_probe, 1672 .id_table = aic31xx_i2c_id, 1673 }; 1674 module_i2c_driver(aic31xx_i2c_driver); 1675 1676 MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>"); 1677 MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver"); 1678 MODULE_LICENSE("GPL v2"); 1679