1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ALSA SoC TLV320AIC31xx CODEC Driver 4 * 5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ 6 * Jyri Sarha <jsarha@ti.com> 7 * 8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com> 9 * 10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated 11 * high performance codecs which provides a stereo DAC, a mono ADC, 12 * and mono/stereo Class-D speaker driver. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/init.h> 18 #include <linux/delay.h> 19 #include <linux/pm.h> 20 #include <linux/i2c.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/acpi.h> 24 #include <linux/of.h> 25 #include <linux/of_gpio.h> 26 #include <linux/slab.h> 27 #include <sound/core.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 #include <dt-bindings/sound/tlv320aic31xx-micbias.h> 34 35 #include "tlv320aic31xx.h" 36 37 static const struct reg_default aic31xx_reg_defaults[] = { 38 { AIC31XX_CLKMUX, 0x00 }, 39 { AIC31XX_PLLPR, 0x11 }, 40 { AIC31XX_PLLJ, 0x04 }, 41 { AIC31XX_PLLDMSB, 0x00 }, 42 { AIC31XX_PLLDLSB, 0x00 }, 43 { AIC31XX_NDAC, 0x01 }, 44 { AIC31XX_MDAC, 0x01 }, 45 { AIC31XX_DOSRMSB, 0x00 }, 46 { AIC31XX_DOSRLSB, 0x80 }, 47 { AIC31XX_NADC, 0x01 }, 48 { AIC31XX_MADC, 0x01 }, 49 { AIC31XX_AOSR, 0x80 }, 50 { AIC31XX_IFACE1, 0x00 }, 51 { AIC31XX_DATA_OFFSET, 0x00 }, 52 { AIC31XX_IFACE2, 0x00 }, 53 { AIC31XX_BCLKN, 0x01 }, 54 { AIC31XX_DACSETUP, 0x14 }, 55 { AIC31XX_DACMUTE, 0x0c }, 56 { AIC31XX_LDACVOL, 0x00 }, 57 { AIC31XX_RDACVOL, 0x00 }, 58 { AIC31XX_ADCSETUP, 0x00 }, 59 { AIC31XX_ADCFGA, 0x80 }, 60 { AIC31XX_ADCVOL, 0x00 }, 61 { AIC31XX_HPDRIVER, 0x04 }, 62 { AIC31XX_SPKAMP, 0x06 }, 63 { AIC31XX_DACMIXERROUTE, 0x00 }, 64 { AIC31XX_LANALOGHPL, 0x7f }, 65 { AIC31XX_RANALOGHPR, 0x7f }, 66 { AIC31XX_LANALOGSPL, 0x7f }, 67 { AIC31XX_RANALOGSPR, 0x7f }, 68 { AIC31XX_HPLGAIN, 0x02 }, 69 { AIC31XX_HPRGAIN, 0x02 }, 70 { AIC31XX_SPLGAIN, 0x00 }, 71 { AIC31XX_SPRGAIN, 0x00 }, 72 { AIC31XX_MICBIAS, 0x00 }, 73 { AIC31XX_MICPGA, 0x80 }, 74 { AIC31XX_MICPGAPI, 0x00 }, 75 { AIC31XX_MICPGAMI, 0x00 }, 76 }; 77 78 static bool aic31xx_volatile(struct device *dev, unsigned int reg) 79 { 80 switch (reg) { 81 case AIC31XX_PAGECTL: /* regmap implementation requires this */ 82 case AIC31XX_RESET: /* always clears after write */ 83 case AIC31XX_OT_FLAG: 84 case AIC31XX_ADCFLAG: 85 case AIC31XX_DACFLAG1: 86 case AIC31XX_DACFLAG2: 87 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 88 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 89 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 90 case AIC31XX_INTRDACFLAG2: 91 case AIC31XX_INTRADCFLAG2: 92 return true; 93 } 94 return false; 95 } 96 97 static bool aic31xx_writeable(struct device *dev, unsigned int reg) 98 { 99 switch (reg) { 100 case AIC31XX_OT_FLAG: 101 case AIC31XX_ADCFLAG: 102 case AIC31XX_DACFLAG1: 103 case AIC31XX_DACFLAG2: 104 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 105 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 106 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 107 case AIC31XX_INTRDACFLAG2: 108 case AIC31XX_INTRADCFLAG2: 109 return false; 110 } 111 return true; 112 } 113 114 static const struct regmap_range_cfg aic31xx_ranges[] = { 115 { 116 .range_min = 0, 117 .range_max = 12 * 128, 118 .selector_reg = AIC31XX_PAGECTL, 119 .selector_mask = 0xff, 120 .selector_shift = 0, 121 .window_start = 0, 122 .window_len = 128, 123 }, 124 }; 125 126 static const struct regmap_config aic31xx_i2c_regmap = { 127 .reg_bits = 8, 128 .val_bits = 8, 129 .writeable_reg = aic31xx_writeable, 130 .volatile_reg = aic31xx_volatile, 131 .reg_defaults = aic31xx_reg_defaults, 132 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults), 133 .cache_type = REGCACHE_RBTREE, 134 .ranges = aic31xx_ranges, 135 .num_ranges = ARRAY_SIZE(aic31xx_ranges), 136 .max_register = 12 * 128, 137 }; 138 139 static const char * const aic31xx_supply_names[] = { 140 "HPVDD", 141 "SPRVDD", 142 "SPLVDD", 143 "AVDD", 144 "IOVDD", 145 "DVDD", 146 }; 147 148 #define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names) 149 150 struct aic31xx_disable_nb { 151 struct notifier_block nb; 152 struct aic31xx_priv *aic31xx; 153 }; 154 155 struct aic31xx_priv { 156 struct snd_soc_codec *codec; 157 u8 i2c_regs_status; 158 struct device *dev; 159 struct regmap *regmap; 160 enum aic31xx_type codec_type; 161 struct gpio_desc *gpio_reset; 162 int micbias_vg; 163 struct aic31xx_pdata pdata; 164 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES]; 165 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES]; 166 unsigned int sysclk; 167 u8 p_div; 168 int rate_div_line; 169 }; 170 171 struct aic31xx_rate_divs { 172 u32 mclk_p; 173 u32 rate; 174 u8 pll_j; 175 u16 pll_d; 176 u16 dosr; 177 u8 ndac; 178 u8 mdac; 179 u8 aosr; 180 u8 nadc; 181 u8 madc; 182 }; 183 184 /* ADC dividers can be disabled by configuring them to 0 */ 185 static const struct aic31xx_rate_divs aic31xx_divs[] = { 186 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */ 187 /* 8k rate */ 188 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2}, 189 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3}, 190 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2}, 191 /* 11.025k rate */ 192 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2}, 193 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3}, 194 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2}, 195 /* 16k rate */ 196 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2}, 197 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3}, 198 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2}, 199 /* 22.05k rate */ 200 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2}, 201 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3}, 202 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2}, 203 /* 32k rate */ 204 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2}, 205 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3}, 206 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2}, 207 /* 44.1k rate */ 208 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2}, 209 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3}, 210 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2}, 211 /* 48k rate */ 212 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2}, 213 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4}, 214 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2}, 215 /* 88.2k rate */ 216 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2}, 217 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3}, 218 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2}, 219 /* 96k rate */ 220 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2}, 221 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4}, 222 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2}, 223 /* 176.4k rate */ 224 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2}, 225 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3}, 226 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2}, 227 /* 192k rate */ 228 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2}, 229 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4}, 230 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2}, 231 }; 232 233 static const char * const ldac_in_text[] = { 234 "Off", "Left Data", "Right Data", "Mono" 235 }; 236 237 static const char * const rdac_in_text[] = { 238 "Off", "Right Data", "Left Data", "Mono" 239 }; 240 241 static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text); 242 243 static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text); 244 245 static const char * const mic_select_text[] = { 246 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm" 247 }; 248 249 static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6, 250 mic_select_text); 251 static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4, 252 mic_select_text); 253 static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2, 254 mic_select_text); 255 256 static SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text); 257 static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4, 258 mic_select_text); 259 260 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0); 261 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0); 262 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0); 263 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0); 264 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0); 265 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0); 266 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0); 267 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0); 268 269 /* 270 * controls to be exported to the user space 271 */ 272 static const struct snd_kcontrol_new common31xx_snd_controls[] = { 273 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL, 274 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv), 275 276 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN, 277 AIC31XX_HPRGAIN, 2, 1, 0), 278 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN, 279 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv), 280 281 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL, 282 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv), 283 }; 284 285 static const struct snd_kcontrol_new aic31xx_snd_controls[] = { 286 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1, 287 adc_fgain_tlv), 288 289 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1), 290 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL, 291 0, -24, 40, 6, 0, adc_cgain_tlv), 292 293 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0, 294 119, 0, mic_pga_tlv), 295 }; 296 297 static const struct snd_kcontrol_new aic311x_snd_controls[] = { 298 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 299 AIC31XX_SPRGAIN, 2, 1, 0), 300 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 301 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv), 302 303 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 304 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv), 305 }; 306 307 static const struct snd_kcontrol_new aic310x_snd_controls[] = { 308 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 309 2, 1, 0), 310 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 311 3, 3, 0, class_D_drv_tlv), 312 313 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 314 0, 0x7F, 1, sp_vol_tlv), 315 }; 316 317 static const struct snd_kcontrol_new ldac_in_control = 318 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum); 319 320 static const struct snd_kcontrol_new rdac_in_control = 321 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum); 322 323 static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg, 324 unsigned int mask, unsigned int wbits, int sleep, 325 int count) 326 { 327 unsigned int bits; 328 int counter = count; 329 int ret = regmap_read(aic31xx->regmap, reg, &bits); 330 331 while ((bits & mask) != wbits && counter && !ret) { 332 usleep_range(sleep, sleep * 2); 333 ret = regmap_read(aic31xx->regmap, reg, &bits); 334 counter--; 335 } 336 if ((bits & mask) != wbits) { 337 dev_err(aic31xx->dev, 338 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n", 339 __func__, reg, bits, wbits, ret, mask, 340 (count - counter) * sleep); 341 ret = -1; 342 } 343 return ret; 344 } 345 346 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg)) 347 348 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w, 349 struct snd_kcontrol *kcontrol, int event) 350 { 351 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 352 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 353 unsigned int reg = AIC31XX_DACFLAG1; 354 unsigned int mask; 355 356 switch (WIDGET_BIT(w->reg, w->shift)) { 357 case WIDGET_BIT(AIC31XX_DACSETUP, 7): 358 mask = AIC31XX_LDACPWRSTATUS_MASK; 359 break; 360 case WIDGET_BIT(AIC31XX_DACSETUP, 6): 361 mask = AIC31XX_RDACPWRSTATUS_MASK; 362 break; 363 case WIDGET_BIT(AIC31XX_HPDRIVER, 7): 364 mask = AIC31XX_HPLDRVPWRSTATUS_MASK; 365 break; 366 case WIDGET_BIT(AIC31XX_HPDRIVER, 6): 367 mask = AIC31XX_HPRDRVPWRSTATUS_MASK; 368 break; 369 case WIDGET_BIT(AIC31XX_SPKAMP, 7): 370 mask = AIC31XX_SPLDRVPWRSTATUS_MASK; 371 break; 372 case WIDGET_BIT(AIC31XX_SPKAMP, 6): 373 mask = AIC31XX_SPRDRVPWRSTATUS_MASK; 374 break; 375 case WIDGET_BIT(AIC31XX_ADCSETUP, 7): 376 mask = AIC31XX_ADCPWRSTATUS_MASK; 377 reg = AIC31XX_ADCFLAG; 378 break; 379 default: 380 dev_err(codec->dev, "Unknown widget '%s' calling %s\n", 381 w->name, __func__); 382 return -EINVAL; 383 } 384 385 switch (event) { 386 case SND_SOC_DAPM_POST_PMU: 387 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100); 388 case SND_SOC_DAPM_POST_PMD: 389 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100); 390 default: 391 dev_dbg(codec->dev, 392 "Unhandled dapm widget event %d from %s\n", 393 event, w->name); 394 } 395 return 0; 396 } 397 398 static const struct snd_kcontrol_new aic31xx_left_output_switches[] = { 399 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 400 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0), 401 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0), 402 }; 403 404 static const struct snd_kcontrol_new aic31xx_right_output_switches[] = { 405 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 406 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0), 407 }; 408 409 static const struct snd_kcontrol_new dac31xx_left_output_switches[] = { 410 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 411 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0), 412 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0), 413 }; 414 415 static const struct snd_kcontrol_new dac31xx_right_output_switches[] = { 416 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 417 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0), 418 }; 419 420 static const struct snd_kcontrol_new p_term_mic1lp = 421 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum); 422 423 static const struct snd_kcontrol_new p_term_mic1rp = 424 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum); 425 426 static const struct snd_kcontrol_new p_term_mic1lm = 427 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum); 428 429 static const struct snd_kcontrol_new m_term_mic1lm = 430 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum); 431 432 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch = 433 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0); 434 435 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch = 436 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0); 437 438 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch = 439 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0); 440 441 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch = 442 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0); 443 444 static int mic_bias_event(struct snd_soc_dapm_widget *w, 445 struct snd_kcontrol *kcontrol, int event) 446 { 447 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 448 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 449 450 switch (event) { 451 case SND_SOC_DAPM_POST_PMU: 452 /* change mic bias voltage to user defined */ 453 snd_soc_update_bits(codec, AIC31XX_MICBIAS, 454 AIC31XX_MICBIAS_MASK, 455 aic31xx->micbias_vg << 456 AIC31XX_MICBIAS_SHIFT); 457 dev_dbg(codec->dev, "%s: turned on\n", __func__); 458 break; 459 case SND_SOC_DAPM_PRE_PMD: 460 /* turn mic bias off */ 461 snd_soc_update_bits(codec, AIC31XX_MICBIAS, 462 AIC31XX_MICBIAS_MASK, 0); 463 dev_dbg(codec->dev, "%s: turned off\n", __func__); 464 break; 465 } 466 return 0; 467 } 468 469 static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = { 470 SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0), 471 472 SND_SOC_DAPM_MUX("DAC Left Input", 473 SND_SOC_NOPM, 0, 0, &ldac_in_control), 474 SND_SOC_DAPM_MUX("DAC Right Input", 475 SND_SOC_NOPM, 0, 0, &rdac_in_control), 476 /* DACs */ 477 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback", 478 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event, 479 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 480 481 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback", 482 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event, 483 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 484 485 /* HP */ 486 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0, 487 &aic31xx_dapm_hpl_switch), 488 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0, 489 &aic31xx_dapm_hpr_switch), 490 491 /* Output drivers */ 492 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0, 493 NULL, 0, aic31xx_dapm_power_event, 494 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 495 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0, 496 NULL, 0, aic31xx_dapm_power_event, 497 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 498 499 /* Mic Bias */ 500 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event, 501 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 502 503 /* Outputs */ 504 SND_SOC_DAPM_OUTPUT("HPL"), 505 SND_SOC_DAPM_OUTPUT("HPR"), 506 }; 507 508 static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = { 509 /* Inputs */ 510 SND_SOC_DAPM_INPUT("AIN1"), 511 SND_SOC_DAPM_INPUT("AIN2"), 512 513 /* Output Mixers */ 514 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 515 dac31xx_left_output_switches, 516 ARRAY_SIZE(dac31xx_left_output_switches)), 517 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 518 dac31xx_right_output_switches, 519 ARRAY_SIZE(dac31xx_right_output_switches)), 520 }; 521 522 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = { 523 /* Inputs */ 524 SND_SOC_DAPM_INPUT("MIC1LP"), 525 SND_SOC_DAPM_INPUT("MIC1RP"), 526 SND_SOC_DAPM_INPUT("MIC1LM"), 527 528 /* Input Selection to MIC_PGA */ 529 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0, 530 &p_term_mic1lp), 531 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0, 532 &p_term_mic1rp), 533 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0, 534 &p_term_mic1lm), 535 536 /* ADC */ 537 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0, 538 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 539 SND_SOC_DAPM_POST_PMD), 540 541 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0, 542 &m_term_mic1lm), 543 544 /* Enabling & Disabling MIC Gain Ctl */ 545 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA, 546 7, 1, NULL, 0), 547 548 /* Output Mixers */ 549 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 550 aic31xx_left_output_switches, 551 ARRAY_SIZE(aic31xx_left_output_switches)), 552 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 553 aic31xx_right_output_switches, 554 ARRAY_SIZE(aic31xx_right_output_switches)), 555 }; 556 557 static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = { 558 /* AIC3111 and AIC3110 have stereo class-D amplifier */ 559 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 560 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 561 SND_SOC_DAPM_POST_PMD), 562 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0, 563 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 564 SND_SOC_DAPM_POST_PMD), 565 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0, 566 &aic31xx_dapm_spl_switch), 567 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0, 568 &aic31xx_dapm_spr_switch), 569 SND_SOC_DAPM_OUTPUT("SPL"), 570 SND_SOC_DAPM_OUTPUT("SPR"), 571 }; 572 573 /* AIC3100 and AIC3120 have only mono class-D amplifier */ 574 static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = { 575 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 576 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 577 SND_SOC_DAPM_POST_PMD), 578 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0, 579 &aic31xx_dapm_spl_switch), 580 SND_SOC_DAPM_OUTPUT("SPK"), 581 }; 582 583 static const struct snd_soc_dapm_route 584 common31xx_audio_map[] = { 585 /* DAC Input Routing */ 586 {"DAC Left Input", "Left Data", "DAC IN"}, 587 {"DAC Left Input", "Right Data", "DAC IN"}, 588 {"DAC Left Input", "Mono", "DAC IN"}, 589 {"DAC Right Input", "Left Data", "DAC IN"}, 590 {"DAC Right Input", "Right Data", "DAC IN"}, 591 {"DAC Right Input", "Mono", "DAC IN"}, 592 {"DAC Left", NULL, "DAC Left Input"}, 593 {"DAC Right", NULL, "DAC Right Input"}, 594 595 /* HPL path */ 596 {"HP Left", "Switch", "Output Left"}, 597 {"HPL Driver", NULL, "HP Left"}, 598 {"HPL", NULL, "HPL Driver"}, 599 600 /* HPR path */ 601 {"HP Right", "Switch", "Output Right"}, 602 {"HPR Driver", NULL, "HP Right"}, 603 {"HPR", NULL, "HPR Driver"}, 604 }; 605 606 static const struct snd_soc_dapm_route 607 dac31xx_audio_map[] = { 608 /* Left Output */ 609 {"Output Left", "From Left DAC", "DAC Left"}, 610 {"Output Left", "From AIN1", "AIN1"}, 611 {"Output Left", "From AIN2", "AIN2"}, 612 613 /* Right Output */ 614 {"Output Right", "From Right DAC", "DAC Right"}, 615 {"Output Right", "From AIN2", "AIN2"}, 616 }; 617 618 static const struct snd_soc_dapm_route 619 aic31xx_audio_map[] = { 620 /* Mic input */ 621 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"}, 622 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"}, 623 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"}, 624 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"}, 625 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"}, 626 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"}, 627 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"}, 628 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"}, 629 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"}, 630 631 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"}, 632 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"}, 633 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"}, 634 635 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"}, 636 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"}, 637 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"}, 638 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"}, 639 640 {"ADC", NULL, "MIC_GAIN_CTL"}, 641 642 /* Left Output */ 643 {"Output Left", "From Left DAC", "DAC Left"}, 644 {"Output Left", "From MIC1LP", "MIC1LP"}, 645 {"Output Left", "From MIC1RP", "MIC1RP"}, 646 647 /* Right Output */ 648 {"Output Right", "From Right DAC", "DAC Right"}, 649 {"Output Right", "From MIC1RP", "MIC1RP"}, 650 }; 651 652 static const struct snd_soc_dapm_route 653 aic311x_audio_map[] = { 654 /* SP L path */ 655 {"Speaker Left", "Switch", "Output Left"}, 656 {"SPL ClassD", NULL, "Speaker Left"}, 657 {"SPL", NULL, "SPL ClassD"}, 658 659 /* SP R path */ 660 {"Speaker Right", "Switch", "Output Right"}, 661 {"SPR ClassD", NULL, "Speaker Right"}, 662 {"SPR", NULL, "SPR ClassD"}, 663 }; 664 665 static const struct snd_soc_dapm_route 666 aic310x_audio_map[] = { 667 /* SP L path */ 668 {"Speaker", "Switch", "Output Left"}, 669 {"SPK ClassD", NULL, "Speaker"}, 670 {"SPK", NULL, "SPK ClassD"}, 671 }; 672 673 static int aic31xx_add_controls(struct snd_soc_codec *codec) 674 { 675 int ret = 0; 676 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 677 678 if (!(aic31xx->codec_type & DAC31XX_BIT)) 679 ret = snd_soc_add_codec_controls( 680 codec, aic31xx_snd_controls, 681 ARRAY_SIZE(aic31xx_snd_controls)); 682 if (ret) 683 return ret; 684 685 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) 686 ret = snd_soc_add_codec_controls( 687 codec, aic311x_snd_controls, 688 ARRAY_SIZE(aic311x_snd_controls)); 689 else 690 ret = snd_soc_add_codec_controls( 691 codec, aic310x_snd_controls, 692 ARRAY_SIZE(aic310x_snd_controls)); 693 694 return ret; 695 } 696 697 static int aic31xx_add_widgets(struct snd_soc_codec *codec) 698 { 699 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 700 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 701 int ret = 0; 702 703 if (aic31xx->codec_type & DAC31XX_BIT) { 704 ret = snd_soc_dapm_new_controls( 705 dapm, dac31xx_dapm_widgets, 706 ARRAY_SIZE(dac31xx_dapm_widgets)); 707 if (ret) 708 return ret; 709 710 ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map, 711 ARRAY_SIZE(dac31xx_audio_map)); 712 if (ret) 713 return ret; 714 } else { 715 ret = snd_soc_dapm_new_controls( 716 dapm, aic31xx_dapm_widgets, 717 ARRAY_SIZE(aic31xx_dapm_widgets)); 718 if (ret) 719 return ret; 720 721 ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map, 722 ARRAY_SIZE(aic31xx_audio_map)); 723 if (ret) 724 return ret; 725 } 726 727 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) { 728 ret = snd_soc_dapm_new_controls( 729 dapm, aic311x_dapm_widgets, 730 ARRAY_SIZE(aic311x_dapm_widgets)); 731 if (ret) 732 return ret; 733 734 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map, 735 ARRAY_SIZE(aic311x_audio_map)); 736 if (ret) 737 return ret; 738 } else { 739 ret = snd_soc_dapm_new_controls( 740 dapm, aic310x_dapm_widgets, 741 ARRAY_SIZE(aic310x_dapm_widgets)); 742 if (ret) 743 return ret; 744 745 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map, 746 ARRAY_SIZE(aic310x_audio_map)); 747 if (ret) 748 return ret; 749 } 750 751 return 0; 752 } 753 754 static int aic31xx_setup_pll(struct snd_soc_codec *codec, 755 struct snd_pcm_hw_params *params) 756 { 757 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 758 int bclk_score = snd_soc_params_to_frame_size(params); 759 int mclk_p; 760 int bclk_n = 0; 761 int match = -1; 762 int i; 763 764 if (!aic31xx->sysclk || !aic31xx->p_div) { 765 dev_err(codec->dev, "Master clock not supplied\n"); 766 return -EINVAL; 767 } 768 mclk_p = aic31xx->sysclk / aic31xx->p_div; 769 770 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */ 771 snd_soc_update_bits(codec, AIC31XX_CLKMUX, 772 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL); 773 snd_soc_update_bits(codec, AIC31XX_IFACE2, 774 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK); 775 776 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { 777 if (aic31xx_divs[i].rate == params_rate(params) && 778 aic31xx_divs[i].mclk_p == mclk_p) { 779 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) % 780 snd_soc_params_to_frame_size(params); 781 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) / 782 snd_soc_params_to_frame_size(params); 783 if (s < bclk_score && bn > 0) { 784 match = i; 785 bclk_n = bn; 786 bclk_score = s; 787 } 788 } 789 } 790 791 if (match == -1) { 792 dev_err(codec->dev, 793 "%s: Sample rate (%u) and format not supported\n", 794 __func__, params_rate(params)); 795 /* See bellow for details how fix this. */ 796 return -EINVAL; 797 } 798 if (bclk_score != 0) { 799 dev_warn(codec->dev, "Can not produce exact bitclock"); 800 /* This is fine if using dsp format, but if using i2s 801 there may be trouble. To fix the issue edit the 802 aic31xx_divs table for your mclk and sample 803 rate. Details can be found from: 804 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf 805 Section: 5.6 CLOCK Generation and PLL 806 */ 807 } 808 i = match; 809 810 /* PLL configuration */ 811 snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK, 812 (aic31xx->p_div << 4) | 0x01); 813 snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j); 814 815 snd_soc_write(codec, AIC31XX_PLLDMSB, 816 aic31xx_divs[i].pll_d >> 8); 817 snd_soc_write(codec, AIC31XX_PLLDLSB, 818 aic31xx_divs[i].pll_d & 0xff); 819 820 /* DAC dividers configuration */ 821 snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK, 822 aic31xx_divs[i].ndac); 823 snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK, 824 aic31xx_divs[i].mdac); 825 826 snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8); 827 snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff); 828 829 /* ADC dividers configuration. Write reset value 1 if not used. */ 830 snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK, 831 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1); 832 snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK, 833 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1); 834 835 snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr); 836 837 /* Bit clock divider configuration. */ 838 snd_soc_update_bits(codec, AIC31XX_BCLKN, 839 AIC31XX_PLL_MASK, bclk_n); 840 841 aic31xx->rate_div_line = i; 842 843 dev_dbg(codec->dev, 844 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n", 845 aic31xx_divs[i].pll_j, 846 aic31xx_divs[i].pll_d, 847 aic31xx->p_div, 848 aic31xx_divs[i].dosr, 849 aic31xx_divs[i].ndac, 850 aic31xx_divs[i].mdac, 851 aic31xx_divs[i].aosr, 852 aic31xx_divs[i].nadc, 853 aic31xx_divs[i].madc, 854 bclk_n 855 ); 856 857 return 0; 858 } 859 860 static int aic31xx_hw_params(struct snd_pcm_substream *substream, 861 struct snd_pcm_hw_params *params, 862 struct snd_soc_dai *dai) 863 { 864 struct snd_soc_codec *codec = dai->codec; 865 u8 data = 0; 866 867 dev_dbg(codec->dev, "## %s: width %d rate %d\n", 868 __func__, params_width(params), 869 params_rate(params)); 870 871 switch (params_width(params)) { 872 case 16: 873 break; 874 case 20: 875 data = (AIC31XX_WORD_LEN_20BITS << 876 AIC31XX_IFACE1_DATALEN_SHIFT); 877 break; 878 case 24: 879 data = (AIC31XX_WORD_LEN_24BITS << 880 AIC31XX_IFACE1_DATALEN_SHIFT); 881 break; 882 case 32: 883 data = (AIC31XX_WORD_LEN_32BITS << 884 AIC31XX_IFACE1_DATALEN_SHIFT); 885 break; 886 default: 887 dev_err(codec->dev, "%s: Unsupported width %d\n", 888 __func__, params_width(params)); 889 return -EINVAL; 890 } 891 892 snd_soc_update_bits(codec, AIC31XX_IFACE1, 893 AIC31XX_IFACE1_DATALEN_MASK, 894 data); 895 896 return aic31xx_setup_pll(codec, params); 897 } 898 899 static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute) 900 { 901 struct snd_soc_codec *codec = codec_dai->codec; 902 903 if (mute) { 904 snd_soc_update_bits(codec, AIC31XX_DACMUTE, 905 AIC31XX_DACMUTE_MASK, 906 AIC31XX_DACMUTE_MASK); 907 } else { 908 snd_soc_update_bits(codec, AIC31XX_DACMUTE, 909 AIC31XX_DACMUTE_MASK, 0x0); 910 } 911 912 return 0; 913 } 914 915 static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 916 unsigned int fmt) 917 { 918 struct snd_soc_codec *codec = codec_dai->codec; 919 u8 iface_reg1 = 0; 920 u8 iface_reg2 = 0; 921 u8 dsp_a_val = 0; 922 923 dev_dbg(codec->dev, "## %s: fmt = 0x%x\n", __func__, fmt); 924 925 /* set master/slave audio interface */ 926 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 927 case SND_SOC_DAIFMT_CBM_CFM: 928 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER; 929 break; 930 case SND_SOC_DAIFMT_CBS_CFM: 931 iface_reg1 |= AIC31XX_WCLK_MASTER; 932 break; 933 case SND_SOC_DAIFMT_CBM_CFS: 934 iface_reg1 |= AIC31XX_BCLK_MASTER; 935 break; 936 case SND_SOC_DAIFMT_CBS_CFS: 937 break; 938 default: 939 dev_err(codec->dev, "Invalid DAI master/slave interface\n"); 940 return -EINVAL; 941 } 942 943 /* signal polarity */ 944 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 945 case SND_SOC_DAIFMT_NB_NF: 946 break; 947 case SND_SOC_DAIFMT_IB_NF: 948 iface_reg2 |= AIC31XX_BCLKINV_MASK; 949 break; 950 default: 951 dev_err(codec->dev, "Invalid DAI clock signal polarity\n"); 952 return -EINVAL; 953 } 954 955 /* interface format */ 956 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 957 case SND_SOC_DAIFMT_I2S: 958 break; 959 case SND_SOC_DAIFMT_DSP_A: 960 dsp_a_val = 0x1; /* fall through */ 961 case SND_SOC_DAIFMT_DSP_B: 962 /* 963 * NOTE: This CODEC samples on the falling edge of BCLK in 964 * DSP mode, this is inverted compared to what most DAIs 965 * expect, so we invert for this mode 966 */ 967 iface_reg2 ^= AIC31XX_BCLKINV_MASK; 968 iface_reg1 |= (AIC31XX_DSP_MODE << 969 AIC31XX_IFACE1_DATATYPE_SHIFT); 970 break; 971 case SND_SOC_DAIFMT_RIGHT_J: 972 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE << 973 AIC31XX_IFACE1_DATATYPE_SHIFT); 974 break; 975 case SND_SOC_DAIFMT_LEFT_J: 976 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE << 977 AIC31XX_IFACE1_DATATYPE_SHIFT); 978 break; 979 default: 980 dev_err(codec->dev, "Invalid DAI interface format\n"); 981 return -EINVAL; 982 } 983 984 snd_soc_update_bits(codec, AIC31XX_IFACE1, 985 AIC31XX_IFACE1_DATATYPE_MASK | 986 AIC31XX_IFACE1_MASTER_MASK, 987 iface_reg1); 988 snd_soc_update_bits(codec, AIC31XX_DATA_OFFSET, 989 AIC31XX_DATA_OFFSET_MASK, 990 dsp_a_val); 991 snd_soc_update_bits(codec, AIC31XX_IFACE2, 992 AIC31XX_BCLKINV_MASK, 993 iface_reg2); 994 995 return 0; 996 } 997 998 static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 999 int clk_id, unsigned int freq, int dir) 1000 { 1001 struct snd_soc_codec *codec = codec_dai->codec; 1002 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 1003 int i; 1004 1005 dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n", 1006 __func__, clk_id, freq, dir); 1007 1008 for (i = 1; i < 8; i++) 1009 if (freq / i <= 20000000) 1010 break; 1011 if (freq/i > 20000000) { 1012 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n", 1013 __func__, freq); 1014 return -EINVAL; 1015 } 1016 aic31xx->p_div = i; 1017 1018 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) 1019 if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div) 1020 break; 1021 if (i == ARRAY_SIZE(aic31xx_divs)) { 1022 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n", 1023 __func__, freq); 1024 return -EINVAL; 1025 } 1026 1027 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */ 1028 snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK, 1029 clk_id << AIC31XX_PLL_CLKIN_SHIFT); 1030 1031 aic31xx->sysclk = freq; 1032 1033 return 0; 1034 } 1035 1036 static int aic31xx_regulator_event(struct notifier_block *nb, 1037 unsigned long event, void *data) 1038 { 1039 struct aic31xx_disable_nb *disable_nb = 1040 container_of(nb, struct aic31xx_disable_nb, nb); 1041 struct aic31xx_priv *aic31xx = disable_nb->aic31xx; 1042 1043 if (event & REGULATOR_EVENT_DISABLE) { 1044 /* 1045 * Put codec to reset and as at least one of the 1046 * supplies was disabled. 1047 */ 1048 if (aic31xx->gpio_reset) 1049 gpiod_set_value(aic31xx->gpio_reset, 1); 1050 1051 regcache_mark_dirty(aic31xx->regmap); 1052 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__); 1053 } 1054 1055 return 0; 1056 } 1057 1058 static int aic31xx_reset(struct aic31xx_priv *aic31xx) 1059 { 1060 int ret = 0; 1061 1062 if (aic31xx->gpio_reset) { 1063 gpiod_set_value(aic31xx->gpio_reset, 1); 1064 ndelay(10); /* At least 10ns */ 1065 gpiod_set_value(aic31xx->gpio_reset, 0); 1066 } else { 1067 ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1); 1068 } 1069 mdelay(1); /* At least 1ms */ 1070 1071 return ret; 1072 } 1073 1074 static void aic31xx_clk_on(struct snd_soc_codec *codec) 1075 { 1076 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 1077 u8 mask = AIC31XX_PM_MASK; 1078 u8 on = AIC31XX_PM_MASK; 1079 1080 dev_dbg(codec->dev, "codec clock -> on (rate %d)\n", 1081 aic31xx_divs[aic31xx->rate_div_line].rate); 1082 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, on); 1083 mdelay(10); 1084 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, on); 1085 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, on); 1086 if (aic31xx_divs[aic31xx->rate_div_line].nadc) 1087 snd_soc_update_bits(codec, AIC31XX_NADC, mask, on); 1088 if (aic31xx_divs[aic31xx->rate_div_line].madc) 1089 snd_soc_update_bits(codec, AIC31XX_MADC, mask, on); 1090 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, on); 1091 } 1092 1093 static void aic31xx_clk_off(struct snd_soc_codec *codec) 1094 { 1095 u8 mask = AIC31XX_PM_MASK; 1096 u8 off = 0; 1097 1098 dev_dbg(codec->dev, "codec clock -> off\n"); 1099 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, off); 1100 snd_soc_update_bits(codec, AIC31XX_MADC, mask, off); 1101 snd_soc_update_bits(codec, AIC31XX_NADC, mask, off); 1102 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, off); 1103 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, off); 1104 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, off); 1105 } 1106 1107 static int aic31xx_power_on(struct snd_soc_codec *codec) 1108 { 1109 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 1110 int ret; 1111 1112 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies), 1113 aic31xx->supplies); 1114 if (ret) 1115 return ret; 1116 1117 regcache_cache_only(aic31xx->regmap, false); 1118 1119 /* Reset device registers for a consistent power-on like state */ 1120 ret = aic31xx_reset(aic31xx); 1121 if (ret < 0) 1122 dev_err(aic31xx->dev, "Could not reset device: %d\n", ret); 1123 1124 ret = regcache_sync(aic31xx->regmap); 1125 if (ret) { 1126 dev_err(codec->dev, 1127 "Failed to restore cache: %d\n", ret); 1128 regcache_cache_only(aic31xx->regmap, true); 1129 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1130 aic31xx->supplies); 1131 return ret; 1132 } 1133 1134 return 0; 1135 } 1136 1137 static void aic31xx_power_off(struct snd_soc_codec *codec) 1138 { 1139 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 1140 1141 regcache_cache_only(aic31xx->regmap, true); 1142 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1143 aic31xx->supplies); 1144 } 1145 1146 static int aic31xx_set_bias_level(struct snd_soc_codec *codec, 1147 enum snd_soc_bias_level level) 1148 { 1149 dev_dbg(codec->dev, "## %s: %d -> %d\n", __func__, 1150 snd_soc_codec_get_bias_level(codec), level); 1151 1152 switch (level) { 1153 case SND_SOC_BIAS_ON: 1154 break; 1155 case SND_SOC_BIAS_PREPARE: 1156 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) 1157 aic31xx_clk_on(codec); 1158 break; 1159 case SND_SOC_BIAS_STANDBY: 1160 switch (snd_soc_codec_get_bias_level(codec)) { 1161 case SND_SOC_BIAS_OFF: 1162 aic31xx_power_on(codec); 1163 break; 1164 case SND_SOC_BIAS_PREPARE: 1165 aic31xx_clk_off(codec); 1166 break; 1167 default: 1168 BUG(); 1169 } 1170 break; 1171 case SND_SOC_BIAS_OFF: 1172 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY) 1173 aic31xx_power_off(codec); 1174 break; 1175 } 1176 1177 return 0; 1178 } 1179 1180 static int aic31xx_codec_probe(struct snd_soc_codec *codec) 1181 { 1182 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 1183 int i, ret; 1184 1185 dev_dbg(aic31xx->dev, "## %s\n", __func__); 1186 1187 aic31xx->codec = codec; 1188 1189 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) { 1190 aic31xx->disable_nb[i].nb.notifier_call = 1191 aic31xx_regulator_event; 1192 aic31xx->disable_nb[i].aic31xx = aic31xx; 1193 ret = regulator_register_notifier(aic31xx->supplies[i].consumer, 1194 &aic31xx->disable_nb[i].nb); 1195 if (ret) { 1196 dev_err(codec->dev, 1197 "Failed to request regulator notifier: %d\n", 1198 ret); 1199 return ret; 1200 } 1201 } 1202 1203 regcache_cache_only(aic31xx->regmap, true); 1204 regcache_mark_dirty(aic31xx->regmap); 1205 1206 ret = aic31xx_add_controls(codec); 1207 if (ret) 1208 return ret; 1209 1210 ret = aic31xx_add_widgets(codec); 1211 if (ret) 1212 return ret; 1213 1214 return 0; 1215 } 1216 1217 static int aic31xx_codec_remove(struct snd_soc_codec *codec) 1218 { 1219 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 1220 int i; 1221 1222 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) 1223 regulator_unregister_notifier(aic31xx->supplies[i].consumer, 1224 &aic31xx->disable_nb[i].nb); 1225 1226 return 0; 1227 } 1228 1229 static const struct snd_soc_codec_driver soc_codec_driver_aic31xx = { 1230 .probe = aic31xx_codec_probe, 1231 .remove = aic31xx_codec_remove, 1232 .set_bias_level = aic31xx_set_bias_level, 1233 .suspend_bias_off = true, 1234 1235 .component_driver = { 1236 .controls = common31xx_snd_controls, 1237 .num_controls = ARRAY_SIZE(common31xx_snd_controls), 1238 .dapm_widgets = common31xx_dapm_widgets, 1239 .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets), 1240 .dapm_routes = common31xx_audio_map, 1241 .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map), 1242 }, 1243 }; 1244 1245 static const struct snd_soc_dai_ops aic31xx_dai_ops = { 1246 .hw_params = aic31xx_hw_params, 1247 .set_sysclk = aic31xx_set_dai_sysclk, 1248 .set_fmt = aic31xx_set_dai_fmt, 1249 .digital_mute = aic31xx_dac_mute, 1250 }; 1251 1252 static struct snd_soc_dai_driver dac31xx_dai_driver[] = { 1253 { 1254 .name = "tlv320dac31xx-hifi", 1255 .playback = { 1256 .stream_name = "Playback", 1257 .channels_min = 2, 1258 .channels_max = 2, 1259 .rates = AIC31XX_RATES, 1260 .formats = AIC31XX_FORMATS, 1261 }, 1262 .ops = &aic31xx_dai_ops, 1263 .symmetric_rates = 1, 1264 } 1265 }; 1266 1267 static struct snd_soc_dai_driver aic31xx_dai_driver[] = { 1268 { 1269 .name = "tlv320aic31xx-hifi", 1270 .playback = { 1271 .stream_name = "Playback", 1272 .channels_min = 2, 1273 .channels_max = 2, 1274 .rates = AIC31XX_RATES, 1275 .formats = AIC31XX_FORMATS, 1276 }, 1277 .capture = { 1278 .stream_name = "Capture", 1279 .channels_min = 2, 1280 .channels_max = 2, 1281 .rates = AIC31XX_RATES, 1282 .formats = AIC31XX_FORMATS, 1283 }, 1284 .ops = &aic31xx_dai_ops, 1285 .symmetric_rates = 1, 1286 } 1287 }; 1288 1289 #if defined(CONFIG_OF) 1290 static const struct of_device_id tlv320aic31xx_of_match[] = { 1291 { .compatible = "ti,tlv320aic310x" }, 1292 { .compatible = "ti,tlv320aic311x" }, 1293 { .compatible = "ti,tlv320aic3100" }, 1294 { .compatible = "ti,tlv320aic3110" }, 1295 { .compatible = "ti,tlv320aic3120" }, 1296 { .compatible = "ti,tlv320aic3111" }, 1297 { .compatible = "ti,tlv320dac3100" }, 1298 { .compatible = "ti,tlv320dac3101" }, 1299 {}, 1300 }; 1301 MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match); 1302 #endif /* CONFIG_OF */ 1303 1304 #ifdef CONFIG_ACPI 1305 static const struct acpi_device_id aic31xx_acpi_match[] = { 1306 { "10TI3100", 0 }, 1307 { } 1308 }; 1309 MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match); 1310 #endif 1311 1312 static int aic31xx_i2c_probe(struct i2c_client *i2c, 1313 const struct i2c_device_id *id) 1314 { 1315 struct aic31xx_priv *aic31xx; 1316 unsigned int micbias_value = MICBIAS_2_0V; 1317 int i, ret; 1318 1319 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__, 1320 id->name, (int)id->driver_data); 1321 1322 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL); 1323 if (!aic31xx) 1324 return -ENOMEM; 1325 1326 aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap); 1327 if (IS_ERR(aic31xx->regmap)) { 1328 ret = PTR_ERR(aic31xx->regmap); 1329 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1330 ret); 1331 return ret; 1332 } 1333 aic31xx->dev = &i2c->dev; 1334 1335 aic31xx->codec_type = id->driver_data; 1336 1337 dev_set_drvdata(aic31xx->dev, aic31xx); 1338 1339 fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg", 1340 &micbias_value); 1341 switch (micbias_value) { 1342 case MICBIAS_2_0V: 1343 case MICBIAS_2_5V: 1344 case MICBIAS_AVDDV: 1345 aic31xx->micbias_vg = micbias_value; 1346 break; 1347 default: 1348 dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n", 1349 micbias_value); 1350 aic31xx->micbias_vg = MICBIAS_2_0V; 1351 } 1352 1353 if (dev_get_platdata(aic31xx->dev)) { 1354 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata)); 1355 aic31xx->codec_type = aic31xx->pdata.codec_type; 1356 aic31xx->micbias_vg = aic31xx->pdata.micbias_vg; 1357 } 1358 1359 aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset", 1360 GPIOD_OUT_LOW); 1361 if (IS_ERR(aic31xx->gpio_reset)) { 1362 dev_err(aic31xx->dev, "not able to acquire gpio\n"); 1363 return PTR_ERR(aic31xx->gpio_reset); 1364 } 1365 1366 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) 1367 aic31xx->supplies[i].supply = aic31xx_supply_names[i]; 1368 1369 ret = devm_regulator_bulk_get(aic31xx->dev, 1370 ARRAY_SIZE(aic31xx->supplies), 1371 aic31xx->supplies); 1372 if (ret) { 1373 dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret); 1374 return ret; 1375 } 1376 1377 if (aic31xx->codec_type & DAC31XX_BIT) 1378 return snd_soc_register_codec(&i2c->dev, 1379 &soc_codec_driver_aic31xx, 1380 dac31xx_dai_driver, 1381 ARRAY_SIZE(dac31xx_dai_driver)); 1382 else 1383 return snd_soc_register_codec(&i2c->dev, 1384 &soc_codec_driver_aic31xx, 1385 aic31xx_dai_driver, 1386 ARRAY_SIZE(aic31xx_dai_driver)); 1387 } 1388 1389 static int aic31xx_i2c_remove(struct i2c_client *i2c) 1390 { 1391 snd_soc_unregister_codec(&i2c->dev); 1392 return 0; 1393 } 1394 1395 static const struct i2c_device_id aic31xx_i2c_id[] = { 1396 { "tlv320aic310x", AIC3100 }, 1397 { "tlv320aic311x", AIC3110 }, 1398 { "tlv320aic3100", AIC3100 }, 1399 { "tlv320aic3110", AIC3110 }, 1400 { "tlv320aic3120", AIC3120 }, 1401 { "tlv320aic3111", AIC3111 }, 1402 { "tlv320dac3100", DAC3100 }, 1403 { "tlv320dac3101", DAC3101 }, 1404 { } 1405 }; 1406 MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id); 1407 1408 static struct i2c_driver aic31xx_i2c_driver = { 1409 .driver = { 1410 .name = "tlv320aic31xx-codec", 1411 .of_match_table = of_match_ptr(tlv320aic31xx_of_match), 1412 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match), 1413 }, 1414 .probe = aic31xx_i2c_probe, 1415 .remove = aic31xx_i2c_remove, 1416 .id_table = aic31xx_i2c_id, 1417 }; 1418 module_i2c_driver(aic31xx_i2c_driver); 1419 1420 MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>"); 1421 MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver"); 1422 MODULE_LICENSE("GPL v2"); 1423