1 /* 2 * ALSA SoC TLV320AIC31XX codec driver 3 * 4 * Copyright (C) 2014 Texas Instruments, Inc. 5 * 6 * Author: Jyri Sarha <jsarha@ti.com> 7 * 8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com> 9 * 10 * This package is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * THIS PACKAGE IS PROVIDED AS IS AND WITHOUT ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 17 * 18 * The TLV320AIC31xx series of audio codec is a low-power, highly integrated 19 * high performance codec which provides a stereo DAC, a mono ADC, 20 * and mono/stereo Class-D speaker driver. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/moduleparam.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/pm.h> 28 #include <linux/i2c.h> 29 #include <linux/gpio.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/of_gpio.h> 32 #include <linux/slab.h> 33 #include <sound/core.h> 34 #include <sound/pcm.h> 35 #include <sound/pcm_params.h> 36 #include <sound/soc.h> 37 #include <sound/initval.h> 38 #include <sound/tlv.h> 39 #include <dt-bindings/sound/tlv320aic31xx-micbias.h> 40 41 #include "tlv320aic31xx.h" 42 43 static const struct reg_default aic31xx_reg_defaults[] = { 44 { AIC31XX_CLKMUX, 0x00 }, 45 { AIC31XX_PLLPR, 0x11 }, 46 { AIC31XX_PLLJ, 0x04 }, 47 { AIC31XX_PLLDMSB, 0x00 }, 48 { AIC31XX_PLLDLSB, 0x00 }, 49 { AIC31XX_NDAC, 0x01 }, 50 { AIC31XX_MDAC, 0x01 }, 51 { AIC31XX_DOSRMSB, 0x00 }, 52 { AIC31XX_DOSRLSB, 0x80 }, 53 { AIC31XX_NADC, 0x01 }, 54 { AIC31XX_MADC, 0x01 }, 55 { AIC31XX_AOSR, 0x80 }, 56 { AIC31XX_IFACE1, 0x00 }, 57 { AIC31XX_DATA_OFFSET, 0x00 }, 58 { AIC31XX_IFACE2, 0x00 }, 59 { AIC31XX_BCLKN, 0x01 }, 60 { AIC31XX_DACSETUP, 0x14 }, 61 { AIC31XX_DACMUTE, 0x0c }, 62 { AIC31XX_LDACVOL, 0x00 }, 63 { AIC31XX_RDACVOL, 0x00 }, 64 { AIC31XX_ADCSETUP, 0x00 }, 65 { AIC31XX_ADCFGA, 0x80 }, 66 { AIC31XX_ADCVOL, 0x00 }, 67 { AIC31XX_HPDRIVER, 0x04 }, 68 { AIC31XX_SPKAMP, 0x06 }, 69 { AIC31XX_DACMIXERROUTE, 0x00 }, 70 { AIC31XX_LANALOGHPL, 0x7f }, 71 { AIC31XX_RANALOGHPR, 0x7f }, 72 { AIC31XX_LANALOGSPL, 0x7f }, 73 { AIC31XX_RANALOGSPR, 0x7f }, 74 { AIC31XX_HPLGAIN, 0x02 }, 75 { AIC31XX_HPRGAIN, 0x02 }, 76 { AIC31XX_SPLGAIN, 0x00 }, 77 { AIC31XX_SPRGAIN, 0x00 }, 78 { AIC31XX_MICBIAS, 0x00 }, 79 { AIC31XX_MICPGA, 0x80 }, 80 { AIC31XX_MICPGAPI, 0x00 }, 81 { AIC31XX_MICPGAMI, 0x00 }, 82 }; 83 84 static bool aic31xx_volatile(struct device *dev, unsigned int reg) 85 { 86 switch (reg) { 87 case AIC31XX_PAGECTL: /* regmap implementation requires this */ 88 case AIC31XX_RESET: /* always clears after write */ 89 case AIC31XX_OT_FLAG: 90 case AIC31XX_ADCFLAG: 91 case AIC31XX_DACFLAG1: 92 case AIC31XX_DACFLAG2: 93 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 94 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 95 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 96 case AIC31XX_INTRDACFLAG2: 97 case AIC31XX_INTRADCFLAG2: 98 return true; 99 } 100 return false; 101 } 102 103 static bool aic31xx_writeable(struct device *dev, unsigned int reg) 104 { 105 switch (reg) { 106 case AIC31XX_OT_FLAG: 107 case AIC31XX_ADCFLAG: 108 case AIC31XX_DACFLAG1: 109 case AIC31XX_DACFLAG2: 110 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 111 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 112 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 113 case AIC31XX_INTRDACFLAG2: 114 case AIC31XX_INTRADCFLAG2: 115 return false; 116 } 117 return true; 118 } 119 120 static const struct regmap_range_cfg aic31xx_ranges[] = { 121 { 122 .range_min = 0, 123 .range_max = 12 * 128, 124 .selector_reg = AIC31XX_PAGECTL, 125 .selector_mask = 0xff, 126 .selector_shift = 0, 127 .window_start = 0, 128 .window_len = 128, 129 }, 130 }; 131 132 static const struct regmap_config aic31xx_i2c_regmap = { 133 .reg_bits = 8, 134 .val_bits = 8, 135 .writeable_reg = aic31xx_writeable, 136 .volatile_reg = aic31xx_volatile, 137 .reg_defaults = aic31xx_reg_defaults, 138 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults), 139 .cache_type = REGCACHE_RBTREE, 140 .ranges = aic31xx_ranges, 141 .num_ranges = ARRAY_SIZE(aic31xx_ranges), 142 .max_register = 12 * 128, 143 }; 144 145 #define AIC31XX_NUM_SUPPLIES 6 146 static const char * const aic31xx_supply_names[AIC31XX_NUM_SUPPLIES] = { 147 "HPVDD", 148 "SPRVDD", 149 "SPLVDD", 150 "AVDD", 151 "IOVDD", 152 "DVDD", 153 }; 154 155 struct aic31xx_disable_nb { 156 struct notifier_block nb; 157 struct aic31xx_priv *aic31xx; 158 }; 159 160 struct aic31xx_priv { 161 struct snd_soc_codec *codec; 162 u8 i2c_regs_status; 163 struct device *dev; 164 struct regmap *regmap; 165 struct aic31xx_pdata pdata; 166 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES]; 167 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES]; 168 unsigned int sysclk; 169 int rate_div_line; 170 }; 171 172 struct aic31xx_rate_divs { 173 u32 mclk; 174 u32 rate; 175 u8 p_val; 176 u8 pll_j; 177 u16 pll_d; 178 u16 dosr; 179 u8 ndac; 180 u8 mdac; 181 u8 aosr; 182 u8 nadc; 183 u8 madc; 184 }; 185 186 /* ADC dividers can be disabled by cofiguring them to 0 */ 187 static const struct aic31xx_rate_divs aic31xx_divs[] = { 188 /* mclk rate pll: p j d dosr ndac mdac aors nadc madc */ 189 /* 8k rate */ 190 {12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2}, 191 {24000000, 8000, 2, 8, 1920, 128, 48, 2, 128, 48, 2}, 192 {25000000, 8000, 2, 7, 8643, 128, 48, 2, 128, 48, 2}, 193 /* 11.025k rate */ 194 {12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2}, 195 {24000000, 11025, 2, 7, 5264, 128, 32, 2, 128, 32, 2}, 196 {25000000, 11025, 2, 7, 2253, 128, 32, 2, 128, 32, 2}, 197 /* 16k rate */ 198 {12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2}, 199 {24000000, 16000, 2, 8, 1920, 128, 24, 2, 128, 24, 2}, 200 {25000000, 16000, 2, 7, 8643, 128, 24, 2, 128, 24, 2}, 201 /* 22.05k rate */ 202 {12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2}, 203 {24000000, 22050, 2, 7, 5264, 128, 16, 2, 128, 16, 2}, 204 {25000000, 22050, 2, 7, 2253, 128, 16, 2, 128, 16, 2}, 205 /* 32k rate */ 206 {12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2}, 207 {24000000, 32000, 2, 8, 1920, 128, 12, 2, 128, 12, 2}, 208 {25000000, 32000, 2, 7, 8643, 128, 12, 2, 128, 12, 2}, 209 /* 44.1k rate */ 210 {12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2}, 211 {24000000, 44100, 2, 7, 5264, 128, 8, 2, 128, 8, 2}, 212 {25000000, 44100, 2, 7, 2253, 128, 8, 2, 128, 8, 2}, 213 /* 48k rate */ 214 {12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2}, 215 {24000000, 48000, 2, 8, 1920, 128, 8, 2, 128, 8, 2}, 216 {25000000, 48000, 2, 7, 8643, 128, 8, 2, 128, 8, 2}, 217 /* 88.2k rate */ 218 {12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2}, 219 {24000000, 88200, 2, 7, 5264, 64, 8, 2, 64, 8, 2}, 220 {25000000, 88200, 2, 7, 2253, 64, 8, 2, 64, 8, 2}, 221 /* 96k rate */ 222 {12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2}, 223 {24000000, 96000, 2, 8, 1920, 64, 8, 2, 64, 8, 2}, 224 {25000000, 96000, 2, 7, 8643, 64, 8, 2, 64, 8, 2}, 225 /* 176.4k rate */ 226 {12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2}, 227 {24000000, 176400, 2, 7, 5264, 32, 8, 2, 32, 8, 2}, 228 {25000000, 176400, 2, 7, 2253, 32, 8, 2, 32, 8, 2}, 229 /* 192k rate */ 230 {12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2}, 231 {24000000, 192000, 2, 8, 1920, 32, 8, 2, 32, 8, 2}, 232 {25000000, 192000, 2, 7, 8643, 32, 8, 2, 32, 8, 2}, 233 }; 234 235 static const char * const ldac_in_text[] = { 236 "Off", "Left Data", "Right Data", "Mono" 237 }; 238 239 static const char * const rdac_in_text[] = { 240 "Off", "Right Data", "Left Data", "Mono" 241 }; 242 243 static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text); 244 245 static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text); 246 247 static const char * const mic_select_text[] = { 248 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm" 249 }; 250 251 static const 252 SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6, mic_select_text); 253 static const 254 SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4, mic_select_text); 255 static const 256 SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2, mic_select_text); 257 258 static const 259 SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text); 260 static const 261 SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4, mic_select_text); 262 263 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0); 264 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0); 265 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0); 266 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0); 267 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0); 268 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0); 269 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0); 270 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0); 271 272 /* 273 * controls to be exported to the user space 274 */ 275 static const struct snd_kcontrol_new aic31xx_snd_controls[] = { 276 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL, 277 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv), 278 279 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1, 280 adc_fgain_tlv), 281 282 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1), 283 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL, 284 0, -24, 40, 6, 0, adc_cgain_tlv), 285 286 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0, 287 119, 0, mic_pga_tlv), 288 289 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN, 290 AIC31XX_HPRGAIN, 2, 1, 0), 291 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN, 292 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv), 293 294 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL, 295 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv), 296 }; 297 298 static const struct snd_kcontrol_new aic311x_snd_controls[] = { 299 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 300 AIC31XX_SPRGAIN, 2, 1, 0), 301 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 302 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv), 303 304 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 305 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv), 306 }; 307 308 static const struct snd_kcontrol_new aic310x_snd_controls[] = { 309 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 310 2, 1, 0), 311 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 312 3, 3, 0, class_D_drv_tlv), 313 314 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 315 0, 0x7F, 1, sp_vol_tlv), 316 }; 317 318 static const struct snd_kcontrol_new ldac_in_control = 319 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum); 320 321 static const struct snd_kcontrol_new rdac_in_control = 322 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum); 323 324 static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg, 325 unsigned int mask, unsigned int wbits, int sleep, 326 int count) 327 { 328 unsigned int bits; 329 int counter = count; 330 int ret = regmap_read(aic31xx->regmap, reg, &bits); 331 while ((bits & mask) != wbits && counter && !ret) { 332 usleep_range(sleep, sleep * 2); 333 ret = regmap_read(aic31xx->regmap, reg, &bits); 334 counter--; 335 } 336 if ((bits & mask) != wbits) { 337 dev_err(aic31xx->dev, 338 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n", 339 __func__, reg, bits, wbits, ret, mask, 340 (count - counter) * sleep); 341 ret = -1; 342 } 343 return ret; 344 } 345 346 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg)) 347 348 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w, 349 struct snd_kcontrol *kcontrol, int event) 350 { 351 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(w->codec); 352 unsigned int reg = AIC31XX_DACFLAG1; 353 unsigned int mask; 354 355 switch (WIDGET_BIT(w->reg, w->shift)) { 356 case WIDGET_BIT(AIC31XX_DACSETUP, 7): 357 mask = AIC31XX_LDACPWRSTATUS_MASK; 358 break; 359 case WIDGET_BIT(AIC31XX_DACSETUP, 6): 360 mask = AIC31XX_RDACPWRSTATUS_MASK; 361 break; 362 case WIDGET_BIT(AIC31XX_HPDRIVER, 7): 363 mask = AIC31XX_HPLDRVPWRSTATUS_MASK; 364 break; 365 case WIDGET_BIT(AIC31XX_HPDRIVER, 6): 366 mask = AIC31XX_HPRDRVPWRSTATUS_MASK; 367 break; 368 case WIDGET_BIT(AIC31XX_SPKAMP, 7): 369 mask = AIC31XX_SPLDRVPWRSTATUS_MASK; 370 break; 371 case WIDGET_BIT(AIC31XX_SPKAMP, 6): 372 mask = AIC31XX_SPRDRVPWRSTATUS_MASK; 373 break; 374 case WIDGET_BIT(AIC31XX_ADCSETUP, 7): 375 mask = AIC31XX_ADCPWRSTATUS_MASK; 376 reg = AIC31XX_ADCFLAG; 377 break; 378 default: 379 dev_err(w->codec->dev, "Unknown widget '%s' calling %s/n", 380 w->name, __func__); 381 return -EINVAL; 382 } 383 384 switch (event) { 385 case SND_SOC_DAPM_POST_PMU: 386 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100); 387 case SND_SOC_DAPM_POST_PMD: 388 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100); 389 default: 390 dev_dbg(w->codec->dev, 391 "Unhandled dapm widget event %d from %s\n", 392 event, w->name); 393 } 394 return 0; 395 } 396 397 static const struct snd_kcontrol_new left_output_switches[] = { 398 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 399 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0), 400 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0), 401 }; 402 403 static const struct snd_kcontrol_new right_output_switches[] = { 404 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 405 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0), 406 }; 407 408 static const struct snd_kcontrol_new p_term_mic1lp = 409 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum); 410 411 static const struct snd_kcontrol_new p_term_mic1rp = 412 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum); 413 414 static const struct snd_kcontrol_new p_term_mic1lm = 415 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum); 416 417 static const struct snd_kcontrol_new m_term_mic1lm = 418 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum); 419 420 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch = 421 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0); 422 423 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch = 424 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0); 425 426 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch = 427 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0); 428 429 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch = 430 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0); 431 432 static int mic_bias_event(struct snd_soc_dapm_widget *w, 433 struct snd_kcontrol *kcontrol, int event) 434 { 435 struct snd_soc_codec *codec = w->codec; 436 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 437 switch (event) { 438 case SND_SOC_DAPM_POST_PMU: 439 /* change mic bias voltage to user defined */ 440 snd_soc_update_bits(codec, AIC31XX_MICBIAS, 441 AIC31XX_MICBIAS_MASK, 442 aic31xx->pdata.micbias_vg << 443 AIC31XX_MICBIAS_SHIFT); 444 dev_dbg(codec->dev, "%s: turned on\n", __func__); 445 break; 446 case SND_SOC_DAPM_PRE_PMD: 447 /* turn mic bias off */ 448 snd_soc_update_bits(codec, AIC31XX_MICBIAS, 449 AIC31XX_MICBIAS_MASK, 0); 450 dev_dbg(codec->dev, "%s: turned off\n", __func__); 451 break; 452 } 453 return 0; 454 } 455 456 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = { 457 SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0), 458 459 SND_SOC_DAPM_MUX("DAC Left Input", 460 SND_SOC_NOPM, 0, 0, &ldac_in_control), 461 SND_SOC_DAPM_MUX("DAC Right Input", 462 SND_SOC_NOPM, 0, 0, &rdac_in_control), 463 /* DACs */ 464 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback", 465 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event, 466 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 467 468 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback", 469 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event, 470 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 471 472 /* Output Mixers */ 473 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 474 left_output_switches, 475 ARRAY_SIZE(left_output_switches)), 476 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 477 right_output_switches, 478 ARRAY_SIZE(right_output_switches)), 479 480 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0, 481 &aic31xx_dapm_hpl_switch), 482 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0, 483 &aic31xx_dapm_hpr_switch), 484 485 /* Output drivers */ 486 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0, 487 NULL, 0, aic31xx_dapm_power_event, 488 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 489 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0, 490 NULL, 0, aic31xx_dapm_power_event, 491 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 492 493 /* ADC */ 494 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0, 495 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 496 SND_SOC_DAPM_POST_PMD), 497 498 /* Input Selection to MIC_PGA */ 499 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0, 500 &p_term_mic1lp), 501 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0, 502 &p_term_mic1rp), 503 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0, 504 &p_term_mic1lm), 505 506 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0, 507 &m_term_mic1lm), 508 /* Enabling & Disabling MIC Gain Ctl */ 509 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA, 510 7, 1, NULL, 0), 511 512 /* Mic Bias */ 513 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event, 514 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 515 516 /* Outputs */ 517 SND_SOC_DAPM_OUTPUT("HPL"), 518 SND_SOC_DAPM_OUTPUT("HPR"), 519 520 /* Inputs */ 521 SND_SOC_DAPM_INPUT("MIC1LP"), 522 SND_SOC_DAPM_INPUT("MIC1RP"), 523 SND_SOC_DAPM_INPUT("MIC1LM"), 524 }; 525 526 static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = { 527 /* AIC3111 and AIC3110 have stereo class-D amplifier */ 528 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 529 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 530 SND_SOC_DAPM_POST_PMD), 531 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0, 532 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 533 SND_SOC_DAPM_POST_PMD), 534 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0, 535 &aic31xx_dapm_spl_switch), 536 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0, 537 &aic31xx_dapm_spr_switch), 538 SND_SOC_DAPM_OUTPUT("SPL"), 539 SND_SOC_DAPM_OUTPUT("SPR"), 540 }; 541 542 /* AIC3100 and AIC3120 have only mono class-D amplifier */ 543 static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = { 544 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 545 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 546 SND_SOC_DAPM_POST_PMD), 547 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0, 548 &aic31xx_dapm_spl_switch), 549 SND_SOC_DAPM_OUTPUT("SPK"), 550 }; 551 552 static const struct snd_soc_dapm_route 553 aic31xx_audio_map[] = { 554 /* DAC Input Routing */ 555 {"DAC Left Input", "Left Data", "DAC IN"}, 556 {"DAC Left Input", "Right Data", "DAC IN"}, 557 {"DAC Left Input", "Mono", "DAC IN"}, 558 {"DAC Right Input", "Left Data", "DAC IN"}, 559 {"DAC Right Input", "Right Data", "DAC IN"}, 560 {"DAC Right Input", "Mono", "DAC IN"}, 561 {"DAC Left", NULL, "DAC Left Input"}, 562 {"DAC Right", NULL, "DAC Right Input"}, 563 564 /* Mic input */ 565 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"}, 566 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"}, 567 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"}, 568 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"}, 569 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"}, 570 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"}, 571 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"}, 572 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"}, 573 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"}, 574 575 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"}, 576 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"}, 577 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"}, 578 579 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"}, 580 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"}, 581 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"}, 582 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"}, 583 584 {"ADC", NULL, "MIC_GAIN_CTL"}, 585 586 /* Left Output */ 587 {"Output Left", "From Left DAC", "DAC Left"}, 588 {"Output Left", "From MIC1LP", "MIC1LP"}, 589 {"Output Left", "From MIC1RP", "MIC1RP"}, 590 591 /* Right Output */ 592 {"Output Right", "From Right DAC", "DAC Right"}, 593 {"Output Right", "From MIC1RP", "MIC1RP"}, 594 595 /* HPL path */ 596 {"HP Left", "Switch", "Output Left"}, 597 {"HPL Driver", NULL, "HP Left"}, 598 {"HPL", NULL, "HPL Driver"}, 599 600 /* HPR path */ 601 {"HP Right", "Switch", "Output Right"}, 602 {"HPR Driver", NULL, "HP Right"}, 603 {"HPR", NULL, "HPR Driver"}, 604 }; 605 606 static const struct snd_soc_dapm_route 607 aic311x_audio_map[] = { 608 /* SP L path */ 609 {"Speaker Left", "Switch", "Output Left"}, 610 {"SPL ClassD", NULL, "Speaker Left"}, 611 {"SPL", NULL, "SPL ClassD"}, 612 613 /* SP R path */ 614 {"Speaker Right", "Switch", "Output Right"}, 615 {"SPR ClassD", NULL, "Speaker Right"}, 616 {"SPR", NULL, "SPR ClassD"}, 617 }; 618 619 static const struct snd_soc_dapm_route 620 aic310x_audio_map[] = { 621 /* SP L path */ 622 {"Speaker", "Switch", "Output Left"}, 623 {"SPK ClassD", NULL, "Speaker"}, 624 {"SPK", NULL, "SPK ClassD"}, 625 }; 626 627 static int aic31xx_add_controls(struct snd_soc_codec *codec) 628 { 629 int ret = 0; 630 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 631 632 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) 633 ret = snd_soc_add_codec_controls( 634 codec, aic311x_snd_controls, 635 ARRAY_SIZE(aic311x_snd_controls)); 636 else 637 ret = snd_soc_add_codec_controls( 638 codec, aic310x_snd_controls, 639 ARRAY_SIZE(aic310x_snd_controls)); 640 641 return ret; 642 } 643 644 static int aic31xx_add_widgets(struct snd_soc_codec *codec) 645 { 646 struct snd_soc_dapm_context *dapm = &codec->dapm; 647 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 648 int ret = 0; 649 650 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) { 651 ret = snd_soc_dapm_new_controls( 652 dapm, aic311x_dapm_widgets, 653 ARRAY_SIZE(aic311x_dapm_widgets)); 654 if (ret) 655 return ret; 656 657 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map, 658 ARRAY_SIZE(aic311x_audio_map)); 659 if (ret) 660 return ret; 661 } else { 662 ret = snd_soc_dapm_new_controls( 663 dapm, aic310x_dapm_widgets, 664 ARRAY_SIZE(aic310x_dapm_widgets)); 665 if (ret) 666 return ret; 667 668 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map, 669 ARRAY_SIZE(aic310x_audio_map)); 670 if (ret) 671 return ret; 672 } 673 674 return 0; 675 } 676 677 static int aic31xx_setup_pll(struct snd_soc_codec *codec, 678 struct snd_pcm_hw_params *params) 679 { 680 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 681 int bclk_n = 0; 682 int i; 683 684 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */ 685 snd_soc_update_bits(codec, AIC31XX_CLKMUX, 686 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL); 687 snd_soc_update_bits(codec, AIC31XX_IFACE2, 688 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK); 689 690 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { 691 if (aic31xx_divs[i].rate == params_rate(params) && 692 aic31xx_divs[i].mclk == aic31xx->sysclk) 693 break; 694 } 695 696 if (i == ARRAY_SIZE(aic31xx_divs)) { 697 dev_err(codec->dev, "%s: Sampling rate %u not supported\n", 698 __func__, params_rate(params)); 699 return -EINVAL; 700 } 701 702 /* PLL configuration */ 703 snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK, 704 (aic31xx_divs[i].p_val << 4) | 0x01); 705 snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j); 706 707 snd_soc_write(codec, AIC31XX_PLLDMSB, 708 aic31xx_divs[i].pll_d >> 8); 709 snd_soc_write(codec, AIC31XX_PLLDLSB, 710 aic31xx_divs[i].pll_d & 0xff); 711 712 /* DAC dividers configuration */ 713 snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK, 714 aic31xx_divs[i].ndac); 715 snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK, 716 aic31xx_divs[i].mdac); 717 718 snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8); 719 snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff); 720 721 /* ADC dividers configuration. Write reset value 1 if not used. */ 722 snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK, 723 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1); 724 snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK, 725 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1); 726 727 snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr); 728 729 /* Bit clock divider configuration. */ 730 bclk_n = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) 731 / snd_soc_params_to_frame_size(params); 732 if (bclk_n == 0) { 733 dev_err(codec->dev, "%s: Not enough BLCK bandwidth\n", 734 __func__); 735 return -EINVAL; 736 } 737 738 snd_soc_update_bits(codec, AIC31XX_BCLKN, 739 AIC31XX_PLL_MASK, bclk_n); 740 741 aic31xx->rate_div_line = i; 742 743 dev_dbg(codec->dev, 744 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n", 745 aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d, 746 aic31xx_divs[i].p_val, aic31xx_divs[i].dosr, 747 aic31xx_divs[i].ndac, aic31xx_divs[i].mdac, 748 aic31xx_divs[i].aosr, aic31xx_divs[i].nadc, 749 aic31xx_divs[i].madc, bclk_n); 750 751 return 0; 752 } 753 754 static int aic31xx_hw_params(struct snd_pcm_substream *substream, 755 struct snd_pcm_hw_params *params, 756 struct snd_soc_dai *dai) 757 { 758 struct snd_soc_codec *codec = dai->codec; 759 u8 data = 0; 760 761 dev_dbg(codec->dev, "## %s: format %d width %d rate %d\n", 762 __func__, params_format(params), params_width(params), 763 params_rate(params)); 764 765 switch (params_width(params)) { 766 case 16: 767 break; 768 case 20: 769 data = (AIC31XX_WORD_LEN_20BITS << 770 AIC31XX_IFACE1_DATALEN_SHIFT); 771 break; 772 case 24: 773 data = (AIC31XX_WORD_LEN_24BITS << 774 AIC31XX_IFACE1_DATALEN_SHIFT); 775 break; 776 case 32: 777 data = (AIC31XX_WORD_LEN_32BITS << 778 AIC31XX_IFACE1_DATALEN_SHIFT); 779 break; 780 default: 781 dev_err(codec->dev, "%s: Unsupported format %d\n", 782 __func__, params_format(params)); 783 return -EINVAL; 784 } 785 786 snd_soc_update_bits(codec, AIC31XX_IFACE1, 787 AIC31XX_IFACE1_DATALEN_MASK, 788 data); 789 790 return aic31xx_setup_pll(codec, params); 791 } 792 793 static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute) 794 { 795 struct snd_soc_codec *codec = codec_dai->codec; 796 797 if (mute) { 798 snd_soc_update_bits(codec, AIC31XX_DACMUTE, 799 AIC31XX_DACMUTE_MASK, 800 AIC31XX_DACMUTE_MASK); 801 } else { 802 snd_soc_update_bits(codec, AIC31XX_DACMUTE, 803 AIC31XX_DACMUTE_MASK, 0x0); 804 } 805 806 return 0; 807 } 808 809 static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 810 unsigned int fmt) 811 { 812 struct snd_soc_codec *codec = codec_dai->codec; 813 u8 iface_reg1 = 0; 814 u8 iface_reg3 = 0; 815 u8 dsp_a_val = 0; 816 817 dev_dbg(codec->dev, "## %s: fmt = 0x%x\n", __func__, fmt); 818 819 /* set master/slave audio interface */ 820 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 821 case SND_SOC_DAIFMT_CBM_CFM: 822 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER; 823 break; 824 default: 825 dev_alert(codec->dev, "Invalid DAI master/slave interface\n"); 826 return -EINVAL; 827 } 828 829 /* interface format */ 830 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 831 case SND_SOC_DAIFMT_I2S: 832 break; 833 case SND_SOC_DAIFMT_DSP_A: 834 dsp_a_val = 0x1; 835 case SND_SOC_DAIFMT_DSP_B: 836 /* NOTE: BCLKINV bit value 1 equas NB and 0 equals IB */ 837 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 838 case SND_SOC_DAIFMT_NB_NF: 839 iface_reg3 |= AIC31XX_BCLKINV_MASK; 840 break; 841 case SND_SOC_DAIFMT_IB_NF: 842 break; 843 default: 844 return -EINVAL; 845 } 846 iface_reg1 |= (AIC31XX_DSP_MODE << 847 AIC31XX_IFACE1_DATATYPE_SHIFT); 848 break; 849 case SND_SOC_DAIFMT_RIGHT_J: 850 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE << 851 AIC31XX_IFACE1_DATATYPE_SHIFT); 852 break; 853 case SND_SOC_DAIFMT_LEFT_J: 854 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE << 855 AIC31XX_IFACE1_DATATYPE_SHIFT); 856 break; 857 default: 858 dev_err(codec->dev, "Invalid DAI interface format\n"); 859 return -EINVAL; 860 } 861 862 snd_soc_update_bits(codec, AIC31XX_IFACE1, 863 AIC31XX_IFACE1_DATATYPE_MASK | 864 AIC31XX_IFACE1_MASTER_MASK, 865 iface_reg1); 866 snd_soc_update_bits(codec, AIC31XX_DATA_OFFSET, 867 AIC31XX_DATA_OFFSET_MASK, 868 dsp_a_val); 869 snd_soc_update_bits(codec, AIC31XX_IFACE2, 870 AIC31XX_BCLKINV_MASK, 871 iface_reg3); 872 873 return 0; 874 } 875 876 static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 877 int clk_id, unsigned int freq, int dir) 878 { 879 struct snd_soc_codec *codec = codec_dai->codec; 880 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 881 int i; 882 883 dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n", 884 __func__, clk_id, freq, dir); 885 886 for (i = 0; aic31xx_divs[i].mclk != freq; i++) { 887 if (i == ARRAY_SIZE(aic31xx_divs)) { 888 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n", 889 __func__, freq); 890 return -EINVAL; 891 } 892 } 893 894 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */ 895 snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK, 896 clk_id << AIC31XX_PLL_CLKIN_SHIFT); 897 898 aic31xx->sysclk = freq; 899 return 0; 900 } 901 902 static int aic31xx_regulator_event(struct notifier_block *nb, 903 unsigned long event, void *data) 904 { 905 struct aic31xx_disable_nb *disable_nb = 906 container_of(nb, struct aic31xx_disable_nb, nb); 907 struct aic31xx_priv *aic31xx = disable_nb->aic31xx; 908 909 if (event & REGULATOR_EVENT_DISABLE) { 910 /* 911 * Put codec to reset and as at least one of the 912 * supplies was disabled. 913 */ 914 if (gpio_is_valid(aic31xx->pdata.gpio_reset)) 915 gpio_set_value(aic31xx->pdata.gpio_reset, 0); 916 917 regcache_mark_dirty(aic31xx->regmap); 918 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__); 919 } 920 921 return 0; 922 } 923 924 static void aic31xx_clk_on(struct snd_soc_codec *codec) 925 { 926 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 927 u8 mask = AIC31XX_PM_MASK; 928 u8 on = AIC31XX_PM_MASK; 929 930 dev_dbg(codec->dev, "codec clock -> on (rate %d)\n", 931 aic31xx_divs[aic31xx->rate_div_line].rate); 932 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, on); 933 mdelay(10); 934 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, on); 935 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, on); 936 if (aic31xx_divs[aic31xx->rate_div_line].nadc) 937 snd_soc_update_bits(codec, AIC31XX_NADC, mask, on); 938 if (aic31xx_divs[aic31xx->rate_div_line].madc) 939 snd_soc_update_bits(codec, AIC31XX_MADC, mask, on); 940 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, on); 941 } 942 943 static void aic31xx_clk_off(struct snd_soc_codec *codec) 944 { 945 u8 mask = AIC31XX_PM_MASK; 946 u8 off = 0; 947 948 dev_dbg(codec->dev, "codec clock -> off\n"); 949 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, off); 950 snd_soc_update_bits(codec, AIC31XX_MADC, mask, off); 951 snd_soc_update_bits(codec, AIC31XX_NADC, mask, off); 952 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, off); 953 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, off); 954 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, off); 955 } 956 957 static int aic31xx_power_on(struct snd_soc_codec *codec) 958 { 959 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 960 int ret = 0; 961 962 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies), 963 aic31xx->supplies); 964 if (ret) 965 return ret; 966 967 if (gpio_is_valid(aic31xx->pdata.gpio_reset)) { 968 gpio_set_value(aic31xx->pdata.gpio_reset, 1); 969 udelay(100); 970 } 971 regcache_cache_only(aic31xx->regmap, false); 972 ret = regcache_sync(aic31xx->regmap); 973 if (ret != 0) { 974 dev_err(codec->dev, 975 "Failed to restore cache: %d\n", ret); 976 regcache_cache_only(aic31xx->regmap, true); 977 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 978 aic31xx->supplies); 979 return ret; 980 } 981 return 0; 982 } 983 984 static int aic31xx_power_off(struct snd_soc_codec *codec) 985 { 986 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 987 int ret = 0; 988 989 regcache_cache_only(aic31xx->regmap, true); 990 ret = regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 991 aic31xx->supplies); 992 993 return ret; 994 } 995 996 static int aic31xx_set_bias_level(struct snd_soc_codec *codec, 997 enum snd_soc_bias_level level) 998 { 999 dev_dbg(codec->dev, "## %s: %d -> %d\n", __func__, 1000 codec->dapm.bias_level, level); 1001 1002 switch (level) { 1003 case SND_SOC_BIAS_ON: 1004 break; 1005 case SND_SOC_BIAS_PREPARE: 1006 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) 1007 aic31xx_clk_on(codec); 1008 break; 1009 case SND_SOC_BIAS_STANDBY: 1010 switch (codec->dapm.bias_level) { 1011 case SND_SOC_BIAS_OFF: 1012 aic31xx_power_on(codec); 1013 break; 1014 case SND_SOC_BIAS_PREPARE: 1015 aic31xx_clk_off(codec); 1016 break; 1017 default: 1018 BUG(); 1019 } 1020 break; 1021 case SND_SOC_BIAS_OFF: 1022 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) 1023 aic31xx_power_off(codec); 1024 break; 1025 } 1026 codec->dapm.bias_level = level; 1027 1028 return 0; 1029 } 1030 1031 static int aic31xx_suspend(struct snd_soc_codec *codec) 1032 { 1033 aic31xx_set_bias_level(codec, SND_SOC_BIAS_OFF); 1034 return 0; 1035 } 1036 1037 static int aic31xx_resume(struct snd_soc_codec *codec) 1038 { 1039 aic31xx_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1040 return 0; 1041 } 1042 1043 static int aic31xx_codec_probe(struct snd_soc_codec *codec) 1044 { 1045 int ret = 0; 1046 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 1047 int i; 1048 1049 dev_dbg(aic31xx->dev, "## %s\n", __func__); 1050 1051 aic31xx = snd_soc_codec_get_drvdata(codec); 1052 1053 aic31xx->codec = codec; 1054 1055 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) { 1056 aic31xx->disable_nb[i].nb.notifier_call = 1057 aic31xx_regulator_event; 1058 aic31xx->disable_nb[i].aic31xx = aic31xx; 1059 ret = regulator_register_notifier(aic31xx->supplies[i].consumer, 1060 &aic31xx->disable_nb[i].nb); 1061 if (ret) { 1062 dev_err(codec->dev, 1063 "Failed to request regulator notifier: %d\n", 1064 ret); 1065 return ret; 1066 } 1067 } 1068 1069 regcache_cache_only(aic31xx->regmap, true); 1070 regcache_mark_dirty(aic31xx->regmap); 1071 1072 ret = aic31xx_add_controls(codec); 1073 if (ret) 1074 return ret; 1075 1076 ret = aic31xx_add_widgets(codec); 1077 1078 return ret; 1079 } 1080 1081 static int aic31xx_codec_remove(struct snd_soc_codec *codec) 1082 { 1083 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 1084 int i; 1085 /* power down chip */ 1086 aic31xx_set_bias_level(codec, SND_SOC_BIAS_OFF); 1087 1088 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) 1089 regulator_unregister_notifier(aic31xx->supplies[i].consumer, 1090 &aic31xx->disable_nb[i].nb); 1091 1092 return 0; 1093 } 1094 1095 static struct snd_soc_codec_driver soc_codec_driver_aic31xx = { 1096 .probe = aic31xx_codec_probe, 1097 .remove = aic31xx_codec_remove, 1098 .suspend = aic31xx_suspend, 1099 .resume = aic31xx_resume, 1100 .set_bias_level = aic31xx_set_bias_level, 1101 .controls = aic31xx_snd_controls, 1102 .num_controls = ARRAY_SIZE(aic31xx_snd_controls), 1103 .dapm_widgets = aic31xx_dapm_widgets, 1104 .num_dapm_widgets = ARRAY_SIZE(aic31xx_dapm_widgets), 1105 .dapm_routes = aic31xx_audio_map, 1106 .num_dapm_routes = ARRAY_SIZE(aic31xx_audio_map), 1107 }; 1108 1109 static struct snd_soc_dai_ops aic31xx_dai_ops = { 1110 .hw_params = aic31xx_hw_params, 1111 .set_sysclk = aic31xx_set_dai_sysclk, 1112 .set_fmt = aic31xx_set_dai_fmt, 1113 .digital_mute = aic31xx_dac_mute, 1114 }; 1115 1116 static struct snd_soc_dai_driver aic31xx_dai_driver[] = { 1117 { 1118 .name = "tlv320aic31xx-hifi", 1119 .playback = { 1120 .stream_name = "Playback", 1121 .channels_min = 1, 1122 .channels_max = 2, 1123 .rates = AIC31XX_RATES, 1124 .formats = AIC31XX_FORMATS, 1125 }, 1126 .capture = { 1127 .stream_name = "Capture", 1128 .channels_min = 1, 1129 .channels_max = 2, 1130 .rates = AIC31XX_RATES, 1131 .formats = AIC31XX_FORMATS, 1132 }, 1133 .ops = &aic31xx_dai_ops, 1134 .symmetric_rates = 1, 1135 } 1136 }; 1137 1138 #if defined(CONFIG_OF) 1139 static const struct of_device_id tlv320aic31xx_of_match[] = { 1140 { .compatible = "ti,tlv320aic310x" }, 1141 { .compatible = "ti,tlv320aic311x" }, 1142 { .compatible = "ti,tlv320aic3100" }, 1143 { .compatible = "ti,tlv320aic3110" }, 1144 { .compatible = "ti,tlv320aic3120" }, 1145 { .compatible = "ti,tlv320aic3111" }, 1146 {}, 1147 }; 1148 MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match); 1149 1150 static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx) 1151 { 1152 struct device_node *np = aic31xx->dev->of_node; 1153 unsigned int value = MICBIAS_2_0V; 1154 int ret; 1155 1156 of_property_read_u32(np, "ai31xx-micbias-vg", &value); 1157 switch (value) { 1158 case MICBIAS_2_0V: 1159 case MICBIAS_2_5V: 1160 case MICBIAS_AVDDV: 1161 aic31xx->pdata.micbias_vg = value; 1162 break; 1163 default: 1164 dev_err(aic31xx->dev, 1165 "Bad ai31xx-micbias-vg value %d DT\n", 1166 value); 1167 aic31xx->pdata.micbias_vg = MICBIAS_2_0V; 1168 } 1169 1170 ret = of_get_named_gpio(np, "gpio-reset", 0); 1171 if (ret > 0) 1172 aic31xx->pdata.gpio_reset = ret; 1173 } 1174 #else /* CONFIG_OF */ 1175 static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx) 1176 { 1177 } 1178 #endif /* CONFIG_OF */ 1179 1180 static void aic31xx_device_init(struct aic31xx_priv *aic31xx) 1181 { 1182 int ret, i; 1183 1184 dev_set_drvdata(aic31xx->dev, aic31xx); 1185 1186 if (dev_get_platdata(aic31xx->dev)) 1187 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), 1188 sizeof(aic31xx->pdata)); 1189 else if (aic31xx->dev->of_node) 1190 aic31xx_pdata_from_of(aic31xx); 1191 1192 if (aic31xx->pdata.gpio_reset) { 1193 ret = devm_gpio_request_one(aic31xx->dev, 1194 aic31xx->pdata.gpio_reset, 1195 GPIOF_OUT_INIT_HIGH, 1196 "aic31xx-reset-pin"); 1197 if (ret < 0) { 1198 dev_err(aic31xx->dev, "not able to acquire gpio\n"); 1199 return; 1200 } 1201 } 1202 1203 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) 1204 aic31xx->supplies[i].supply = aic31xx_supply_names[i]; 1205 1206 ret = devm_regulator_bulk_get(aic31xx->dev, 1207 ARRAY_SIZE(aic31xx->supplies), 1208 aic31xx->supplies); 1209 if (ret != 0) 1210 dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret); 1211 1212 } 1213 1214 static int aic31xx_i2c_probe(struct i2c_client *i2c, 1215 const struct i2c_device_id *id) 1216 { 1217 struct aic31xx_priv *aic31xx; 1218 int ret; 1219 const struct regmap_config *regmap_config; 1220 1221 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__, 1222 id->name, (int) id->driver_data); 1223 1224 regmap_config = &aic31xx_i2c_regmap; 1225 1226 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL); 1227 if (aic31xx == NULL) 1228 return -ENOMEM; 1229 1230 aic31xx->regmap = devm_regmap_init_i2c(i2c, regmap_config); 1231 if (IS_ERR(aic31xx->regmap)) { 1232 ret = PTR_ERR(aic31xx->regmap); 1233 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1234 ret); 1235 return ret; 1236 } 1237 aic31xx->dev = &i2c->dev; 1238 1239 aic31xx->pdata.codec_type = id->driver_data; 1240 1241 aic31xx_device_init(aic31xx); 1242 1243 return snd_soc_register_codec(&i2c->dev, &soc_codec_driver_aic31xx, 1244 aic31xx_dai_driver, 1245 ARRAY_SIZE(aic31xx_dai_driver)); 1246 } 1247 1248 static int aic31xx_i2c_remove(struct i2c_client *i2c) 1249 { 1250 snd_soc_unregister_codec(&i2c->dev); 1251 return 0; 1252 } 1253 1254 static const struct i2c_device_id aic31xx_i2c_id[] = { 1255 { "tlv320aic310x", AIC3100 }, 1256 { "tlv320aic311x", AIC3110 }, 1257 { "tlv320aic3100", AIC3100 }, 1258 { "tlv320aic3110", AIC3110 }, 1259 { "tlv320aic3120", AIC3120 }, 1260 { "tlv320aic3111", AIC3111 }, 1261 { } 1262 }; 1263 MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id); 1264 1265 static struct i2c_driver aic31xx_i2c_driver = { 1266 .driver = { 1267 .name = "tlv320aic31xx-codec", 1268 .owner = THIS_MODULE, 1269 .of_match_table = of_match_ptr(tlv320aic31xx_of_match), 1270 }, 1271 .probe = aic31xx_i2c_probe, 1272 .remove = aic31xx_i2c_remove, 1273 .id_table = aic31xx_i2c_id, 1274 }; 1275 1276 module_i2c_driver(aic31xx_i2c_driver); 1277 1278 MODULE_DESCRIPTION("ASoC TLV320AIC3111 codec driver"); 1279 MODULE_AUTHOR("Jyri Sarha"); 1280 MODULE_LICENSE("GPL"); 1281