1 /* 2 * ALSA SoC TLV320AIC31XX codec driver 3 * 4 * Copyright (C) 2014 Texas Instruments, Inc. 5 * 6 * Author: Jyri Sarha <jsarha@ti.com> 7 * 8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com> 9 * 10 * This package is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 * 14 * THIS PACKAGE IS PROVIDED AS IS AND WITHOUT ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 17 * 18 * The TLV320AIC31xx series of audio codec is a low-power, highly integrated 19 * high performance codec which provides a stereo DAC, a mono ADC, 20 * and mono/stereo Class-D speaker driver. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/moduleparam.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/pm.h> 28 #include <linux/i2c.h> 29 #include <linux/gpio.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/of.h> 32 #include <linux/of_gpio.h> 33 #include <linux/slab.h> 34 #include <sound/core.h> 35 #include <sound/pcm.h> 36 #include <sound/pcm_params.h> 37 #include <sound/soc.h> 38 #include <sound/initval.h> 39 #include <sound/tlv.h> 40 #include <dt-bindings/sound/tlv320aic31xx-micbias.h> 41 42 #include "tlv320aic31xx.h" 43 44 static const struct reg_default aic31xx_reg_defaults[] = { 45 { AIC31XX_CLKMUX, 0x00 }, 46 { AIC31XX_PLLPR, 0x11 }, 47 { AIC31XX_PLLJ, 0x04 }, 48 { AIC31XX_PLLDMSB, 0x00 }, 49 { AIC31XX_PLLDLSB, 0x00 }, 50 { AIC31XX_NDAC, 0x01 }, 51 { AIC31XX_MDAC, 0x01 }, 52 { AIC31XX_DOSRMSB, 0x00 }, 53 { AIC31XX_DOSRLSB, 0x80 }, 54 { AIC31XX_NADC, 0x01 }, 55 { AIC31XX_MADC, 0x01 }, 56 { AIC31XX_AOSR, 0x80 }, 57 { AIC31XX_IFACE1, 0x00 }, 58 { AIC31XX_DATA_OFFSET, 0x00 }, 59 { AIC31XX_IFACE2, 0x00 }, 60 { AIC31XX_BCLKN, 0x01 }, 61 { AIC31XX_DACSETUP, 0x14 }, 62 { AIC31XX_DACMUTE, 0x0c }, 63 { AIC31XX_LDACVOL, 0x00 }, 64 { AIC31XX_RDACVOL, 0x00 }, 65 { AIC31XX_ADCSETUP, 0x00 }, 66 { AIC31XX_ADCFGA, 0x80 }, 67 { AIC31XX_ADCVOL, 0x00 }, 68 { AIC31XX_HPDRIVER, 0x04 }, 69 { AIC31XX_SPKAMP, 0x06 }, 70 { AIC31XX_DACMIXERROUTE, 0x00 }, 71 { AIC31XX_LANALOGHPL, 0x7f }, 72 { AIC31XX_RANALOGHPR, 0x7f }, 73 { AIC31XX_LANALOGSPL, 0x7f }, 74 { AIC31XX_RANALOGSPR, 0x7f }, 75 { AIC31XX_HPLGAIN, 0x02 }, 76 { AIC31XX_HPRGAIN, 0x02 }, 77 { AIC31XX_SPLGAIN, 0x00 }, 78 { AIC31XX_SPRGAIN, 0x00 }, 79 { AIC31XX_MICBIAS, 0x00 }, 80 { AIC31XX_MICPGA, 0x80 }, 81 { AIC31XX_MICPGAPI, 0x00 }, 82 { AIC31XX_MICPGAMI, 0x00 }, 83 }; 84 85 static bool aic31xx_volatile(struct device *dev, unsigned int reg) 86 { 87 switch (reg) { 88 case AIC31XX_PAGECTL: /* regmap implementation requires this */ 89 case AIC31XX_RESET: /* always clears after write */ 90 case AIC31XX_OT_FLAG: 91 case AIC31XX_ADCFLAG: 92 case AIC31XX_DACFLAG1: 93 case AIC31XX_DACFLAG2: 94 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 95 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 96 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 97 case AIC31XX_INTRDACFLAG2: 98 case AIC31XX_INTRADCFLAG2: 99 return true; 100 } 101 return false; 102 } 103 104 static bool aic31xx_writeable(struct device *dev, unsigned int reg) 105 { 106 switch (reg) { 107 case AIC31XX_OT_FLAG: 108 case AIC31XX_ADCFLAG: 109 case AIC31XX_DACFLAG1: 110 case AIC31XX_DACFLAG2: 111 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 112 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 113 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 114 case AIC31XX_INTRDACFLAG2: 115 case AIC31XX_INTRADCFLAG2: 116 return false; 117 } 118 return true; 119 } 120 121 static const struct regmap_range_cfg aic31xx_ranges[] = { 122 { 123 .range_min = 0, 124 .range_max = 12 * 128, 125 .selector_reg = AIC31XX_PAGECTL, 126 .selector_mask = 0xff, 127 .selector_shift = 0, 128 .window_start = 0, 129 .window_len = 128, 130 }, 131 }; 132 133 static const struct regmap_config aic31xx_i2c_regmap = { 134 .reg_bits = 8, 135 .val_bits = 8, 136 .writeable_reg = aic31xx_writeable, 137 .volatile_reg = aic31xx_volatile, 138 .reg_defaults = aic31xx_reg_defaults, 139 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults), 140 .cache_type = REGCACHE_RBTREE, 141 .ranges = aic31xx_ranges, 142 .num_ranges = ARRAY_SIZE(aic31xx_ranges), 143 .max_register = 12 * 128, 144 }; 145 146 #define AIC31XX_NUM_SUPPLIES 6 147 static const char * const aic31xx_supply_names[AIC31XX_NUM_SUPPLIES] = { 148 "HPVDD", 149 "SPRVDD", 150 "SPLVDD", 151 "AVDD", 152 "IOVDD", 153 "DVDD", 154 }; 155 156 struct aic31xx_disable_nb { 157 struct notifier_block nb; 158 struct aic31xx_priv *aic31xx; 159 }; 160 161 struct aic31xx_priv { 162 struct snd_soc_codec *codec; 163 u8 i2c_regs_status; 164 struct device *dev; 165 struct regmap *regmap; 166 struct aic31xx_pdata pdata; 167 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES]; 168 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES]; 169 unsigned int sysclk; 170 u8 p_div; 171 int rate_div_line; 172 }; 173 174 struct aic31xx_rate_divs { 175 u32 mclk_p; 176 u32 rate; 177 u8 pll_j; 178 u16 pll_d; 179 u16 dosr; 180 u8 ndac; 181 u8 mdac; 182 u8 aosr; 183 u8 nadc; 184 u8 madc; 185 }; 186 187 /* ADC dividers can be disabled by cofiguring them to 0 */ 188 static const struct aic31xx_rate_divs aic31xx_divs[] = { 189 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */ 190 /* 8k rate */ 191 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2}, 192 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3}, 193 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2}, 194 /* 11.025k rate */ 195 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2}, 196 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3}, 197 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2}, 198 /* 16k rate */ 199 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2}, 200 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3}, 201 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2}, 202 /* 22.05k rate */ 203 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2}, 204 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3}, 205 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2}, 206 /* 32k rate */ 207 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2}, 208 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3}, 209 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2}, 210 /* 44.1k rate */ 211 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2}, 212 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3}, 213 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2}, 214 /* 48k rate */ 215 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2}, 216 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4}, 217 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2}, 218 /* 88.2k rate */ 219 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2}, 220 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3}, 221 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2}, 222 /* 96k rate */ 223 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2}, 224 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4}, 225 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2}, 226 /* 176.4k rate */ 227 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2}, 228 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3}, 229 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2}, 230 /* 192k rate */ 231 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2}, 232 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4}, 233 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2}, 234 }; 235 236 static const char * const ldac_in_text[] = { 237 "Off", "Left Data", "Right Data", "Mono" 238 }; 239 240 static const char * const rdac_in_text[] = { 241 "Off", "Right Data", "Left Data", "Mono" 242 }; 243 244 static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text); 245 246 static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text); 247 248 static const char * const mic_select_text[] = { 249 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm" 250 }; 251 252 static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6, 253 mic_select_text); 254 static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4, 255 mic_select_text); 256 static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2, 257 mic_select_text); 258 259 static SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text); 260 static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4, 261 mic_select_text); 262 263 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0); 264 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0); 265 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0); 266 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0); 267 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0); 268 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0); 269 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0); 270 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0); 271 272 /* 273 * controls to be exported to the user space 274 */ 275 static const struct snd_kcontrol_new aic31xx_snd_controls[] = { 276 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL, 277 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv), 278 279 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1, 280 adc_fgain_tlv), 281 282 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1), 283 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL, 284 0, -24, 40, 6, 0, adc_cgain_tlv), 285 286 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0, 287 119, 0, mic_pga_tlv), 288 289 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN, 290 AIC31XX_HPRGAIN, 2, 1, 0), 291 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN, 292 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv), 293 294 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL, 295 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv), 296 }; 297 298 static const struct snd_kcontrol_new aic311x_snd_controls[] = { 299 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 300 AIC31XX_SPRGAIN, 2, 1, 0), 301 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 302 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv), 303 304 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 305 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv), 306 }; 307 308 static const struct snd_kcontrol_new aic310x_snd_controls[] = { 309 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 310 2, 1, 0), 311 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 312 3, 3, 0, class_D_drv_tlv), 313 314 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 315 0, 0x7F, 1, sp_vol_tlv), 316 }; 317 318 static const struct snd_kcontrol_new ldac_in_control = 319 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum); 320 321 static const struct snd_kcontrol_new rdac_in_control = 322 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum); 323 324 static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg, 325 unsigned int mask, unsigned int wbits, int sleep, 326 int count) 327 { 328 unsigned int bits; 329 int counter = count; 330 int ret = regmap_read(aic31xx->regmap, reg, &bits); 331 332 while ((bits & mask) != wbits && counter && !ret) { 333 usleep_range(sleep, sleep * 2); 334 ret = regmap_read(aic31xx->regmap, reg, &bits); 335 counter--; 336 } 337 if ((bits & mask) != wbits) { 338 dev_err(aic31xx->dev, 339 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n", 340 __func__, reg, bits, wbits, ret, mask, 341 (count - counter) * sleep); 342 ret = -1; 343 } 344 return ret; 345 } 346 347 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg)) 348 349 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w, 350 struct snd_kcontrol *kcontrol, int event) 351 { 352 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(w->codec); 353 unsigned int reg = AIC31XX_DACFLAG1; 354 unsigned int mask; 355 356 switch (WIDGET_BIT(w->reg, w->shift)) { 357 case WIDGET_BIT(AIC31XX_DACSETUP, 7): 358 mask = AIC31XX_LDACPWRSTATUS_MASK; 359 break; 360 case WIDGET_BIT(AIC31XX_DACSETUP, 6): 361 mask = AIC31XX_RDACPWRSTATUS_MASK; 362 break; 363 case WIDGET_BIT(AIC31XX_HPDRIVER, 7): 364 mask = AIC31XX_HPLDRVPWRSTATUS_MASK; 365 break; 366 case WIDGET_BIT(AIC31XX_HPDRIVER, 6): 367 mask = AIC31XX_HPRDRVPWRSTATUS_MASK; 368 break; 369 case WIDGET_BIT(AIC31XX_SPKAMP, 7): 370 mask = AIC31XX_SPLDRVPWRSTATUS_MASK; 371 break; 372 case WIDGET_BIT(AIC31XX_SPKAMP, 6): 373 mask = AIC31XX_SPRDRVPWRSTATUS_MASK; 374 break; 375 case WIDGET_BIT(AIC31XX_ADCSETUP, 7): 376 mask = AIC31XX_ADCPWRSTATUS_MASK; 377 reg = AIC31XX_ADCFLAG; 378 break; 379 default: 380 dev_err(w->codec->dev, "Unknown widget '%s' calling %s\n", 381 w->name, __func__); 382 return -EINVAL; 383 } 384 385 switch (event) { 386 case SND_SOC_DAPM_POST_PMU: 387 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100); 388 case SND_SOC_DAPM_POST_PMD: 389 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100); 390 default: 391 dev_dbg(w->codec->dev, 392 "Unhandled dapm widget event %d from %s\n", 393 event, w->name); 394 } 395 return 0; 396 } 397 398 static const struct snd_kcontrol_new left_output_switches[] = { 399 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 400 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0), 401 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0), 402 }; 403 404 static const struct snd_kcontrol_new right_output_switches[] = { 405 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 406 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0), 407 }; 408 409 static const struct snd_kcontrol_new p_term_mic1lp = 410 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum); 411 412 static const struct snd_kcontrol_new p_term_mic1rp = 413 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum); 414 415 static const struct snd_kcontrol_new p_term_mic1lm = 416 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum); 417 418 static const struct snd_kcontrol_new m_term_mic1lm = 419 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum); 420 421 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch = 422 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0); 423 424 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch = 425 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0); 426 427 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch = 428 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0); 429 430 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch = 431 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0); 432 433 static int mic_bias_event(struct snd_soc_dapm_widget *w, 434 struct snd_kcontrol *kcontrol, int event) 435 { 436 struct snd_soc_codec *codec = w->codec; 437 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 438 439 switch (event) { 440 case SND_SOC_DAPM_POST_PMU: 441 /* change mic bias voltage to user defined */ 442 snd_soc_update_bits(codec, AIC31XX_MICBIAS, 443 AIC31XX_MICBIAS_MASK, 444 aic31xx->pdata.micbias_vg << 445 AIC31XX_MICBIAS_SHIFT); 446 dev_dbg(codec->dev, "%s: turned on\n", __func__); 447 break; 448 case SND_SOC_DAPM_PRE_PMD: 449 /* turn mic bias off */ 450 snd_soc_update_bits(codec, AIC31XX_MICBIAS, 451 AIC31XX_MICBIAS_MASK, 0); 452 dev_dbg(codec->dev, "%s: turned off\n", __func__); 453 break; 454 } 455 return 0; 456 } 457 458 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = { 459 SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0), 460 461 SND_SOC_DAPM_MUX("DAC Left Input", 462 SND_SOC_NOPM, 0, 0, &ldac_in_control), 463 SND_SOC_DAPM_MUX("DAC Right Input", 464 SND_SOC_NOPM, 0, 0, &rdac_in_control), 465 /* DACs */ 466 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback", 467 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event, 468 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 469 470 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback", 471 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event, 472 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 473 474 /* Output Mixers */ 475 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 476 left_output_switches, 477 ARRAY_SIZE(left_output_switches)), 478 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 479 right_output_switches, 480 ARRAY_SIZE(right_output_switches)), 481 482 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0, 483 &aic31xx_dapm_hpl_switch), 484 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0, 485 &aic31xx_dapm_hpr_switch), 486 487 /* Output drivers */ 488 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0, 489 NULL, 0, aic31xx_dapm_power_event, 490 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 491 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0, 492 NULL, 0, aic31xx_dapm_power_event, 493 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 494 495 /* ADC */ 496 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0, 497 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 498 SND_SOC_DAPM_POST_PMD), 499 500 /* Input Selection to MIC_PGA */ 501 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0, 502 &p_term_mic1lp), 503 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0, 504 &p_term_mic1rp), 505 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0, 506 &p_term_mic1lm), 507 508 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0, 509 &m_term_mic1lm), 510 /* Enabling & Disabling MIC Gain Ctl */ 511 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA, 512 7, 1, NULL, 0), 513 514 /* Mic Bias */ 515 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event, 516 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 517 518 /* Outputs */ 519 SND_SOC_DAPM_OUTPUT("HPL"), 520 SND_SOC_DAPM_OUTPUT("HPR"), 521 522 /* Inputs */ 523 SND_SOC_DAPM_INPUT("MIC1LP"), 524 SND_SOC_DAPM_INPUT("MIC1RP"), 525 SND_SOC_DAPM_INPUT("MIC1LM"), 526 }; 527 528 static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = { 529 /* AIC3111 and AIC3110 have stereo class-D amplifier */ 530 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 531 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 532 SND_SOC_DAPM_POST_PMD), 533 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0, 534 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 535 SND_SOC_DAPM_POST_PMD), 536 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0, 537 &aic31xx_dapm_spl_switch), 538 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0, 539 &aic31xx_dapm_spr_switch), 540 SND_SOC_DAPM_OUTPUT("SPL"), 541 SND_SOC_DAPM_OUTPUT("SPR"), 542 }; 543 544 /* AIC3100 and AIC3120 have only mono class-D amplifier */ 545 static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = { 546 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 547 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 548 SND_SOC_DAPM_POST_PMD), 549 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0, 550 &aic31xx_dapm_spl_switch), 551 SND_SOC_DAPM_OUTPUT("SPK"), 552 }; 553 554 static const struct snd_soc_dapm_route 555 aic31xx_audio_map[] = { 556 /* DAC Input Routing */ 557 {"DAC Left Input", "Left Data", "DAC IN"}, 558 {"DAC Left Input", "Right Data", "DAC IN"}, 559 {"DAC Left Input", "Mono", "DAC IN"}, 560 {"DAC Right Input", "Left Data", "DAC IN"}, 561 {"DAC Right Input", "Right Data", "DAC IN"}, 562 {"DAC Right Input", "Mono", "DAC IN"}, 563 {"DAC Left", NULL, "DAC Left Input"}, 564 {"DAC Right", NULL, "DAC Right Input"}, 565 566 /* Mic input */ 567 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"}, 568 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"}, 569 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"}, 570 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"}, 571 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"}, 572 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"}, 573 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"}, 574 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"}, 575 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"}, 576 577 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"}, 578 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"}, 579 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"}, 580 581 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"}, 582 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"}, 583 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"}, 584 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"}, 585 586 {"ADC", NULL, "MIC_GAIN_CTL"}, 587 588 /* Left Output */ 589 {"Output Left", "From Left DAC", "DAC Left"}, 590 {"Output Left", "From MIC1LP", "MIC1LP"}, 591 {"Output Left", "From MIC1RP", "MIC1RP"}, 592 593 /* Right Output */ 594 {"Output Right", "From Right DAC", "DAC Right"}, 595 {"Output Right", "From MIC1RP", "MIC1RP"}, 596 597 /* HPL path */ 598 {"HP Left", "Switch", "Output Left"}, 599 {"HPL Driver", NULL, "HP Left"}, 600 {"HPL", NULL, "HPL Driver"}, 601 602 /* HPR path */ 603 {"HP Right", "Switch", "Output Right"}, 604 {"HPR Driver", NULL, "HP Right"}, 605 {"HPR", NULL, "HPR Driver"}, 606 }; 607 608 static const struct snd_soc_dapm_route 609 aic311x_audio_map[] = { 610 /* SP L path */ 611 {"Speaker Left", "Switch", "Output Left"}, 612 {"SPL ClassD", NULL, "Speaker Left"}, 613 {"SPL", NULL, "SPL ClassD"}, 614 615 /* SP R path */ 616 {"Speaker Right", "Switch", "Output Right"}, 617 {"SPR ClassD", NULL, "Speaker Right"}, 618 {"SPR", NULL, "SPR ClassD"}, 619 }; 620 621 static const struct snd_soc_dapm_route 622 aic310x_audio_map[] = { 623 /* SP L path */ 624 {"Speaker", "Switch", "Output Left"}, 625 {"SPK ClassD", NULL, "Speaker"}, 626 {"SPK", NULL, "SPK ClassD"}, 627 }; 628 629 static int aic31xx_add_controls(struct snd_soc_codec *codec) 630 { 631 int ret = 0; 632 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 633 634 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) 635 ret = snd_soc_add_codec_controls( 636 codec, aic311x_snd_controls, 637 ARRAY_SIZE(aic311x_snd_controls)); 638 else 639 ret = snd_soc_add_codec_controls( 640 codec, aic310x_snd_controls, 641 ARRAY_SIZE(aic310x_snd_controls)); 642 643 return ret; 644 } 645 646 static int aic31xx_add_widgets(struct snd_soc_codec *codec) 647 { 648 struct snd_soc_dapm_context *dapm = &codec->dapm; 649 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 650 int ret = 0; 651 652 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) { 653 ret = snd_soc_dapm_new_controls( 654 dapm, aic311x_dapm_widgets, 655 ARRAY_SIZE(aic311x_dapm_widgets)); 656 if (ret) 657 return ret; 658 659 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map, 660 ARRAY_SIZE(aic311x_audio_map)); 661 if (ret) 662 return ret; 663 } else { 664 ret = snd_soc_dapm_new_controls( 665 dapm, aic310x_dapm_widgets, 666 ARRAY_SIZE(aic310x_dapm_widgets)); 667 if (ret) 668 return ret; 669 670 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map, 671 ARRAY_SIZE(aic310x_audio_map)); 672 if (ret) 673 return ret; 674 } 675 676 return 0; 677 } 678 679 static int aic31xx_setup_pll(struct snd_soc_codec *codec, 680 struct snd_pcm_hw_params *params) 681 { 682 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 683 int bclk_score = snd_soc_params_to_frame_size(params); 684 int mclk_p = aic31xx->sysclk / aic31xx->p_div; 685 int bclk_n = 0; 686 int match = -1; 687 int i; 688 689 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */ 690 snd_soc_update_bits(codec, AIC31XX_CLKMUX, 691 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL); 692 snd_soc_update_bits(codec, AIC31XX_IFACE2, 693 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK); 694 695 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { 696 if (aic31xx_divs[i].rate == params_rate(params) && 697 aic31xx_divs[i].mclk_p == mclk_p) { 698 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) % 699 snd_soc_params_to_frame_size(params); 700 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) / 701 snd_soc_params_to_frame_size(params); 702 if (s < bclk_score && bn > 0) { 703 match = i; 704 bclk_n = bn; 705 bclk_score = s; 706 } 707 } 708 } 709 710 if (match == -1) { 711 dev_err(codec->dev, 712 "%s: Sample rate (%u) and format not supported\n", 713 __func__, params_rate(params)); 714 /* See bellow for details how fix this. */ 715 return -EINVAL; 716 } 717 if (bclk_score != 0) { 718 dev_warn(codec->dev, "Can not produce exact bitclock"); 719 /* This is fine if using dsp format, but if using i2s 720 there may be trouble. To fix the issue edit the 721 aic31xx_divs table for your mclk and sample 722 rate. Details can be found from: 723 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf 724 Section: 5.6 CLOCK Generation and PLL 725 */ 726 } 727 i = match; 728 729 /* PLL configuration */ 730 snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK, 731 (aic31xx->p_div << 4) | 0x01); 732 snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j); 733 734 snd_soc_write(codec, AIC31XX_PLLDMSB, 735 aic31xx_divs[i].pll_d >> 8); 736 snd_soc_write(codec, AIC31XX_PLLDLSB, 737 aic31xx_divs[i].pll_d & 0xff); 738 739 /* DAC dividers configuration */ 740 snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK, 741 aic31xx_divs[i].ndac); 742 snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK, 743 aic31xx_divs[i].mdac); 744 745 snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8); 746 snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff); 747 748 /* ADC dividers configuration. Write reset value 1 if not used. */ 749 snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK, 750 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1); 751 snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK, 752 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1); 753 754 snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr); 755 756 /* Bit clock divider configuration. */ 757 snd_soc_update_bits(codec, AIC31XX_BCLKN, 758 AIC31XX_PLL_MASK, bclk_n); 759 760 aic31xx->rate_div_line = i; 761 762 dev_dbg(codec->dev, 763 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n", 764 aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d, 765 aic31xx->p_div, aic31xx_divs[i].dosr, 766 aic31xx_divs[i].ndac, aic31xx_divs[i].mdac, 767 aic31xx_divs[i].aosr, aic31xx_divs[i].nadc, 768 aic31xx_divs[i].madc, bclk_n); 769 770 return 0; 771 } 772 773 static int aic31xx_hw_params(struct snd_pcm_substream *substream, 774 struct snd_pcm_hw_params *params, 775 struct snd_soc_dai *dai) 776 { 777 struct snd_soc_codec *codec = dai->codec; 778 u8 data = 0; 779 780 dev_dbg(codec->dev, "## %s: width %d rate %d\n", 781 __func__, params_width(params), 782 params_rate(params)); 783 784 switch (params_width(params)) { 785 case 16: 786 break; 787 case 20: 788 data = (AIC31XX_WORD_LEN_20BITS << 789 AIC31XX_IFACE1_DATALEN_SHIFT); 790 break; 791 case 24: 792 data = (AIC31XX_WORD_LEN_24BITS << 793 AIC31XX_IFACE1_DATALEN_SHIFT); 794 break; 795 case 32: 796 data = (AIC31XX_WORD_LEN_32BITS << 797 AIC31XX_IFACE1_DATALEN_SHIFT); 798 break; 799 default: 800 dev_err(codec->dev, "%s: Unsupported width %d\n", 801 __func__, params_width(params)); 802 return -EINVAL; 803 } 804 805 snd_soc_update_bits(codec, AIC31XX_IFACE1, 806 AIC31XX_IFACE1_DATALEN_MASK, 807 data); 808 809 return aic31xx_setup_pll(codec, params); 810 } 811 812 static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute) 813 { 814 struct snd_soc_codec *codec = codec_dai->codec; 815 816 if (mute) { 817 snd_soc_update_bits(codec, AIC31XX_DACMUTE, 818 AIC31XX_DACMUTE_MASK, 819 AIC31XX_DACMUTE_MASK); 820 } else { 821 snd_soc_update_bits(codec, AIC31XX_DACMUTE, 822 AIC31XX_DACMUTE_MASK, 0x0); 823 } 824 825 return 0; 826 } 827 828 static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 829 unsigned int fmt) 830 { 831 struct snd_soc_codec *codec = codec_dai->codec; 832 u8 iface_reg1 = 0; 833 u8 iface_reg2 = 0; 834 u8 dsp_a_val = 0; 835 836 dev_dbg(codec->dev, "## %s: fmt = 0x%x\n", __func__, fmt); 837 838 /* set master/slave audio interface */ 839 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 840 case SND_SOC_DAIFMT_CBM_CFM: 841 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER; 842 break; 843 default: 844 dev_alert(codec->dev, "Invalid DAI master/slave interface\n"); 845 return -EINVAL; 846 } 847 848 /* interface format */ 849 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 850 case SND_SOC_DAIFMT_I2S: 851 break; 852 case SND_SOC_DAIFMT_DSP_A: 853 dsp_a_val = 0x1; 854 case SND_SOC_DAIFMT_DSP_B: 855 /* NOTE: BCLKINV bit value 1 equas NB and 0 equals IB */ 856 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 857 case SND_SOC_DAIFMT_NB_NF: 858 iface_reg2 |= AIC31XX_BCLKINV_MASK; 859 break; 860 case SND_SOC_DAIFMT_IB_NF: 861 break; 862 default: 863 return -EINVAL; 864 } 865 iface_reg1 |= (AIC31XX_DSP_MODE << 866 AIC31XX_IFACE1_DATATYPE_SHIFT); 867 break; 868 case SND_SOC_DAIFMT_RIGHT_J: 869 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE << 870 AIC31XX_IFACE1_DATATYPE_SHIFT); 871 break; 872 case SND_SOC_DAIFMT_LEFT_J: 873 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE << 874 AIC31XX_IFACE1_DATATYPE_SHIFT); 875 break; 876 default: 877 dev_err(codec->dev, "Invalid DAI interface format\n"); 878 return -EINVAL; 879 } 880 881 snd_soc_update_bits(codec, AIC31XX_IFACE1, 882 AIC31XX_IFACE1_DATATYPE_MASK | 883 AIC31XX_IFACE1_MASTER_MASK, 884 iface_reg1); 885 snd_soc_update_bits(codec, AIC31XX_DATA_OFFSET, 886 AIC31XX_DATA_OFFSET_MASK, 887 dsp_a_val); 888 snd_soc_update_bits(codec, AIC31XX_IFACE2, 889 AIC31XX_BCLKINV_MASK, 890 iface_reg2); 891 892 return 0; 893 } 894 895 static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 896 int clk_id, unsigned int freq, int dir) 897 { 898 struct snd_soc_codec *codec = codec_dai->codec; 899 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 900 int i; 901 902 dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n", 903 __func__, clk_id, freq, dir); 904 905 for (i = 1; freq/i > 20000000 && i < 8; i++) 906 ; 907 if (freq/i > 20000000) { 908 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n", 909 __func__, freq); 910 return -EINVAL; 911 } 912 aic31xx->p_div = i; 913 914 for (i = 0; i < ARRAY_SIZE(aic31xx_divs) && 915 aic31xx_divs[i].mclk_p != freq/aic31xx->p_div; i++) 916 ; 917 if (i == ARRAY_SIZE(aic31xx_divs)) { 918 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n", 919 __func__, freq); 920 return -EINVAL; 921 } 922 923 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */ 924 snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK, 925 clk_id << AIC31XX_PLL_CLKIN_SHIFT); 926 927 aic31xx->sysclk = freq; 928 return 0; 929 } 930 931 static int aic31xx_regulator_event(struct notifier_block *nb, 932 unsigned long event, void *data) 933 { 934 struct aic31xx_disable_nb *disable_nb = 935 container_of(nb, struct aic31xx_disable_nb, nb); 936 struct aic31xx_priv *aic31xx = disable_nb->aic31xx; 937 938 if (event & REGULATOR_EVENT_DISABLE) { 939 /* 940 * Put codec to reset and as at least one of the 941 * supplies was disabled. 942 */ 943 if (gpio_is_valid(aic31xx->pdata.gpio_reset)) 944 gpio_set_value(aic31xx->pdata.gpio_reset, 0); 945 946 regcache_mark_dirty(aic31xx->regmap); 947 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__); 948 } 949 950 return 0; 951 } 952 953 static void aic31xx_clk_on(struct snd_soc_codec *codec) 954 { 955 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 956 u8 mask = AIC31XX_PM_MASK; 957 u8 on = AIC31XX_PM_MASK; 958 959 dev_dbg(codec->dev, "codec clock -> on (rate %d)\n", 960 aic31xx_divs[aic31xx->rate_div_line].rate); 961 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, on); 962 mdelay(10); 963 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, on); 964 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, on); 965 if (aic31xx_divs[aic31xx->rate_div_line].nadc) 966 snd_soc_update_bits(codec, AIC31XX_NADC, mask, on); 967 if (aic31xx_divs[aic31xx->rate_div_line].madc) 968 snd_soc_update_bits(codec, AIC31XX_MADC, mask, on); 969 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, on); 970 } 971 972 static void aic31xx_clk_off(struct snd_soc_codec *codec) 973 { 974 u8 mask = AIC31XX_PM_MASK; 975 u8 off = 0; 976 977 dev_dbg(codec->dev, "codec clock -> off\n"); 978 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, off); 979 snd_soc_update_bits(codec, AIC31XX_MADC, mask, off); 980 snd_soc_update_bits(codec, AIC31XX_NADC, mask, off); 981 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, off); 982 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, off); 983 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, off); 984 } 985 986 static int aic31xx_power_on(struct snd_soc_codec *codec) 987 { 988 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 989 int ret = 0; 990 991 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies), 992 aic31xx->supplies); 993 if (ret) 994 return ret; 995 996 if (gpio_is_valid(aic31xx->pdata.gpio_reset)) { 997 gpio_set_value(aic31xx->pdata.gpio_reset, 1); 998 udelay(100); 999 } 1000 regcache_cache_only(aic31xx->regmap, false); 1001 ret = regcache_sync(aic31xx->regmap); 1002 if (ret != 0) { 1003 dev_err(codec->dev, 1004 "Failed to restore cache: %d\n", ret); 1005 regcache_cache_only(aic31xx->regmap, true); 1006 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1007 aic31xx->supplies); 1008 return ret; 1009 } 1010 return 0; 1011 } 1012 1013 static int aic31xx_power_off(struct snd_soc_codec *codec) 1014 { 1015 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 1016 int ret = 0; 1017 1018 regcache_cache_only(aic31xx->regmap, true); 1019 ret = regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1020 aic31xx->supplies); 1021 1022 return ret; 1023 } 1024 1025 static int aic31xx_set_bias_level(struct snd_soc_codec *codec, 1026 enum snd_soc_bias_level level) 1027 { 1028 dev_dbg(codec->dev, "## %s: %d -> %d\n", __func__, 1029 codec->dapm.bias_level, level); 1030 1031 switch (level) { 1032 case SND_SOC_BIAS_ON: 1033 break; 1034 case SND_SOC_BIAS_PREPARE: 1035 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) 1036 aic31xx_clk_on(codec); 1037 break; 1038 case SND_SOC_BIAS_STANDBY: 1039 switch (codec->dapm.bias_level) { 1040 case SND_SOC_BIAS_OFF: 1041 aic31xx_power_on(codec); 1042 break; 1043 case SND_SOC_BIAS_PREPARE: 1044 aic31xx_clk_off(codec); 1045 break; 1046 default: 1047 BUG(); 1048 } 1049 break; 1050 case SND_SOC_BIAS_OFF: 1051 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) 1052 aic31xx_power_off(codec); 1053 break; 1054 } 1055 codec->dapm.bias_level = level; 1056 1057 return 0; 1058 } 1059 1060 static int aic31xx_codec_probe(struct snd_soc_codec *codec) 1061 { 1062 int ret = 0; 1063 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 1064 int i; 1065 1066 dev_dbg(aic31xx->dev, "## %s\n", __func__); 1067 1068 aic31xx = snd_soc_codec_get_drvdata(codec); 1069 1070 aic31xx->codec = codec; 1071 1072 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) { 1073 aic31xx->disable_nb[i].nb.notifier_call = 1074 aic31xx_regulator_event; 1075 aic31xx->disable_nb[i].aic31xx = aic31xx; 1076 ret = regulator_register_notifier(aic31xx->supplies[i].consumer, 1077 &aic31xx->disable_nb[i].nb); 1078 if (ret) { 1079 dev_err(codec->dev, 1080 "Failed to request regulator notifier: %d\n", 1081 ret); 1082 return ret; 1083 } 1084 } 1085 1086 regcache_cache_only(aic31xx->regmap, true); 1087 regcache_mark_dirty(aic31xx->regmap); 1088 1089 ret = aic31xx_add_controls(codec); 1090 if (ret) 1091 return ret; 1092 1093 ret = aic31xx_add_widgets(codec); 1094 1095 return ret; 1096 } 1097 1098 static int aic31xx_codec_remove(struct snd_soc_codec *codec) 1099 { 1100 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); 1101 int i; 1102 1103 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) 1104 regulator_unregister_notifier(aic31xx->supplies[i].consumer, 1105 &aic31xx->disable_nb[i].nb); 1106 1107 return 0; 1108 } 1109 1110 static struct snd_soc_codec_driver soc_codec_driver_aic31xx = { 1111 .probe = aic31xx_codec_probe, 1112 .remove = aic31xx_codec_remove, 1113 .set_bias_level = aic31xx_set_bias_level, 1114 .suspend_bias_off = true, 1115 1116 .controls = aic31xx_snd_controls, 1117 .num_controls = ARRAY_SIZE(aic31xx_snd_controls), 1118 .dapm_widgets = aic31xx_dapm_widgets, 1119 .num_dapm_widgets = ARRAY_SIZE(aic31xx_dapm_widgets), 1120 .dapm_routes = aic31xx_audio_map, 1121 .num_dapm_routes = ARRAY_SIZE(aic31xx_audio_map), 1122 }; 1123 1124 static struct snd_soc_dai_ops aic31xx_dai_ops = { 1125 .hw_params = aic31xx_hw_params, 1126 .set_sysclk = aic31xx_set_dai_sysclk, 1127 .set_fmt = aic31xx_set_dai_fmt, 1128 .digital_mute = aic31xx_dac_mute, 1129 }; 1130 1131 static struct snd_soc_dai_driver aic31xx_dai_driver[] = { 1132 { 1133 .name = "tlv320aic31xx-hifi", 1134 .playback = { 1135 .stream_name = "Playback", 1136 .channels_min = 1, 1137 .channels_max = 2, 1138 .rates = AIC31XX_RATES, 1139 .formats = AIC31XX_FORMATS, 1140 }, 1141 .capture = { 1142 .stream_name = "Capture", 1143 .channels_min = 1, 1144 .channels_max = 2, 1145 .rates = AIC31XX_RATES, 1146 .formats = AIC31XX_FORMATS, 1147 }, 1148 .ops = &aic31xx_dai_ops, 1149 .symmetric_rates = 1, 1150 } 1151 }; 1152 1153 #if defined(CONFIG_OF) 1154 static const struct of_device_id tlv320aic31xx_of_match[] = { 1155 { .compatible = "ti,tlv320aic310x" }, 1156 { .compatible = "ti,tlv320aic311x" }, 1157 { .compatible = "ti,tlv320aic3100" }, 1158 { .compatible = "ti,tlv320aic3110" }, 1159 { .compatible = "ti,tlv320aic3120" }, 1160 { .compatible = "ti,tlv320aic3111" }, 1161 {}, 1162 }; 1163 MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match); 1164 1165 static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx) 1166 { 1167 struct device_node *np = aic31xx->dev->of_node; 1168 unsigned int value = MICBIAS_2_0V; 1169 int ret; 1170 1171 of_property_read_u32(np, "ai31xx-micbias-vg", &value); 1172 switch (value) { 1173 case MICBIAS_2_0V: 1174 case MICBIAS_2_5V: 1175 case MICBIAS_AVDDV: 1176 aic31xx->pdata.micbias_vg = value; 1177 break; 1178 default: 1179 dev_err(aic31xx->dev, 1180 "Bad ai31xx-micbias-vg value %d DT\n", 1181 value); 1182 aic31xx->pdata.micbias_vg = MICBIAS_2_0V; 1183 } 1184 1185 ret = of_get_named_gpio(np, "gpio-reset", 0); 1186 if (ret > 0) 1187 aic31xx->pdata.gpio_reset = ret; 1188 } 1189 #else /* CONFIG_OF */ 1190 static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx) 1191 { 1192 } 1193 #endif /* CONFIG_OF */ 1194 1195 static int aic31xx_device_init(struct aic31xx_priv *aic31xx) 1196 { 1197 int ret, i; 1198 1199 dev_set_drvdata(aic31xx->dev, aic31xx); 1200 1201 if (dev_get_platdata(aic31xx->dev)) 1202 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), 1203 sizeof(aic31xx->pdata)); 1204 else if (aic31xx->dev->of_node) 1205 aic31xx_pdata_from_of(aic31xx); 1206 1207 if (aic31xx->pdata.gpio_reset) { 1208 ret = devm_gpio_request_one(aic31xx->dev, 1209 aic31xx->pdata.gpio_reset, 1210 GPIOF_OUT_INIT_HIGH, 1211 "aic31xx-reset-pin"); 1212 if (ret < 0) { 1213 dev_err(aic31xx->dev, "not able to acquire gpio\n"); 1214 return ret; 1215 } 1216 } 1217 1218 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) 1219 aic31xx->supplies[i].supply = aic31xx_supply_names[i]; 1220 1221 ret = devm_regulator_bulk_get(aic31xx->dev, 1222 ARRAY_SIZE(aic31xx->supplies), 1223 aic31xx->supplies); 1224 if (ret != 0) 1225 dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret); 1226 1227 return ret; 1228 } 1229 1230 static int aic31xx_i2c_probe(struct i2c_client *i2c, 1231 const struct i2c_device_id *id) 1232 { 1233 struct aic31xx_priv *aic31xx; 1234 int ret; 1235 const struct regmap_config *regmap_config; 1236 1237 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__, 1238 id->name, (int) id->driver_data); 1239 1240 regmap_config = &aic31xx_i2c_regmap; 1241 1242 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL); 1243 if (aic31xx == NULL) 1244 return -ENOMEM; 1245 1246 aic31xx->regmap = devm_regmap_init_i2c(i2c, regmap_config); 1247 if (IS_ERR(aic31xx->regmap)) { 1248 ret = PTR_ERR(aic31xx->regmap); 1249 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1250 ret); 1251 return ret; 1252 } 1253 aic31xx->dev = &i2c->dev; 1254 1255 aic31xx->pdata.codec_type = id->driver_data; 1256 1257 ret = aic31xx_device_init(aic31xx); 1258 if (ret) 1259 return ret; 1260 1261 return snd_soc_register_codec(&i2c->dev, &soc_codec_driver_aic31xx, 1262 aic31xx_dai_driver, 1263 ARRAY_SIZE(aic31xx_dai_driver)); 1264 } 1265 1266 static int aic31xx_i2c_remove(struct i2c_client *i2c) 1267 { 1268 snd_soc_unregister_codec(&i2c->dev); 1269 return 0; 1270 } 1271 1272 static const struct i2c_device_id aic31xx_i2c_id[] = { 1273 { "tlv320aic310x", AIC3100 }, 1274 { "tlv320aic311x", AIC3110 }, 1275 { "tlv320aic3100", AIC3100 }, 1276 { "tlv320aic3110", AIC3110 }, 1277 { "tlv320aic3120", AIC3120 }, 1278 { "tlv320aic3111", AIC3111 }, 1279 { } 1280 }; 1281 MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id); 1282 1283 static struct i2c_driver aic31xx_i2c_driver = { 1284 .driver = { 1285 .name = "tlv320aic31xx-codec", 1286 .owner = THIS_MODULE, 1287 .of_match_table = of_match_ptr(tlv320aic31xx_of_match), 1288 }, 1289 .probe = aic31xx_i2c_probe, 1290 .remove = aic31xx_i2c_remove, 1291 .id_table = aic31xx_i2c_id, 1292 }; 1293 1294 module_i2c_driver(aic31xx_i2c_driver); 1295 1296 MODULE_DESCRIPTION("ASoC TLV320AIC3111 codec driver"); 1297 MODULE_AUTHOR("Jyri Sarha"); 1298 MODULE_LICENSE("GPL"); 1299