1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ALSA SoC TLV320AIC31xx CODEC Driver 4 * 5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ 6 * Jyri Sarha <jsarha@ti.com> 7 * 8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com> 9 * 10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated 11 * high performance codecs which provides a stereo DAC, a mono ADC, 12 * and mono/stereo Class-D speaker driver. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/init.h> 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/pm.h> 21 #include <linux/i2c.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/acpi.h> 25 #include <linux/of.h> 26 #include <linux/of_gpio.h> 27 #include <linux/slab.h> 28 #include <sound/core.h> 29 #include <sound/jack.h> 30 #include <sound/pcm.h> 31 #include <sound/pcm_params.h> 32 #include <sound/soc.h> 33 #include <sound/initval.h> 34 #include <sound/tlv.h> 35 #include <dt-bindings/sound/tlv320aic31xx.h> 36 37 #include "tlv320aic31xx.h" 38 39 static int aic31xx_set_jack(struct snd_soc_component *component, 40 struct snd_soc_jack *jack, void *data); 41 42 static const struct reg_default aic31xx_reg_defaults[] = { 43 { AIC31XX_CLKMUX, 0x00 }, 44 { AIC31XX_PLLPR, 0x11 }, 45 { AIC31XX_PLLJ, 0x04 }, 46 { AIC31XX_PLLDMSB, 0x00 }, 47 { AIC31XX_PLLDLSB, 0x00 }, 48 { AIC31XX_NDAC, 0x01 }, 49 { AIC31XX_MDAC, 0x01 }, 50 { AIC31XX_DOSRMSB, 0x00 }, 51 { AIC31XX_DOSRLSB, 0x80 }, 52 { AIC31XX_NADC, 0x01 }, 53 { AIC31XX_MADC, 0x01 }, 54 { AIC31XX_AOSR, 0x80 }, 55 { AIC31XX_IFACE1, 0x00 }, 56 { AIC31XX_DATA_OFFSET, 0x00 }, 57 { AIC31XX_IFACE2, 0x00 }, 58 { AIC31XX_BCLKN, 0x01 }, 59 { AIC31XX_DACSETUP, 0x14 }, 60 { AIC31XX_DACMUTE, 0x0c }, 61 { AIC31XX_LDACVOL, 0x00 }, 62 { AIC31XX_RDACVOL, 0x00 }, 63 { AIC31XX_ADCSETUP, 0x00 }, 64 { AIC31XX_ADCFGA, 0x80 }, 65 { AIC31XX_ADCVOL, 0x00 }, 66 { AIC31XX_HPDRIVER, 0x04 }, 67 { AIC31XX_SPKAMP, 0x06 }, 68 { AIC31XX_DACMIXERROUTE, 0x00 }, 69 { AIC31XX_LANALOGHPL, 0x7f }, 70 { AIC31XX_RANALOGHPR, 0x7f }, 71 { AIC31XX_LANALOGSPL, 0x7f }, 72 { AIC31XX_RANALOGSPR, 0x7f }, 73 { AIC31XX_HPLGAIN, 0x02 }, 74 { AIC31XX_HPRGAIN, 0x02 }, 75 { AIC31XX_SPLGAIN, 0x00 }, 76 { AIC31XX_SPRGAIN, 0x00 }, 77 { AIC31XX_MICBIAS, 0x00 }, 78 { AIC31XX_MICPGA, 0x80 }, 79 { AIC31XX_MICPGAPI, 0x00 }, 80 { AIC31XX_MICPGAMI, 0x00 }, 81 }; 82 83 static bool aic31xx_volatile(struct device *dev, unsigned int reg) 84 { 85 switch (reg) { 86 case AIC31XX_PAGECTL: /* regmap implementation requires this */ 87 case AIC31XX_RESET: /* always clears after write */ 88 case AIC31XX_OT_FLAG: 89 case AIC31XX_ADCFLAG: 90 case AIC31XX_DACFLAG1: 91 case AIC31XX_DACFLAG2: 92 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 93 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 94 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 95 case AIC31XX_INTRDACFLAG2: 96 case AIC31XX_INTRADCFLAG2: 97 case AIC31XX_HSDETECT: 98 return true; 99 } 100 return false; 101 } 102 103 static bool aic31xx_writeable(struct device *dev, unsigned int reg) 104 { 105 switch (reg) { 106 case AIC31XX_OT_FLAG: 107 case AIC31XX_ADCFLAG: 108 case AIC31XX_DACFLAG1: 109 case AIC31XX_DACFLAG2: 110 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 111 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 112 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 113 case AIC31XX_INTRDACFLAG2: 114 case AIC31XX_INTRADCFLAG2: 115 return false; 116 } 117 return true; 118 } 119 120 static const struct regmap_range_cfg aic31xx_ranges[] = { 121 { 122 .range_min = 0, 123 .range_max = 12 * 128, 124 .selector_reg = AIC31XX_PAGECTL, 125 .selector_mask = 0xff, 126 .selector_shift = 0, 127 .window_start = 0, 128 .window_len = 128, 129 }, 130 }; 131 132 static const struct regmap_config aic31xx_i2c_regmap = { 133 .reg_bits = 8, 134 .val_bits = 8, 135 .writeable_reg = aic31xx_writeable, 136 .volatile_reg = aic31xx_volatile, 137 .reg_defaults = aic31xx_reg_defaults, 138 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults), 139 .cache_type = REGCACHE_RBTREE, 140 .ranges = aic31xx_ranges, 141 .num_ranges = ARRAY_SIZE(aic31xx_ranges), 142 .max_register = 12 * 128, 143 }; 144 145 static const char * const aic31xx_supply_names[] = { 146 "HPVDD", 147 "SPRVDD", 148 "SPLVDD", 149 "AVDD", 150 "IOVDD", 151 "DVDD", 152 }; 153 154 #define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names) 155 156 struct aic31xx_disable_nb { 157 struct notifier_block nb; 158 struct aic31xx_priv *aic31xx; 159 }; 160 161 struct aic31xx_priv { 162 struct snd_soc_component *component; 163 u8 i2c_regs_status; 164 struct device *dev; 165 struct regmap *regmap; 166 enum aic31xx_type codec_type; 167 struct gpio_desc *gpio_reset; 168 int micbias_vg; 169 struct aic31xx_pdata pdata; 170 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES]; 171 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES]; 172 struct snd_soc_jack *jack; 173 u32 sysclk_id; 174 unsigned int sysclk; 175 u8 p_div; 176 int rate_div_line; 177 bool master_dapm_route_applied; 178 int irq; 179 u8 ocmv; /* output common-mode voltage */ 180 }; 181 182 struct aic31xx_rate_divs { 183 u32 mclk_p; 184 u32 rate; 185 u8 pll_r; 186 u8 pll_j; 187 u16 pll_d; 188 u16 dosr; 189 u8 ndac; 190 u8 mdac; 191 u8 aosr; 192 u8 nadc; 193 u8 madc; 194 }; 195 196 /* ADC dividers can be disabled by configuring them to 0 */ 197 static const struct aic31xx_rate_divs aic31xx_divs[] = { 198 /* mclk/p rate pll: r j d dosr ndac mdac aors nadc madc */ 199 /* 8k rate */ 200 { 512000, 8000, 4, 48, 0, 128, 48, 2, 128, 48, 2}, 201 {12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2}, 202 {12000000, 8000, 1, 8, 1920, 128, 32, 3, 128, 32, 3}, 203 {12500000, 8000, 1, 7, 8643, 128, 48, 2, 128, 48, 2}, 204 /* 11.025k rate */ 205 { 705600, 11025, 3, 48, 0, 128, 24, 3, 128, 24, 3}, 206 {12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2}, 207 {12000000, 11025, 1, 8, 4672, 128, 24, 3, 128, 24, 3}, 208 {12500000, 11025, 1, 7, 2253, 128, 32, 2, 128, 32, 2}, 209 /* 16k rate */ 210 { 512000, 16000, 4, 48, 0, 128, 16, 3, 128, 16, 3}, 211 { 1024000, 16000, 2, 48, 0, 128, 16, 3, 128, 16, 3}, 212 {12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2}, 213 {12000000, 16000, 1, 8, 1920, 128, 16, 3, 128, 16, 3}, 214 {12500000, 16000, 1, 7, 8643, 128, 24, 2, 128, 24, 2}, 215 /* 22.05k rate */ 216 { 705600, 22050, 4, 36, 0, 128, 12, 3, 128, 12, 3}, 217 { 1411200, 22050, 2, 36, 0, 128, 12, 3, 128, 12, 3}, 218 {12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2}, 219 {12000000, 22050, 1, 8, 4672, 128, 12, 3, 128, 12, 3}, 220 {12500000, 22050, 1, 7, 2253, 128, 16, 2, 128, 16, 2}, 221 /* 32k rate */ 222 { 1024000, 32000, 2, 48, 0, 128, 12, 2, 128, 12, 2}, 223 { 2048000, 32000, 1, 48, 0, 128, 12, 2, 128, 12, 2}, 224 {12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2}, 225 {12000000, 32000, 1, 8, 1920, 128, 8, 3, 128, 8, 3}, 226 {12500000, 32000, 1, 7, 8643, 128, 12, 2, 128, 12, 2}, 227 /* 44.1k rate */ 228 { 1411200, 44100, 2, 32, 0, 128, 8, 2, 128, 8, 2}, 229 { 2822400, 44100, 1, 32, 0, 128, 8, 2, 128, 8, 2}, 230 {12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2}, 231 {12000000, 44100, 1, 8, 4672, 128, 6, 3, 128, 6, 3}, 232 {12500000, 44100, 1, 7, 2253, 128, 8, 2, 128, 8, 2}, 233 /* 48k rate */ 234 { 1536000, 48000, 2, 32, 0, 128, 8, 2, 128, 8, 2}, 235 { 3072000, 48000, 1, 32, 0, 128, 8, 2, 128, 8, 2}, 236 {12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2}, 237 {12000000, 48000, 1, 7, 6800, 96, 5, 4, 96, 5, 4}, 238 {12500000, 48000, 1, 7, 8643, 128, 8, 2, 128, 8, 2}, 239 /* 88.2k rate */ 240 { 2822400, 88200, 2, 16, 0, 64, 8, 2, 64, 8, 2}, 241 { 5644800, 88200, 1, 16, 0, 64, 8, 2, 64, 8, 2}, 242 {12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2}, 243 {12000000, 88200, 1, 8, 4672, 64, 6, 3, 64, 6, 3}, 244 {12500000, 88200, 1, 7, 2253, 64, 8, 2, 64, 8, 2}, 245 /* 96k rate */ 246 { 3072000, 96000, 2, 16, 0, 64, 8, 2, 64, 8, 2}, 247 { 6144000, 96000, 1, 16, 0, 64, 8, 2, 64, 8, 2}, 248 {12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2}, 249 {12000000, 96000, 1, 7, 6800, 48, 5, 4, 48, 5, 4}, 250 {12500000, 96000, 1, 7, 8643, 64, 8, 2, 64, 8, 2}, 251 /* 176.4k rate */ 252 { 5644800, 176400, 2, 8, 0, 32, 8, 2, 32, 8, 2}, 253 {11289600, 176400, 1, 8, 0, 32, 8, 2, 32, 8, 2}, 254 {12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2}, 255 {12000000, 176400, 1, 8, 4672, 32, 6, 3, 32, 6, 3}, 256 {12500000, 176400, 1, 7, 2253, 32, 8, 2, 32, 8, 2}, 257 /* 192k rate */ 258 { 6144000, 192000, 2, 8, 0, 32, 8, 2, 32, 8, 2}, 259 {12288000, 192000, 1, 8, 0, 32, 8, 2, 32, 8, 2}, 260 {12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2}, 261 {12000000, 192000, 1, 7, 6800, 24, 5, 4, 24, 5, 4}, 262 {12500000, 192000, 1, 7, 8643, 32, 8, 2, 32, 8, 2}, 263 }; 264 265 static const char * const ldac_in_text[] = { 266 "Off", "Left Data", "Right Data", "Mono" 267 }; 268 269 static const char * const rdac_in_text[] = { 270 "Off", "Right Data", "Left Data", "Mono" 271 }; 272 273 static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text); 274 275 static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text); 276 277 static const char * const mic_select_text[] = { 278 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm" 279 }; 280 281 static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6, 282 mic_select_text); 283 static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4, 284 mic_select_text); 285 static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2, 286 mic_select_text); 287 288 static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4, 289 mic_select_text); 290 291 static const char * const hp_poweron_time_text[] = { 292 "0us", "15.3us", "153us", "1.53ms", "15.3ms", "76.2ms", 293 "153ms", "304ms", "610ms", "1.22s", "3.04s", "6.1s" }; 294 295 static SOC_ENUM_SINGLE_DECL(hp_poweron_time_enum, AIC31XX_HPPOP, 3, 296 hp_poweron_time_text); 297 298 static const char * const hp_rampup_step_text[] = { 299 "0ms", "0.98ms", "1.95ms", "3.9ms" }; 300 301 static SOC_ENUM_SINGLE_DECL(hp_rampup_step_enum, AIC31XX_HPPOP, 1, 302 hp_rampup_step_text); 303 304 static const char * const vol_soft_step_mode_text[] = { 305 "fast", "slow", "disabled" }; 306 307 static SOC_ENUM_SINGLE_DECL(vol_soft_step_mode_enum, AIC31XX_DACSETUP, 0, 308 vol_soft_step_mode_text); 309 310 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0); 311 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0); 312 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0); 313 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0); 314 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0); 315 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0); 316 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0); 317 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0); 318 319 /* 320 * controls to be exported to the user space 321 */ 322 static const struct snd_kcontrol_new common31xx_snd_controls[] = { 323 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL, 324 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv), 325 326 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN, 327 AIC31XX_HPRGAIN, 2, 1, 0), 328 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN, 329 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv), 330 331 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL, 332 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv), 333 334 /* HP de-pop control: apply power not immediately but via ramp 335 * function with these psarameters. Note that power up sequence 336 * has to wait for this to complete; this is implemented by 337 * polling HP driver status in aic31xx_dapm_power_event() 338 */ 339 SOC_ENUM("HP Output Driver Power-On time", hp_poweron_time_enum), 340 SOC_ENUM("HP Output Driver Ramp-up step", hp_rampup_step_enum), 341 342 SOC_ENUM("Volume Soft Stepping", vol_soft_step_mode_enum), 343 }; 344 345 static const struct snd_kcontrol_new aic31xx_snd_controls[] = { 346 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1, 347 adc_fgain_tlv), 348 349 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1), 350 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL, 351 0, -24, 40, 6, 0, adc_cgain_tlv), 352 353 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0, 354 119, 0, mic_pga_tlv), 355 }; 356 357 static const struct snd_kcontrol_new aic311x_snd_controls[] = { 358 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 359 AIC31XX_SPRGAIN, 2, 1, 0), 360 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 361 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv), 362 363 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 364 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv), 365 }; 366 367 static const struct snd_kcontrol_new aic310x_snd_controls[] = { 368 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 369 2, 1, 0), 370 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 371 3, 3, 0, class_D_drv_tlv), 372 373 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 374 0, 0x7F, 1, sp_vol_tlv), 375 }; 376 377 static const struct snd_kcontrol_new ldac_in_control = 378 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum); 379 380 static const struct snd_kcontrol_new rdac_in_control = 381 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum); 382 383 static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg, 384 unsigned int mask, unsigned int wbits, int sleep, 385 int count) 386 { 387 unsigned int bits; 388 int counter = count; 389 int ret = regmap_read(aic31xx->regmap, reg, &bits); 390 391 while ((bits & mask) != wbits && counter && !ret) { 392 usleep_range(sleep, sleep * 2); 393 ret = regmap_read(aic31xx->regmap, reg, &bits); 394 counter--; 395 } 396 if ((bits & mask) != wbits) { 397 dev_err(aic31xx->dev, 398 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n", 399 __func__, reg, bits, wbits, ret, mask, 400 (count - counter) * sleep); 401 ret = -1; 402 } 403 return ret; 404 } 405 406 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg)) 407 408 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w, 409 struct snd_kcontrol *kcontrol, int event) 410 { 411 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 412 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 413 unsigned int reg = AIC31XX_DACFLAG1; 414 unsigned int mask; 415 unsigned int timeout = 500 * USEC_PER_MSEC; 416 417 switch (WIDGET_BIT(w->reg, w->shift)) { 418 case WIDGET_BIT(AIC31XX_DACSETUP, 7): 419 mask = AIC31XX_LDACPWRSTATUS_MASK; 420 break; 421 case WIDGET_BIT(AIC31XX_DACSETUP, 6): 422 mask = AIC31XX_RDACPWRSTATUS_MASK; 423 break; 424 case WIDGET_BIT(AIC31XX_HPDRIVER, 7): 425 mask = AIC31XX_HPLDRVPWRSTATUS_MASK; 426 if (event == SND_SOC_DAPM_POST_PMU) 427 timeout = 7 * USEC_PER_SEC; 428 break; 429 case WIDGET_BIT(AIC31XX_HPDRIVER, 6): 430 mask = AIC31XX_HPRDRVPWRSTATUS_MASK; 431 if (event == SND_SOC_DAPM_POST_PMU) 432 timeout = 7 * USEC_PER_SEC; 433 break; 434 case WIDGET_BIT(AIC31XX_SPKAMP, 7): 435 mask = AIC31XX_SPLDRVPWRSTATUS_MASK; 436 break; 437 case WIDGET_BIT(AIC31XX_SPKAMP, 6): 438 mask = AIC31XX_SPRDRVPWRSTATUS_MASK; 439 break; 440 case WIDGET_BIT(AIC31XX_ADCSETUP, 7): 441 mask = AIC31XX_ADCPWRSTATUS_MASK; 442 reg = AIC31XX_ADCFLAG; 443 break; 444 default: 445 dev_err(component->dev, "Unknown widget '%s' calling %s\n", 446 w->name, __func__); 447 return -EINVAL; 448 } 449 450 switch (event) { 451 case SND_SOC_DAPM_POST_PMU: 452 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 453 5000, timeout / 5000); 454 case SND_SOC_DAPM_POST_PMD: 455 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 456 5000, timeout / 5000); 457 default: 458 dev_dbg(component->dev, 459 "Unhandled dapm widget event %d from %s\n", 460 event, w->name); 461 } 462 return 0; 463 } 464 465 static const struct snd_kcontrol_new aic31xx_left_output_switches[] = { 466 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 467 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0), 468 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0), 469 }; 470 471 static const struct snd_kcontrol_new aic31xx_right_output_switches[] = { 472 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 473 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0), 474 }; 475 476 static const struct snd_kcontrol_new dac31xx_left_output_switches[] = { 477 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 478 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0), 479 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0), 480 }; 481 482 static const struct snd_kcontrol_new dac31xx_right_output_switches[] = { 483 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 484 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0), 485 }; 486 487 static const struct snd_kcontrol_new p_term_mic1lp = 488 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum); 489 490 static const struct snd_kcontrol_new p_term_mic1rp = 491 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum); 492 493 static const struct snd_kcontrol_new p_term_mic1lm = 494 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum); 495 496 static const struct snd_kcontrol_new m_term_mic1lm = 497 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum); 498 499 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch = 500 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0); 501 502 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch = 503 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0); 504 505 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch = 506 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0); 507 508 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch = 509 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0); 510 511 static int mic_bias_event(struct snd_soc_dapm_widget *w, 512 struct snd_kcontrol *kcontrol, int event) 513 { 514 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 515 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 516 517 switch (event) { 518 case SND_SOC_DAPM_POST_PMU: 519 /* change mic bias voltage to user defined */ 520 snd_soc_component_update_bits(component, AIC31XX_MICBIAS, 521 AIC31XX_MICBIAS_MASK, 522 aic31xx->micbias_vg << 523 AIC31XX_MICBIAS_SHIFT); 524 dev_dbg(component->dev, "%s: turned on\n", __func__); 525 break; 526 case SND_SOC_DAPM_PRE_PMD: 527 /* turn mic bias off */ 528 snd_soc_component_update_bits(component, AIC31XX_MICBIAS, 529 AIC31XX_MICBIAS_MASK, 0); 530 dev_dbg(component->dev, "%s: turned off\n", __func__); 531 break; 532 } 533 return 0; 534 } 535 536 static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = { 537 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0), 538 539 SND_SOC_DAPM_MUX("DAC Left Input", 540 SND_SOC_NOPM, 0, 0, &ldac_in_control), 541 SND_SOC_DAPM_MUX("DAC Right Input", 542 SND_SOC_NOPM, 0, 0, &rdac_in_control), 543 /* DACs */ 544 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback", 545 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event, 546 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 547 548 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback", 549 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event, 550 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 551 552 /* HP */ 553 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0, 554 &aic31xx_dapm_hpl_switch), 555 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0, 556 &aic31xx_dapm_hpr_switch), 557 558 /* Output drivers */ 559 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0, 560 NULL, 0, aic31xx_dapm_power_event, 561 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 562 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0, 563 NULL, 0, aic31xx_dapm_power_event, 564 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 565 566 /* Mic Bias */ 567 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event, 568 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 569 570 /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */ 571 SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0, 572 NULL, 0), 573 574 /* Outputs */ 575 SND_SOC_DAPM_OUTPUT("HPL"), 576 SND_SOC_DAPM_OUTPUT("HPR"), 577 }; 578 579 static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = { 580 /* Inputs */ 581 SND_SOC_DAPM_INPUT("AIN1"), 582 SND_SOC_DAPM_INPUT("AIN2"), 583 584 /* Output Mixers */ 585 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 586 dac31xx_left_output_switches, 587 ARRAY_SIZE(dac31xx_left_output_switches)), 588 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 589 dac31xx_right_output_switches, 590 ARRAY_SIZE(dac31xx_right_output_switches)), 591 }; 592 593 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = { 594 /* Inputs */ 595 SND_SOC_DAPM_INPUT("MIC1LP"), 596 SND_SOC_DAPM_INPUT("MIC1RP"), 597 SND_SOC_DAPM_INPUT("MIC1LM"), 598 599 /* Input Selection to MIC_PGA */ 600 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0, 601 &p_term_mic1lp), 602 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0, 603 &p_term_mic1rp), 604 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0, 605 &p_term_mic1lm), 606 607 /* ADC */ 608 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0, 609 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 610 SND_SOC_DAPM_POST_PMD), 611 612 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0, 613 &m_term_mic1lm), 614 615 /* Enabling & Disabling MIC Gain Ctl */ 616 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA, 617 7, 1, NULL, 0), 618 619 /* Output Mixers */ 620 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 621 aic31xx_left_output_switches, 622 ARRAY_SIZE(aic31xx_left_output_switches)), 623 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 624 aic31xx_right_output_switches, 625 ARRAY_SIZE(aic31xx_right_output_switches)), 626 627 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 628 }; 629 630 static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = { 631 /* AIC3111 and AIC3110 have stereo class-D amplifier */ 632 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 633 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 634 SND_SOC_DAPM_POST_PMD), 635 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0, 636 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 637 SND_SOC_DAPM_POST_PMD), 638 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0, 639 &aic31xx_dapm_spl_switch), 640 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0, 641 &aic31xx_dapm_spr_switch), 642 SND_SOC_DAPM_OUTPUT("SPL"), 643 SND_SOC_DAPM_OUTPUT("SPR"), 644 }; 645 646 /* AIC3100 and AIC3120 have only mono class-D amplifier */ 647 static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = { 648 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 649 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 650 SND_SOC_DAPM_POST_PMD), 651 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0, 652 &aic31xx_dapm_spl_switch), 653 SND_SOC_DAPM_OUTPUT("SPK"), 654 }; 655 656 static const struct snd_soc_dapm_route 657 common31xx_audio_map[] = { 658 /* DAC Input Routing */ 659 {"DAC Left Input", "Left Data", "AIF IN"}, 660 {"DAC Left Input", "Right Data", "AIF IN"}, 661 {"DAC Left Input", "Mono", "AIF IN"}, 662 {"DAC Right Input", "Left Data", "AIF IN"}, 663 {"DAC Right Input", "Right Data", "AIF IN"}, 664 {"DAC Right Input", "Mono", "AIF IN"}, 665 {"DAC Left", NULL, "DAC Left Input"}, 666 {"DAC Right", NULL, "DAC Right Input"}, 667 668 /* HPL path */ 669 {"HP Left", "Switch", "Output Left"}, 670 {"HPL Driver", NULL, "HP Left"}, 671 {"HPL", NULL, "HPL Driver"}, 672 673 /* HPR path */ 674 {"HP Right", "Switch", "Output Right"}, 675 {"HPR Driver", NULL, "HP Right"}, 676 {"HPR", NULL, "HPR Driver"}, 677 }; 678 679 static const struct snd_soc_dapm_route 680 dac31xx_audio_map[] = { 681 /* Left Output */ 682 {"Output Left", "From Left DAC", "DAC Left"}, 683 {"Output Left", "From AIN1", "AIN1"}, 684 {"Output Left", "From AIN2", "AIN2"}, 685 686 /* Right Output */ 687 {"Output Right", "From Right DAC", "DAC Right"}, 688 {"Output Right", "From AIN2", "AIN2"}, 689 }; 690 691 static const struct snd_soc_dapm_route 692 aic31xx_audio_map[] = { 693 /* Mic input */ 694 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"}, 695 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"}, 696 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"}, 697 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"}, 698 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"}, 699 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"}, 700 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"}, 701 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"}, 702 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"}, 703 704 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"}, 705 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"}, 706 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"}, 707 708 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"}, 709 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"}, 710 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"}, 711 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"}, 712 713 {"ADC", NULL, "MIC_GAIN_CTL"}, 714 715 {"AIF OUT", NULL, "ADC"}, 716 717 /* Left Output */ 718 {"Output Left", "From Left DAC", "DAC Left"}, 719 {"Output Left", "From MIC1LP", "MIC1LP"}, 720 {"Output Left", "From MIC1RP", "MIC1RP"}, 721 722 /* Right Output */ 723 {"Output Right", "From Right DAC", "DAC Right"}, 724 {"Output Right", "From MIC1RP", "MIC1RP"}, 725 }; 726 727 static const struct snd_soc_dapm_route 728 aic311x_audio_map[] = { 729 /* SP L path */ 730 {"Speaker Left", "Switch", "Output Left"}, 731 {"SPL ClassD", NULL, "Speaker Left"}, 732 {"SPL", NULL, "SPL ClassD"}, 733 734 /* SP R path */ 735 {"Speaker Right", "Switch", "Output Right"}, 736 {"SPR ClassD", NULL, "Speaker Right"}, 737 {"SPR", NULL, "SPR ClassD"}, 738 }; 739 740 static const struct snd_soc_dapm_route 741 aic310x_audio_map[] = { 742 /* SP L path */ 743 {"Speaker", "Switch", "Output Left"}, 744 {"SPK ClassD", NULL, "Speaker"}, 745 {"SPK", NULL, "SPK ClassD"}, 746 }; 747 748 /* 749 * Always connected DAPM routes for codec clock master modes. 750 * If the codec is the master on the I2S bus, we need to power up components 751 * to have valid DAC_CLK. 752 * 753 * In order to have the I2S clocks on the bus either the DACs/ADC need to be 754 * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set. 755 * 756 * Otherwise the codec will not generate clocks on the bus. 757 */ 758 static const struct snd_soc_dapm_route 759 common31xx_cm_audio_map[] = { 760 {"HPL", NULL, "AIF IN"}, 761 {"HPR", NULL, "AIF IN"}, 762 763 {"AIF IN", NULL, "Activate I2S clocks"}, 764 }; 765 766 static const struct snd_soc_dapm_route 767 aic31xx_cm_audio_map[] = { 768 {"AIF OUT", NULL, "MIC1LP"}, 769 {"AIF OUT", NULL, "MIC1RP"}, 770 {"AIF OUT", NULL, "MIC1LM"}, 771 772 {"AIF OUT", NULL, "Activate I2S clocks"}, 773 }; 774 775 static int aic31xx_add_controls(struct snd_soc_component *component) 776 { 777 int ret = 0; 778 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 779 780 if (!(aic31xx->codec_type & DAC31XX_BIT)) 781 ret = snd_soc_add_component_controls( 782 component, aic31xx_snd_controls, 783 ARRAY_SIZE(aic31xx_snd_controls)); 784 if (ret) 785 return ret; 786 787 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) 788 ret = snd_soc_add_component_controls( 789 component, aic311x_snd_controls, 790 ARRAY_SIZE(aic311x_snd_controls)); 791 else 792 ret = snd_soc_add_component_controls( 793 component, aic310x_snd_controls, 794 ARRAY_SIZE(aic310x_snd_controls)); 795 796 return ret; 797 } 798 799 static int aic31xx_add_widgets(struct snd_soc_component *component) 800 { 801 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 802 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 803 int ret = 0; 804 805 if (aic31xx->codec_type & DAC31XX_BIT) { 806 ret = snd_soc_dapm_new_controls( 807 dapm, dac31xx_dapm_widgets, 808 ARRAY_SIZE(dac31xx_dapm_widgets)); 809 if (ret) 810 return ret; 811 812 ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map, 813 ARRAY_SIZE(dac31xx_audio_map)); 814 if (ret) 815 return ret; 816 } else { 817 ret = snd_soc_dapm_new_controls( 818 dapm, aic31xx_dapm_widgets, 819 ARRAY_SIZE(aic31xx_dapm_widgets)); 820 if (ret) 821 return ret; 822 823 ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map, 824 ARRAY_SIZE(aic31xx_audio_map)); 825 if (ret) 826 return ret; 827 } 828 829 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) { 830 ret = snd_soc_dapm_new_controls( 831 dapm, aic311x_dapm_widgets, 832 ARRAY_SIZE(aic311x_dapm_widgets)); 833 if (ret) 834 return ret; 835 836 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map, 837 ARRAY_SIZE(aic311x_audio_map)); 838 if (ret) 839 return ret; 840 } else { 841 ret = snd_soc_dapm_new_controls( 842 dapm, aic310x_dapm_widgets, 843 ARRAY_SIZE(aic310x_dapm_widgets)); 844 if (ret) 845 return ret; 846 847 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map, 848 ARRAY_SIZE(aic310x_audio_map)); 849 if (ret) 850 return ret; 851 } 852 853 return 0; 854 } 855 856 static int aic31xx_setup_pll(struct snd_soc_component *component, 857 struct snd_pcm_hw_params *params) 858 { 859 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 860 int bclk_score = snd_soc_params_to_frame_size(params); 861 int mclk_p; 862 int bclk_n = 0; 863 int match = -1; 864 int i; 865 866 if (!aic31xx->sysclk || !aic31xx->p_div) { 867 dev_err(component->dev, "Master clock not supplied\n"); 868 return -EINVAL; 869 } 870 mclk_p = aic31xx->sysclk / aic31xx->p_div; 871 872 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */ 873 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, 874 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL); 875 snd_soc_component_update_bits(component, AIC31XX_IFACE2, 876 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK); 877 878 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { 879 if (aic31xx_divs[i].rate == params_rate(params) && 880 aic31xx_divs[i].mclk_p == mclk_p) { 881 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) % 882 snd_soc_params_to_frame_size(params); 883 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) / 884 snd_soc_params_to_frame_size(params); 885 if (s < bclk_score && bn > 0) { 886 match = i; 887 bclk_n = bn; 888 bclk_score = s; 889 } 890 } 891 } 892 893 if (match == -1) { 894 dev_err(component->dev, 895 "%s: Sample rate (%u) and format not supported\n", 896 __func__, params_rate(params)); 897 /* See bellow for details how fix this. */ 898 return -EINVAL; 899 } 900 if (bclk_score != 0) { 901 dev_warn(component->dev, "Can not produce exact bitclock"); 902 /* This is fine if using dsp format, but if using i2s 903 there may be trouble. To fix the issue edit the 904 aic31xx_divs table for your mclk and sample 905 rate. Details can be found from: 906 https://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf 907 Section: 5.6 CLOCK Generation and PLL 908 */ 909 } 910 i = match; 911 912 /* PLL configuration */ 913 snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK, 914 (aic31xx->p_div << 4) | aic31xx_divs[i].pll_r); 915 snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j); 916 917 snd_soc_component_write(component, AIC31XX_PLLDMSB, 918 aic31xx_divs[i].pll_d >> 8); 919 snd_soc_component_write(component, AIC31XX_PLLDLSB, 920 aic31xx_divs[i].pll_d & 0xff); 921 922 /* DAC dividers configuration */ 923 snd_soc_component_update_bits(component, AIC31XX_NDAC, AIC31XX_PLL_MASK, 924 aic31xx_divs[i].ndac); 925 snd_soc_component_update_bits(component, AIC31XX_MDAC, AIC31XX_PLL_MASK, 926 aic31xx_divs[i].mdac); 927 928 snd_soc_component_write(component, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8); 929 snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff); 930 931 /* ADC dividers configuration. Write reset value 1 if not used. */ 932 snd_soc_component_update_bits(component, AIC31XX_NADC, AIC31XX_PLL_MASK, 933 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1); 934 snd_soc_component_update_bits(component, AIC31XX_MADC, AIC31XX_PLL_MASK, 935 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1); 936 937 snd_soc_component_write(component, AIC31XX_AOSR, aic31xx_divs[i].aosr); 938 939 /* Bit clock divider configuration. */ 940 snd_soc_component_update_bits(component, AIC31XX_BCLKN, 941 AIC31XX_PLL_MASK, bclk_n); 942 943 aic31xx->rate_div_line = i; 944 945 dev_dbg(component->dev, 946 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n", 947 aic31xx_divs[i].pll_j, 948 aic31xx_divs[i].pll_d, 949 aic31xx->p_div, 950 aic31xx_divs[i].dosr, 951 aic31xx_divs[i].ndac, 952 aic31xx_divs[i].mdac, 953 aic31xx_divs[i].aosr, 954 aic31xx_divs[i].nadc, 955 aic31xx_divs[i].madc, 956 bclk_n 957 ); 958 959 return 0; 960 } 961 962 static int aic31xx_hw_params(struct snd_pcm_substream *substream, 963 struct snd_pcm_hw_params *params, 964 struct snd_soc_dai *dai) 965 { 966 struct snd_soc_component *component = dai->component; 967 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 968 u8 data = 0; 969 970 dev_dbg(component->dev, "## %s: width %d rate %d\n", 971 __func__, params_width(params), 972 params_rate(params)); 973 974 switch (params_width(params)) { 975 case 16: 976 break; 977 case 20: 978 data = (AIC31XX_WORD_LEN_20BITS << 979 AIC31XX_IFACE1_DATALEN_SHIFT); 980 break; 981 case 24: 982 data = (AIC31XX_WORD_LEN_24BITS << 983 AIC31XX_IFACE1_DATALEN_SHIFT); 984 break; 985 case 32: 986 data = (AIC31XX_WORD_LEN_32BITS << 987 AIC31XX_IFACE1_DATALEN_SHIFT); 988 break; 989 default: 990 dev_err(component->dev, "%s: Unsupported width %d\n", 991 __func__, params_width(params)); 992 return -EINVAL; 993 } 994 995 snd_soc_component_update_bits(component, AIC31XX_IFACE1, 996 AIC31XX_IFACE1_DATALEN_MASK, 997 data); 998 999 /* 1000 * If BCLK is used as PLL input, the sysclk is determined by the hw 1001 * params. So it must be updated here to match the input frequency. 1002 */ 1003 if (aic31xx->sysclk_id == AIC31XX_PLL_CLKIN_BCLK) { 1004 aic31xx->sysclk = params_rate(params) * params_width(params) * 1005 params_channels(params); 1006 aic31xx->p_div = 1; 1007 } 1008 1009 return aic31xx_setup_pll(component, params); 1010 } 1011 1012 static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute, 1013 int direction) 1014 { 1015 struct snd_soc_component *component = codec_dai->component; 1016 1017 if (mute) { 1018 snd_soc_component_update_bits(component, AIC31XX_DACMUTE, 1019 AIC31XX_DACMUTE_MASK, 1020 AIC31XX_DACMUTE_MASK); 1021 } else { 1022 snd_soc_component_update_bits(component, AIC31XX_DACMUTE, 1023 AIC31XX_DACMUTE_MASK, 0x0); 1024 } 1025 1026 return 0; 1027 } 1028 1029 static int aic31xx_clock_master_routes(struct snd_soc_component *component, 1030 unsigned int fmt) 1031 { 1032 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1033 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1034 int ret; 1035 1036 fmt &= SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK; 1037 if (fmt == SND_SOC_DAIFMT_CBC_CFC && 1038 aic31xx->master_dapm_route_applied) { 1039 /* 1040 * Remove the DAPM route(s) for codec clock master modes, 1041 * if applied 1042 */ 1043 ret = snd_soc_dapm_del_routes(dapm, common31xx_cm_audio_map, 1044 ARRAY_SIZE(common31xx_cm_audio_map)); 1045 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT)) 1046 ret = snd_soc_dapm_del_routes(dapm, 1047 aic31xx_cm_audio_map, 1048 ARRAY_SIZE(aic31xx_cm_audio_map)); 1049 1050 if (ret) 1051 return ret; 1052 1053 aic31xx->master_dapm_route_applied = false; 1054 } else if (fmt != SND_SOC_DAIFMT_CBC_CFC && 1055 !aic31xx->master_dapm_route_applied) { 1056 /* 1057 * Add the needed DAPM route(s) for codec clock master modes, 1058 * if it is not done already 1059 */ 1060 ret = snd_soc_dapm_add_routes(dapm, common31xx_cm_audio_map, 1061 ARRAY_SIZE(common31xx_cm_audio_map)); 1062 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT)) 1063 ret = snd_soc_dapm_add_routes(dapm, 1064 aic31xx_cm_audio_map, 1065 ARRAY_SIZE(aic31xx_cm_audio_map)); 1066 1067 if (ret) 1068 return ret; 1069 1070 aic31xx->master_dapm_route_applied = true; 1071 } 1072 1073 return 0; 1074 } 1075 1076 static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 1077 unsigned int fmt) 1078 { 1079 struct snd_soc_component *component = codec_dai->component; 1080 u8 iface_reg1 = 0; 1081 u8 iface_reg2 = 0; 1082 u8 dsp_a_val = 0; 1083 1084 dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt); 1085 1086 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1087 case SND_SOC_DAIFMT_CBP_CFP: 1088 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER; 1089 break; 1090 case SND_SOC_DAIFMT_CBC_CFP: 1091 iface_reg1 |= AIC31XX_WCLK_MASTER; 1092 break; 1093 case SND_SOC_DAIFMT_CBP_CFC: 1094 iface_reg1 |= AIC31XX_BCLK_MASTER; 1095 break; 1096 case SND_SOC_DAIFMT_CBC_CFC: 1097 break; 1098 default: 1099 dev_err(component->dev, "Invalid DAI clock provider\n"); 1100 return -EINVAL; 1101 } 1102 1103 /* signal polarity */ 1104 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1105 case SND_SOC_DAIFMT_NB_NF: 1106 break; 1107 case SND_SOC_DAIFMT_IB_NF: 1108 iface_reg2 |= AIC31XX_BCLKINV_MASK; 1109 break; 1110 default: 1111 dev_err(component->dev, "Invalid DAI clock signal polarity\n"); 1112 return -EINVAL; 1113 } 1114 1115 /* interface format */ 1116 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1117 case SND_SOC_DAIFMT_I2S: 1118 break; 1119 case SND_SOC_DAIFMT_DSP_A: 1120 dsp_a_val = 0x1; 1121 fallthrough; 1122 case SND_SOC_DAIFMT_DSP_B: 1123 /* 1124 * NOTE: This CODEC samples on the falling edge of BCLK in 1125 * DSP mode, this is inverted compared to what most DAIs 1126 * expect, so we invert for this mode 1127 */ 1128 iface_reg2 ^= AIC31XX_BCLKINV_MASK; 1129 iface_reg1 |= (AIC31XX_DSP_MODE << 1130 AIC31XX_IFACE1_DATATYPE_SHIFT); 1131 break; 1132 case SND_SOC_DAIFMT_RIGHT_J: 1133 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE << 1134 AIC31XX_IFACE1_DATATYPE_SHIFT); 1135 break; 1136 case SND_SOC_DAIFMT_LEFT_J: 1137 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE << 1138 AIC31XX_IFACE1_DATATYPE_SHIFT); 1139 break; 1140 default: 1141 dev_err(component->dev, "Invalid DAI interface format\n"); 1142 return -EINVAL; 1143 } 1144 1145 snd_soc_component_update_bits(component, AIC31XX_IFACE1, 1146 AIC31XX_IFACE1_DATATYPE_MASK | 1147 AIC31XX_IFACE1_MASTER_MASK, 1148 iface_reg1); 1149 snd_soc_component_update_bits(component, AIC31XX_DATA_OFFSET, 1150 AIC31XX_DATA_OFFSET_MASK, 1151 dsp_a_val); 1152 snd_soc_component_update_bits(component, AIC31XX_IFACE2, 1153 AIC31XX_BCLKINV_MASK, 1154 iface_reg2); 1155 1156 return aic31xx_clock_master_routes(component, fmt); 1157 } 1158 1159 static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1160 int clk_id, unsigned int freq, int dir) 1161 { 1162 struct snd_soc_component *component = codec_dai->component; 1163 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1164 int i; 1165 1166 dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n", 1167 __func__, clk_id, freq, dir); 1168 1169 for (i = 1; i < 8; i++) 1170 if (freq / i <= 20000000) 1171 break; 1172 if (freq/i > 20000000) { 1173 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n", 1174 __func__, freq); 1175 return -EINVAL; 1176 } 1177 aic31xx->p_div = i; 1178 1179 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) 1180 if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div) 1181 break; 1182 if (i == ARRAY_SIZE(aic31xx_divs)) { 1183 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n", 1184 __func__, freq); 1185 return -EINVAL; 1186 } 1187 1188 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */ 1189 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK, 1190 clk_id << AIC31XX_PLL_CLKIN_SHIFT); 1191 1192 aic31xx->sysclk_id = clk_id; 1193 aic31xx->sysclk = freq; 1194 1195 return 0; 1196 } 1197 1198 static int aic31xx_regulator_event(struct notifier_block *nb, 1199 unsigned long event, void *data) 1200 { 1201 struct aic31xx_disable_nb *disable_nb = 1202 container_of(nb, struct aic31xx_disable_nb, nb); 1203 struct aic31xx_priv *aic31xx = disable_nb->aic31xx; 1204 1205 if (event & REGULATOR_EVENT_DISABLE) { 1206 /* 1207 * Put codec to reset and as at least one of the 1208 * supplies was disabled. 1209 */ 1210 if (aic31xx->gpio_reset) 1211 gpiod_set_value(aic31xx->gpio_reset, 1); 1212 1213 regcache_mark_dirty(aic31xx->regmap); 1214 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__); 1215 } 1216 1217 return 0; 1218 } 1219 1220 static int aic31xx_reset(struct aic31xx_priv *aic31xx) 1221 { 1222 int ret = 0; 1223 1224 if (aic31xx->gpio_reset) { 1225 gpiod_set_value(aic31xx->gpio_reset, 1); 1226 ndelay(10); /* At least 10ns */ 1227 gpiod_set_value(aic31xx->gpio_reset, 0); 1228 } else { 1229 ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1); 1230 } 1231 mdelay(1); /* At least 1ms */ 1232 1233 return ret; 1234 } 1235 1236 static void aic31xx_clk_on(struct snd_soc_component *component) 1237 { 1238 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1239 u8 mask = AIC31XX_PM_MASK; 1240 u8 on = AIC31XX_PM_MASK; 1241 1242 dev_dbg(component->dev, "codec clock -> on (rate %d)\n", 1243 aic31xx_divs[aic31xx->rate_div_line].rate); 1244 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on); 1245 mdelay(10); 1246 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on); 1247 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on); 1248 if (aic31xx_divs[aic31xx->rate_div_line].nadc) 1249 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on); 1250 if (aic31xx_divs[aic31xx->rate_div_line].madc) 1251 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on); 1252 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on); 1253 } 1254 1255 static void aic31xx_clk_off(struct snd_soc_component *component) 1256 { 1257 u8 mask = AIC31XX_PM_MASK; 1258 u8 off = 0; 1259 1260 dev_dbg(component->dev, "codec clock -> off\n"); 1261 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off); 1262 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off); 1263 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off); 1264 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off); 1265 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off); 1266 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off); 1267 } 1268 1269 static int aic31xx_power_on(struct snd_soc_component *component) 1270 { 1271 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1272 int ret; 1273 1274 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies), 1275 aic31xx->supplies); 1276 if (ret) 1277 return ret; 1278 1279 regcache_cache_only(aic31xx->regmap, false); 1280 1281 /* Reset device registers for a consistent power-on like state */ 1282 ret = aic31xx_reset(aic31xx); 1283 if (ret < 0) 1284 dev_err(aic31xx->dev, "Could not reset device: %d\n", ret); 1285 1286 ret = regcache_sync(aic31xx->regmap); 1287 if (ret) { 1288 dev_err(component->dev, 1289 "Failed to restore cache: %d\n", ret); 1290 regcache_cache_only(aic31xx->regmap, true); 1291 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1292 aic31xx->supplies); 1293 return ret; 1294 } 1295 1296 /* 1297 * The jack detection configuration is in the same register 1298 * that is used to report jack detect status so is volatile 1299 * and not covered by the cache sync, restore it separately. 1300 */ 1301 aic31xx_set_jack(component, aic31xx->jack, NULL); 1302 1303 return 0; 1304 } 1305 1306 static void aic31xx_power_off(struct snd_soc_component *component) 1307 { 1308 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1309 1310 regcache_cache_only(aic31xx->regmap, true); 1311 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1312 aic31xx->supplies); 1313 } 1314 1315 static int aic31xx_set_bias_level(struct snd_soc_component *component, 1316 enum snd_soc_bias_level level) 1317 { 1318 dev_dbg(component->dev, "## %s: %d -> %d\n", __func__, 1319 snd_soc_component_get_bias_level(component), level); 1320 1321 switch (level) { 1322 case SND_SOC_BIAS_ON: 1323 break; 1324 case SND_SOC_BIAS_PREPARE: 1325 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 1326 aic31xx_clk_on(component); 1327 break; 1328 case SND_SOC_BIAS_STANDBY: 1329 switch (snd_soc_component_get_bias_level(component)) { 1330 case SND_SOC_BIAS_OFF: 1331 aic31xx_power_on(component); 1332 break; 1333 case SND_SOC_BIAS_PREPARE: 1334 aic31xx_clk_off(component); 1335 break; 1336 default: 1337 BUG(); 1338 } 1339 break; 1340 case SND_SOC_BIAS_OFF: 1341 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 1342 aic31xx_power_off(component); 1343 break; 1344 } 1345 1346 return 0; 1347 } 1348 1349 static int aic31xx_set_jack(struct snd_soc_component *component, 1350 struct snd_soc_jack *jack, void *data) 1351 { 1352 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1353 1354 aic31xx->jack = jack; 1355 1356 /* Enable/Disable jack detection */ 1357 regmap_write(aic31xx->regmap, AIC31XX_HSDETECT, 1358 jack ? AIC31XX_HSD_ENABLE : 0); 1359 1360 return 0; 1361 } 1362 1363 static int aic31xx_codec_probe(struct snd_soc_component *component) 1364 { 1365 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1366 int i, ret; 1367 1368 dev_dbg(aic31xx->dev, "## %s\n", __func__); 1369 1370 aic31xx->component = component; 1371 1372 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) { 1373 aic31xx->disable_nb[i].nb.notifier_call = 1374 aic31xx_regulator_event; 1375 aic31xx->disable_nb[i].aic31xx = aic31xx; 1376 ret = devm_regulator_register_notifier( 1377 aic31xx->supplies[i].consumer, 1378 &aic31xx->disable_nb[i].nb); 1379 if (ret) { 1380 dev_err(component->dev, 1381 "Failed to request regulator notifier: %d\n", 1382 ret); 1383 return ret; 1384 } 1385 } 1386 1387 regcache_cache_only(aic31xx->regmap, true); 1388 regcache_mark_dirty(aic31xx->regmap); 1389 1390 ret = aic31xx_add_controls(component); 1391 if (ret) 1392 return ret; 1393 1394 ret = aic31xx_add_widgets(component); 1395 if (ret) 1396 return ret; 1397 1398 /* set output common-mode voltage */ 1399 snd_soc_component_update_bits(component, AIC31XX_HPDRIVER, 1400 AIC31XX_HPD_OCMV_MASK, 1401 aic31xx->ocmv << AIC31XX_HPD_OCMV_SHIFT); 1402 1403 return 0; 1404 } 1405 1406 static const struct snd_soc_component_driver soc_codec_driver_aic31xx = { 1407 .probe = aic31xx_codec_probe, 1408 .set_jack = aic31xx_set_jack, 1409 .set_bias_level = aic31xx_set_bias_level, 1410 .controls = common31xx_snd_controls, 1411 .num_controls = ARRAY_SIZE(common31xx_snd_controls), 1412 .dapm_widgets = common31xx_dapm_widgets, 1413 .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets), 1414 .dapm_routes = common31xx_audio_map, 1415 .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map), 1416 .suspend_bias_off = 1, 1417 .idle_bias_on = 1, 1418 .use_pmdown_time = 1, 1419 .endianness = 1, 1420 }; 1421 1422 static const struct snd_soc_dai_ops aic31xx_dai_ops = { 1423 .hw_params = aic31xx_hw_params, 1424 .set_sysclk = aic31xx_set_dai_sysclk, 1425 .set_fmt = aic31xx_set_dai_fmt, 1426 .mute_stream = aic31xx_dac_mute, 1427 .no_capture_mute = 1, 1428 }; 1429 1430 static struct snd_soc_dai_driver dac31xx_dai_driver[] = { 1431 { 1432 .name = "tlv320dac31xx-hifi", 1433 .playback = { 1434 .stream_name = "Playback", 1435 .channels_min = 2, 1436 .channels_max = 2, 1437 .rates = AIC31XX_RATES, 1438 .formats = AIC31XX_FORMATS, 1439 }, 1440 .ops = &aic31xx_dai_ops, 1441 .symmetric_rate = 1, 1442 } 1443 }; 1444 1445 static struct snd_soc_dai_driver aic31xx_dai_driver[] = { 1446 { 1447 .name = "tlv320aic31xx-hifi", 1448 .playback = { 1449 .stream_name = "Playback", 1450 .channels_min = 2, 1451 .channels_max = 2, 1452 .rates = AIC31XX_RATES, 1453 .formats = AIC31XX_FORMATS, 1454 }, 1455 .capture = { 1456 .stream_name = "Capture", 1457 .channels_min = 2, 1458 .channels_max = 2, 1459 .rates = AIC31XX_RATES, 1460 .formats = AIC31XX_FORMATS, 1461 }, 1462 .ops = &aic31xx_dai_ops, 1463 .symmetric_rate = 1, 1464 } 1465 }; 1466 1467 #if defined(CONFIG_OF) 1468 static const struct of_device_id tlv320aic31xx_of_match[] = { 1469 { .compatible = "ti,tlv320aic310x" }, 1470 { .compatible = "ti,tlv320aic311x" }, 1471 { .compatible = "ti,tlv320aic3100" }, 1472 { .compatible = "ti,tlv320aic3110" }, 1473 { .compatible = "ti,tlv320aic3120" }, 1474 { .compatible = "ti,tlv320aic3111" }, 1475 { .compatible = "ti,tlv320dac3100" }, 1476 { .compatible = "ti,tlv320dac3101" }, 1477 {}, 1478 }; 1479 MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match); 1480 #endif /* CONFIG_OF */ 1481 1482 #ifdef CONFIG_ACPI 1483 static const struct acpi_device_id aic31xx_acpi_match[] = { 1484 { "10TI3100", 0 }, 1485 { } 1486 }; 1487 MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match); 1488 #endif 1489 1490 static irqreturn_t aic31xx_irq(int irq, void *data) 1491 { 1492 struct aic31xx_priv *aic31xx = data; 1493 struct device *dev = aic31xx->dev; 1494 unsigned int value; 1495 bool handled = false; 1496 int ret; 1497 1498 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG, &value); 1499 if (ret) { 1500 dev_err(dev, "Failed to read interrupt mask: %d\n", ret); 1501 goto exit; 1502 } 1503 1504 if (value) 1505 handled = true; 1506 else 1507 goto read_overflow; 1508 1509 if (value & AIC31XX_HPLSCDETECT) 1510 dev_err(dev, "Short circuit on Left output is detected\n"); 1511 if (value & AIC31XX_HPRSCDETECT) 1512 dev_err(dev, "Short circuit on Right output is detected\n"); 1513 if (value & (AIC31XX_HSPLUG | AIC31XX_BUTTONPRESS)) { 1514 unsigned int val; 1515 int status = 0; 1516 1517 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG2, 1518 &val); 1519 if (ret) { 1520 dev_err(dev, "Failed to read interrupt mask: %d\n", 1521 ret); 1522 goto exit; 1523 } 1524 1525 if (val & AIC31XX_BUTTONPRESS) 1526 status |= SND_JACK_BTN_0; 1527 1528 ret = regmap_read(aic31xx->regmap, AIC31XX_HSDETECT, &val); 1529 if (ret) { 1530 dev_err(dev, "Failed to read headset type: %d\n", ret); 1531 goto exit; 1532 } 1533 1534 switch ((val & AIC31XX_HSD_TYPE_MASK) >> 1535 AIC31XX_HSD_TYPE_SHIFT) { 1536 case AIC31XX_HSD_HP: 1537 status |= SND_JACK_HEADPHONE; 1538 break; 1539 case AIC31XX_HSD_HS: 1540 status |= SND_JACK_HEADSET; 1541 break; 1542 default: 1543 break; 1544 } 1545 1546 if (aic31xx->jack) 1547 snd_soc_jack_report(aic31xx->jack, status, 1548 AIC31XX_JACK_MASK); 1549 } 1550 if (value & ~(AIC31XX_HPLSCDETECT | 1551 AIC31XX_HPRSCDETECT | 1552 AIC31XX_HSPLUG | 1553 AIC31XX_BUTTONPRESS)) 1554 dev_err(dev, "Unknown DAC interrupt flags: 0x%08x\n", value); 1555 1556 read_overflow: 1557 ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value); 1558 if (ret) { 1559 dev_err(dev, "Failed to read overflow flag: %d\n", ret); 1560 goto exit; 1561 } 1562 1563 if (value) 1564 handled = true; 1565 else 1566 goto exit; 1567 1568 if (value & AIC31XX_DAC_OF_LEFT) 1569 dev_warn(dev, "Left-channel DAC overflow has occurred\n"); 1570 if (value & AIC31XX_DAC_OF_RIGHT) 1571 dev_warn(dev, "Right-channel DAC overflow has occurred\n"); 1572 if (value & AIC31XX_DAC_OF_SHIFTER) 1573 dev_warn(dev, "DAC barrel shifter overflow has occurred\n"); 1574 if (value & AIC31XX_ADC_OF) 1575 dev_warn(dev, "ADC overflow has occurred\n"); 1576 if (value & AIC31XX_ADC_OF_SHIFTER) 1577 dev_warn(dev, "ADC barrel shifter overflow has occurred\n"); 1578 if (value & ~(AIC31XX_DAC_OF_LEFT | 1579 AIC31XX_DAC_OF_RIGHT | 1580 AIC31XX_DAC_OF_SHIFTER | 1581 AIC31XX_ADC_OF | 1582 AIC31XX_ADC_OF_SHIFTER)) 1583 dev_warn(dev, "Unknown overflow interrupt flags: 0x%08x\n", value); 1584 1585 exit: 1586 if (handled) 1587 return IRQ_HANDLED; 1588 else 1589 return IRQ_NONE; 1590 } 1591 1592 static void aic31xx_configure_ocmv(struct aic31xx_priv *priv) 1593 { 1594 struct device *dev = priv->dev; 1595 int dvdd, avdd; 1596 u32 value; 1597 1598 if (dev->fwnode && 1599 fwnode_property_read_u32(dev->fwnode, "ai31xx-ocmv", &value)) { 1600 /* OCMV setting is forced by DT */ 1601 if (value <= 3) { 1602 priv->ocmv = value; 1603 return; 1604 } 1605 } 1606 1607 avdd = regulator_get_voltage(priv->supplies[3].consumer); 1608 dvdd = regulator_get_voltage(priv->supplies[5].consumer); 1609 1610 if (avdd > 3600000 || dvdd > 1950000) { 1611 dev_warn(dev, 1612 "Too high supply voltage(s) AVDD: %d, DVDD: %d\n", 1613 avdd, dvdd); 1614 } else if (avdd == 3600000 && dvdd == 1950000) { 1615 priv->ocmv = AIC31XX_HPD_OCMV_1_8V; 1616 } else if (avdd >= 3300000 && dvdd >= 1800000) { 1617 priv->ocmv = AIC31XX_HPD_OCMV_1_65V; 1618 } else if (avdd >= 3000000 && dvdd >= 1650000) { 1619 priv->ocmv = AIC31XX_HPD_OCMV_1_5V; 1620 } else if (avdd >= 2700000 && dvdd >= 1525000) { 1621 priv->ocmv = AIC31XX_HPD_OCMV_1_35V; 1622 } else { 1623 dev_warn(dev, 1624 "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n", 1625 avdd, dvdd); 1626 } 1627 } 1628 1629 static const struct i2c_device_id aic31xx_i2c_id[] = { 1630 { "tlv320aic310x", AIC3100 }, 1631 { "tlv320aic311x", AIC3110 }, 1632 { "tlv320aic3100", AIC3100 }, 1633 { "tlv320aic3110", AIC3110 }, 1634 { "tlv320aic3120", AIC3120 }, 1635 { "tlv320aic3111", AIC3111 }, 1636 { "tlv320dac3100", DAC3100 }, 1637 { "tlv320dac3101", DAC3101 }, 1638 { } 1639 }; 1640 MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id); 1641 1642 static int aic31xx_i2c_probe(struct i2c_client *i2c) 1643 { 1644 struct aic31xx_priv *aic31xx; 1645 unsigned int micbias_value = MICBIAS_2_0V; 1646 const struct i2c_device_id *id = i2c_match_id(aic31xx_i2c_id, i2c); 1647 int i, ret; 1648 1649 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__, 1650 id->name, (int)id->driver_data); 1651 1652 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL); 1653 if (!aic31xx) 1654 return -ENOMEM; 1655 1656 aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap); 1657 if (IS_ERR(aic31xx->regmap)) { 1658 ret = PTR_ERR(aic31xx->regmap); 1659 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1660 ret); 1661 return ret; 1662 } 1663 regcache_cache_only(aic31xx->regmap, true); 1664 1665 aic31xx->dev = &i2c->dev; 1666 aic31xx->irq = i2c->irq; 1667 1668 aic31xx->codec_type = id->driver_data; 1669 1670 dev_set_drvdata(aic31xx->dev, aic31xx); 1671 1672 fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg", 1673 &micbias_value); 1674 switch (micbias_value) { 1675 case MICBIAS_2_0V: 1676 case MICBIAS_2_5V: 1677 case MICBIAS_AVDDV: 1678 aic31xx->micbias_vg = micbias_value; 1679 break; 1680 default: 1681 dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n", 1682 micbias_value); 1683 aic31xx->micbias_vg = MICBIAS_2_0V; 1684 } 1685 1686 if (dev_get_platdata(aic31xx->dev)) { 1687 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata)); 1688 aic31xx->codec_type = aic31xx->pdata.codec_type; 1689 aic31xx->micbias_vg = aic31xx->pdata.micbias_vg; 1690 } 1691 1692 aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset", 1693 GPIOD_OUT_LOW); 1694 if (IS_ERR(aic31xx->gpio_reset)) 1695 return dev_err_probe(aic31xx->dev, PTR_ERR(aic31xx->gpio_reset), 1696 "not able to acquire gpio\n"); 1697 1698 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) 1699 aic31xx->supplies[i].supply = aic31xx_supply_names[i]; 1700 1701 ret = devm_regulator_bulk_get(aic31xx->dev, 1702 ARRAY_SIZE(aic31xx->supplies), 1703 aic31xx->supplies); 1704 if (ret) 1705 return dev_err_probe(aic31xx->dev, ret, "Failed to request supplies\n"); 1706 1707 aic31xx_configure_ocmv(aic31xx); 1708 1709 if (aic31xx->irq > 0) { 1710 regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1, 1711 AIC31XX_GPIO1_FUNC_MASK, 1712 AIC31XX_GPIO1_INT1 << 1713 AIC31XX_GPIO1_FUNC_SHIFT); 1714 1715 regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL, 1716 AIC31XX_HSPLUGDET | 1717 AIC31XX_BUTTONPRESSDET | 1718 AIC31XX_SC | 1719 AIC31XX_ENGINE); 1720 1721 ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq, 1722 NULL, aic31xx_irq, 1723 IRQF_ONESHOT, "aic31xx-irq", 1724 aic31xx); 1725 if (ret) { 1726 dev_err(aic31xx->dev, "Unable to request IRQ\n"); 1727 return ret; 1728 } 1729 } 1730 1731 if (aic31xx->codec_type & DAC31XX_BIT) 1732 return devm_snd_soc_register_component(&i2c->dev, 1733 &soc_codec_driver_aic31xx, 1734 dac31xx_dai_driver, 1735 ARRAY_SIZE(dac31xx_dai_driver)); 1736 else 1737 return devm_snd_soc_register_component(&i2c->dev, 1738 &soc_codec_driver_aic31xx, 1739 aic31xx_dai_driver, 1740 ARRAY_SIZE(aic31xx_dai_driver)); 1741 } 1742 1743 static struct i2c_driver aic31xx_i2c_driver = { 1744 .driver = { 1745 .name = "tlv320aic31xx-codec", 1746 .of_match_table = of_match_ptr(tlv320aic31xx_of_match), 1747 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match), 1748 }, 1749 .probe_new = aic31xx_i2c_probe, 1750 .id_table = aic31xx_i2c_id, 1751 }; 1752 module_i2c_driver(aic31xx_i2c_driver); 1753 1754 MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>"); 1755 MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver"); 1756 MODULE_LICENSE("GPL v2"); 1757