1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ALSA SoC TLV320AIC31xx CODEC Driver 4 * 5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/ 6 * Jyri Sarha <jsarha@ti.com> 7 * 8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com> 9 * 10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated 11 * high performance codecs which provides a stereo DAC, a mono ADC, 12 * and mono/stereo Class-D speaker driver. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/init.h> 18 #include <linux/delay.h> 19 #include <linux/pm.h> 20 #include <linux/i2c.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/acpi.h> 24 #include <linux/of.h> 25 #include <linux/of_gpio.h> 26 #include <linux/slab.h> 27 #include <sound/core.h> 28 #include <sound/jack.h> 29 #include <sound/pcm.h> 30 #include <sound/pcm_params.h> 31 #include <sound/soc.h> 32 #include <sound/initval.h> 33 #include <sound/tlv.h> 34 #include <dt-bindings/sound/tlv320aic31xx-micbias.h> 35 36 #include "tlv320aic31xx.h" 37 38 static const struct reg_default aic31xx_reg_defaults[] = { 39 { AIC31XX_CLKMUX, 0x00 }, 40 { AIC31XX_PLLPR, 0x11 }, 41 { AIC31XX_PLLJ, 0x04 }, 42 { AIC31XX_PLLDMSB, 0x00 }, 43 { AIC31XX_PLLDLSB, 0x00 }, 44 { AIC31XX_NDAC, 0x01 }, 45 { AIC31XX_MDAC, 0x01 }, 46 { AIC31XX_DOSRMSB, 0x00 }, 47 { AIC31XX_DOSRLSB, 0x80 }, 48 { AIC31XX_NADC, 0x01 }, 49 { AIC31XX_MADC, 0x01 }, 50 { AIC31XX_AOSR, 0x80 }, 51 { AIC31XX_IFACE1, 0x00 }, 52 { AIC31XX_DATA_OFFSET, 0x00 }, 53 { AIC31XX_IFACE2, 0x00 }, 54 { AIC31XX_BCLKN, 0x01 }, 55 { AIC31XX_DACSETUP, 0x14 }, 56 { AIC31XX_DACMUTE, 0x0c }, 57 { AIC31XX_LDACVOL, 0x00 }, 58 { AIC31XX_RDACVOL, 0x00 }, 59 { AIC31XX_ADCSETUP, 0x00 }, 60 { AIC31XX_ADCFGA, 0x80 }, 61 { AIC31XX_ADCVOL, 0x00 }, 62 { AIC31XX_HPDRIVER, 0x04 }, 63 { AIC31XX_SPKAMP, 0x06 }, 64 { AIC31XX_DACMIXERROUTE, 0x00 }, 65 { AIC31XX_LANALOGHPL, 0x7f }, 66 { AIC31XX_RANALOGHPR, 0x7f }, 67 { AIC31XX_LANALOGSPL, 0x7f }, 68 { AIC31XX_RANALOGSPR, 0x7f }, 69 { AIC31XX_HPLGAIN, 0x02 }, 70 { AIC31XX_HPRGAIN, 0x02 }, 71 { AIC31XX_SPLGAIN, 0x00 }, 72 { AIC31XX_SPRGAIN, 0x00 }, 73 { AIC31XX_MICBIAS, 0x00 }, 74 { AIC31XX_MICPGA, 0x80 }, 75 { AIC31XX_MICPGAPI, 0x00 }, 76 { AIC31XX_MICPGAMI, 0x00 }, 77 }; 78 79 static bool aic31xx_volatile(struct device *dev, unsigned int reg) 80 { 81 switch (reg) { 82 case AIC31XX_PAGECTL: /* regmap implementation requires this */ 83 case AIC31XX_RESET: /* always clears after write */ 84 case AIC31XX_OT_FLAG: 85 case AIC31XX_ADCFLAG: 86 case AIC31XX_DACFLAG1: 87 case AIC31XX_DACFLAG2: 88 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 89 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 90 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 91 case AIC31XX_INTRDACFLAG2: 92 case AIC31XX_INTRADCFLAG2: 93 case AIC31XX_HSDETECT: 94 return true; 95 } 96 return false; 97 } 98 99 static bool aic31xx_writeable(struct device *dev, unsigned int reg) 100 { 101 switch (reg) { 102 case AIC31XX_OT_FLAG: 103 case AIC31XX_ADCFLAG: 104 case AIC31XX_DACFLAG1: 105 case AIC31XX_DACFLAG2: 106 case AIC31XX_OFFLAG: /* Sticky interrupt flags */ 107 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */ 108 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */ 109 case AIC31XX_INTRDACFLAG2: 110 case AIC31XX_INTRADCFLAG2: 111 return false; 112 } 113 return true; 114 } 115 116 static const struct regmap_range_cfg aic31xx_ranges[] = { 117 { 118 .range_min = 0, 119 .range_max = 12 * 128, 120 .selector_reg = AIC31XX_PAGECTL, 121 .selector_mask = 0xff, 122 .selector_shift = 0, 123 .window_start = 0, 124 .window_len = 128, 125 }, 126 }; 127 128 static const struct regmap_config aic31xx_i2c_regmap = { 129 .reg_bits = 8, 130 .val_bits = 8, 131 .writeable_reg = aic31xx_writeable, 132 .volatile_reg = aic31xx_volatile, 133 .reg_defaults = aic31xx_reg_defaults, 134 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults), 135 .cache_type = REGCACHE_RBTREE, 136 .ranges = aic31xx_ranges, 137 .num_ranges = ARRAY_SIZE(aic31xx_ranges), 138 .max_register = 12 * 128, 139 }; 140 141 static const char * const aic31xx_supply_names[] = { 142 "HPVDD", 143 "SPRVDD", 144 "SPLVDD", 145 "AVDD", 146 "IOVDD", 147 "DVDD", 148 }; 149 150 #define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names) 151 152 struct aic31xx_disable_nb { 153 struct notifier_block nb; 154 struct aic31xx_priv *aic31xx; 155 }; 156 157 struct aic31xx_priv { 158 struct snd_soc_component *component; 159 u8 i2c_regs_status; 160 struct device *dev; 161 struct regmap *regmap; 162 enum aic31xx_type codec_type; 163 struct gpio_desc *gpio_reset; 164 int micbias_vg; 165 struct aic31xx_pdata pdata; 166 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES]; 167 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES]; 168 struct snd_soc_jack *jack; 169 unsigned int sysclk; 170 u8 p_div; 171 int rate_div_line; 172 bool master_dapm_route_applied; 173 int irq; 174 u8 ocmv; /* output common-mode voltage */ 175 }; 176 177 struct aic31xx_rate_divs { 178 u32 mclk_p; 179 u32 rate; 180 u8 pll_j; 181 u16 pll_d; 182 u16 dosr; 183 u8 ndac; 184 u8 mdac; 185 u8 aosr; 186 u8 nadc; 187 u8 madc; 188 }; 189 190 /* ADC dividers can be disabled by configuring them to 0 */ 191 static const struct aic31xx_rate_divs aic31xx_divs[] = { 192 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */ 193 /* 8k rate */ 194 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2}, 195 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3}, 196 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2}, 197 /* 11.025k rate */ 198 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2}, 199 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3}, 200 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2}, 201 /* 16k rate */ 202 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2}, 203 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3}, 204 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2}, 205 /* 22.05k rate */ 206 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2}, 207 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3}, 208 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2}, 209 /* 32k rate */ 210 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2}, 211 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3}, 212 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2}, 213 /* 44.1k rate */ 214 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2}, 215 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3}, 216 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2}, 217 /* 48k rate */ 218 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2}, 219 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4}, 220 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2}, 221 /* 88.2k rate */ 222 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2}, 223 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3}, 224 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2}, 225 /* 96k rate */ 226 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2}, 227 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4}, 228 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2}, 229 /* 176.4k rate */ 230 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2}, 231 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3}, 232 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2}, 233 /* 192k rate */ 234 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2}, 235 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4}, 236 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2}, 237 }; 238 239 static const char * const ldac_in_text[] = { 240 "Off", "Left Data", "Right Data", "Mono" 241 }; 242 243 static const char * const rdac_in_text[] = { 244 "Off", "Right Data", "Left Data", "Mono" 245 }; 246 247 static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text); 248 249 static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text); 250 251 static const char * const mic_select_text[] = { 252 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm" 253 }; 254 255 static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6, 256 mic_select_text); 257 static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4, 258 mic_select_text); 259 static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2, 260 mic_select_text); 261 262 static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4, 263 mic_select_text); 264 265 static const char * const hp_poweron_time_text[] = { 266 "0us", "15.3us", "153us", "1.53ms", "15.3ms", "76.2ms", 267 "153ms", "304ms", "610ms", "1.22s", "3.04s", "6.1s" }; 268 269 static SOC_ENUM_SINGLE_DECL(hp_poweron_time_enum, AIC31XX_HPPOP, 3, 270 hp_poweron_time_text); 271 272 static const char * const hp_rampup_step_text[] = { 273 "0ms", "0.98ms", "1.95ms", "3.9ms" }; 274 275 static SOC_ENUM_SINGLE_DECL(hp_rampup_step_enum, AIC31XX_HPPOP, 1, 276 hp_rampup_step_text); 277 278 static const char * const vol_soft_step_mode_text[] = { 279 "fast", "slow", "disabled" }; 280 281 static SOC_ENUM_SINGLE_DECL(vol_soft_step_mode_enum, AIC31XX_DACSETUP, 0, 282 vol_soft_step_mode_text); 283 284 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0); 285 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0); 286 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0); 287 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0); 288 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0); 289 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0); 290 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0); 291 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0); 292 293 /* 294 * controls to be exported to the user space 295 */ 296 static const struct snd_kcontrol_new common31xx_snd_controls[] = { 297 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL, 298 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv), 299 300 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN, 301 AIC31XX_HPRGAIN, 2, 1, 0), 302 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN, 303 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv), 304 305 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL, 306 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv), 307 308 /* HP de-pop control: apply power not immediately but via ramp 309 * function with these psarameters. Note that power up sequence 310 * has to wait for this to complete; this is implemented by 311 * polling HP driver status in aic31xx_dapm_power_event() 312 */ 313 SOC_ENUM("HP Output Driver Power-On time", hp_poweron_time_enum), 314 SOC_ENUM("HP Output Driver Ramp-up step", hp_rampup_step_enum), 315 316 SOC_ENUM("Volume Soft Stepping", vol_soft_step_mode_enum), 317 }; 318 319 static const struct snd_kcontrol_new aic31xx_snd_controls[] = { 320 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1, 321 adc_fgain_tlv), 322 323 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1), 324 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL, 325 0, -24, 40, 6, 0, adc_cgain_tlv), 326 327 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0, 328 119, 0, mic_pga_tlv), 329 }; 330 331 static const struct snd_kcontrol_new aic311x_snd_controls[] = { 332 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 333 AIC31XX_SPRGAIN, 2, 1, 0), 334 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 335 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv), 336 337 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 338 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv), 339 }; 340 341 static const struct snd_kcontrol_new aic310x_snd_controls[] = { 342 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN, 343 2, 1, 0), 344 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN, 345 3, 3, 0, class_D_drv_tlv), 346 347 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL, 348 0, 0x7F, 1, sp_vol_tlv), 349 }; 350 351 static const struct snd_kcontrol_new ldac_in_control = 352 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum); 353 354 static const struct snd_kcontrol_new rdac_in_control = 355 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum); 356 357 static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg, 358 unsigned int mask, unsigned int wbits, int sleep, 359 int count) 360 { 361 unsigned int bits; 362 int counter = count; 363 int ret = regmap_read(aic31xx->regmap, reg, &bits); 364 365 while ((bits & mask) != wbits && counter && !ret) { 366 usleep_range(sleep, sleep * 2); 367 ret = regmap_read(aic31xx->regmap, reg, &bits); 368 counter--; 369 } 370 if ((bits & mask) != wbits) { 371 dev_err(aic31xx->dev, 372 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n", 373 __func__, reg, bits, wbits, ret, mask, 374 (count - counter) * sleep); 375 ret = -1; 376 } 377 return ret; 378 } 379 380 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg)) 381 382 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w, 383 struct snd_kcontrol *kcontrol, int event) 384 { 385 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 386 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 387 unsigned int reg = AIC31XX_DACFLAG1; 388 unsigned int mask; 389 unsigned int timeout = 500 * USEC_PER_MSEC; 390 391 switch (WIDGET_BIT(w->reg, w->shift)) { 392 case WIDGET_BIT(AIC31XX_DACSETUP, 7): 393 mask = AIC31XX_LDACPWRSTATUS_MASK; 394 break; 395 case WIDGET_BIT(AIC31XX_DACSETUP, 6): 396 mask = AIC31XX_RDACPWRSTATUS_MASK; 397 break; 398 case WIDGET_BIT(AIC31XX_HPDRIVER, 7): 399 mask = AIC31XX_HPLDRVPWRSTATUS_MASK; 400 if (event == SND_SOC_DAPM_POST_PMU) 401 timeout = 7 * USEC_PER_SEC; 402 break; 403 case WIDGET_BIT(AIC31XX_HPDRIVER, 6): 404 mask = AIC31XX_HPRDRVPWRSTATUS_MASK; 405 if (event == SND_SOC_DAPM_POST_PMU) 406 timeout = 7 * USEC_PER_SEC; 407 break; 408 case WIDGET_BIT(AIC31XX_SPKAMP, 7): 409 mask = AIC31XX_SPLDRVPWRSTATUS_MASK; 410 break; 411 case WIDGET_BIT(AIC31XX_SPKAMP, 6): 412 mask = AIC31XX_SPRDRVPWRSTATUS_MASK; 413 break; 414 case WIDGET_BIT(AIC31XX_ADCSETUP, 7): 415 mask = AIC31XX_ADCPWRSTATUS_MASK; 416 reg = AIC31XX_ADCFLAG; 417 break; 418 default: 419 dev_err(component->dev, "Unknown widget '%s' calling %s\n", 420 w->name, __func__); 421 return -EINVAL; 422 } 423 424 switch (event) { 425 case SND_SOC_DAPM_POST_PMU: 426 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 427 5000, timeout / 5000); 428 case SND_SOC_DAPM_POST_PMD: 429 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 430 5000, timeout / 5000); 431 default: 432 dev_dbg(component->dev, 433 "Unhandled dapm widget event %d from %s\n", 434 event, w->name); 435 } 436 return 0; 437 } 438 439 static const struct snd_kcontrol_new aic31xx_left_output_switches[] = { 440 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 441 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0), 442 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0), 443 }; 444 445 static const struct snd_kcontrol_new aic31xx_right_output_switches[] = { 446 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 447 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0), 448 }; 449 450 static const struct snd_kcontrol_new dac31xx_left_output_switches[] = { 451 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0), 452 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0), 453 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0), 454 }; 455 456 static const struct snd_kcontrol_new dac31xx_right_output_switches[] = { 457 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0), 458 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0), 459 }; 460 461 static const struct snd_kcontrol_new p_term_mic1lp = 462 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum); 463 464 static const struct snd_kcontrol_new p_term_mic1rp = 465 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum); 466 467 static const struct snd_kcontrol_new p_term_mic1lm = 468 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum); 469 470 static const struct snd_kcontrol_new m_term_mic1lm = 471 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum); 472 473 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch = 474 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0); 475 476 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch = 477 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0); 478 479 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch = 480 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0); 481 482 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch = 483 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0); 484 485 static int mic_bias_event(struct snd_soc_dapm_widget *w, 486 struct snd_kcontrol *kcontrol, int event) 487 { 488 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 489 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 490 491 switch (event) { 492 case SND_SOC_DAPM_POST_PMU: 493 /* change mic bias voltage to user defined */ 494 snd_soc_component_update_bits(component, AIC31XX_MICBIAS, 495 AIC31XX_MICBIAS_MASK, 496 aic31xx->micbias_vg << 497 AIC31XX_MICBIAS_SHIFT); 498 dev_dbg(component->dev, "%s: turned on\n", __func__); 499 break; 500 case SND_SOC_DAPM_PRE_PMD: 501 /* turn mic bias off */ 502 snd_soc_component_update_bits(component, AIC31XX_MICBIAS, 503 AIC31XX_MICBIAS_MASK, 0); 504 dev_dbg(component->dev, "%s: turned off\n", __func__); 505 break; 506 } 507 return 0; 508 } 509 510 static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = { 511 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0), 512 513 SND_SOC_DAPM_MUX("DAC Left Input", 514 SND_SOC_NOPM, 0, 0, &ldac_in_control), 515 SND_SOC_DAPM_MUX("DAC Right Input", 516 SND_SOC_NOPM, 0, 0, &rdac_in_control), 517 /* DACs */ 518 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback", 519 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event, 520 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 521 522 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback", 523 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event, 524 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 525 526 /* HP */ 527 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0, 528 &aic31xx_dapm_hpl_switch), 529 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0, 530 &aic31xx_dapm_hpr_switch), 531 532 /* Output drivers */ 533 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0, 534 NULL, 0, aic31xx_dapm_power_event, 535 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 536 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0, 537 NULL, 0, aic31xx_dapm_power_event, 538 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU), 539 540 /* Mic Bias */ 541 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event, 542 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 543 544 /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */ 545 SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0, 546 NULL, 0), 547 548 /* Outputs */ 549 SND_SOC_DAPM_OUTPUT("HPL"), 550 SND_SOC_DAPM_OUTPUT("HPR"), 551 }; 552 553 static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = { 554 /* Inputs */ 555 SND_SOC_DAPM_INPUT("AIN1"), 556 SND_SOC_DAPM_INPUT("AIN2"), 557 558 /* Output Mixers */ 559 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 560 dac31xx_left_output_switches, 561 ARRAY_SIZE(dac31xx_left_output_switches)), 562 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 563 dac31xx_right_output_switches, 564 ARRAY_SIZE(dac31xx_right_output_switches)), 565 }; 566 567 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = { 568 /* Inputs */ 569 SND_SOC_DAPM_INPUT("MIC1LP"), 570 SND_SOC_DAPM_INPUT("MIC1RP"), 571 SND_SOC_DAPM_INPUT("MIC1LM"), 572 573 /* Input Selection to MIC_PGA */ 574 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0, 575 &p_term_mic1lp), 576 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0, 577 &p_term_mic1rp), 578 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0, 579 &p_term_mic1lm), 580 581 /* ADC */ 582 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0, 583 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 584 SND_SOC_DAPM_POST_PMD), 585 586 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0, 587 &m_term_mic1lm), 588 589 /* Enabling & Disabling MIC Gain Ctl */ 590 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA, 591 7, 1, NULL, 0), 592 593 /* Output Mixers */ 594 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0, 595 aic31xx_left_output_switches, 596 ARRAY_SIZE(aic31xx_left_output_switches)), 597 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0, 598 aic31xx_right_output_switches, 599 ARRAY_SIZE(aic31xx_right_output_switches)), 600 601 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 602 }; 603 604 static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = { 605 /* AIC3111 and AIC3110 have stereo class-D amplifier */ 606 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 607 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 608 SND_SOC_DAPM_POST_PMD), 609 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0, 610 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 611 SND_SOC_DAPM_POST_PMD), 612 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0, 613 &aic31xx_dapm_spl_switch), 614 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0, 615 &aic31xx_dapm_spr_switch), 616 SND_SOC_DAPM_OUTPUT("SPL"), 617 SND_SOC_DAPM_OUTPUT("SPR"), 618 }; 619 620 /* AIC3100 and AIC3120 have only mono class-D amplifier */ 621 static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = { 622 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0, 623 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU | 624 SND_SOC_DAPM_POST_PMD), 625 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0, 626 &aic31xx_dapm_spl_switch), 627 SND_SOC_DAPM_OUTPUT("SPK"), 628 }; 629 630 static const struct snd_soc_dapm_route 631 common31xx_audio_map[] = { 632 /* DAC Input Routing */ 633 {"DAC Left Input", "Left Data", "AIF IN"}, 634 {"DAC Left Input", "Right Data", "AIF IN"}, 635 {"DAC Left Input", "Mono", "AIF IN"}, 636 {"DAC Right Input", "Left Data", "AIF IN"}, 637 {"DAC Right Input", "Right Data", "AIF IN"}, 638 {"DAC Right Input", "Mono", "AIF IN"}, 639 {"DAC Left", NULL, "DAC Left Input"}, 640 {"DAC Right", NULL, "DAC Right Input"}, 641 642 /* HPL path */ 643 {"HP Left", "Switch", "Output Left"}, 644 {"HPL Driver", NULL, "HP Left"}, 645 {"HPL", NULL, "HPL Driver"}, 646 647 /* HPR path */ 648 {"HP Right", "Switch", "Output Right"}, 649 {"HPR Driver", NULL, "HP Right"}, 650 {"HPR", NULL, "HPR Driver"}, 651 }; 652 653 static const struct snd_soc_dapm_route 654 dac31xx_audio_map[] = { 655 /* Left Output */ 656 {"Output Left", "From Left DAC", "DAC Left"}, 657 {"Output Left", "From AIN1", "AIN1"}, 658 {"Output Left", "From AIN2", "AIN2"}, 659 660 /* Right Output */ 661 {"Output Right", "From Right DAC", "DAC Right"}, 662 {"Output Right", "From AIN2", "AIN2"}, 663 }; 664 665 static const struct snd_soc_dapm_route 666 aic31xx_audio_map[] = { 667 /* Mic input */ 668 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"}, 669 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"}, 670 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"}, 671 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"}, 672 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"}, 673 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"}, 674 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"}, 675 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"}, 676 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"}, 677 678 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"}, 679 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"}, 680 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"}, 681 682 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"}, 683 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"}, 684 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"}, 685 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"}, 686 687 {"ADC", NULL, "MIC_GAIN_CTL"}, 688 689 {"AIF OUT", NULL, "ADC"}, 690 691 /* Left Output */ 692 {"Output Left", "From Left DAC", "DAC Left"}, 693 {"Output Left", "From MIC1LP", "MIC1LP"}, 694 {"Output Left", "From MIC1RP", "MIC1RP"}, 695 696 /* Right Output */ 697 {"Output Right", "From Right DAC", "DAC Right"}, 698 {"Output Right", "From MIC1RP", "MIC1RP"}, 699 }; 700 701 static const struct snd_soc_dapm_route 702 aic311x_audio_map[] = { 703 /* SP L path */ 704 {"Speaker Left", "Switch", "Output Left"}, 705 {"SPL ClassD", NULL, "Speaker Left"}, 706 {"SPL", NULL, "SPL ClassD"}, 707 708 /* SP R path */ 709 {"Speaker Right", "Switch", "Output Right"}, 710 {"SPR ClassD", NULL, "Speaker Right"}, 711 {"SPR", NULL, "SPR ClassD"}, 712 }; 713 714 static const struct snd_soc_dapm_route 715 aic310x_audio_map[] = { 716 /* SP L path */ 717 {"Speaker", "Switch", "Output Left"}, 718 {"SPK ClassD", NULL, "Speaker"}, 719 {"SPK", NULL, "SPK ClassD"}, 720 }; 721 722 /* 723 * Always connected DAPM routes for codec clock master modes. 724 * If the codec is the master on the I2S bus, we need to power up components 725 * to have valid DAC_CLK. 726 * 727 * In order to have the I2S clocks on the bus either the DACs/ADC need to be 728 * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set. 729 * 730 * Otherwise the codec will not generate clocks on the bus. 731 */ 732 static const struct snd_soc_dapm_route 733 common31xx_cm_audio_map[] = { 734 {"HPL", NULL, "AIF IN"}, 735 {"HPR", NULL, "AIF IN"}, 736 737 {"AIF IN", NULL, "Activate I2S clocks"}, 738 }; 739 740 static const struct snd_soc_dapm_route 741 aic31xx_cm_audio_map[] = { 742 {"AIF OUT", NULL, "MIC1LP"}, 743 {"AIF OUT", NULL, "MIC1RP"}, 744 {"AIF OUT", NULL, "MIC1LM"}, 745 746 {"AIF OUT", NULL, "Activate I2S clocks"}, 747 }; 748 749 static int aic31xx_add_controls(struct snd_soc_component *component) 750 { 751 int ret = 0; 752 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 753 754 if (!(aic31xx->codec_type & DAC31XX_BIT)) 755 ret = snd_soc_add_component_controls( 756 component, aic31xx_snd_controls, 757 ARRAY_SIZE(aic31xx_snd_controls)); 758 if (ret) 759 return ret; 760 761 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) 762 ret = snd_soc_add_component_controls( 763 component, aic311x_snd_controls, 764 ARRAY_SIZE(aic311x_snd_controls)); 765 else 766 ret = snd_soc_add_component_controls( 767 component, aic310x_snd_controls, 768 ARRAY_SIZE(aic310x_snd_controls)); 769 770 return ret; 771 } 772 773 static int aic31xx_add_widgets(struct snd_soc_component *component) 774 { 775 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 776 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 777 int ret = 0; 778 779 if (aic31xx->codec_type & DAC31XX_BIT) { 780 ret = snd_soc_dapm_new_controls( 781 dapm, dac31xx_dapm_widgets, 782 ARRAY_SIZE(dac31xx_dapm_widgets)); 783 if (ret) 784 return ret; 785 786 ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map, 787 ARRAY_SIZE(dac31xx_audio_map)); 788 if (ret) 789 return ret; 790 } else { 791 ret = snd_soc_dapm_new_controls( 792 dapm, aic31xx_dapm_widgets, 793 ARRAY_SIZE(aic31xx_dapm_widgets)); 794 if (ret) 795 return ret; 796 797 ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map, 798 ARRAY_SIZE(aic31xx_audio_map)); 799 if (ret) 800 return ret; 801 } 802 803 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) { 804 ret = snd_soc_dapm_new_controls( 805 dapm, aic311x_dapm_widgets, 806 ARRAY_SIZE(aic311x_dapm_widgets)); 807 if (ret) 808 return ret; 809 810 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map, 811 ARRAY_SIZE(aic311x_audio_map)); 812 if (ret) 813 return ret; 814 } else { 815 ret = snd_soc_dapm_new_controls( 816 dapm, aic310x_dapm_widgets, 817 ARRAY_SIZE(aic310x_dapm_widgets)); 818 if (ret) 819 return ret; 820 821 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map, 822 ARRAY_SIZE(aic310x_audio_map)); 823 if (ret) 824 return ret; 825 } 826 827 return 0; 828 } 829 830 static int aic31xx_setup_pll(struct snd_soc_component *component, 831 struct snd_pcm_hw_params *params) 832 { 833 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 834 int bclk_score = snd_soc_params_to_frame_size(params); 835 int mclk_p; 836 int bclk_n = 0; 837 int match = -1; 838 int i; 839 840 if (!aic31xx->sysclk || !aic31xx->p_div) { 841 dev_err(component->dev, "Master clock not supplied\n"); 842 return -EINVAL; 843 } 844 mclk_p = aic31xx->sysclk / aic31xx->p_div; 845 846 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */ 847 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, 848 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL); 849 snd_soc_component_update_bits(component, AIC31XX_IFACE2, 850 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK); 851 852 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) { 853 if (aic31xx_divs[i].rate == params_rate(params) && 854 aic31xx_divs[i].mclk_p == mclk_p) { 855 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) % 856 snd_soc_params_to_frame_size(params); 857 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) / 858 snd_soc_params_to_frame_size(params); 859 if (s < bclk_score && bn > 0) { 860 match = i; 861 bclk_n = bn; 862 bclk_score = s; 863 } 864 } 865 } 866 867 if (match == -1) { 868 dev_err(component->dev, 869 "%s: Sample rate (%u) and format not supported\n", 870 __func__, params_rate(params)); 871 /* See bellow for details how fix this. */ 872 return -EINVAL; 873 } 874 if (bclk_score != 0) { 875 dev_warn(component->dev, "Can not produce exact bitclock"); 876 /* This is fine if using dsp format, but if using i2s 877 there may be trouble. To fix the issue edit the 878 aic31xx_divs table for your mclk and sample 879 rate. Details can be found from: 880 https://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf 881 Section: 5.6 CLOCK Generation and PLL 882 */ 883 } 884 i = match; 885 886 /* PLL configuration */ 887 snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK, 888 (aic31xx->p_div << 4) | 0x01); 889 snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j); 890 891 snd_soc_component_write(component, AIC31XX_PLLDMSB, 892 aic31xx_divs[i].pll_d >> 8); 893 snd_soc_component_write(component, AIC31XX_PLLDLSB, 894 aic31xx_divs[i].pll_d & 0xff); 895 896 /* DAC dividers configuration */ 897 snd_soc_component_update_bits(component, AIC31XX_NDAC, AIC31XX_PLL_MASK, 898 aic31xx_divs[i].ndac); 899 snd_soc_component_update_bits(component, AIC31XX_MDAC, AIC31XX_PLL_MASK, 900 aic31xx_divs[i].mdac); 901 902 snd_soc_component_write(component, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8); 903 snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff); 904 905 /* ADC dividers configuration. Write reset value 1 if not used. */ 906 snd_soc_component_update_bits(component, AIC31XX_NADC, AIC31XX_PLL_MASK, 907 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1); 908 snd_soc_component_update_bits(component, AIC31XX_MADC, AIC31XX_PLL_MASK, 909 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1); 910 911 snd_soc_component_write(component, AIC31XX_AOSR, aic31xx_divs[i].aosr); 912 913 /* Bit clock divider configuration. */ 914 snd_soc_component_update_bits(component, AIC31XX_BCLKN, 915 AIC31XX_PLL_MASK, bclk_n); 916 917 aic31xx->rate_div_line = i; 918 919 dev_dbg(component->dev, 920 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n", 921 aic31xx_divs[i].pll_j, 922 aic31xx_divs[i].pll_d, 923 aic31xx->p_div, 924 aic31xx_divs[i].dosr, 925 aic31xx_divs[i].ndac, 926 aic31xx_divs[i].mdac, 927 aic31xx_divs[i].aosr, 928 aic31xx_divs[i].nadc, 929 aic31xx_divs[i].madc, 930 bclk_n 931 ); 932 933 return 0; 934 } 935 936 static int aic31xx_hw_params(struct snd_pcm_substream *substream, 937 struct snd_pcm_hw_params *params, 938 struct snd_soc_dai *dai) 939 { 940 struct snd_soc_component *component = dai->component; 941 u8 data = 0; 942 943 dev_dbg(component->dev, "## %s: width %d rate %d\n", 944 __func__, params_width(params), 945 params_rate(params)); 946 947 switch (params_width(params)) { 948 case 16: 949 break; 950 case 20: 951 data = (AIC31XX_WORD_LEN_20BITS << 952 AIC31XX_IFACE1_DATALEN_SHIFT); 953 break; 954 case 24: 955 data = (AIC31XX_WORD_LEN_24BITS << 956 AIC31XX_IFACE1_DATALEN_SHIFT); 957 break; 958 case 32: 959 data = (AIC31XX_WORD_LEN_32BITS << 960 AIC31XX_IFACE1_DATALEN_SHIFT); 961 break; 962 default: 963 dev_err(component->dev, "%s: Unsupported width %d\n", 964 __func__, params_width(params)); 965 return -EINVAL; 966 } 967 968 snd_soc_component_update_bits(component, AIC31XX_IFACE1, 969 AIC31XX_IFACE1_DATALEN_MASK, 970 data); 971 972 return aic31xx_setup_pll(component, params); 973 } 974 975 static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute, 976 int direction) 977 { 978 struct snd_soc_component *component = codec_dai->component; 979 980 if (mute) { 981 snd_soc_component_update_bits(component, AIC31XX_DACMUTE, 982 AIC31XX_DACMUTE_MASK, 983 AIC31XX_DACMUTE_MASK); 984 } else { 985 snd_soc_component_update_bits(component, AIC31XX_DACMUTE, 986 AIC31XX_DACMUTE_MASK, 0x0); 987 } 988 989 return 0; 990 } 991 992 static int aic31xx_clock_master_routes(struct snd_soc_component *component, 993 unsigned int fmt) 994 { 995 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 996 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 997 int ret; 998 999 fmt &= SND_SOC_DAIFMT_MASTER_MASK; 1000 if (fmt == SND_SOC_DAIFMT_CBS_CFS && 1001 aic31xx->master_dapm_route_applied) { 1002 /* 1003 * Remove the DAPM route(s) for codec clock master modes, 1004 * if applied 1005 */ 1006 ret = snd_soc_dapm_del_routes(dapm, common31xx_cm_audio_map, 1007 ARRAY_SIZE(common31xx_cm_audio_map)); 1008 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT)) 1009 ret = snd_soc_dapm_del_routes(dapm, 1010 aic31xx_cm_audio_map, 1011 ARRAY_SIZE(aic31xx_cm_audio_map)); 1012 1013 if (ret) 1014 return ret; 1015 1016 aic31xx->master_dapm_route_applied = false; 1017 } else if (fmt != SND_SOC_DAIFMT_CBS_CFS && 1018 !aic31xx->master_dapm_route_applied) { 1019 /* 1020 * Add the needed DAPM route(s) for codec clock master modes, 1021 * if it is not done already 1022 */ 1023 ret = snd_soc_dapm_add_routes(dapm, common31xx_cm_audio_map, 1024 ARRAY_SIZE(common31xx_cm_audio_map)); 1025 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT)) 1026 ret = snd_soc_dapm_add_routes(dapm, 1027 aic31xx_cm_audio_map, 1028 ARRAY_SIZE(aic31xx_cm_audio_map)); 1029 1030 if (ret) 1031 return ret; 1032 1033 aic31xx->master_dapm_route_applied = true; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 1040 unsigned int fmt) 1041 { 1042 struct snd_soc_component *component = codec_dai->component; 1043 u8 iface_reg1 = 0; 1044 u8 iface_reg2 = 0; 1045 u8 dsp_a_val = 0; 1046 1047 dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt); 1048 1049 /* set master/slave audio interface */ 1050 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1051 case SND_SOC_DAIFMT_CBM_CFM: 1052 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER; 1053 break; 1054 case SND_SOC_DAIFMT_CBS_CFM: 1055 iface_reg1 |= AIC31XX_WCLK_MASTER; 1056 break; 1057 case SND_SOC_DAIFMT_CBM_CFS: 1058 iface_reg1 |= AIC31XX_BCLK_MASTER; 1059 break; 1060 case SND_SOC_DAIFMT_CBS_CFS: 1061 break; 1062 default: 1063 dev_err(component->dev, "Invalid DAI master/slave interface\n"); 1064 return -EINVAL; 1065 } 1066 1067 /* signal polarity */ 1068 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1069 case SND_SOC_DAIFMT_NB_NF: 1070 break; 1071 case SND_SOC_DAIFMT_IB_NF: 1072 iface_reg2 |= AIC31XX_BCLKINV_MASK; 1073 break; 1074 default: 1075 dev_err(component->dev, "Invalid DAI clock signal polarity\n"); 1076 return -EINVAL; 1077 } 1078 1079 /* interface format */ 1080 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1081 case SND_SOC_DAIFMT_I2S: 1082 break; 1083 case SND_SOC_DAIFMT_DSP_A: 1084 dsp_a_val = 0x1; 1085 fallthrough; 1086 case SND_SOC_DAIFMT_DSP_B: 1087 /* 1088 * NOTE: This CODEC samples on the falling edge of BCLK in 1089 * DSP mode, this is inverted compared to what most DAIs 1090 * expect, so we invert for this mode 1091 */ 1092 iface_reg2 ^= AIC31XX_BCLKINV_MASK; 1093 iface_reg1 |= (AIC31XX_DSP_MODE << 1094 AIC31XX_IFACE1_DATATYPE_SHIFT); 1095 break; 1096 case SND_SOC_DAIFMT_RIGHT_J: 1097 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE << 1098 AIC31XX_IFACE1_DATATYPE_SHIFT); 1099 break; 1100 case SND_SOC_DAIFMT_LEFT_J: 1101 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE << 1102 AIC31XX_IFACE1_DATATYPE_SHIFT); 1103 break; 1104 default: 1105 dev_err(component->dev, "Invalid DAI interface format\n"); 1106 return -EINVAL; 1107 } 1108 1109 snd_soc_component_update_bits(component, AIC31XX_IFACE1, 1110 AIC31XX_IFACE1_DATATYPE_MASK | 1111 AIC31XX_IFACE1_MASTER_MASK, 1112 iface_reg1); 1113 snd_soc_component_update_bits(component, AIC31XX_DATA_OFFSET, 1114 AIC31XX_DATA_OFFSET_MASK, 1115 dsp_a_val); 1116 snd_soc_component_update_bits(component, AIC31XX_IFACE2, 1117 AIC31XX_BCLKINV_MASK, 1118 iface_reg2); 1119 1120 return aic31xx_clock_master_routes(component, fmt); 1121 } 1122 1123 static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1124 int clk_id, unsigned int freq, int dir) 1125 { 1126 struct snd_soc_component *component = codec_dai->component; 1127 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1128 int i; 1129 1130 dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n", 1131 __func__, clk_id, freq, dir); 1132 1133 for (i = 1; i < 8; i++) 1134 if (freq / i <= 20000000) 1135 break; 1136 if (freq/i > 20000000) { 1137 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n", 1138 __func__, freq); 1139 return -EINVAL; 1140 } 1141 aic31xx->p_div = i; 1142 1143 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) 1144 if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div) 1145 break; 1146 if (i == ARRAY_SIZE(aic31xx_divs)) { 1147 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n", 1148 __func__, freq); 1149 return -EINVAL; 1150 } 1151 1152 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */ 1153 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK, 1154 clk_id << AIC31XX_PLL_CLKIN_SHIFT); 1155 1156 aic31xx->sysclk = freq; 1157 1158 return 0; 1159 } 1160 1161 static int aic31xx_regulator_event(struct notifier_block *nb, 1162 unsigned long event, void *data) 1163 { 1164 struct aic31xx_disable_nb *disable_nb = 1165 container_of(nb, struct aic31xx_disable_nb, nb); 1166 struct aic31xx_priv *aic31xx = disable_nb->aic31xx; 1167 1168 if (event & REGULATOR_EVENT_DISABLE) { 1169 /* 1170 * Put codec to reset and as at least one of the 1171 * supplies was disabled. 1172 */ 1173 if (aic31xx->gpio_reset) 1174 gpiod_set_value(aic31xx->gpio_reset, 1); 1175 1176 regcache_mark_dirty(aic31xx->regmap); 1177 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__); 1178 } 1179 1180 return 0; 1181 } 1182 1183 static int aic31xx_reset(struct aic31xx_priv *aic31xx) 1184 { 1185 int ret = 0; 1186 1187 if (aic31xx->gpio_reset) { 1188 gpiod_set_value(aic31xx->gpio_reset, 1); 1189 ndelay(10); /* At least 10ns */ 1190 gpiod_set_value(aic31xx->gpio_reset, 0); 1191 } else { 1192 ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1); 1193 } 1194 mdelay(1); /* At least 1ms */ 1195 1196 return ret; 1197 } 1198 1199 static void aic31xx_clk_on(struct snd_soc_component *component) 1200 { 1201 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1202 u8 mask = AIC31XX_PM_MASK; 1203 u8 on = AIC31XX_PM_MASK; 1204 1205 dev_dbg(component->dev, "codec clock -> on (rate %d)\n", 1206 aic31xx_divs[aic31xx->rate_div_line].rate); 1207 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on); 1208 mdelay(10); 1209 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on); 1210 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on); 1211 if (aic31xx_divs[aic31xx->rate_div_line].nadc) 1212 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on); 1213 if (aic31xx_divs[aic31xx->rate_div_line].madc) 1214 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on); 1215 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on); 1216 } 1217 1218 static void aic31xx_clk_off(struct snd_soc_component *component) 1219 { 1220 u8 mask = AIC31XX_PM_MASK; 1221 u8 off = 0; 1222 1223 dev_dbg(component->dev, "codec clock -> off\n"); 1224 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off); 1225 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off); 1226 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off); 1227 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off); 1228 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off); 1229 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off); 1230 } 1231 1232 static int aic31xx_power_on(struct snd_soc_component *component) 1233 { 1234 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1235 int ret; 1236 1237 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies), 1238 aic31xx->supplies); 1239 if (ret) 1240 return ret; 1241 1242 regcache_cache_only(aic31xx->regmap, false); 1243 1244 /* Reset device registers for a consistent power-on like state */ 1245 ret = aic31xx_reset(aic31xx); 1246 if (ret < 0) 1247 dev_err(aic31xx->dev, "Could not reset device: %d\n", ret); 1248 1249 ret = regcache_sync(aic31xx->regmap); 1250 if (ret) { 1251 dev_err(component->dev, 1252 "Failed to restore cache: %d\n", ret); 1253 regcache_cache_only(aic31xx->regmap, true); 1254 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1255 aic31xx->supplies); 1256 return ret; 1257 } 1258 1259 return 0; 1260 } 1261 1262 static void aic31xx_power_off(struct snd_soc_component *component) 1263 { 1264 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1265 1266 regcache_cache_only(aic31xx->regmap, true); 1267 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), 1268 aic31xx->supplies); 1269 } 1270 1271 static int aic31xx_set_bias_level(struct snd_soc_component *component, 1272 enum snd_soc_bias_level level) 1273 { 1274 dev_dbg(component->dev, "## %s: %d -> %d\n", __func__, 1275 snd_soc_component_get_bias_level(component), level); 1276 1277 switch (level) { 1278 case SND_SOC_BIAS_ON: 1279 break; 1280 case SND_SOC_BIAS_PREPARE: 1281 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 1282 aic31xx_clk_on(component); 1283 break; 1284 case SND_SOC_BIAS_STANDBY: 1285 switch (snd_soc_component_get_bias_level(component)) { 1286 case SND_SOC_BIAS_OFF: 1287 aic31xx_power_on(component); 1288 break; 1289 case SND_SOC_BIAS_PREPARE: 1290 aic31xx_clk_off(component); 1291 break; 1292 default: 1293 BUG(); 1294 } 1295 break; 1296 case SND_SOC_BIAS_OFF: 1297 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY) 1298 aic31xx_power_off(component); 1299 break; 1300 } 1301 1302 return 0; 1303 } 1304 1305 static int aic31xx_set_jack(struct snd_soc_component *component, 1306 struct snd_soc_jack *jack, void *data) 1307 { 1308 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1309 1310 aic31xx->jack = jack; 1311 1312 /* Enable/Disable jack detection */ 1313 regmap_write(aic31xx->regmap, AIC31XX_HSDETECT, 1314 jack ? AIC31XX_HSD_ENABLE : 0); 1315 1316 return 0; 1317 } 1318 1319 static int aic31xx_codec_probe(struct snd_soc_component *component) 1320 { 1321 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component); 1322 int i, ret; 1323 1324 dev_dbg(aic31xx->dev, "## %s\n", __func__); 1325 1326 aic31xx->component = component; 1327 1328 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) { 1329 aic31xx->disable_nb[i].nb.notifier_call = 1330 aic31xx_regulator_event; 1331 aic31xx->disable_nb[i].aic31xx = aic31xx; 1332 ret = devm_regulator_register_notifier( 1333 aic31xx->supplies[i].consumer, 1334 &aic31xx->disable_nb[i].nb); 1335 if (ret) { 1336 dev_err(component->dev, 1337 "Failed to request regulator notifier: %d\n", 1338 ret); 1339 return ret; 1340 } 1341 } 1342 1343 regcache_cache_only(aic31xx->regmap, true); 1344 regcache_mark_dirty(aic31xx->regmap); 1345 1346 ret = aic31xx_add_controls(component); 1347 if (ret) 1348 return ret; 1349 1350 ret = aic31xx_add_widgets(component); 1351 if (ret) 1352 return ret; 1353 1354 /* set output common-mode voltage */ 1355 snd_soc_component_update_bits(component, AIC31XX_HPDRIVER, 1356 AIC31XX_HPD_OCMV_MASK, 1357 aic31xx->ocmv << AIC31XX_HPD_OCMV_SHIFT); 1358 1359 return 0; 1360 } 1361 1362 static const struct snd_soc_component_driver soc_codec_driver_aic31xx = { 1363 .probe = aic31xx_codec_probe, 1364 .set_jack = aic31xx_set_jack, 1365 .set_bias_level = aic31xx_set_bias_level, 1366 .controls = common31xx_snd_controls, 1367 .num_controls = ARRAY_SIZE(common31xx_snd_controls), 1368 .dapm_widgets = common31xx_dapm_widgets, 1369 .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets), 1370 .dapm_routes = common31xx_audio_map, 1371 .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map), 1372 .suspend_bias_off = 1, 1373 .idle_bias_on = 1, 1374 .use_pmdown_time = 1, 1375 .endianness = 1, 1376 .non_legacy_dai_naming = 1, 1377 }; 1378 1379 static const struct snd_soc_dai_ops aic31xx_dai_ops = { 1380 .hw_params = aic31xx_hw_params, 1381 .set_sysclk = aic31xx_set_dai_sysclk, 1382 .set_fmt = aic31xx_set_dai_fmt, 1383 .mute_stream = aic31xx_dac_mute, 1384 .no_capture_mute = 1, 1385 }; 1386 1387 static struct snd_soc_dai_driver dac31xx_dai_driver[] = { 1388 { 1389 .name = "tlv320dac31xx-hifi", 1390 .playback = { 1391 .stream_name = "Playback", 1392 .channels_min = 2, 1393 .channels_max = 2, 1394 .rates = AIC31XX_RATES, 1395 .formats = AIC31XX_FORMATS, 1396 }, 1397 .ops = &aic31xx_dai_ops, 1398 .symmetric_rates = 1, 1399 } 1400 }; 1401 1402 static struct snd_soc_dai_driver aic31xx_dai_driver[] = { 1403 { 1404 .name = "tlv320aic31xx-hifi", 1405 .playback = { 1406 .stream_name = "Playback", 1407 .channels_min = 2, 1408 .channels_max = 2, 1409 .rates = AIC31XX_RATES, 1410 .formats = AIC31XX_FORMATS, 1411 }, 1412 .capture = { 1413 .stream_name = "Capture", 1414 .channels_min = 2, 1415 .channels_max = 2, 1416 .rates = AIC31XX_RATES, 1417 .formats = AIC31XX_FORMATS, 1418 }, 1419 .ops = &aic31xx_dai_ops, 1420 .symmetric_rates = 1, 1421 } 1422 }; 1423 1424 #if defined(CONFIG_OF) 1425 static const struct of_device_id tlv320aic31xx_of_match[] = { 1426 { .compatible = "ti,tlv320aic310x" }, 1427 { .compatible = "ti,tlv320aic311x" }, 1428 { .compatible = "ti,tlv320aic3100" }, 1429 { .compatible = "ti,tlv320aic3110" }, 1430 { .compatible = "ti,tlv320aic3120" }, 1431 { .compatible = "ti,tlv320aic3111" }, 1432 { .compatible = "ti,tlv320dac3100" }, 1433 { .compatible = "ti,tlv320dac3101" }, 1434 {}, 1435 }; 1436 MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match); 1437 #endif /* CONFIG_OF */ 1438 1439 #ifdef CONFIG_ACPI 1440 static const struct acpi_device_id aic31xx_acpi_match[] = { 1441 { "10TI3100", 0 }, 1442 { } 1443 }; 1444 MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match); 1445 #endif 1446 1447 static irqreturn_t aic31xx_irq(int irq, void *data) 1448 { 1449 struct aic31xx_priv *aic31xx = data; 1450 struct device *dev = aic31xx->dev; 1451 unsigned int value; 1452 bool handled = false; 1453 int ret; 1454 1455 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG, &value); 1456 if (ret) { 1457 dev_err(dev, "Failed to read interrupt mask: %d\n", ret); 1458 goto exit; 1459 } 1460 1461 if (value) 1462 handled = true; 1463 else 1464 goto read_overflow; 1465 1466 if (value & AIC31XX_HPLSCDETECT) 1467 dev_err(dev, "Short circuit on Left output is detected\n"); 1468 if (value & AIC31XX_HPRSCDETECT) 1469 dev_err(dev, "Short circuit on Right output is detected\n"); 1470 if (value & (AIC31XX_HSPLUG | AIC31XX_BUTTONPRESS)) { 1471 unsigned int val; 1472 int status = 0; 1473 1474 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG2, 1475 &val); 1476 if (ret) { 1477 dev_err(dev, "Failed to read interrupt mask: %d\n", 1478 ret); 1479 goto exit; 1480 } 1481 1482 if (val & AIC31XX_BUTTONPRESS) 1483 status |= SND_JACK_BTN_0; 1484 1485 ret = regmap_read(aic31xx->regmap, AIC31XX_HSDETECT, &val); 1486 if (ret) { 1487 dev_err(dev, "Failed to read headset type: %d\n", ret); 1488 goto exit; 1489 } 1490 1491 switch ((val & AIC31XX_HSD_TYPE_MASK) >> 1492 AIC31XX_HSD_TYPE_SHIFT) { 1493 case AIC31XX_HSD_HP: 1494 status |= SND_JACK_HEADPHONE; 1495 break; 1496 case AIC31XX_HSD_HS: 1497 status |= SND_JACK_HEADSET; 1498 break; 1499 default: 1500 break; 1501 } 1502 1503 if (aic31xx->jack) 1504 snd_soc_jack_report(aic31xx->jack, status, 1505 AIC31XX_JACK_MASK); 1506 } 1507 if (value & ~(AIC31XX_HPLSCDETECT | 1508 AIC31XX_HPRSCDETECT | 1509 AIC31XX_HSPLUG | 1510 AIC31XX_BUTTONPRESS)) 1511 dev_err(dev, "Unknown DAC interrupt flags: 0x%08x\n", value); 1512 1513 read_overflow: 1514 ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value); 1515 if (ret) { 1516 dev_err(dev, "Failed to read overflow flag: %d\n", ret); 1517 goto exit; 1518 } 1519 1520 if (value) 1521 handled = true; 1522 else 1523 goto exit; 1524 1525 if (value & AIC31XX_DAC_OF_LEFT) 1526 dev_warn(dev, "Left-channel DAC overflow has occurred\n"); 1527 if (value & AIC31XX_DAC_OF_RIGHT) 1528 dev_warn(dev, "Right-channel DAC overflow has occurred\n"); 1529 if (value & AIC31XX_DAC_OF_SHIFTER) 1530 dev_warn(dev, "DAC barrel shifter overflow has occurred\n"); 1531 if (value & AIC31XX_ADC_OF) 1532 dev_warn(dev, "ADC overflow has occurred\n"); 1533 if (value & AIC31XX_ADC_OF_SHIFTER) 1534 dev_warn(dev, "ADC barrel shifter overflow has occurred\n"); 1535 if (value & ~(AIC31XX_DAC_OF_LEFT | 1536 AIC31XX_DAC_OF_RIGHT | 1537 AIC31XX_DAC_OF_SHIFTER | 1538 AIC31XX_ADC_OF | 1539 AIC31XX_ADC_OF_SHIFTER)) 1540 dev_warn(dev, "Unknown overflow interrupt flags: 0x%08x\n", value); 1541 1542 exit: 1543 if (handled) 1544 return IRQ_HANDLED; 1545 else 1546 return IRQ_NONE; 1547 } 1548 1549 static void aic31xx_configure_ocmv(struct aic31xx_priv *priv) 1550 { 1551 struct device *dev = priv->dev; 1552 int dvdd, avdd; 1553 u32 value; 1554 1555 if (dev->fwnode && 1556 fwnode_property_read_u32(dev->fwnode, "ai31xx-ocmv", &value)) { 1557 /* OCMV setting is forced by DT */ 1558 if (value <= 3) { 1559 priv->ocmv = value; 1560 return; 1561 } 1562 } 1563 1564 avdd = regulator_get_voltage(priv->supplies[3].consumer); 1565 dvdd = regulator_get_voltage(priv->supplies[5].consumer); 1566 1567 if (avdd > 3600000 || dvdd > 1950000) { 1568 dev_warn(dev, 1569 "Too high supply voltage(s) AVDD: %d, DVDD: %d\n", 1570 avdd, dvdd); 1571 } else if (avdd == 3600000 && dvdd == 1950000) { 1572 priv->ocmv = AIC31XX_HPD_OCMV_1_8V; 1573 } else if (avdd >= 3300000 && dvdd >= 1800000) { 1574 priv->ocmv = AIC31XX_HPD_OCMV_1_65V; 1575 } else if (avdd >= 3000000 && dvdd >= 1650000) { 1576 priv->ocmv = AIC31XX_HPD_OCMV_1_5V; 1577 } else if (avdd >= 2700000 && dvdd >= 1525000) { 1578 priv->ocmv = AIC31XX_HPD_OCMV_1_35V; 1579 } else { 1580 dev_warn(dev, 1581 "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n", 1582 avdd, dvdd); 1583 } 1584 } 1585 1586 static int aic31xx_i2c_probe(struct i2c_client *i2c, 1587 const struct i2c_device_id *id) 1588 { 1589 struct aic31xx_priv *aic31xx; 1590 unsigned int micbias_value = MICBIAS_2_0V; 1591 int i, ret; 1592 1593 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__, 1594 id->name, (int)id->driver_data); 1595 1596 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL); 1597 if (!aic31xx) 1598 return -ENOMEM; 1599 1600 aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap); 1601 if (IS_ERR(aic31xx->regmap)) { 1602 ret = PTR_ERR(aic31xx->regmap); 1603 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 1604 ret); 1605 return ret; 1606 } 1607 aic31xx->dev = &i2c->dev; 1608 aic31xx->irq = i2c->irq; 1609 1610 aic31xx->codec_type = id->driver_data; 1611 1612 dev_set_drvdata(aic31xx->dev, aic31xx); 1613 1614 fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg", 1615 &micbias_value); 1616 switch (micbias_value) { 1617 case MICBIAS_2_0V: 1618 case MICBIAS_2_5V: 1619 case MICBIAS_AVDDV: 1620 aic31xx->micbias_vg = micbias_value; 1621 break; 1622 default: 1623 dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n", 1624 micbias_value); 1625 aic31xx->micbias_vg = MICBIAS_2_0V; 1626 } 1627 1628 if (dev_get_platdata(aic31xx->dev)) { 1629 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata)); 1630 aic31xx->codec_type = aic31xx->pdata.codec_type; 1631 aic31xx->micbias_vg = aic31xx->pdata.micbias_vg; 1632 } 1633 1634 aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset", 1635 GPIOD_OUT_LOW); 1636 if (IS_ERR(aic31xx->gpio_reset)) { 1637 if (PTR_ERR(aic31xx->gpio_reset) != -EPROBE_DEFER) 1638 dev_err(aic31xx->dev, "not able to acquire gpio\n"); 1639 return PTR_ERR(aic31xx->gpio_reset); 1640 } 1641 1642 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) 1643 aic31xx->supplies[i].supply = aic31xx_supply_names[i]; 1644 1645 ret = devm_regulator_bulk_get(aic31xx->dev, 1646 ARRAY_SIZE(aic31xx->supplies), 1647 aic31xx->supplies); 1648 if (ret) { 1649 if (ret != -EPROBE_DEFER) 1650 dev_err(aic31xx->dev, 1651 "Failed to request supplies: %d\n", ret); 1652 return ret; 1653 } 1654 1655 aic31xx_configure_ocmv(aic31xx); 1656 1657 if (aic31xx->irq > 0) { 1658 regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1, 1659 AIC31XX_GPIO1_FUNC_MASK, 1660 AIC31XX_GPIO1_INT1 << 1661 AIC31XX_GPIO1_FUNC_SHIFT); 1662 1663 regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL, 1664 AIC31XX_HSPLUGDET | 1665 AIC31XX_BUTTONPRESSDET | 1666 AIC31XX_SC | 1667 AIC31XX_ENGINE); 1668 1669 ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq, 1670 NULL, aic31xx_irq, 1671 IRQF_ONESHOT, "aic31xx-irq", 1672 aic31xx); 1673 if (ret) { 1674 dev_err(aic31xx->dev, "Unable to request IRQ\n"); 1675 return ret; 1676 } 1677 } 1678 1679 if (aic31xx->codec_type & DAC31XX_BIT) 1680 return devm_snd_soc_register_component(&i2c->dev, 1681 &soc_codec_driver_aic31xx, 1682 dac31xx_dai_driver, 1683 ARRAY_SIZE(dac31xx_dai_driver)); 1684 else 1685 return devm_snd_soc_register_component(&i2c->dev, 1686 &soc_codec_driver_aic31xx, 1687 aic31xx_dai_driver, 1688 ARRAY_SIZE(aic31xx_dai_driver)); 1689 } 1690 1691 static const struct i2c_device_id aic31xx_i2c_id[] = { 1692 { "tlv320aic310x", AIC3100 }, 1693 { "tlv320aic311x", AIC3110 }, 1694 { "tlv320aic3100", AIC3100 }, 1695 { "tlv320aic3110", AIC3110 }, 1696 { "tlv320aic3120", AIC3120 }, 1697 { "tlv320aic3111", AIC3111 }, 1698 { "tlv320dac3100", DAC3100 }, 1699 { "tlv320dac3101", DAC3101 }, 1700 { } 1701 }; 1702 MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id); 1703 1704 static struct i2c_driver aic31xx_i2c_driver = { 1705 .driver = { 1706 .name = "tlv320aic31xx-codec", 1707 .of_match_table = of_match_ptr(tlv320aic31xx_of_match), 1708 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match), 1709 }, 1710 .probe = aic31xx_i2c_probe, 1711 .id_table = aic31xx_i2c_id, 1712 }; 1713 module_i2c_driver(aic31xx_i2c_driver); 1714 1715 MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>"); 1716 MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver"); 1717 MODULE_LICENSE("GPL v2"); 1718