1 // SPDX-License-Identifier: GPL-2.0 2 // TLV320ADCX140 Sound driver 3 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 4 5 #include <linux/module.h> 6 #include <linux/moduleparam.h> 7 #include <linux/init.h> 8 #include <linux/delay.h> 9 #include <linux/pm.h> 10 #include <linux/i2c.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/regulator/consumer.h> 13 #include <linux/acpi.h> 14 #include <linux/of.h> 15 #include <linux/of_gpio.h> 16 #include <linux/slab.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/initval.h> 22 #include <sound/tlv.h> 23 24 #include "tlv320adcx140.h" 25 26 struct adcx140_priv { 27 struct snd_soc_component *component; 28 struct regulator *supply_areg; 29 struct gpio_desc *gpio_reset; 30 struct regmap *regmap; 31 struct device *dev; 32 33 int micbias_vg; 34 35 unsigned int dai_fmt; 36 unsigned int tdm_delay; 37 unsigned int slot_width; 38 }; 39 40 static const struct reg_default adcx140_reg_defaults[] = { 41 { ADCX140_PAGE_SELECT, 0x00 }, 42 { ADCX140_SW_RESET, 0x00 }, 43 { ADCX140_SLEEP_CFG, 0x00 }, 44 { ADCX140_SHDN_CFG, 0x05 }, 45 { ADCX140_ASI_CFG0, 0x30 }, 46 { ADCX140_ASI_CFG1, 0x00 }, 47 { ADCX140_ASI_CFG2, 0x00 }, 48 { ADCX140_ASI_CH1, 0x00 }, 49 { ADCX140_ASI_CH2, 0x01 }, 50 { ADCX140_ASI_CH3, 0x02 }, 51 { ADCX140_ASI_CH4, 0x03 }, 52 { ADCX140_ASI_CH5, 0x04 }, 53 { ADCX140_ASI_CH6, 0x05 }, 54 { ADCX140_ASI_CH7, 0x06 }, 55 { ADCX140_ASI_CH8, 0x07 }, 56 { ADCX140_MST_CFG0, 0x02 }, 57 { ADCX140_MST_CFG1, 0x48 }, 58 { ADCX140_ASI_STS, 0xff }, 59 { ADCX140_CLK_SRC, 0x10 }, 60 { ADCX140_PDMCLK_CFG, 0x40 }, 61 { ADCX140_PDM_CFG, 0x00 }, 62 { ADCX140_GPIO_CFG0, 0x22 }, 63 { ADCX140_GPO_CFG1, 0x00 }, 64 { ADCX140_GPO_CFG2, 0x00 }, 65 { ADCX140_GPO_CFG3, 0x00 }, 66 { ADCX140_GPO_CFG4, 0x00 }, 67 { ADCX140_GPO_VAL, 0x00 }, 68 { ADCX140_GPIO_MON, 0x00 }, 69 { ADCX140_GPI_CFG0, 0x00 }, 70 { ADCX140_GPI_CFG1, 0x00 }, 71 { ADCX140_GPI_MON, 0x00 }, 72 { ADCX140_INT_CFG, 0x00 }, 73 { ADCX140_INT_MASK0, 0xff }, 74 { ADCX140_INT_LTCH0, 0x00 }, 75 { ADCX140_BIAS_CFG, 0x00 }, 76 { ADCX140_CH1_CFG0, 0x00 }, 77 { ADCX140_CH1_CFG1, 0x00 }, 78 { ADCX140_CH1_CFG2, 0xc9 }, 79 { ADCX140_CH1_CFG3, 0x80 }, 80 { ADCX140_CH1_CFG4, 0x00 }, 81 { ADCX140_CH2_CFG0, 0x00 }, 82 { ADCX140_CH2_CFG1, 0x00 }, 83 { ADCX140_CH2_CFG2, 0xc9 }, 84 { ADCX140_CH2_CFG3, 0x80 }, 85 { ADCX140_CH2_CFG4, 0x00 }, 86 { ADCX140_CH3_CFG0, 0x00 }, 87 { ADCX140_CH3_CFG1, 0x00 }, 88 { ADCX140_CH3_CFG2, 0xc9 }, 89 { ADCX140_CH3_CFG3, 0x80 }, 90 { ADCX140_CH3_CFG4, 0x00 }, 91 { ADCX140_CH4_CFG0, 0x00 }, 92 { ADCX140_CH4_CFG1, 0x00 }, 93 { ADCX140_CH4_CFG2, 0xc9 }, 94 { ADCX140_CH4_CFG3, 0x80 }, 95 { ADCX140_CH4_CFG4, 0x00 }, 96 { ADCX140_CH5_CFG2, 0xc9 }, 97 { ADCX140_CH5_CFG3, 0x80 }, 98 { ADCX140_CH5_CFG4, 0x00 }, 99 { ADCX140_CH6_CFG2, 0xc9 }, 100 { ADCX140_CH6_CFG3, 0x80 }, 101 { ADCX140_CH6_CFG4, 0x00 }, 102 { ADCX140_CH7_CFG2, 0xc9 }, 103 { ADCX140_CH7_CFG3, 0x80 }, 104 { ADCX140_CH7_CFG4, 0x00 }, 105 { ADCX140_CH8_CFG2, 0xc9 }, 106 { ADCX140_CH8_CFG3, 0x80 }, 107 { ADCX140_CH8_CFG4, 0x00 }, 108 { ADCX140_DSP_CFG0, 0x01 }, 109 { ADCX140_DSP_CFG1, 0x40 }, 110 { ADCX140_DRE_CFG0, 0x7b }, 111 { ADCX140_IN_CH_EN, 0xf0 }, 112 { ADCX140_ASI_OUT_CH_EN, 0x00 }, 113 { ADCX140_PWR_CFG, 0x00 }, 114 { ADCX140_DEV_STS0, 0x00 }, 115 { ADCX140_DEV_STS1, 0x80 }, 116 }; 117 118 static const struct regmap_range_cfg adcx140_ranges[] = { 119 { 120 .range_min = 0, 121 .range_max = 12 * 128, 122 .selector_reg = ADCX140_PAGE_SELECT, 123 .selector_mask = 0xff, 124 .selector_shift = 0, 125 .window_start = 0, 126 .window_len = 128, 127 }, 128 }; 129 130 static bool adcx140_volatile(struct device *dev, unsigned int reg) 131 { 132 switch (reg) { 133 case ADCX140_SW_RESET: 134 case ADCX140_DEV_STS0: 135 case ADCX140_DEV_STS1: 136 case ADCX140_ASI_STS: 137 return true; 138 default: 139 return false; 140 } 141 } 142 143 static const struct regmap_config adcx140_i2c_regmap = { 144 .reg_bits = 8, 145 .val_bits = 8, 146 .reg_defaults = adcx140_reg_defaults, 147 .num_reg_defaults = ARRAY_SIZE(adcx140_reg_defaults), 148 .cache_type = REGCACHE_FLAT, 149 .ranges = adcx140_ranges, 150 .num_ranges = ARRAY_SIZE(adcx140_ranges), 151 .max_register = 12 * 128, 152 .volatile_reg = adcx140_volatile, 153 }; 154 155 /* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */ 156 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10000, 50, 0); 157 158 /* ADC gain. From 0 to 42 dB in 1 dB steps */ 159 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0); 160 161 static const char * const resistor_text[] = { 162 "2.5 kOhm", "10 kOhm", "20 kOhm" 163 }; 164 165 static SOC_ENUM_SINGLE_DECL(in1_resistor_enum, ADCX140_CH1_CFG0, 2, 166 resistor_text); 167 static SOC_ENUM_SINGLE_DECL(in2_resistor_enum, ADCX140_CH2_CFG0, 2, 168 resistor_text); 169 static SOC_ENUM_SINGLE_DECL(in3_resistor_enum, ADCX140_CH3_CFG0, 2, 170 resistor_text); 171 static SOC_ENUM_SINGLE_DECL(in4_resistor_enum, ADCX140_CH4_CFG0, 2, 172 resistor_text); 173 174 static const struct snd_kcontrol_new in1_resistor_controls[] = { 175 SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum), 176 }; 177 static const struct snd_kcontrol_new in2_resistor_controls[] = { 178 SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum), 179 }; 180 static const struct snd_kcontrol_new in3_resistor_controls[] = { 181 SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum), 182 }; 183 static const struct snd_kcontrol_new in4_resistor_controls[] = { 184 SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum), 185 }; 186 187 /* Analog/Digital Selection */ 188 static const char *adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"}; 189 static const char *adcx140_analog_sel_text[] = {"Analog", "Line In"}; 190 191 static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum, 192 ADCX140_CH1_CFG0, 5, 193 adcx140_mic_sel_text); 194 195 static const struct snd_kcontrol_new adcx140_dapm_mic1p_control = 196 SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum); 197 198 static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum, 199 ADCX140_CH1_CFG0, 7, 200 adcx140_analog_sel_text); 201 202 static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control = 203 SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum); 204 205 static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum, 206 ADCX140_CH1_CFG0, 5, 207 adcx140_mic_sel_text); 208 209 static const struct snd_kcontrol_new adcx140_dapm_mic1m_control = 210 SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum); 211 212 static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum, 213 ADCX140_CH2_CFG0, 5, 214 adcx140_mic_sel_text); 215 216 static const struct snd_kcontrol_new adcx140_dapm_mic2p_control = 217 SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum); 218 219 static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum, 220 ADCX140_CH2_CFG0, 7, 221 adcx140_analog_sel_text); 222 223 static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control = 224 SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum); 225 226 static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum, 227 ADCX140_CH2_CFG0, 5, 228 adcx140_mic_sel_text); 229 230 static const struct snd_kcontrol_new adcx140_dapm_mic2m_control = 231 SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum); 232 233 static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum, 234 ADCX140_CH3_CFG0, 5, 235 adcx140_mic_sel_text); 236 237 static const struct snd_kcontrol_new adcx140_dapm_mic3p_control = 238 SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum); 239 240 static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum, 241 ADCX140_CH3_CFG0, 7, 242 adcx140_analog_sel_text); 243 244 static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control = 245 SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum); 246 247 static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum, 248 ADCX140_CH3_CFG0, 5, 249 adcx140_mic_sel_text); 250 251 static const struct snd_kcontrol_new adcx140_dapm_mic3m_control = 252 SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum); 253 254 static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum, 255 ADCX140_CH4_CFG0, 5, 256 adcx140_mic_sel_text); 257 258 static const struct snd_kcontrol_new adcx140_dapm_mic4p_control = 259 SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum); 260 261 static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum, 262 ADCX140_CH4_CFG0, 7, 263 adcx140_analog_sel_text); 264 265 static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control = 266 SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum); 267 268 static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum, 269 ADCX140_CH4_CFG0, 5, 270 adcx140_mic_sel_text); 271 272 static const struct snd_kcontrol_new adcx140_dapm_mic4m_control = 273 SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum); 274 275 static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch = 276 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0); 277 static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch = 278 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0); 279 static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch = 280 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0); 281 static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch = 282 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0); 283 284 /* Output Mixer */ 285 static const struct snd_kcontrol_new adcx140_output_mixer_controls[] = { 286 SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0), 287 SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0), 288 SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0), 289 SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0), 290 }; 291 292 static const struct snd_soc_dapm_widget adcx140_dapm_widgets[] = { 293 /* Analog Differential Inputs */ 294 SND_SOC_DAPM_INPUT("MIC1P"), 295 SND_SOC_DAPM_INPUT("MIC1M"), 296 SND_SOC_DAPM_INPUT("MIC2P"), 297 SND_SOC_DAPM_INPUT("MIC2M"), 298 SND_SOC_DAPM_INPUT("MIC3P"), 299 SND_SOC_DAPM_INPUT("MIC3M"), 300 SND_SOC_DAPM_INPUT("MIC4P"), 301 SND_SOC_DAPM_INPUT("MIC4M"), 302 303 SND_SOC_DAPM_OUTPUT("CH1_OUT"), 304 SND_SOC_DAPM_OUTPUT("CH2_OUT"), 305 SND_SOC_DAPM_OUTPUT("CH3_OUT"), 306 SND_SOC_DAPM_OUTPUT("CH4_OUT"), 307 SND_SOC_DAPM_OUTPUT("CH5_OUT"), 308 SND_SOC_DAPM_OUTPUT("CH6_OUT"), 309 SND_SOC_DAPM_OUTPUT("CH7_OUT"), 310 SND_SOC_DAPM_OUTPUT("CH8_OUT"), 311 312 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0, 313 &adcx140_output_mixer_controls[0], 314 ARRAY_SIZE(adcx140_output_mixer_controls)), 315 316 /* Input Selection to MIC_PGA */ 317 SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0, 318 &adcx140_dapm_mic1p_control), 319 SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0, 320 &adcx140_dapm_mic2p_control), 321 SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0, 322 &adcx140_dapm_mic3p_control), 323 SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0, 324 &adcx140_dapm_mic4p_control), 325 326 /* Input Selection to MIC_PGA */ 327 SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0, 328 &adcx140_dapm_mic1_analog_control), 329 SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0, 330 &adcx140_dapm_mic2_analog_control), 331 SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0, 332 &adcx140_dapm_mic3_analog_control), 333 SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0, 334 &adcx140_dapm_mic4_analog_control), 335 336 SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0, 337 &adcx140_dapm_mic1m_control), 338 SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0, 339 &adcx140_dapm_mic2m_control), 340 SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0, 341 &adcx140_dapm_mic3m_control), 342 SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0, 343 &adcx140_dapm_mic4m_control), 344 345 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0), 346 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0), 347 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0), 348 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0), 349 350 SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0), 351 SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0), 352 SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0), 353 SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0), 354 355 SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0, 356 &adcx140_dapm_ch1_en_switch), 357 SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0, 358 &adcx140_dapm_ch2_en_switch), 359 SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0, 360 &adcx140_dapm_ch3_en_switch), 361 SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0, 362 &adcx140_dapm_ch4_en_switch), 363 364 SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 365 in1_resistor_controls), 366 SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 367 in2_resistor_controls), 368 SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 369 in3_resistor_controls), 370 SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 371 in4_resistor_controls), 372 }; 373 374 static const struct snd_soc_dapm_route adcx140_audio_map[] = { 375 /* Outputs */ 376 {"CH1_OUT", NULL, "Output Mixer"}, 377 {"CH2_OUT", NULL, "Output Mixer"}, 378 {"CH3_OUT", NULL, "Output Mixer"}, 379 {"CH4_OUT", NULL, "Output Mixer"}, 380 381 {"CH1_ASI_EN", "Switch", "CH1_ADC"}, 382 {"CH2_ASI_EN", "Switch", "CH2_ADC"}, 383 {"CH3_ASI_EN", "Switch", "CH3_ADC"}, 384 {"CH4_ASI_EN", "Switch", "CH4_ADC"}, 385 386 /* Mic input */ 387 {"CH1_ADC", NULL, "MIC_GAIN_CTL_CH1"}, 388 {"CH2_ADC", NULL, "MIC_GAIN_CTL_CH2"}, 389 {"CH3_ADC", NULL, "MIC_GAIN_CTL_CH3"}, 390 {"CH4_ADC", NULL, "MIC_GAIN_CTL_CH4"}, 391 392 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"}, 393 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"}, 394 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"}, 395 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"}, 396 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"}, 397 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"}, 398 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"}, 399 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"}, 400 401 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"}, 402 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"}, 403 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"}, 404 405 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"}, 406 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"}, 407 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"}, 408 409 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"}, 410 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"}, 411 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"}, 412 413 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"}, 414 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"}, 415 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"}, 416 417 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"}, 418 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"}, 419 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"}, 420 421 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"}, 422 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"}, 423 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"}, 424 425 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"}, 426 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"}, 427 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"}, 428 429 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"}, 430 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"}, 431 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"}, 432 433 {"MIC1 Analog Mux", "Line In", "MIC1P"}, 434 {"MIC2 Analog Mux", "Line In", "MIC2P"}, 435 {"MIC3 Analog Mux", "Line In", "MIC3P"}, 436 {"MIC4 Analog Mux", "Line In", "MIC4P"}, 437 438 {"MIC1P Input Mux", "Analog", "MIC1P"}, 439 {"MIC1M Input Mux", "Analog", "MIC1M"}, 440 {"MIC2P Input Mux", "Analog", "MIC2P"}, 441 {"MIC2M Input Mux", "Analog", "MIC2M"}, 442 {"MIC3P Input Mux", "Analog", "MIC3P"}, 443 {"MIC3M Input Mux", "Analog", "MIC3M"}, 444 {"MIC4P Input Mux", "Analog", "MIC4P"}, 445 {"MIC4M Input Mux", "Analog", "MIC4M"}, 446 }; 447 448 static const struct snd_kcontrol_new adcx140_snd_controls[] = { 449 SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0, 450 adc_tlv), 451 SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH1_CFG2, 2, 42, 0, 452 adc_tlv), 453 SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH1_CFG3, 2, 42, 0, 454 adc_tlv), 455 SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH1_CFG4, 2, 42, 0, 456 adc_tlv), 457 458 SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2, 459 0, 0xff, 0, dig_vol_tlv), 460 SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2, 461 0, 0xff, 0, dig_vol_tlv), 462 SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2, 463 0, 0xff, 0, dig_vol_tlv), 464 SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2, 465 0, 0xff, 0, dig_vol_tlv), 466 SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2, 467 0, 0xff, 0, dig_vol_tlv), 468 SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2, 469 0, 0xff, 0, dig_vol_tlv), 470 SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2, 471 0, 0xff, 0, dig_vol_tlv), 472 SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2, 473 0, 0xff, 0, dig_vol_tlv), 474 }; 475 476 static int adcx140_reset(struct adcx140_priv *adcx140) 477 { 478 int ret = 0; 479 480 if (adcx140->gpio_reset) { 481 gpiod_direction_output(adcx140->gpio_reset, 0); 482 /* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */ 483 usleep_range(30000, 100000); 484 gpiod_direction_output(adcx140->gpio_reset, 1); 485 } else { 486 ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET, 487 ADCX140_RESET); 488 } 489 490 /* 8.4.2: wait >= 10 ms after entering sleep mode. */ 491 usleep_range(10000, 100000); 492 493 return 0; 494 } 495 496 static int adcx140_hw_params(struct snd_pcm_substream *substream, 497 struct snd_pcm_hw_params *params, 498 struct snd_soc_dai *dai) 499 { 500 struct snd_soc_component *component = dai->component; 501 u8 data = 0; 502 503 switch (params_width(params)) { 504 case 16: 505 data = ADCX140_16_BIT_WORD; 506 break; 507 case 20: 508 data = ADCX140_20_BIT_WORD; 509 break; 510 case 24: 511 data = ADCX140_24_BIT_WORD; 512 break; 513 case 32: 514 data = ADCX140_32_BIT_WORD; 515 break; 516 default: 517 dev_err(component->dev, "%s: Unsupported width %d\n", 518 __func__, params_width(params)); 519 return -EINVAL; 520 } 521 522 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0, 523 ADCX140_WORD_LEN_MSK, data); 524 525 return 0; 526 } 527 528 static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai, 529 unsigned int fmt) 530 { 531 struct snd_soc_component *component = codec_dai->component; 532 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 533 u8 iface_reg1 = 0; 534 u8 iface_reg2 = 0; 535 536 /* set master/slave audio interface */ 537 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 538 case SND_SOC_DAIFMT_CBM_CFM: 539 iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER; 540 break; 541 case SND_SOC_DAIFMT_CBS_CFS: 542 break; 543 case SND_SOC_DAIFMT_CBS_CFM: 544 case SND_SOC_DAIFMT_CBM_CFS: 545 default: 546 dev_err(component->dev, "Invalid DAI master/slave interface\n"); 547 return -EINVAL; 548 } 549 550 /* signal polarity */ 551 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 552 case SND_SOC_DAIFMT_NB_IF: 553 iface_reg1 |= ADCX140_FSYNCINV_BIT; 554 break; 555 case SND_SOC_DAIFMT_IB_IF: 556 iface_reg1 |= ADCX140_BCLKINV_BIT | ADCX140_FSYNCINV_BIT; 557 break; 558 case SND_SOC_DAIFMT_IB_NF: 559 iface_reg1 |= ADCX140_BCLKINV_BIT; 560 break; 561 case SND_SOC_DAIFMT_NB_NF: 562 break; 563 default: 564 dev_err(component->dev, "Invalid DAI clock signal polarity\n"); 565 return -EINVAL; 566 } 567 568 /* interface format */ 569 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 570 case SND_SOC_DAIFMT_I2S: 571 iface_reg1 |= ADCX140_I2S_MODE_BIT; 572 break; 573 case SND_SOC_DAIFMT_LEFT_J: 574 iface_reg1 |= ADCX140_LEFT_JUST_BIT; 575 break; 576 case SND_SOC_DAIFMT_DSP_A: 577 case SND_SOC_DAIFMT_DSP_B: 578 break; 579 default: 580 dev_err(component->dev, "Invalid DAI interface format\n"); 581 return -EINVAL; 582 } 583 584 adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 585 586 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0, 587 ADCX140_FSYNCINV_BIT | 588 ADCX140_BCLKINV_BIT | 589 ADCX140_ASI_FORMAT_MSK, 590 iface_reg1); 591 snd_soc_component_update_bits(component, ADCX140_MST_CFG0, 592 ADCX140_BCLK_FSYNC_MASTER, iface_reg2); 593 594 return 0; 595 } 596 597 static int adcx140_set_dai_tdm_slot(struct snd_soc_dai *codec_dai, 598 unsigned int tx_mask, unsigned int rx_mask, 599 int slots, int slot_width) 600 { 601 struct snd_soc_component *component = codec_dai->component; 602 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 603 unsigned int lsb; 604 605 if (tx_mask != rx_mask) { 606 dev_err(component->dev, "tx and rx masks must be symmetric\n"); 607 return -EINVAL; 608 } 609 610 /* TDM based on DSP mode requires slots to be adjacent */ 611 lsb = __ffs(tx_mask); 612 if ((lsb + 1) != __fls(tx_mask)) { 613 dev_err(component->dev, "Invalid mask, slots must be adjacent\n"); 614 return -EINVAL; 615 } 616 617 switch (slot_width) { 618 case 16: 619 case 20: 620 case 24: 621 case 32: 622 break; 623 default: 624 dev_err(component->dev, "Unsupported slot width %d\n", slot_width); 625 return -EINVAL; 626 } 627 628 adcx140->tdm_delay = lsb; 629 adcx140->slot_width = slot_width; 630 631 return 0; 632 } 633 634 static int adcx140_prepare(struct snd_pcm_substream *substream, 635 struct snd_soc_dai *dai) 636 { 637 struct snd_soc_component *component = dai->component; 638 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 639 int offset = 0; 640 int width = adcx140->slot_width; 641 642 if (!width) 643 width = substream->runtime->sample_bits; 644 645 /* TDM slot selection only valid in DSP_A/_B mode */ 646 if (adcx140->dai_fmt == SND_SOC_DAIFMT_DSP_A) 647 offset += (adcx140->tdm_delay * width + 1); 648 else if (adcx140->dai_fmt == SND_SOC_DAIFMT_DSP_B) 649 offset += adcx140->tdm_delay * width; 650 651 /* Configure data offset */ 652 snd_soc_component_update_bits(component, ADCX140_ASI_CFG1, 653 ADCX140_TX_OFFSET_MASK, offset); 654 655 return 0; 656 } 657 658 static const struct snd_soc_dai_ops adcx140_dai_ops = { 659 .hw_params = adcx140_hw_params, 660 .set_fmt = adcx140_set_dai_fmt, 661 .prepare = adcx140_prepare, 662 .set_tdm_slot = adcx140_set_dai_tdm_slot, 663 }; 664 665 static int adcx140_codec_probe(struct snd_soc_component *component) 666 { 667 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 668 int sleep_cfg_val = ADCX140_WAKE_DEV; 669 u8 bias_source; 670 u8 vref_source; 671 int ret; 672 673 ret = device_property_read_u8(adcx140->dev, "ti,mic-bias-source", 674 &bias_source); 675 if (ret) 676 bias_source = ADCX140_MIC_BIAS_VAL_VREF; 677 678 if (bias_source != ADCX140_MIC_BIAS_VAL_VREF && 679 bias_source != ADCX140_MIC_BIAS_VAL_VREF_1096 && 680 bias_source != ADCX140_MIC_BIAS_VAL_AVDD) { 681 dev_err(adcx140->dev, "Mic Bias source value is invalid\n"); 682 return -EINVAL; 683 } 684 685 ret = device_property_read_u8(adcx140->dev, "ti,vref-source", 686 &vref_source); 687 if (ret) 688 vref_source = ADCX140_MIC_BIAS_VREF_275V; 689 690 if (vref_source != ADCX140_MIC_BIAS_VREF_275V && 691 vref_source != ADCX140_MIC_BIAS_VREF_25V && 692 vref_source != ADCX140_MIC_BIAS_VREF_1375V) { 693 dev_err(adcx140->dev, "Mic Bias source value is invalid\n"); 694 return -EINVAL; 695 } 696 697 bias_source |= vref_source; 698 699 ret = adcx140_reset(adcx140); 700 if (ret) 701 goto out; 702 703 if(adcx140->supply_areg == NULL) 704 sleep_cfg_val |= ADCX140_AREG_INTERNAL; 705 706 ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val); 707 if (ret) { 708 dev_err(adcx140->dev, "setting sleep config failed %d\n", ret); 709 goto out; 710 } 711 712 /* 8.4.3: Wait >= 1ms after entering active mode. */ 713 usleep_range(1000, 100000); 714 715 ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG, 716 ADCX140_MIC_BIAS_VAL_MSK | 717 ADCX140_MIC_BIAS_VREF_MSK, bias_source); 718 if (ret) 719 dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret); 720 out: 721 return ret; 722 } 723 724 static int adcx140_set_bias_level(struct snd_soc_component *component, 725 enum snd_soc_bias_level level) 726 { 727 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 728 int pwr_cfg = 0; 729 730 switch (level) { 731 case SND_SOC_BIAS_ON: 732 case SND_SOC_BIAS_PREPARE: 733 case SND_SOC_BIAS_STANDBY: 734 pwr_cfg = ADCX140_PWR_CFG_BIAS_PDZ | ADCX140_PWR_CFG_PLL_PDZ | 735 ADCX140_PWR_CFG_ADC_PDZ; 736 break; 737 case SND_SOC_BIAS_OFF: 738 pwr_cfg = 0x0; 739 break; 740 } 741 742 return regmap_write(adcx140->regmap, ADCX140_PWR_CFG, pwr_cfg); 743 } 744 745 static const struct snd_soc_component_driver soc_codec_driver_adcx140 = { 746 .probe = adcx140_codec_probe, 747 .set_bias_level = adcx140_set_bias_level, 748 .controls = adcx140_snd_controls, 749 .num_controls = ARRAY_SIZE(adcx140_snd_controls), 750 .dapm_widgets = adcx140_dapm_widgets, 751 .num_dapm_widgets = ARRAY_SIZE(adcx140_dapm_widgets), 752 .dapm_routes = adcx140_audio_map, 753 .num_dapm_routes = ARRAY_SIZE(adcx140_audio_map), 754 .suspend_bias_off = 1, 755 .idle_bias_on = 0, 756 .use_pmdown_time = 1, 757 .endianness = 1, 758 .non_legacy_dai_naming = 1, 759 }; 760 761 static struct snd_soc_dai_driver adcx140_dai_driver[] = { 762 { 763 .name = "tlv320adcx140-codec", 764 .capture = { 765 .stream_name = "Capture", 766 .channels_min = 2, 767 .channels_max = ADCX140_MAX_CHANNELS, 768 .rates = ADCX140_RATES, 769 .formats = ADCX140_FORMATS, 770 }, 771 .ops = &adcx140_dai_ops, 772 .symmetric_rates = 1, 773 } 774 }; 775 776 static const struct of_device_id tlv320adcx140_of_match[] = { 777 { .compatible = "ti,tlv320adc3140" }, 778 { .compatible = "ti,tlv320adc5140" }, 779 { .compatible = "ti,tlv320adc6140" }, 780 {}, 781 }; 782 MODULE_DEVICE_TABLE(of, tlv320adcx140_of_match); 783 784 static int adcx140_i2c_probe(struct i2c_client *i2c, 785 const struct i2c_device_id *id) 786 { 787 struct adcx140_priv *adcx140; 788 int ret; 789 790 adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL); 791 if (!adcx140) 792 return -ENOMEM; 793 794 adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev, 795 "reset", GPIOD_OUT_LOW); 796 if (IS_ERR(adcx140->gpio_reset)) 797 dev_info(&i2c->dev, "Reset GPIO not defined\n"); 798 799 adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev, 800 "areg"); 801 if (IS_ERR(adcx140->supply_areg)) { 802 if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER) 803 return -EPROBE_DEFER; 804 else 805 adcx140->supply_areg = NULL; 806 } else { 807 ret = regulator_enable(adcx140->supply_areg); 808 if (ret) { 809 dev_err(adcx140->dev, "Failed to enable areg\n"); 810 return ret; 811 } 812 } 813 814 adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap); 815 if (IS_ERR(adcx140->regmap)) { 816 ret = PTR_ERR(adcx140->regmap); 817 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 818 ret); 819 return ret; 820 } 821 adcx140->dev = &i2c->dev; 822 i2c_set_clientdata(i2c, adcx140); 823 824 return devm_snd_soc_register_component(&i2c->dev, 825 &soc_codec_driver_adcx140, 826 adcx140_dai_driver, 1); 827 } 828 829 static const struct i2c_device_id adcx140_i2c_id[] = { 830 { "tlv320adc3140", 0 }, 831 { "tlv320adc5140", 1 }, 832 { "tlv320adc6140", 2 }, 833 {} 834 }; 835 MODULE_DEVICE_TABLE(i2c, adcx140_i2c_id); 836 837 static struct i2c_driver adcx140_i2c_driver = { 838 .driver = { 839 .name = "tlv320adcx140-codec", 840 .of_match_table = of_match_ptr(tlv320adcx140_of_match), 841 }, 842 .probe = adcx140_i2c_probe, 843 .id_table = adcx140_i2c_id, 844 }; 845 module_i2c_driver(adcx140_i2c_driver); 846 847 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 848 MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver"); 849 MODULE_LICENSE("GPL v2"); 850