1 // SPDX-License-Identifier: GPL-2.0 2 // TLV320ADCX140 Sound driver 3 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 4 5 #include <linux/module.h> 6 #include <linux/moduleparam.h> 7 #include <linux/init.h> 8 #include <linux/delay.h> 9 #include <linux/pm.h> 10 #include <linux/i2c.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/regulator/consumer.h> 13 #include <linux/acpi.h> 14 #include <linux/of.h> 15 #include <linux/of_gpio.h> 16 #include <linux/slab.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/initval.h> 22 #include <sound/tlv.h> 23 24 #include "tlv320adcx140.h" 25 26 struct adcx140_priv { 27 struct snd_soc_component *component; 28 struct regulator *supply_areg; 29 struct gpio_desc *gpio_reset; 30 struct regmap *regmap; 31 struct device *dev; 32 33 int micbias_vg; 34 35 unsigned int dai_fmt; 36 unsigned int tdm_delay; 37 unsigned int slot_width; 38 }; 39 40 static const struct reg_default adcx140_reg_defaults[] = { 41 { ADCX140_PAGE_SELECT, 0x00 }, 42 { ADCX140_SW_RESET, 0x00 }, 43 { ADCX140_SLEEP_CFG, 0x00 }, 44 { ADCX140_SHDN_CFG, 0x05 }, 45 { ADCX140_ASI_CFG0, 0x30 }, 46 { ADCX140_ASI_CFG1, 0x00 }, 47 { ADCX140_ASI_CFG2, 0x00 }, 48 { ADCX140_ASI_CH1, 0x00 }, 49 { ADCX140_ASI_CH2, 0x01 }, 50 { ADCX140_ASI_CH3, 0x02 }, 51 { ADCX140_ASI_CH4, 0x03 }, 52 { ADCX140_ASI_CH5, 0x04 }, 53 { ADCX140_ASI_CH6, 0x05 }, 54 { ADCX140_ASI_CH7, 0x06 }, 55 { ADCX140_ASI_CH8, 0x07 }, 56 { ADCX140_MST_CFG0, 0x02 }, 57 { ADCX140_MST_CFG1, 0x48 }, 58 { ADCX140_ASI_STS, 0xff }, 59 { ADCX140_CLK_SRC, 0x10 }, 60 { ADCX140_PDMCLK_CFG, 0x40 }, 61 { ADCX140_PDM_CFG, 0x00 }, 62 { ADCX140_GPIO_CFG0, 0x22 }, 63 { ADCX140_GPO_CFG1, 0x00 }, 64 { ADCX140_GPO_CFG2, 0x00 }, 65 { ADCX140_GPO_CFG3, 0x00 }, 66 { ADCX140_GPO_CFG4, 0x00 }, 67 { ADCX140_GPO_VAL, 0x00 }, 68 { ADCX140_GPIO_MON, 0x00 }, 69 { ADCX140_GPI_CFG0, 0x00 }, 70 { ADCX140_GPI_CFG1, 0x00 }, 71 { ADCX140_GPI_MON, 0x00 }, 72 { ADCX140_INT_CFG, 0x00 }, 73 { ADCX140_INT_MASK0, 0xff }, 74 { ADCX140_INT_LTCH0, 0x00 }, 75 { ADCX140_BIAS_CFG, 0x00 }, 76 { ADCX140_CH1_CFG0, 0x00 }, 77 { ADCX140_CH1_CFG1, 0x00 }, 78 { ADCX140_CH1_CFG2, 0xc9 }, 79 { ADCX140_CH1_CFG3, 0x80 }, 80 { ADCX140_CH1_CFG4, 0x00 }, 81 { ADCX140_CH2_CFG0, 0x00 }, 82 { ADCX140_CH2_CFG1, 0x00 }, 83 { ADCX140_CH2_CFG2, 0xc9 }, 84 { ADCX140_CH2_CFG3, 0x80 }, 85 { ADCX140_CH2_CFG4, 0x00 }, 86 { ADCX140_CH3_CFG0, 0x00 }, 87 { ADCX140_CH3_CFG1, 0x00 }, 88 { ADCX140_CH3_CFG2, 0xc9 }, 89 { ADCX140_CH3_CFG3, 0x80 }, 90 { ADCX140_CH3_CFG4, 0x00 }, 91 { ADCX140_CH4_CFG0, 0x00 }, 92 { ADCX140_CH4_CFG1, 0x00 }, 93 { ADCX140_CH4_CFG2, 0xc9 }, 94 { ADCX140_CH4_CFG3, 0x80 }, 95 { ADCX140_CH4_CFG4, 0x00 }, 96 { ADCX140_CH5_CFG2, 0xc9 }, 97 { ADCX140_CH5_CFG3, 0x80 }, 98 { ADCX140_CH5_CFG4, 0x00 }, 99 { ADCX140_CH6_CFG2, 0xc9 }, 100 { ADCX140_CH6_CFG3, 0x80 }, 101 { ADCX140_CH6_CFG4, 0x00 }, 102 { ADCX140_CH7_CFG2, 0xc9 }, 103 { ADCX140_CH7_CFG3, 0x80 }, 104 { ADCX140_CH7_CFG4, 0x00 }, 105 { ADCX140_CH8_CFG2, 0xc9 }, 106 { ADCX140_CH8_CFG3, 0x80 }, 107 { ADCX140_CH8_CFG4, 0x00 }, 108 { ADCX140_DSP_CFG0, 0x01 }, 109 { ADCX140_DSP_CFG1, 0x40 }, 110 { ADCX140_DRE_CFG0, 0x7b }, 111 { ADCX140_AGC_CFG0, 0xe7 }, 112 { ADCX140_IN_CH_EN, 0xf0 }, 113 { ADCX140_ASI_OUT_CH_EN, 0x00 }, 114 { ADCX140_PWR_CFG, 0x00 }, 115 { ADCX140_DEV_STS0, 0x00 }, 116 { ADCX140_DEV_STS1, 0x80 }, 117 }; 118 119 static const struct regmap_range_cfg adcx140_ranges[] = { 120 { 121 .range_min = 0, 122 .range_max = 12 * 128, 123 .selector_reg = ADCX140_PAGE_SELECT, 124 .selector_mask = 0xff, 125 .selector_shift = 0, 126 .window_start = 0, 127 .window_len = 128, 128 }, 129 }; 130 131 static bool adcx140_volatile(struct device *dev, unsigned int reg) 132 { 133 switch (reg) { 134 case ADCX140_SW_RESET: 135 case ADCX140_DEV_STS0: 136 case ADCX140_DEV_STS1: 137 case ADCX140_ASI_STS: 138 return true; 139 default: 140 return false; 141 } 142 } 143 144 static const struct regmap_config adcx140_i2c_regmap = { 145 .reg_bits = 8, 146 .val_bits = 8, 147 .reg_defaults = adcx140_reg_defaults, 148 .num_reg_defaults = ARRAY_SIZE(adcx140_reg_defaults), 149 .cache_type = REGCACHE_FLAT, 150 .ranges = adcx140_ranges, 151 .num_ranges = ARRAY_SIZE(adcx140_ranges), 152 .max_register = 12 * 128, 153 .volatile_reg = adcx140_volatile, 154 }; 155 156 /* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */ 157 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10000, 50, 0); 158 159 /* ADC gain. From 0 to 42 dB in 1 dB steps */ 160 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0); 161 162 /* DRE Level. From -12 dB to -66 dB in 1 dB steps */ 163 static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0); 164 /* DRE Max Gain. From 2 dB to 26 dB in 2 dB steps */ 165 static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0); 166 167 /* AGC Level. From -6 dB to -36 dB in 2 dB steps */ 168 static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0); 169 /* AGC Max Gain. From 3 dB to 42 dB in 3 dB steps */ 170 static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0); 171 172 static const char * const decimation_filter_text[] = { 173 "Linear Phase", "Low Latency", "Ultra-low Latency" 174 }; 175 176 static SOC_ENUM_SINGLE_DECL(decimation_filter_enum, ADCX140_DSP_CFG0, 4, 177 decimation_filter_text); 178 179 static const struct snd_kcontrol_new decimation_filter_controls[] = { 180 SOC_DAPM_ENUM("Decimation Filter", decimation_filter_enum), 181 }; 182 183 static const char * const pdmclk_text[] = { 184 "2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz" 185 }; 186 187 static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0, 188 pdmclk_text); 189 190 static const struct snd_kcontrol_new pdmclk_div_controls[] = { 191 SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum), 192 }; 193 194 static const char * const resistor_text[] = { 195 "2.5 kOhm", "10 kOhm", "20 kOhm" 196 }; 197 198 static SOC_ENUM_SINGLE_DECL(in1_resistor_enum, ADCX140_CH1_CFG0, 2, 199 resistor_text); 200 static SOC_ENUM_SINGLE_DECL(in2_resistor_enum, ADCX140_CH2_CFG0, 2, 201 resistor_text); 202 static SOC_ENUM_SINGLE_DECL(in3_resistor_enum, ADCX140_CH3_CFG0, 2, 203 resistor_text); 204 static SOC_ENUM_SINGLE_DECL(in4_resistor_enum, ADCX140_CH4_CFG0, 2, 205 resistor_text); 206 207 static const struct snd_kcontrol_new in1_resistor_controls[] = { 208 SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum), 209 }; 210 static const struct snd_kcontrol_new in2_resistor_controls[] = { 211 SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum), 212 }; 213 static const struct snd_kcontrol_new in3_resistor_controls[] = { 214 SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum), 215 }; 216 static const struct snd_kcontrol_new in4_resistor_controls[] = { 217 SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum), 218 }; 219 220 /* Analog/Digital Selection */ 221 static const char *adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"}; 222 static const char *adcx140_analog_sel_text[] = {"Analog", "Line In"}; 223 224 static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum, 225 ADCX140_CH1_CFG0, 5, 226 adcx140_mic_sel_text); 227 228 static const struct snd_kcontrol_new adcx140_dapm_mic1p_control = 229 SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum); 230 231 static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum, 232 ADCX140_CH1_CFG0, 7, 233 adcx140_analog_sel_text); 234 235 static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control = 236 SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum); 237 238 static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum, 239 ADCX140_CH1_CFG0, 5, 240 adcx140_mic_sel_text); 241 242 static const struct snd_kcontrol_new adcx140_dapm_mic1m_control = 243 SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum); 244 245 static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum, 246 ADCX140_CH2_CFG0, 5, 247 adcx140_mic_sel_text); 248 249 static const struct snd_kcontrol_new adcx140_dapm_mic2p_control = 250 SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum); 251 252 static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum, 253 ADCX140_CH2_CFG0, 7, 254 adcx140_analog_sel_text); 255 256 static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control = 257 SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum); 258 259 static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum, 260 ADCX140_CH2_CFG0, 5, 261 adcx140_mic_sel_text); 262 263 static const struct snd_kcontrol_new adcx140_dapm_mic2m_control = 264 SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum); 265 266 static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum, 267 ADCX140_CH3_CFG0, 5, 268 adcx140_mic_sel_text); 269 270 static const struct snd_kcontrol_new adcx140_dapm_mic3p_control = 271 SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum); 272 273 static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum, 274 ADCX140_CH3_CFG0, 7, 275 adcx140_analog_sel_text); 276 277 static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control = 278 SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum); 279 280 static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum, 281 ADCX140_CH3_CFG0, 5, 282 adcx140_mic_sel_text); 283 284 static const struct snd_kcontrol_new adcx140_dapm_mic3m_control = 285 SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum); 286 287 static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum, 288 ADCX140_CH4_CFG0, 5, 289 adcx140_mic_sel_text); 290 291 static const struct snd_kcontrol_new adcx140_dapm_mic4p_control = 292 SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum); 293 294 static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum, 295 ADCX140_CH4_CFG0, 7, 296 adcx140_analog_sel_text); 297 298 static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control = 299 SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum); 300 301 static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum, 302 ADCX140_CH4_CFG0, 5, 303 adcx140_mic_sel_text); 304 305 static const struct snd_kcontrol_new adcx140_dapm_mic4m_control = 306 SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum); 307 308 static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch = 309 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0); 310 static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch = 311 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0); 312 static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch = 313 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0); 314 static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch = 315 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0); 316 317 static const struct snd_kcontrol_new adcx140_dapm_ch1_dre_en_switch = 318 SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0); 319 static const struct snd_kcontrol_new adcx140_dapm_ch2_dre_en_switch = 320 SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0); 321 static const struct snd_kcontrol_new adcx140_dapm_ch3_dre_en_switch = 322 SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0); 323 static const struct snd_kcontrol_new adcx140_dapm_ch4_dre_en_switch = 324 SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0); 325 326 static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch = 327 SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0); 328 329 /* Output Mixer */ 330 static const struct snd_kcontrol_new adcx140_output_mixer_controls[] = { 331 SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0), 332 SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0), 333 SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0), 334 SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0), 335 }; 336 337 static const struct snd_soc_dapm_widget adcx140_dapm_widgets[] = { 338 /* Analog Differential Inputs */ 339 SND_SOC_DAPM_INPUT("MIC1P"), 340 SND_SOC_DAPM_INPUT("MIC1M"), 341 SND_SOC_DAPM_INPUT("MIC2P"), 342 SND_SOC_DAPM_INPUT("MIC2M"), 343 SND_SOC_DAPM_INPUT("MIC3P"), 344 SND_SOC_DAPM_INPUT("MIC3M"), 345 SND_SOC_DAPM_INPUT("MIC4P"), 346 SND_SOC_DAPM_INPUT("MIC4M"), 347 348 SND_SOC_DAPM_OUTPUT("CH1_OUT"), 349 SND_SOC_DAPM_OUTPUT("CH2_OUT"), 350 SND_SOC_DAPM_OUTPUT("CH3_OUT"), 351 SND_SOC_DAPM_OUTPUT("CH4_OUT"), 352 SND_SOC_DAPM_OUTPUT("CH5_OUT"), 353 SND_SOC_DAPM_OUTPUT("CH6_OUT"), 354 SND_SOC_DAPM_OUTPUT("CH7_OUT"), 355 SND_SOC_DAPM_OUTPUT("CH8_OUT"), 356 357 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0, 358 &adcx140_output_mixer_controls[0], 359 ARRAY_SIZE(adcx140_output_mixer_controls)), 360 361 /* Input Selection to MIC_PGA */ 362 SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0, 363 &adcx140_dapm_mic1p_control), 364 SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0, 365 &adcx140_dapm_mic2p_control), 366 SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0, 367 &adcx140_dapm_mic3p_control), 368 SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0, 369 &adcx140_dapm_mic4p_control), 370 371 /* Input Selection to MIC_PGA */ 372 SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0, 373 &adcx140_dapm_mic1_analog_control), 374 SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0, 375 &adcx140_dapm_mic2_analog_control), 376 SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0, 377 &adcx140_dapm_mic3_analog_control), 378 SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0, 379 &adcx140_dapm_mic4_analog_control), 380 381 SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0, 382 &adcx140_dapm_mic1m_control), 383 SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0, 384 &adcx140_dapm_mic2m_control), 385 SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0, 386 &adcx140_dapm_mic3m_control), 387 SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0, 388 &adcx140_dapm_mic4m_control), 389 390 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0), 391 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0), 392 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0), 393 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0), 394 395 SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0), 396 SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0), 397 SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0), 398 SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0), 399 400 SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0, 401 &adcx140_dapm_ch1_en_switch), 402 SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0, 403 &adcx140_dapm_ch2_en_switch), 404 SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0, 405 &adcx140_dapm_ch3_en_switch), 406 SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0, 407 &adcx140_dapm_ch4_en_switch), 408 409 SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0, 410 &adcx140_dapm_dre_en_switch), 411 412 SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0, 413 &adcx140_dapm_ch1_dre_en_switch), 414 SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0, 415 &adcx140_dapm_ch2_dre_en_switch), 416 SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0, 417 &adcx140_dapm_ch3_dre_en_switch), 418 SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0, 419 &adcx140_dapm_ch4_dre_en_switch), 420 421 SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 422 in1_resistor_controls), 423 SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 424 in2_resistor_controls), 425 SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 426 in3_resistor_controls), 427 SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0, 428 in4_resistor_controls), 429 430 SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM, 0, 0, 431 pdmclk_div_controls), 432 433 SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0, 434 decimation_filter_controls), 435 }; 436 437 static const struct snd_soc_dapm_route adcx140_audio_map[] = { 438 /* Outputs */ 439 {"CH1_OUT", NULL, "Output Mixer"}, 440 {"CH2_OUT", NULL, "Output Mixer"}, 441 {"CH3_OUT", NULL, "Output Mixer"}, 442 {"CH4_OUT", NULL, "Output Mixer"}, 443 444 {"CH1_ASI_EN", "Switch", "CH1_ADC"}, 445 {"CH2_ASI_EN", "Switch", "CH2_ADC"}, 446 {"CH3_ASI_EN", "Switch", "CH3_ADC"}, 447 {"CH4_ASI_EN", "Switch", "CH4_ADC"}, 448 449 {"Decimation Filter", "Linear Phase", "DRE_ENABLE"}, 450 {"Decimation Filter", "Low Latency", "DRE_ENABLE"}, 451 {"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"}, 452 453 {"DRE_ENABLE", "Switch", "CH1_DRE_EN"}, 454 {"DRE_ENABLE", "Switch", "CH2_DRE_EN"}, 455 {"DRE_ENABLE", "Switch", "CH3_DRE_EN"}, 456 {"DRE_ENABLE", "Switch", "CH4_DRE_EN"}, 457 458 {"CH1_DRE_EN", "Switch", "CH1_ADC"}, 459 {"CH2_DRE_EN", "Switch", "CH2_ADC"}, 460 {"CH3_DRE_EN", "Switch", "CH3_ADC"}, 461 {"CH4_DRE_EN", "Switch", "CH4_ADC"}, 462 463 /* Mic input */ 464 {"CH1_ADC", NULL, "MIC_GAIN_CTL_CH1"}, 465 {"CH2_ADC", NULL, "MIC_GAIN_CTL_CH2"}, 466 {"CH3_ADC", NULL, "MIC_GAIN_CTL_CH3"}, 467 {"CH4_ADC", NULL, "MIC_GAIN_CTL_CH4"}, 468 469 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"}, 470 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"}, 471 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"}, 472 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"}, 473 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"}, 474 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"}, 475 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"}, 476 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"}, 477 478 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"}, 479 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"}, 480 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"}, 481 482 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"}, 483 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"}, 484 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"}, 485 486 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"}, 487 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"}, 488 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"}, 489 490 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"}, 491 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"}, 492 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"}, 493 494 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"}, 495 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"}, 496 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"}, 497 498 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"}, 499 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"}, 500 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"}, 501 502 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"}, 503 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"}, 504 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"}, 505 506 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"}, 507 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"}, 508 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"}, 509 510 {"PDM Clk Div Select", "2.8224 MHz", "MIC1P Input Mux"}, 511 {"PDM Clk Div Select", "1.4112 MHz", "MIC1P Input Mux"}, 512 {"PDM Clk Div Select", "705.6 kHz", "MIC1P Input Mux"}, 513 {"PDM Clk Div Select", "5.6448 MHz", "MIC1P Input Mux"}, 514 515 {"MIC1 Analog Mux", "Line In", "MIC1P"}, 516 {"MIC2 Analog Mux", "Line In", "MIC2P"}, 517 {"MIC3 Analog Mux", "Line In", "MIC3P"}, 518 {"MIC4 Analog Mux", "Line In", "MIC4P"}, 519 520 {"MIC1P Input Mux", "Analog", "MIC1P"}, 521 {"MIC1M Input Mux", "Analog", "MIC1M"}, 522 {"MIC2P Input Mux", "Analog", "MIC2P"}, 523 {"MIC2M Input Mux", "Analog", "MIC2M"}, 524 {"MIC3P Input Mux", "Analog", "MIC3P"}, 525 {"MIC3M Input Mux", "Analog", "MIC3M"}, 526 {"MIC4P Input Mux", "Analog", "MIC4P"}, 527 {"MIC4M Input Mux", "Analog", "MIC4M"}, 528 }; 529 530 static const struct snd_kcontrol_new adcx140_snd_controls[] = { 531 SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0, 532 adc_tlv), 533 SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0, 534 adc_tlv), 535 SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0, 536 adc_tlv), 537 SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0, 538 adc_tlv), 539 540 SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0, 541 dre_thresh_tlv), 542 SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0, 543 dre_gain_tlv), 544 545 SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0, 546 agc_thresh_tlv), 547 SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0, 548 agc_gain_tlv), 549 550 SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2, 551 0, 0xff, 0, dig_vol_tlv), 552 SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2, 553 0, 0xff, 0, dig_vol_tlv), 554 SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2, 555 0, 0xff, 0, dig_vol_tlv), 556 SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2, 557 0, 0xff, 0, dig_vol_tlv), 558 SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2, 559 0, 0xff, 0, dig_vol_tlv), 560 SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2, 561 0, 0xff, 0, dig_vol_tlv), 562 SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2, 563 0, 0xff, 0, dig_vol_tlv), 564 SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2, 565 0, 0xff, 0, dig_vol_tlv), 566 }; 567 568 static int adcx140_reset(struct adcx140_priv *adcx140) 569 { 570 int ret = 0; 571 572 if (adcx140->gpio_reset) { 573 gpiod_direction_output(adcx140->gpio_reset, 0); 574 /* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */ 575 usleep_range(30000, 100000); 576 gpiod_direction_output(adcx140->gpio_reset, 1); 577 } else { 578 ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET, 579 ADCX140_RESET); 580 } 581 582 /* 8.4.2: wait >= 10 ms after entering sleep mode. */ 583 usleep_range(10000, 100000); 584 585 return ret; 586 } 587 588 static int adcx140_hw_params(struct snd_pcm_substream *substream, 589 struct snd_pcm_hw_params *params, 590 struct snd_soc_dai *dai) 591 { 592 struct snd_soc_component *component = dai->component; 593 u8 data = 0; 594 595 switch (params_width(params)) { 596 case 16: 597 data = ADCX140_16_BIT_WORD; 598 break; 599 case 20: 600 data = ADCX140_20_BIT_WORD; 601 break; 602 case 24: 603 data = ADCX140_24_BIT_WORD; 604 break; 605 case 32: 606 data = ADCX140_32_BIT_WORD; 607 break; 608 default: 609 dev_err(component->dev, "%s: Unsupported width %d\n", 610 __func__, params_width(params)); 611 return -EINVAL; 612 } 613 614 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0, 615 ADCX140_WORD_LEN_MSK, data); 616 617 return 0; 618 } 619 620 static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai, 621 unsigned int fmt) 622 { 623 struct snd_soc_component *component = codec_dai->component; 624 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 625 u8 iface_reg1 = 0; 626 u8 iface_reg2 = 0; 627 628 /* set master/slave audio interface */ 629 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 630 case SND_SOC_DAIFMT_CBM_CFM: 631 iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER; 632 break; 633 case SND_SOC_DAIFMT_CBS_CFS: 634 break; 635 case SND_SOC_DAIFMT_CBS_CFM: 636 case SND_SOC_DAIFMT_CBM_CFS: 637 default: 638 dev_err(component->dev, "Invalid DAI master/slave interface\n"); 639 return -EINVAL; 640 } 641 642 /* signal polarity */ 643 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 644 case SND_SOC_DAIFMT_NB_IF: 645 iface_reg1 |= ADCX140_FSYNCINV_BIT; 646 break; 647 case SND_SOC_DAIFMT_IB_IF: 648 iface_reg1 |= ADCX140_BCLKINV_BIT | ADCX140_FSYNCINV_BIT; 649 break; 650 case SND_SOC_DAIFMT_IB_NF: 651 iface_reg1 |= ADCX140_BCLKINV_BIT; 652 break; 653 case SND_SOC_DAIFMT_NB_NF: 654 break; 655 default: 656 dev_err(component->dev, "Invalid DAI clock signal polarity\n"); 657 return -EINVAL; 658 } 659 660 /* interface format */ 661 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 662 case SND_SOC_DAIFMT_I2S: 663 iface_reg1 |= ADCX140_I2S_MODE_BIT; 664 break; 665 case SND_SOC_DAIFMT_LEFT_J: 666 iface_reg1 |= ADCX140_LEFT_JUST_BIT; 667 break; 668 case SND_SOC_DAIFMT_DSP_A: 669 case SND_SOC_DAIFMT_DSP_B: 670 break; 671 default: 672 dev_err(component->dev, "Invalid DAI interface format\n"); 673 return -EINVAL; 674 } 675 676 adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 677 678 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0, 679 ADCX140_FSYNCINV_BIT | 680 ADCX140_BCLKINV_BIT | 681 ADCX140_ASI_FORMAT_MSK, 682 iface_reg1); 683 snd_soc_component_update_bits(component, ADCX140_MST_CFG0, 684 ADCX140_BCLK_FSYNC_MASTER, iface_reg2); 685 686 return 0; 687 } 688 689 static int adcx140_set_dai_tdm_slot(struct snd_soc_dai *codec_dai, 690 unsigned int tx_mask, unsigned int rx_mask, 691 int slots, int slot_width) 692 { 693 struct snd_soc_component *component = codec_dai->component; 694 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 695 unsigned int lsb; 696 697 if (tx_mask != rx_mask) { 698 dev_err(component->dev, "tx and rx masks must be symmetric\n"); 699 return -EINVAL; 700 } 701 702 /* TDM based on DSP mode requires slots to be adjacent */ 703 lsb = __ffs(tx_mask); 704 if ((lsb + 1) != __fls(tx_mask)) { 705 dev_err(component->dev, "Invalid mask, slots must be adjacent\n"); 706 return -EINVAL; 707 } 708 709 switch (slot_width) { 710 case 16: 711 case 20: 712 case 24: 713 case 32: 714 break; 715 default: 716 dev_err(component->dev, "Unsupported slot width %d\n", slot_width); 717 return -EINVAL; 718 } 719 720 adcx140->tdm_delay = lsb; 721 adcx140->slot_width = slot_width; 722 723 return 0; 724 } 725 726 static int adcx140_prepare(struct snd_pcm_substream *substream, 727 struct snd_soc_dai *dai) 728 { 729 struct snd_soc_component *component = dai->component; 730 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 731 int offset = 0; 732 int width = adcx140->slot_width; 733 734 if (!width) 735 width = substream->runtime->sample_bits; 736 737 /* TDM slot selection only valid in DSP_A/_B mode */ 738 if (adcx140->dai_fmt == SND_SOC_DAIFMT_DSP_A) 739 offset += (adcx140->tdm_delay * width + 1); 740 else if (adcx140->dai_fmt == SND_SOC_DAIFMT_DSP_B) 741 offset += adcx140->tdm_delay * width; 742 743 /* Configure data offset */ 744 snd_soc_component_update_bits(component, ADCX140_ASI_CFG1, 745 ADCX140_TX_OFFSET_MASK, offset); 746 747 return 0; 748 } 749 750 static const struct snd_soc_dai_ops adcx140_dai_ops = { 751 .hw_params = adcx140_hw_params, 752 .set_fmt = adcx140_set_dai_fmt, 753 .prepare = adcx140_prepare, 754 .set_tdm_slot = adcx140_set_dai_tdm_slot, 755 }; 756 757 static int adcx140_codec_probe(struct snd_soc_component *component) 758 { 759 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 760 int sleep_cfg_val = ADCX140_WAKE_DEV; 761 u32 bias_source; 762 u32 vref_source; 763 u8 bias_cfg; 764 int pdm_count; 765 u32 pdm_edges[ADCX140_NUM_PDM_EDGES]; 766 u32 pdm_edge_val = 0; 767 int gpi_count; 768 u32 gpi_inputs[ADCX140_NUM_GPI_PINS]; 769 u32 gpi_input_val = 0; 770 int i; 771 int ret; 772 773 ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source", 774 &bias_source); 775 if (ret) 776 bias_source = ADCX140_MIC_BIAS_VAL_VREF; 777 778 if (bias_source > ADCX140_MIC_BIAS_VAL_AVDD) { 779 dev_err(adcx140->dev, "Mic Bias source value is invalid\n"); 780 return -EINVAL; 781 } 782 783 ret = device_property_read_u32(adcx140->dev, "ti,vref-source", 784 &vref_source); 785 if (ret) 786 vref_source = ADCX140_MIC_BIAS_VREF_275V; 787 788 if (vref_source > ADCX140_MIC_BIAS_VREF_1375V) { 789 dev_err(adcx140->dev, "Mic Bias source value is invalid\n"); 790 return -EINVAL; 791 } 792 793 bias_cfg = bias_source << ADCX140_MIC_BIAS_SHIFT | vref_source; 794 795 pdm_count = device_property_count_u32(adcx140->dev, 796 "ti,pdm-edge-select"); 797 if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) { 798 ret = device_property_read_u32_array(adcx140->dev, 799 "ti,pdm-edge-select", 800 pdm_edges, pdm_count); 801 if (ret) 802 return ret; 803 804 for (i = 0; i < pdm_count; i++) 805 pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i); 806 807 ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG, 808 pdm_edge_val); 809 if (ret) 810 return ret; 811 } 812 813 gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config"); 814 if (gpi_count <= ADCX140_NUM_GPI_PINS && gpi_count > 0) { 815 ret = device_property_read_u32_array(adcx140->dev, 816 "ti,gpi-config", 817 gpi_inputs, gpi_count); 818 if (ret) 819 return ret; 820 821 gpi_input_val = gpi_inputs[ADCX140_GPI1_INDEX] << ADCX140_GPI_SHIFT | 822 gpi_inputs[ADCX140_GPI2_INDEX]; 823 824 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0, 825 gpi_input_val); 826 if (ret) 827 return ret; 828 829 gpi_input_val = gpi_inputs[ADCX140_GPI3_INDEX] << ADCX140_GPI_SHIFT | 830 gpi_inputs[ADCX140_GPI4_INDEX]; 831 832 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1, 833 gpi_input_val); 834 if (ret) 835 return ret; 836 } 837 838 ret = adcx140_reset(adcx140); 839 if (ret) 840 goto out; 841 842 if(adcx140->supply_areg == NULL) 843 sleep_cfg_val |= ADCX140_AREG_INTERNAL; 844 845 ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val); 846 if (ret) { 847 dev_err(adcx140->dev, "setting sleep config failed %d\n", ret); 848 goto out; 849 } 850 851 /* 8.4.3: Wait >= 1ms after entering active mode. */ 852 usleep_range(1000, 100000); 853 854 ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG, 855 ADCX140_MIC_BIAS_VAL_MSK | 856 ADCX140_MIC_BIAS_VREF_MSK, bias_cfg); 857 if (ret) 858 dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret); 859 out: 860 return ret; 861 } 862 863 static int adcx140_set_bias_level(struct snd_soc_component *component, 864 enum snd_soc_bias_level level) 865 { 866 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); 867 int pwr_cfg = 0; 868 869 switch (level) { 870 case SND_SOC_BIAS_ON: 871 case SND_SOC_BIAS_PREPARE: 872 case SND_SOC_BIAS_STANDBY: 873 pwr_cfg = ADCX140_PWR_CFG_BIAS_PDZ | ADCX140_PWR_CFG_PLL_PDZ | 874 ADCX140_PWR_CFG_ADC_PDZ; 875 break; 876 case SND_SOC_BIAS_OFF: 877 pwr_cfg = 0x0; 878 break; 879 } 880 881 return regmap_write(adcx140->regmap, ADCX140_PWR_CFG, pwr_cfg); 882 } 883 884 static const struct snd_soc_component_driver soc_codec_driver_adcx140 = { 885 .probe = adcx140_codec_probe, 886 .set_bias_level = adcx140_set_bias_level, 887 .controls = adcx140_snd_controls, 888 .num_controls = ARRAY_SIZE(adcx140_snd_controls), 889 .dapm_widgets = adcx140_dapm_widgets, 890 .num_dapm_widgets = ARRAY_SIZE(adcx140_dapm_widgets), 891 .dapm_routes = adcx140_audio_map, 892 .num_dapm_routes = ARRAY_SIZE(adcx140_audio_map), 893 .suspend_bias_off = 1, 894 .idle_bias_on = 0, 895 .use_pmdown_time = 1, 896 .endianness = 1, 897 .non_legacy_dai_naming = 1, 898 }; 899 900 static struct snd_soc_dai_driver adcx140_dai_driver[] = { 901 { 902 .name = "tlv320adcx140-codec", 903 .capture = { 904 .stream_name = "Capture", 905 .channels_min = 2, 906 .channels_max = ADCX140_MAX_CHANNELS, 907 .rates = ADCX140_RATES, 908 .formats = ADCX140_FORMATS, 909 }, 910 .ops = &adcx140_dai_ops, 911 .symmetric_rates = 1, 912 } 913 }; 914 915 static const struct of_device_id tlv320adcx140_of_match[] = { 916 { .compatible = "ti,tlv320adc3140" }, 917 { .compatible = "ti,tlv320adc5140" }, 918 { .compatible = "ti,tlv320adc6140" }, 919 {}, 920 }; 921 MODULE_DEVICE_TABLE(of, tlv320adcx140_of_match); 922 923 static int adcx140_i2c_probe(struct i2c_client *i2c, 924 const struct i2c_device_id *id) 925 { 926 struct adcx140_priv *adcx140; 927 int ret; 928 929 adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL); 930 if (!adcx140) 931 return -ENOMEM; 932 933 adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev, 934 "reset", GPIOD_OUT_LOW); 935 if (IS_ERR(adcx140->gpio_reset)) 936 dev_info(&i2c->dev, "Reset GPIO not defined\n"); 937 938 adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev, 939 "areg"); 940 if (IS_ERR(adcx140->supply_areg)) { 941 if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER) 942 return -EPROBE_DEFER; 943 else 944 adcx140->supply_areg = NULL; 945 } else { 946 ret = regulator_enable(adcx140->supply_areg); 947 if (ret) { 948 dev_err(adcx140->dev, "Failed to enable areg\n"); 949 return ret; 950 } 951 } 952 953 adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap); 954 if (IS_ERR(adcx140->regmap)) { 955 ret = PTR_ERR(adcx140->regmap); 956 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", 957 ret); 958 return ret; 959 } 960 adcx140->dev = &i2c->dev; 961 i2c_set_clientdata(i2c, adcx140); 962 963 return devm_snd_soc_register_component(&i2c->dev, 964 &soc_codec_driver_adcx140, 965 adcx140_dai_driver, 1); 966 } 967 968 static const struct i2c_device_id adcx140_i2c_id[] = { 969 { "tlv320adc3140", 0 }, 970 { "tlv320adc5140", 1 }, 971 { "tlv320adc6140", 2 }, 972 {} 973 }; 974 MODULE_DEVICE_TABLE(i2c, adcx140_i2c_id); 975 976 static struct i2c_driver adcx140_i2c_driver = { 977 .driver = { 978 .name = "tlv320adcx140-codec", 979 .of_match_table = of_match_ptr(tlv320adcx140_of_match), 980 }, 981 .probe = adcx140_i2c_probe, 982 .id_table = adcx140_i2c_id, 983 }; 984 module_i2c_driver(adcx140_i2c_driver); 985 986 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>"); 987 MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver"); 988 MODULE_LICENSE("GPL v2"); 989