1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Based on sound/soc/codecs/tlv320aic3x.c by Vladimir Barinov 4 // 5 // Copyright (C) 2010 Mistral Solutions Pvt Ltd. 6 // Author: Shahina Shaik <shahina.s@mistralsolutions.com> 7 // 8 // Copyright (C) 2014-2018, Ambarella, Inc. 9 // Author: Dongge wu <dgwu@ambarella.com> 10 // 11 // Copyright (C) 2021 Axis Communications AB 12 // Author: Ricard Wanderlof <ricardw@axis.com> 13 // 14 15 #include <dt-bindings/sound/tlv320adc3xxx.h> 16 #include <linux/clk.h> 17 #include <linux/module.h> 18 #include <linux/moduleparam.h> 19 #include <linux/io.h> 20 #include <linux/init.h> 21 #include <linux/delay.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/pm.h> 24 #include <linux/i2c.h> 25 #include <linux/platform_device.h> 26 #include <linux/cdev.h> 27 #include <linux/of_gpio.h> 28 #include <linux/slab.h> 29 #include <sound/core.h> 30 #include <sound/pcm.h> 31 #include <sound/pcm_params.h> 32 #include <sound/soc.h> 33 #include <sound/soc-dapm.h> 34 #include <sound/tlv.h> 35 #include <sound/initval.h> 36 37 /* 38 * General definitions defining exported functionality. 39 */ 40 41 #define ADC3XXX_MICBIAS_PINS 2 42 43 /* Number of GPIO pins exposed via the gpiolib interface */ 44 #define ADC3XXX_GPIOS_MAX 2 45 46 #define ADC3XXX_RATES SNDRV_PCM_RATE_8000_96000 47 #define ADC3XXX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 48 SNDRV_PCM_FMTBIT_S20_3LE | \ 49 SNDRV_PCM_FMTBIT_S24_3LE | \ 50 SNDRV_PCM_FMTBIT_S32_LE) 51 52 /* 53 * PLL modes, to be used for clk_id for set_sysclk callback. 54 * 55 * The default behavior (AUTO) is to take the first matching entry in the clock 56 * table, which is intended to be the PLL based one if there is more than one. 57 * 58 * Setting the clock source using simple-card (clocks or 59 * system-clock-frequency property) sets clk_id = 0 = ADC3XXX_PLL_AUTO. 60 */ 61 #define ADC3XXX_PLL_AUTO 0 /* Use first available mode */ 62 #define ADC3XXX_PLL_ENABLE 1 /* Use PLL for clock generation */ 63 #define ADC3XXX_PLL_BYPASS 2 /* Don't use PLL for clock generation */ 64 65 /* Register definitions. */ 66 67 #define ADC3XXX_PAGE_SIZE 128 68 #define ADC3XXX_REG(page, reg) ((page * ADC3XXX_PAGE_SIZE) + reg) 69 70 /* 71 * Page 0 registers. 72 */ 73 74 #define ADC3XXX_PAGE_SELECT ADC3XXX_REG(0, 0) 75 #define ADC3XXX_RESET ADC3XXX_REG(0, 1) 76 77 /* 2-3 Reserved */ 78 79 #define ADC3XXX_CLKGEN_MUX ADC3XXX_REG(0, 4) 80 #define ADC3XXX_PLL_PROG_PR ADC3XXX_REG(0, 5) 81 #define ADC3XXX_PLL_PROG_J ADC3XXX_REG(0, 6) 82 #define ADC3XXX_PLL_PROG_D_MSB ADC3XXX_REG(0, 7) 83 #define ADC3XXX_PLL_PROG_D_LSB ADC3XXX_REG(0, 8) 84 85 /* 9-17 Reserved */ 86 87 #define ADC3XXX_ADC_NADC ADC3XXX_REG(0, 18) 88 #define ADC3XXX_ADC_MADC ADC3XXX_REG(0, 19) 89 #define ADC3XXX_ADC_AOSR ADC3XXX_REG(0, 20) 90 #define ADC3XXX_ADC_IADC ADC3XXX_REG(0, 21) 91 92 /* 23-24 Reserved */ 93 94 #define ADC3XXX_CLKOUT_MUX ADC3XXX_REG(0, 25) 95 #define ADC3XXX_CLKOUT_M_DIV ADC3XXX_REG(0, 26) 96 #define ADC3XXX_INTERFACE_CTRL_1 ADC3XXX_REG(0, 27) 97 #define ADC3XXX_CH_OFFSET_1 ADC3XXX_REG(0, 28) 98 #define ADC3XXX_INTERFACE_CTRL_2 ADC3XXX_REG(0, 29) 99 #define ADC3XXX_BCLK_N_DIV ADC3XXX_REG(0, 30) 100 #define ADC3XXX_INTERFACE_CTRL_3 ADC3XXX_REG(0, 31) 101 #define ADC3XXX_INTERFACE_CTRL_4 ADC3XXX_REG(0, 32) 102 #define ADC3XXX_INTERFACE_CTRL_5 ADC3XXX_REG(0, 33) 103 #define ADC3XXX_I2S_SYNC ADC3XXX_REG(0, 34) 104 /* 35 Reserved */ 105 #define ADC3XXX_ADC_FLAG ADC3XXX_REG(0, 36) 106 #define ADC3XXX_CH_OFFSET_2 ADC3XXX_REG(0, 37) 107 #define ADC3XXX_I2S_TDM_CTRL ADC3XXX_REG(0, 38) 108 /* 39-41 Reserved */ 109 #define ADC3XXX_INTR_FLAG_1 ADC3XXX_REG(0, 42) 110 #define ADC3XXX_INTR_FLAG_2 ADC3XXX_REG(0, 43) 111 /* 44 Reserved */ 112 #define ADC3XXX_INTR_FLAG_ADC1 ADC3XXX_REG(0, 45) 113 /* 46 Reserved */ 114 #define ADC3XXX_INTR_FLAG_ADC2 ADC3XXX_REG(0, 47) 115 #define ADC3XXX_INT1_CTRL ADC3XXX_REG(0, 48) 116 #define ADC3XXX_INT2_CTRL ADC3XXX_REG(0, 49) 117 /* 50 Reserved */ 118 #define ADC3XXX_GPIO2_CTRL ADC3XXX_REG(0, 51) 119 #define ADC3XXX_GPIO1_CTRL ADC3XXX_REG(0, 52) 120 #define ADC3XXX_DOUT_CTRL ADC3XXX_REG(0, 53) 121 /* 54-56 Reserved */ 122 #define ADC3XXX_SYNC_CTRL_1 ADC3XXX_REG(0, 57) 123 #define ADC3XXX_SYNC_CTRL_2 ADC3XXX_REG(0, 58) 124 #define ADC3XXX_CIC_GAIN_CTRL ADC3XXX_REG(0, 59) 125 /* 60 Reserved */ 126 #define ADC3XXX_PRB_SELECT ADC3XXX_REG(0, 61) 127 #define ADC3XXX_INST_MODE_CTRL ADC3XXX_REG(0, 62) 128 /* 63-79 Reserved */ 129 #define ADC3XXX_MIC_POLARITY_CTRL ADC3XXX_REG(0, 80) 130 #define ADC3XXX_ADC_DIGITAL ADC3XXX_REG(0, 81) 131 #define ADC3XXX_ADC_FGA ADC3XXX_REG(0, 82) 132 #define ADC3XXX_LADC_VOL ADC3XXX_REG(0, 83) 133 #define ADC3XXX_RADC_VOL ADC3XXX_REG(0, 84) 134 #define ADC3XXX_ADC_PHASE_COMP ADC3XXX_REG(0, 85) 135 #define ADC3XXX_LEFT_CHN_AGC_1 ADC3XXX_REG(0, 86) 136 #define ADC3XXX_LEFT_CHN_AGC_2 ADC3XXX_REG(0, 87) 137 #define ADC3XXX_LEFT_CHN_AGC_3 ADC3XXX_REG(0, 88) 138 #define ADC3XXX_LEFT_CHN_AGC_4 ADC3XXX_REG(0, 89) 139 #define ADC3XXX_LEFT_CHN_AGC_5 ADC3XXX_REG(0, 90) 140 #define ADC3XXX_LEFT_CHN_AGC_6 ADC3XXX_REG(0, 91) 141 #define ADC3XXX_LEFT_CHN_AGC_7 ADC3XXX_REG(0, 92) 142 #define ADC3XXX_LEFT_AGC_GAIN ADC3XXX_REG(0, 93) 143 #define ADC3XXX_RIGHT_CHN_AGC_1 ADC3XXX_REG(0, 94) 144 #define ADC3XXX_RIGHT_CHN_AGC_2 ADC3XXX_REG(0, 95) 145 #define ADC3XXX_RIGHT_CHN_AGC_3 ADC3XXX_REG(0, 96) 146 #define ADC3XXX_RIGHT_CHN_AGC_4 ADC3XXX_REG(0, 97) 147 #define ADC3XXX_RIGHT_CHN_AGC_5 ADC3XXX_REG(0, 98) 148 #define ADC3XXX_RIGHT_CHN_AGC_6 ADC3XXX_REG(0, 99) 149 #define ADC3XXX_RIGHT_CHN_AGC_7 ADC3XXX_REG(0, 100) 150 #define ADC3XXX_RIGHT_AGC_GAIN ADC3XXX_REG(0, 101) 151 /* 102-127 Reserved */ 152 153 /* 154 * Page 1 registers. 155 */ 156 157 /* 1-25 Reserved */ 158 #define ADC3XXX_DITHER_CTRL ADC3XXX_REG(1, 26) 159 /* 27-50 Reserved */ 160 #define ADC3XXX_MICBIAS_CTRL ADC3XXX_REG(1, 51) 161 #define ADC3XXX_LEFT_PGA_SEL_1 ADC3XXX_REG(1, 52) 162 /* 53 Reserved */ 163 #define ADC3XXX_LEFT_PGA_SEL_2 ADC3XXX_REG(1, 54) 164 #define ADC3XXX_RIGHT_PGA_SEL_1 ADC3XXX_REG(1, 55) 165 #define ADC3XXX_RIGHT_PGA_SEL_2 ADC3XXX_REG(1, 57) 166 #define ADC3XXX_LEFT_APGA_CTRL ADC3XXX_REG(1, 59) 167 #define ADC3XXX_RIGHT_APGA_CTRL ADC3XXX_REG(1, 60) 168 #define ADC3XXX_LOW_CURRENT_MODES ADC3XXX_REG(1, 61) 169 #define ADC3XXX_ANALOG_PGA_FLAGS ADC3XXX_REG(1, 62) 170 /* 63-127 Reserved */ 171 172 /* 173 * Register bits. 174 */ 175 176 /* PLL Enable bits */ 177 #define ADC3XXX_ENABLE_PLL_SHIFT 7 178 #define ADC3XXX_ENABLE_PLL (1 << ADC3XXX_ENABLE_PLL_SHIFT) 179 #define ADC3XXX_ENABLE_NADC_SHIFT 7 180 #define ADC3XXX_ENABLE_NADC (1 << ADC3XXX_ENABLE_NADC_SHIFT) 181 #define ADC3XXX_ENABLE_MADC_SHIFT 7 182 #define ADC3XXX_ENABLE_MADC (1 << ADC3XXX_ENABLE_MADC_SHIFT) 183 #define ADC3XXX_ENABLE_BCLK_SHIFT 7 184 #define ADC3XXX_ENABLE_BCLK (1 << ADC3XXX_ENABLE_BCLK_SHIFT) 185 186 /* Power bits */ 187 #define ADC3XXX_LADC_PWR_ON 0x80 188 #define ADC3XXX_RADC_PWR_ON 0x40 189 190 #define ADC3XXX_SOFT_RESET 0x01 191 #define ADC3XXX_BCLK_MASTER 0x08 192 #define ADC3XXX_WCLK_MASTER 0x04 193 194 /* Interface register masks */ 195 #define ADC3XXX_FORMAT_MASK 0xc0 196 #define ADC3XXX_FORMAT_SHIFT 6 197 #define ADC3XXX_WLENGTH_MASK 0x30 198 #define ADC3XXX_WLENGTH_SHIFT 4 199 #define ADC3XXX_CLKDIR_MASK 0x0c 200 #define ADC3XXX_CLKDIR_SHIFT 2 201 202 /* Interface register bit patterns */ 203 #define ADC3XXX_FORMAT_I2S (0 << ADC3XXX_FORMAT_SHIFT) 204 #define ADC3XXX_FORMAT_DSP (1 << ADC3XXX_FORMAT_SHIFT) 205 #define ADC3XXX_FORMAT_RJF (2 << ADC3XXX_FORMAT_SHIFT) 206 #define ADC3XXX_FORMAT_LJF (3 << ADC3XXX_FORMAT_SHIFT) 207 208 #define ADC3XXX_IFACE_16BITS (0 << ADC3XXX_WLENGTH_SHIFT) 209 #define ADC3XXX_IFACE_20BITS (1 << ADC3XXX_WLENGTH_SHIFT) 210 #define ADC3XXX_IFACE_24BITS (2 << ADC3XXX_WLENGTH_SHIFT) 211 #define ADC3XXX_IFACE_32BITS (3 << ADC3XXX_WLENGTH_SHIFT) 212 213 /* PLL P/R bit offsets */ 214 #define ADC3XXX_PLLP_SHIFT 4 215 #define ADC3XXX_PLLR_SHIFT 0 216 #define ADC3XXX_PLL_PR_MASK 0x7f 217 #define ADC3XXX_PLLJ_MASK 0x3f 218 #define ADC3XXX_PLLD_MSB_MASK 0x3f 219 #define ADC3XXX_PLLD_LSB_MASK 0xff 220 #define ADC3XXX_NADC_MASK 0x7f 221 #define ADC3XXX_MADC_MASK 0x7f 222 #define ADC3XXX_AOSR_MASK 0xff 223 #define ADC3XXX_IADC_MASK 0xff 224 #define ADC3XXX_BDIV_MASK 0x7f 225 226 /* PLL_CLKIN bits */ 227 #define ADC3XXX_PLL_CLKIN_SHIFT 2 228 #define ADC3XXX_PLL_CLKIN_MCLK 0x0 229 #define ADC3XXX_PLL_CLKIN_BCLK 0x1 230 #define ADC3XXX_PLL_CLKIN_ZERO 0x3 231 232 /* CODEC_CLKIN bits */ 233 #define ADC3XXX_CODEC_CLKIN_SHIFT 0 234 #define ADC3XXX_CODEC_CLKIN_MCLK 0x0 235 #define ADC3XXX_CODEC_CLKIN_BCLK 0x1 236 #define ADC3XXX_CODEC_CLKIN_PLL_CLK 0x3 237 238 #define ADC3XXX_USE_PLL ((ADC3XXX_PLL_CLKIN_MCLK << ADC3XXX_PLL_CLKIN_SHIFT) | \ 239 (ADC3XXX_CODEC_CLKIN_PLL_CLK << ADC3XXX_CODEC_CLKIN_SHIFT)) 240 #define ADC3XXX_NO_PLL ((ADC3XXX_PLL_CLKIN_ZERO << ADC3XXX_PLL_CLKIN_SHIFT) | \ 241 (ADC3XXX_CODEC_CLKIN_MCLK << ADC3XXX_CODEC_CLKIN_SHIFT)) 242 243 /* Analog PGA control bits */ 244 #define ADC3XXX_LPGA_MUTE 0x80 245 #define ADC3XXX_RPGA_MUTE 0x80 246 247 #define ADC3XXX_LPGA_GAIN_MASK 0x7f 248 #define ADC3XXX_RPGA_GAIN_MASK 0x7f 249 250 /* ADC current modes */ 251 #define ADC3XXX_ADC_LOW_CURR_MODE 0x01 252 253 /* Left ADC Input selection bits */ 254 #define ADC3XXX_LCH_SEL1_SHIFT 0 255 #define ADC3XXX_LCH_SEL2_SHIFT 2 256 #define ADC3XXX_LCH_SEL3_SHIFT 4 257 #define ADC3XXX_LCH_SEL4_SHIFT 6 258 259 #define ADC3XXX_LCH_SEL1X_SHIFT 0 260 #define ADC3XXX_LCH_SEL2X_SHIFT 2 261 #define ADC3XXX_LCH_SEL3X_SHIFT 4 262 #define ADC3XXX_LCH_COMMON_MODE 0x40 263 #define ADC3XXX_BYPASS_LPGA 0x80 264 265 /* Right ADC Input selection bits */ 266 #define ADC3XXX_RCH_SEL1_SHIFT 0 267 #define ADC3XXX_RCH_SEL2_SHIFT 2 268 #define ADC3XXX_RCH_SEL3_SHIFT 4 269 #define ADC3XXX_RCH_SEL4_SHIFT 6 270 271 #define ADC3XXX_RCH_SEL1X_SHIFT 0 272 #define ADC3XXX_RCH_SEL2X_SHIFT 2 273 #define ADC3XXX_RCH_SEL3X_SHIFT 4 274 #define ADC3XXX_RCH_COMMON_MODE 0x40 275 #define ADC3XXX_BYPASS_RPGA 0x80 276 277 /* MICBIAS control bits */ 278 #define ADC3XXX_MICBIAS_MASK 0x2 279 #define ADC3XXX_MICBIAS1_SHIFT 5 280 #define ADC3XXX_MICBIAS2_SHIFT 3 281 282 #define ADC3XXX_ADC_MAX_VOLUME 64 283 #define ADC3XXX_ADC_POS_VOL 24 284 285 /* GPIO control bits (GPIO1_CTRL and GPIO2_CTRL) */ 286 #define ADC3XXX_GPIO_CTRL_CFG_MASK 0x3c 287 #define ADC3XXX_GPIO_CTRL_CFG_SHIFT 2 288 #define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK 0x01 289 #define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT 0 290 #define ADC3XXX_GPIO_CTRL_INPUT_VALUE_MASK 0x02 291 #define ADC3XXX_GPIO_CTRL_INPUT_VALUE_SHIFT 1 292 293 enum adc3xxx_type { 294 ADC3001 = 0, 295 ADC3101 296 }; 297 298 struct adc3xxx { 299 struct device *dev; 300 enum adc3xxx_type type; 301 struct clk *mclk; 302 struct regmap *regmap; 303 struct gpio_desc *rst_pin; 304 unsigned int pll_mode; 305 unsigned int sysclk; 306 unsigned int gpio_cfg[ADC3XXX_GPIOS_MAX]; /* value+1 (0 => not set) */ 307 unsigned int micbias_vg[ADC3XXX_MICBIAS_PINS]; 308 int master; 309 u8 page_no; 310 int use_pll; 311 struct gpio_chip gpio_chip; 312 }; 313 314 static const unsigned int adc3xxx_gpio_ctrl_reg[ADC3XXX_GPIOS_MAX] = { 315 ADC3XXX_GPIO1_CTRL, 316 ADC3XXX_GPIO2_CTRL 317 }; 318 319 static const unsigned int adc3xxx_micbias_shift[ADC3XXX_MICBIAS_PINS] = { 320 ADC3XXX_MICBIAS1_SHIFT, 321 ADC3XXX_MICBIAS2_SHIFT 322 }; 323 324 static const struct reg_default adc3xxx_defaults[] = { 325 /* Page 0 */ 326 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x00 }, 327 { 4, 0x00 }, { 5, 0x11 }, { 6, 0x04 }, { 7, 0x00 }, 328 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x00 }, 329 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x00 }, 330 { 16, 0x00 }, { 17, 0x00 }, { 18, 0x01 }, { 19, 0x01 }, 331 { 20, 0x80 }, { 21, 0x80 }, { 22, 0x04 }, { 23, 0x00 }, 332 { 24, 0x00 }, { 25, 0x00 }, { 26, 0x01 }, { 27, 0x00 }, 333 { 28, 0x00 }, { 29, 0x02 }, { 30, 0x01 }, { 31, 0x00 }, 334 { 32, 0x00 }, { 33, 0x10 }, { 34, 0x00 }, { 35, 0x00 }, 335 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x02 }, { 39, 0x00 }, 336 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x00 }, 337 { 44, 0x00 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 }, 338 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x00 }, 339 { 52, 0x00 }, { 53, 0x12 }, { 54, 0x00 }, { 55, 0x00 }, 340 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x00 }, { 59, 0x44 }, 341 { 60, 0x00 }, { 61, 0x01 }, { 62, 0x00 }, { 63, 0x00 }, 342 { 64, 0x00 }, { 65, 0x00 }, { 66, 0x00 }, { 67, 0x00 }, 343 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 }, 344 { 72, 0x00 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 }, 345 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 }, 346 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x88 }, { 83, 0x00 }, 347 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 }, 348 { 88, 0x7f }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 }, 349 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 }, 350 { 96, 0x7f }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 }, 351 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x00 }, { 103, 0x00 }, 352 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 }, 353 { 108, 0x00 }, { 109, 0x00 }, { 110, 0x00 }, { 111, 0x00 }, 354 { 112, 0x00 }, { 113, 0x00 }, { 114, 0x00 }, { 115, 0x00 }, 355 { 116, 0x00 }, { 117, 0x00 }, { 118, 0x00 }, { 119, 0x00 }, 356 { 120, 0x00 }, { 121, 0x00 }, { 122, 0x00 }, { 123, 0x00 }, 357 { 124, 0x00 }, { 125, 0x00 }, { 126, 0x00 }, { 127, 0x00 }, 358 359 /* Page 1 */ 360 { 128, 0x00 }, { 129, 0x00 }, { 130, 0x00 }, { 131, 0x00 }, 361 { 132, 0x00 }, { 133, 0x00 }, { 134, 0x00 }, { 135, 0x00 }, 362 { 136, 0x00 }, { 137, 0x00 }, { 138, 0x00 }, { 139, 0x00 }, 363 { 140, 0x00 }, { 141, 0x00 }, { 142, 0x00 }, { 143, 0x00 }, 364 { 144, 0x00 }, { 145, 0x00 }, { 146, 0x00 }, { 147, 0x00 }, 365 { 148, 0x00 }, { 149, 0x00 }, { 150, 0x00 }, { 151, 0x00 }, 366 { 152, 0x00 }, { 153, 0x00 }, { 154, 0x00 }, { 155, 0x00 }, 367 { 156, 0x00 }, { 157, 0x00 }, { 158, 0x00 }, { 159, 0x00 }, 368 { 160, 0x00 }, { 161, 0x00 }, { 162, 0x00 }, { 163, 0x00 }, 369 { 164, 0x00 }, { 165, 0x00 }, { 166, 0x00 }, { 167, 0x00 }, 370 { 168, 0x00 }, { 169, 0x00 }, { 170, 0x00 }, { 171, 0x00 }, 371 { 172, 0x00 }, { 173, 0x00 }, { 174, 0x00 }, { 175, 0x00 }, 372 { 176, 0x00 }, { 177, 0x00 }, { 178, 0x00 }, { 179, 0x00 }, 373 { 180, 0xff }, { 181, 0x00 }, { 182, 0x3f }, { 183, 0xff }, 374 { 184, 0x00 }, { 185, 0x3f }, { 186, 0x00 }, { 187, 0x80 }, 375 { 188, 0x80 }, { 189, 0x00 }, { 190, 0x00 }, { 191, 0x00 }, 376 }; 377 378 static bool adc3xxx_volatile_reg(struct device *dev, unsigned int reg) 379 { 380 switch (reg) { 381 case ADC3XXX_RESET: 382 return true; 383 default: 384 return false; 385 } 386 } 387 388 static const struct regmap_range_cfg adc3xxx_ranges[] = { 389 { 390 .range_min = 0, 391 .range_max = 2 * ADC3XXX_PAGE_SIZE, 392 .selector_reg = ADC3XXX_PAGE_SELECT, 393 .selector_mask = 0xff, 394 .selector_shift = 0, 395 .window_start = 0, 396 .window_len = ADC3XXX_PAGE_SIZE, 397 } 398 }; 399 400 static const struct regmap_config adc3xxx_regmap = { 401 .reg_bits = 8, 402 .val_bits = 8, 403 404 .reg_defaults = adc3xxx_defaults, 405 .num_reg_defaults = ARRAY_SIZE(adc3xxx_defaults), 406 407 .volatile_reg = adc3xxx_volatile_reg, 408 409 .cache_type = REGCACHE_RBTREE, 410 411 .ranges = adc3xxx_ranges, 412 .num_ranges = ARRAY_SIZE(adc3xxx_ranges), 413 .max_register = 2 * ADC3XXX_PAGE_SIZE, 414 }; 415 416 struct adc3xxx_rate_divs { 417 u32 mclk; 418 u32 rate; 419 u8 pll_p; 420 u8 pll_r; 421 u8 pll_j; 422 u16 pll_d; 423 u8 nadc; 424 u8 madc; 425 u8 aosr; 426 }; 427 428 /* 429 * PLL and Clock settings. 430 * If p member is 0, PLL is not used. 431 * The order of the entries in this table have the PLL entries before 432 * the non-PLL entries, so that the PLL modes are preferred unless 433 * the PLL mode setting says otherwise. 434 */ 435 static const struct adc3xxx_rate_divs adc3xxx_divs[] = { 436 /* mclk, rate, p, r, j, d, nadc, madc, aosr */ 437 /* 8k rate */ 438 { 12000000, 8000, 1, 1, 7, 1680, 42, 2, 128 }, 439 { 12288000, 8000, 1, 1, 7, 0000, 42, 2, 128 }, 440 /* 11.025k rate */ 441 { 12000000, 11025, 1, 1, 6, 8208, 29, 2, 128 }, 442 /* 16k rate */ 443 { 12000000, 16000, 1, 1, 7, 1680, 21, 2, 128 }, 444 { 12288000, 16000, 1, 1, 7, 0000, 21, 2, 128 }, 445 /* 22.05k rate */ 446 { 12000000, 22050, 1, 1, 7, 560, 15, 2, 128 }, 447 /* 32k rate */ 448 { 12000000, 32000, 1, 1, 8, 1920, 12, 2, 128 }, 449 { 12288000, 32000, 1, 1, 8, 0000, 12, 2, 128 }, 450 /* 44.1k rate */ 451 { 12000000, 44100, 1, 1, 7, 5264, 8, 2, 128 }, 452 /* 48k rate */ 453 { 12000000, 48000, 1, 1, 7, 1680, 7, 2, 128 }, 454 { 12288000, 48000, 1, 1, 7, 0000, 7, 2, 128 }, 455 { 24576000, 48000, 1, 1, 3, 5000, 7, 2, 128 }, /* With PLL */ 456 { 24576000, 48000, 0, 0, 0, 0000, 2, 2, 128 }, /* Without PLL */ 457 /* 88.2k rate */ 458 { 12000000, 88200, 1, 1, 7, 5264, 4, 4, 64 }, 459 /* 96k rate */ 460 { 12000000, 96000, 1, 1, 8, 1920, 4, 4, 64 }, 461 }; 462 463 static int adc3xxx_get_divs(struct device *dev, int mclk, int rate, int pll_mode) 464 { 465 int i; 466 467 dev_dbg(dev, "mclk = %d, rate = %d, clock mode %u\n", 468 mclk, rate, pll_mode); 469 for (i = 0; i < ARRAY_SIZE(adc3xxx_divs); i++) { 470 const struct adc3xxx_rate_divs *mode = &adc3xxx_divs[i]; 471 472 /* Skip this entry if it doesn't fulfill the intended clock 473 * mode requirement. We consider anything besides the two 474 * modes below to be the same as ADC3XXX_PLL_AUTO. 475 */ 476 if ((pll_mode == ADC3XXX_PLL_BYPASS && mode->pll_p) || 477 (pll_mode == ADC3XXX_PLL_ENABLE && !mode->pll_p)) 478 continue; 479 480 if (mode->rate == rate && mode->mclk == mclk) 481 return i; 482 } 483 484 dev_info(dev, "Master clock rate %d and sample rate %d is not supported\n", 485 mclk, rate); 486 return -EINVAL; 487 } 488 489 static int adc3xxx_pll_delay(struct snd_soc_dapm_widget *w, 490 struct snd_kcontrol *kcontrol, int event) 491 { 492 /* 10msec delay needed after PLL power-up to allow 493 * PLL and dividers to stabilize (datasheet p13). 494 */ 495 usleep_range(10000, 20000); 496 497 return 0; 498 } 499 500 static const char * const adc_softstepping_text[] = { "1 step", "2 step", "off" }; 501 static SOC_ENUM_SINGLE_DECL(adc_softstepping_enum, ADC3XXX_ADC_DIGITAL, 0, 502 adc_softstepping_text); 503 504 static const char * const multiplier_text[] = { "1", "2", "4", "8", "16", "32", "64", "128" }; 505 static SOC_ENUM_SINGLE_DECL(left_agc_attack_mult_enum, 506 ADC3XXX_LEFT_CHN_AGC_4, 0, multiplier_text); 507 static SOC_ENUM_SINGLE_DECL(right_agc_attack_mult_enum, 508 ADC3XXX_RIGHT_CHN_AGC_4, 0, multiplier_text); 509 static SOC_ENUM_SINGLE_DECL(left_agc_decay_mult_enum, 510 ADC3XXX_LEFT_CHN_AGC_5, 0, multiplier_text); 511 static SOC_ENUM_SINGLE_DECL(right_agc_decay_mult_enum, 512 ADC3XXX_RIGHT_CHN_AGC_5, 0, multiplier_text); 513 514 static const char * const dither_dc_offset_text[] = { 515 "0mV", "15mV", "30mV", "45mV", "60mV", "75mV", "90mV", "105mV", 516 "-15mV", "-30mV", "-45mV", "-60mV", "-75mV", "-90mV", "-105mV" 517 }; 518 static const unsigned int dither_dc_offset_values[] = { 519 0, 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15 520 }; 521 static SOC_VALUE_ENUM_DOUBLE_DECL(dither_dc_offset_enum, 522 ADC3XXX_DITHER_CTRL, 523 4, 0, 0xf, dither_dc_offset_text, 524 dither_dc_offset_values); 525 526 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 50, 0); 527 static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0); 528 static const DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0); 529 /* AGC target: 8 values: -5.5, -8, -10, -12, -14, -17, -20, -24 dB */ 530 /* It would be nice to declare these in the order above, but empirically 531 * TLV_DB_SCALE_ITEM doesn't take lightly to the increment (second) parameter 532 * being negative, despite there being examples to the contrary in other 533 * drivers. So declare these in the order from lowest to highest, and 534 * set the invert flag in the SOC_DOUBLE_R_TLV declaration instead. 535 */ 536 static const DECLARE_TLV_DB_RANGE(agc_target_tlv, 537 0, 0, TLV_DB_SCALE_ITEM(-2400, 0, 0), 538 1, 3, TLV_DB_SCALE_ITEM(-2000, 300, 0), 539 4, 6, TLV_DB_SCALE_ITEM(-1200, 200, 0), 540 7, 7, TLV_DB_SCALE_ITEM(-550, 0, 0)); 541 /* Since the 'disabled' value (mute) is at the highest value in the dB 542 * range (i.e. just before -32 dB) rather than the lowest, we need to resort 543 * to using a TLV_DB_RANGE in order to get the mute value in the right place. 544 */ 545 static const DECLARE_TLV_DB_RANGE(agc_thresh_tlv, 546 0, 30, TLV_DB_SCALE_ITEM(-9000, 200, 0), 547 31, 31, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */ 548 /* AGC hysteresis: 4 values: 1, 2, 4 dB, disabled (= mute) */ 549 static const DECLARE_TLV_DB_RANGE(agc_hysteresis_tlv, 550 0, 1, TLV_DB_SCALE_ITEM(100, 100, 0), 551 2, 2, TLV_DB_SCALE_ITEM(400, 0, 0), 552 3, 3, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */ 553 static const DECLARE_TLV_DB_SCALE(agc_max_tlv, 0, 50, 0); 554 /* Input attenuation: -6 dB or 0 dB */ 555 static const DECLARE_TLV_DB_SCALE(input_attenuation_tlv, -600, 600, 0); 556 557 static const struct snd_kcontrol_new adc3xxx_snd_controls[] = { 558 SOC_DOUBLE_R_TLV("PGA Capture Volume", ADC3XXX_LEFT_APGA_CTRL, 559 ADC3XXX_RIGHT_APGA_CTRL, 0, 80, 0, pga_tlv), 560 SOC_DOUBLE("PGA Capture Switch", ADC3XXX_ADC_FGA, 7, 3, 1, 1), 561 SOC_DOUBLE_R("AGC Capture Switch", ADC3XXX_LEFT_CHN_AGC_1, 562 ADC3XXX_RIGHT_CHN_AGC_1, 7, 1, 0), 563 SOC_DOUBLE_R_TLV("AGC Target Level Capture Volume", ADC3XXX_LEFT_CHN_AGC_1, 564 ADC3XXX_RIGHT_CHN_AGC_2, 4, 0x07, 1, agc_target_tlv), 565 SOC_DOUBLE_R_TLV("AGC Noise Threshold Capture Volume", ADC3XXX_LEFT_CHN_AGC_2, 566 ADC3XXX_RIGHT_CHN_AGC_2, 1, 0x1f, 1, agc_thresh_tlv), 567 SOC_DOUBLE_R_TLV("AGC Hysteresis Capture Volume", ADC3XXX_LEFT_CHN_AGC_2, 568 ADC3XXX_RIGHT_CHN_AGC_2, 6, 3, 0, agc_hysteresis_tlv), 569 SOC_DOUBLE_R("AGC Clip Stepping Capture Switch", ADC3XXX_LEFT_CHN_AGC_2, 570 ADC3XXX_RIGHT_CHN_AGC_2, 0, 1, 0), 571 /* 572 * Oddly enough, the data sheet says the default value 573 * for the left/right AGC maximum gain register field 574 * (ADC3XXX_LEFT/RIGHT_CHN_AGC_3 bits 0..6) is 0x7f = 127 575 * (verified empirically) even though this value (indeed, above 576 * 0x50) is specified as 'Reserved. Do not use.' in the accompanying 577 * table in the data sheet. 578 */ 579 SOC_DOUBLE_R_TLV("AGC Maximum Capture Volume", ADC3XXX_LEFT_CHN_AGC_3, 580 ADC3XXX_RIGHT_CHN_AGC_3, 0, 0x50, 0, agc_max_tlv), 581 SOC_DOUBLE_R("AGC Attack Time", ADC3XXX_LEFT_CHN_AGC_4, 582 ADC3XXX_RIGHT_CHN_AGC_4, 3, 0x1f, 0), 583 /* Would like to have the multipliers as LR pairs, but there is 584 * no SOC_ENUM_foo which accepts two values in separate registers. 585 */ 586 SOC_ENUM("AGC Left Attack Time Multiplier", left_agc_attack_mult_enum), 587 SOC_ENUM("AGC Right Attack Time Multiplier", right_agc_attack_mult_enum), 588 SOC_DOUBLE_R("AGC Decay Time", ADC3XXX_LEFT_CHN_AGC_5, 589 ADC3XXX_RIGHT_CHN_AGC_5, 3, 0x1f, 0), 590 SOC_ENUM("AGC Left Decay Time Multiplier", left_agc_decay_mult_enum), 591 SOC_ENUM("AGC Right Decay Time Multiplier", right_agc_decay_mult_enum), 592 SOC_DOUBLE_R("AGC Noise Debounce", ADC3XXX_LEFT_CHN_AGC_6, 593 ADC3XXX_RIGHT_CHN_AGC_6, 0, 0x1f, 0), 594 SOC_DOUBLE_R("AGC Signal Debounce", ADC3XXX_LEFT_CHN_AGC_7, 595 ADC3XXX_RIGHT_CHN_AGC_7, 0, 0x0f, 0), 596 /* Read only register */ 597 SOC_DOUBLE_R_S_TLV("AGC Applied Capture Volume", ADC3XXX_LEFT_AGC_GAIN, 598 ADC3XXX_RIGHT_AGC_GAIN, 0, -24, 40, 6, 0, adc_tlv), 599 /* ADC soft stepping */ 600 SOC_ENUM("ADC Soft Stepping", adc_softstepping_enum), 601 /* Left/Right Input attenuation */ 602 SOC_SINGLE_TLV("Left Input IN_1L Capture Volume", 603 ADC3XXX_LEFT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv), 604 SOC_SINGLE_TLV("Left Input IN_2L Capture Volume", 605 ADC3XXX_LEFT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv), 606 SOC_SINGLE_TLV("Left Input IN_3L Capture Volume", 607 ADC3XXX_LEFT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv), 608 SOC_SINGLE_TLV("Left Input IN_1R Capture Volume", 609 ADC3XXX_LEFT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv), 610 SOC_SINGLE_TLV("Left Input DIF_2L_3L Capture Volume", 611 ADC3XXX_LEFT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv), 612 SOC_SINGLE_TLV("Left Input DIF_1L_1R Capture Volume", 613 ADC3XXX_LEFT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv), 614 SOC_SINGLE_TLV("Left Input DIF_2R_3R Capture Volume", 615 ADC3XXX_LEFT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv), 616 SOC_SINGLE_TLV("Right Input IN_1R Capture Volume", 617 ADC3XXX_RIGHT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv), 618 SOC_SINGLE_TLV("Right Input IN_2R Capture Volume", 619 ADC3XXX_RIGHT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv), 620 SOC_SINGLE_TLV("Right Input IN_3R Capture Volume", 621 ADC3XXX_RIGHT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv), 622 SOC_SINGLE_TLV("Right Input IN_1L Capture Volume", 623 ADC3XXX_RIGHT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv), 624 SOC_SINGLE_TLV("Right Input DIF_2R_3R Capture Volume", 625 ADC3XXX_RIGHT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv), 626 SOC_SINGLE_TLV("Right Input DIF_1L_1R Capture Volume", 627 ADC3XXX_RIGHT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv), 628 SOC_SINGLE_TLV("Right Input DIF_2L_3L Capture Volume", 629 ADC3XXX_RIGHT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv), 630 SOC_DOUBLE_R_S_TLV("ADC Volume Control Capture Volume", ADC3XXX_LADC_VOL, 631 ADC3XXX_RADC_VOL, 0, -24, 40, 6, 0, adc_tlv), 632 /* Empirically, the following doesn't work the way it's supposed 633 * to. Values 0, -0.1, -0.2 and -0.3 dB result in the same level, and 634 * -0.4 dB drops about 0.12 dB on a specific chip. 635 */ 636 SOC_DOUBLE_TLV("ADC Fine Volume Control Capture Volume", ADC3XXX_ADC_FGA, 637 4, 0, 4, 1, adc_fine_tlv), 638 SOC_SINGLE("Left ADC Unselected CM Bias Capture Switch", 639 ADC3XXX_LEFT_PGA_SEL_2, 6, 1, 0), 640 SOC_SINGLE("Right ADC Unselected CM Bias Capture Switch", 641 ADC3XXX_RIGHT_PGA_SEL_2, 6, 1, 0), 642 SOC_ENUM("Dither Control DC Offset", dither_dc_offset_enum), 643 }; 644 645 /* Left input selection, Single Ended inputs and Differential inputs */ 646 static const struct snd_kcontrol_new left_input_mixer_controls[] = { 647 SOC_DAPM_SINGLE("IN_1L Capture Switch", 648 ADC3XXX_LEFT_PGA_SEL_1, 1, 0x1, 1), 649 SOC_DAPM_SINGLE("IN_2L Capture Switch", 650 ADC3XXX_LEFT_PGA_SEL_1, 3, 0x1, 1), 651 SOC_DAPM_SINGLE("IN_3L Capture Switch", 652 ADC3XXX_LEFT_PGA_SEL_1, 5, 0x1, 1), 653 SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch", 654 ADC3XXX_LEFT_PGA_SEL_1, 7, 0x1, 1), 655 SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch", 656 ADC3XXX_LEFT_PGA_SEL_2, 5, 0x1, 1), 657 SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch", 658 ADC3XXX_LEFT_PGA_SEL_2, 3, 0x1, 1), 659 SOC_DAPM_SINGLE("IN_1R Capture Switch", 660 ADC3XXX_LEFT_PGA_SEL_2, 1, 0x1, 1), 661 }; 662 663 /* Right input selection, Single Ended inputs and Differential inputs */ 664 static const struct snd_kcontrol_new right_input_mixer_controls[] = { 665 SOC_DAPM_SINGLE("IN_1R Capture Switch", 666 ADC3XXX_RIGHT_PGA_SEL_1, 1, 0x1, 1), 667 SOC_DAPM_SINGLE("IN_2R Capture Switch", 668 ADC3XXX_RIGHT_PGA_SEL_1, 3, 0x1, 1), 669 SOC_DAPM_SINGLE("IN_3R Capture Switch", 670 ADC3XXX_RIGHT_PGA_SEL_1, 5, 0x1, 1), 671 SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch", 672 ADC3XXX_RIGHT_PGA_SEL_1, 7, 0x1, 1), 673 SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch", 674 ADC3XXX_RIGHT_PGA_SEL_2, 5, 0x1, 1), 675 SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch", 676 ADC3XXX_RIGHT_PGA_SEL_2, 3, 0x1, 1), 677 SOC_DAPM_SINGLE("IN_1L Capture Switch", 678 ADC3XXX_RIGHT_PGA_SEL_2, 1, 0x1, 1), 679 }; 680 681 /* Left Digital Mic input for left ADC */ 682 static const struct snd_kcontrol_new left_input_dmic_controls[] = { 683 SOC_DAPM_SINGLE("Left ADC Capture Switch", 684 ADC3XXX_ADC_DIGITAL, 3, 0x1, 0), 685 }; 686 687 /* Right Digital Mic input for Right ADC */ 688 static const struct snd_kcontrol_new right_input_dmic_controls[] = { 689 SOC_DAPM_SINGLE("Right ADC Capture Switch", 690 ADC3XXX_ADC_DIGITAL, 2, 0x1, 0), 691 }; 692 693 /* DAPM widgets */ 694 static const struct snd_soc_dapm_widget adc3xxx_dapm_widgets[] = { 695 696 /* Left Input Selection */ 697 SND_SOC_DAPM_MIXER("Left Input", SND_SOC_NOPM, 0, 0, 698 &left_input_mixer_controls[0], 699 ARRAY_SIZE(left_input_mixer_controls)), 700 /* Right Input Selection */ 701 SND_SOC_DAPM_MIXER("Right Input", SND_SOC_NOPM, 0, 0, 702 &right_input_mixer_controls[0], 703 ARRAY_SIZE(right_input_mixer_controls)), 704 /* PGA selection */ 705 SND_SOC_DAPM_PGA("Left PGA", ADC3XXX_LEFT_APGA_CTRL, 7, 1, NULL, 0), 706 SND_SOC_DAPM_PGA("Right PGA", ADC3XXX_RIGHT_APGA_CTRL, 7, 1, NULL, 0), 707 708 /* Digital Microphone Input Control for Left/Right ADC */ 709 SND_SOC_DAPM_MIXER("Left DMic Input", SND_SOC_NOPM, 0, 0, 710 &left_input_dmic_controls[0], 711 ARRAY_SIZE(left_input_dmic_controls)), 712 SND_SOC_DAPM_MIXER("Right DMic Input", SND_SOC_NOPM, 0, 0, 713 &right_input_dmic_controls[0], 714 ARRAY_SIZE(right_input_dmic_controls)), 715 716 /* Left/Right ADC */ 717 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ADC3XXX_ADC_DIGITAL, 7, 0), 718 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ADC3XXX_ADC_DIGITAL, 6, 0), 719 720 /* Inputs */ 721 SND_SOC_DAPM_INPUT("IN_1L"), 722 SND_SOC_DAPM_INPUT("IN_1R"), 723 SND_SOC_DAPM_INPUT("IN_2L"), 724 SND_SOC_DAPM_INPUT("IN_2R"), 725 SND_SOC_DAPM_INPUT("IN_3L"), 726 SND_SOC_DAPM_INPUT("IN_3R"), 727 SND_SOC_DAPM_INPUT("DIFL_1L_1R"), 728 SND_SOC_DAPM_INPUT("DIFL_2L_3L"), 729 SND_SOC_DAPM_INPUT("DIFL_2R_3R"), 730 SND_SOC_DAPM_INPUT("DIFR_1L_1R"), 731 SND_SOC_DAPM_INPUT("DIFR_2L_3L"), 732 SND_SOC_DAPM_INPUT("DIFR_2R_3R"), 733 SND_SOC_DAPM_INPUT("DMic_L"), 734 SND_SOC_DAPM_INPUT("DMic_R"), 735 736 /* Digital audio interface output */ 737 SND_SOC_DAPM_AIF_OUT("AIF_OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 738 739 /* Clocks */ 740 SND_SOC_DAPM_SUPPLY("PLL_CLK", ADC3XXX_PLL_PROG_PR, ADC3XXX_ENABLE_PLL_SHIFT, 741 0, adc3xxx_pll_delay, SND_SOC_DAPM_POST_PMU), 742 743 SND_SOC_DAPM_SUPPLY("ADC_CLK", ADC3XXX_ADC_NADC, ADC3XXX_ENABLE_NADC_SHIFT, 744 0, NULL, 0), 745 SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK", ADC3XXX_ADC_MADC, ADC3XXX_ENABLE_MADC_SHIFT, 746 0, NULL, 0), 747 748 /* This refers to the generated BCLK in master mode. */ 749 SND_SOC_DAPM_SUPPLY("BCLK", ADC3XXX_BCLK_N_DIV, ADC3XXX_ENABLE_BCLK_SHIFT, 750 0, NULL, 0), 751 }; 752 753 static const struct snd_soc_dapm_route adc3xxx_intercon[] = { 754 /* Left input selection from switches */ 755 { "Left Input", "IN_1L Capture Switch", "IN_1L" }, 756 { "Left Input", "IN_2L Capture Switch", "IN_2L" }, 757 { "Left Input", "IN_3L Capture Switch", "IN_3L" }, 758 { "Left Input", "DIF_2L_3L Capture Switch", "DIFL_2L_3L" }, 759 { "Left Input", "DIF_1L_1R Capture Switch", "DIFL_1L_1R" }, 760 { "Left Input", "DIF_2R_3R Capture Switch", "DIFL_2R_3R" }, 761 { "Left Input", "IN_1R Capture Switch", "IN_1R" }, 762 763 /* Left input selection to left PGA */ 764 { "Left PGA", NULL, "Left Input" }, 765 766 /* Left PGA to left ADC */ 767 { "Left ADC", NULL, "Left PGA" }, 768 769 /* Right input selection from switches */ 770 { "Right Input", "IN_1R Capture Switch", "IN_1R" }, 771 { "Right Input", "IN_2R Capture Switch", "IN_2R" }, 772 { "Right Input", "IN_3R Capture Switch", "IN_3R" }, 773 { "Right Input", "DIF_2R_3R Capture Switch", "DIFR_2R_3R" }, 774 { "Right Input", "DIF_1L_1R Capture Switch", "DIFR_1L_1R" }, 775 { "Right Input", "DIF_2L_3L Capture Switch", "DIFR_2L_3L" }, 776 { "Right Input", "IN_1L Capture Switch", "IN_1L" }, 777 778 /* Right input selection to right PGA */ 779 { "Right PGA", NULL, "Right Input" }, 780 781 /* Right PGA to right ADC */ 782 { "Right ADC", NULL, "Right PGA" }, 783 784 /* Left DMic Input selection from switch */ 785 { "Left DMic Input", "Left ADC Capture Switch", "DMic_L" }, 786 787 /* Left DMic to left ADC */ 788 { "Left ADC", NULL, "Left DMic Input" }, 789 790 /* Right DMic Input selection from switch */ 791 { "Right DMic Input", "Right ADC Capture Switch", "DMic_R" }, 792 793 /* Right DMic to right ADC */ 794 { "Right ADC", NULL, "Right DMic Input" }, 795 796 /* ADC to AIF output */ 797 { "AIF_OUT", NULL, "Left ADC" }, 798 { "AIF_OUT", NULL, "Right ADC" }, 799 800 /* Clocking */ 801 { "ADC_MOD_CLK", NULL, "ADC_CLK" }, 802 { "Left ADC", NULL, "ADC_MOD_CLK" }, 803 { "Right ADC", NULL, "ADC_MOD_CLK" }, 804 805 { "BCLK", NULL, "ADC_CLK" }, 806 }; 807 808 static const struct snd_soc_dapm_route adc3xxx_pll_intercon[] = { 809 { "ADC_CLK", NULL, "PLL_CLK" }, 810 }; 811 812 static const struct snd_soc_dapm_route adc3xxx_bclk_out_intercon[] = { 813 { "AIF_OUT", NULL, "BCLK" } 814 }; 815 816 static int adc3xxx_gpio_request(struct gpio_chip *chip, unsigned int offset) 817 { 818 struct adc3xxx *adc3xxx = gpiochip_get_data(chip); 819 820 if (offset >= ADC3XXX_GPIOS_MAX) 821 return -EINVAL; 822 823 /* GPIO1 is offset 0, GPIO2 is offset 1 */ 824 /* We check here that the GPIO pins are either not configured in the 825 * DT, or that they purposely are set as outputs. 826 * (Input mode not yet implemented). 827 */ 828 if (adc3xxx->gpio_cfg[offset] != 0 && 829 adc3xxx->gpio_cfg[offset] != ADC3XXX_GPIO_GPO + 1) 830 return -EINVAL; 831 832 return 0; 833 } 834 835 static int adc3xxx_gpio_direction_out(struct gpio_chip *chip, 836 unsigned int offset, int value) 837 { 838 struct adc3xxx *adc3xxx = gpiochip_get_data(chip); 839 840 /* Set GPIO output function. */ 841 return regmap_update_bits(adc3xxx->regmap, 842 adc3xxx_gpio_ctrl_reg[offset], 843 ADC3XXX_GPIO_CTRL_CFG_MASK | 844 ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK, 845 ADC3XXX_GPIO_GPO << ADC3XXX_GPIO_CTRL_CFG_SHIFT | 846 !!value << ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT); 847 } 848 849 /* With only GPIO outputs configured, we never get the .direction_out call, 850 * so we set the output mode and output value in the same call. Hence 851 * .set in practice does the same thing as .direction_out . 852 */ 853 static void adc3xxx_gpio_set(struct gpio_chip *chip, unsigned int offset, 854 int value) 855 { 856 (void) adc3xxx_gpio_direction_out(chip, offset, value); 857 } 858 859 /* Even though we only support GPIO output for now, some GPIO clients 860 * want to read the current pin state using the .get callback. 861 */ 862 static int adc3xxx_gpio_get(struct gpio_chip *chip, unsigned int offset) 863 { 864 struct adc3xxx *adc3xxx = gpiochip_get_data(chip); 865 unsigned int regval; 866 int ret; 867 868 /* We only allow output pins, so just read the value set in the output 869 * pin register field. 870 */ 871 ret = regmap_read(adc3xxx->regmap, adc3xxx_gpio_ctrl_reg[offset], ®val); 872 if (ret) 873 return ret; 874 return !!(regval & ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK); 875 } 876 877 static const struct gpio_chip adc3xxx_gpio_chip = { 878 .label = "adc3xxx", 879 .owner = THIS_MODULE, 880 .request = adc3xxx_gpio_request, 881 .direction_output = adc3xxx_gpio_direction_out, 882 .set = adc3xxx_gpio_set, 883 .get = adc3xxx_gpio_get, 884 .can_sleep = 1, 885 }; 886 887 static void adc3xxx_free_gpio(struct adc3xxx *adc3xxx) 888 { 889 gpiochip_remove(&adc3xxx->gpio_chip); 890 } 891 892 static void adc3xxx_init_gpio(struct adc3xxx *adc3xxx) 893 { 894 int gpio, micbias; 895 int ret; 896 897 adc3xxx->gpio_chip = adc3xxx_gpio_chip; 898 adc3xxx->gpio_chip.ngpio = ADC3XXX_GPIOS_MAX; 899 adc3xxx->gpio_chip.parent = adc3xxx->dev; 900 adc3xxx->gpio_chip.base = -1; 901 902 ret = gpiochip_add_data(&adc3xxx->gpio_chip, adc3xxx); 903 if (ret) 904 dev_err(adc3xxx->dev, "Failed to add gpios: %d\n", ret); 905 906 /* Set up potential GPIO configuration from the devicetree. 907 * This allows us to set up things which are not software 908 * controllable GPIOs, such as PDM microphone I/O, 909 */ 910 for (gpio = 0; gpio < ADC3XXX_GPIOS_MAX; gpio++) { 911 unsigned int cfg = adc3xxx->gpio_cfg[gpio]; 912 913 if (cfg) { 914 cfg--; /* actual value to use is stored +1 */ 915 regmap_update_bits(adc3xxx->regmap, 916 adc3xxx_gpio_ctrl_reg[gpio], 917 ADC3XXX_GPIO_CTRL_CFG_MASK, 918 cfg << ADC3XXX_GPIO_CTRL_CFG_SHIFT); 919 } 920 } 921 922 /* Set up micbias voltage */ 923 for (micbias = 0; micbias < ADC3XXX_MICBIAS_PINS; micbias++) { 924 unsigned int vg = adc3xxx->micbias_vg[micbias]; 925 926 regmap_update_bits(adc3xxx->regmap, 927 ADC3XXX_MICBIAS_CTRL, 928 ADC3XXX_MICBIAS_MASK << adc3xxx_micbias_shift[micbias], 929 vg << adc3xxx_micbias_shift[micbias]); 930 } 931 } 932 933 static int adc3xxx_parse_dt_gpio(struct adc3xxx *adc3xxx, 934 const char *propname, unsigned int *cfg) 935 { 936 struct device *dev = adc3xxx->dev; 937 struct device_node *np = dev->of_node; 938 unsigned int val; 939 940 if (!of_property_read_u32(np, propname, &val)) { 941 if (val & ~15 || val == 7 || val >= 11) { 942 dev_err(dev, "Invalid property value for '%s'\n", propname); 943 return -EINVAL; 944 } 945 if (val == ADC3XXX_GPIO_GPI) 946 dev_warn(dev, "GPIO Input read not yet implemented\n"); 947 *cfg = val + 1; /* 0 => not set up, all others shifted +1 */ 948 } 949 return 0; 950 } 951 952 static int adc3xxx_parse_dt_micbias(struct adc3xxx *adc3xxx, 953 const char *propname, unsigned int *vg) 954 { 955 struct device *dev = adc3xxx->dev; 956 struct device_node *np = dev->of_node; 957 unsigned int val; 958 959 if (!of_property_read_u32(np, propname, &val)) { 960 if (val >= ADC3XXX_MICBIAS_AVDD) { 961 dev_err(dev, "Invalid property value for '%s'\n", propname); 962 return -EINVAL; 963 } 964 *vg = val; 965 } 966 return 0; 967 } 968 969 static int adc3xxx_parse_pll_mode(uint32_t val, unsigned int *pll_mode) 970 { 971 if (val != ADC3XXX_PLL_ENABLE && val != ADC3XXX_PLL_BYPASS && 972 val != ADC3XXX_PLL_AUTO) 973 return -EINVAL; 974 975 *pll_mode = val; 976 977 return 0; 978 } 979 980 static void adc3xxx_setup_pll(struct snd_soc_component *component, 981 int div_entry) 982 { 983 int i = div_entry; 984 985 /* P & R values */ 986 snd_soc_component_write(component, ADC3XXX_PLL_PROG_PR, 987 (adc3xxx_divs[i].pll_p << ADC3XXX_PLLP_SHIFT) | 988 (adc3xxx_divs[i].pll_r << ADC3XXX_PLLR_SHIFT)); 989 /* J value */ 990 snd_soc_component_write(component, ADC3XXX_PLL_PROG_J, 991 adc3xxx_divs[i].pll_j & ADC3XXX_PLLJ_MASK); 992 /* D value */ 993 snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_LSB, 994 adc3xxx_divs[i].pll_d & ADC3XXX_PLLD_LSB_MASK); 995 snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_MSB, 996 (adc3xxx_divs[i].pll_d >> 8) & ADC3XXX_PLLD_MSB_MASK); 997 } 998 999 static int adc3xxx_hw_params(struct snd_pcm_substream *substream, 1000 struct snd_pcm_hw_params *params, 1001 struct snd_soc_dai *dai) 1002 { 1003 struct snd_soc_component *component = dai->component; 1004 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component); 1005 struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component); 1006 int i, width = 16; 1007 u8 iface_len, bdiv; 1008 1009 i = adc3xxx_get_divs(component->dev, adc3xxx->sysclk, 1010 params_rate(params), adc3xxx->pll_mode); 1011 1012 if (i < 0) 1013 return i; 1014 1015 /* select data word length */ 1016 switch (params_format(params)) { 1017 case SNDRV_PCM_FORMAT_S16_LE: 1018 iface_len = ADC3XXX_IFACE_16BITS; 1019 width = 16; 1020 break; 1021 case SNDRV_PCM_FORMAT_S20_3LE: 1022 iface_len = ADC3XXX_IFACE_20BITS; 1023 width = 20; 1024 break; 1025 case SNDRV_PCM_FORMAT_S24_LE: 1026 iface_len = ADC3XXX_IFACE_24BITS; 1027 width = 24; 1028 break; 1029 case SNDRV_PCM_FORMAT_S32_LE: 1030 iface_len = ADC3XXX_IFACE_32BITS; 1031 width = 32; 1032 break; 1033 default: 1034 dev_err(component->dev, "Unsupported serial data format\n"); 1035 return -EINVAL; 1036 } 1037 snd_soc_component_update_bits(component, ADC3XXX_INTERFACE_CTRL_1, 1038 ADC3XXX_WLENGTH_MASK, iface_len); 1039 if (adc3xxx_divs[i].pll_p) { /* If PLL used for this mode */ 1040 adc3xxx_setup_pll(component, i); 1041 snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_USE_PLL); 1042 if (!adc3xxx->use_pll) { 1043 snd_soc_dapm_add_routes(dapm, adc3xxx_pll_intercon, 1044 ARRAY_SIZE(adc3xxx_pll_intercon)); 1045 adc3xxx->use_pll = 1; 1046 } 1047 } else { 1048 snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_NO_PLL); 1049 if (adc3xxx->use_pll) { 1050 snd_soc_dapm_del_routes(dapm, adc3xxx_pll_intercon, 1051 ARRAY_SIZE(adc3xxx_pll_intercon)); 1052 adc3xxx->use_pll = 0; 1053 } 1054 } 1055 1056 /* NADC */ 1057 snd_soc_component_update_bits(component, ADC3XXX_ADC_NADC, 1058 ADC3XXX_NADC_MASK, adc3xxx_divs[i].nadc); 1059 /* MADC */ 1060 snd_soc_component_update_bits(component, ADC3XXX_ADC_MADC, 1061 ADC3XXX_MADC_MASK, adc3xxx_divs[i].madc); 1062 /* AOSR */ 1063 snd_soc_component_update_bits(component, ADC3XXX_ADC_AOSR, 1064 ADC3XXX_AOSR_MASK, adc3xxx_divs[i].aosr); 1065 /* BDIV N Value */ 1066 /* BCLK is (by default) set up to be derived from ADC_CLK */ 1067 bdiv = (adc3xxx_divs[i].aosr * adc3xxx_divs[i].madc) / (2 * width); 1068 snd_soc_component_update_bits(component, ADC3XXX_BCLK_N_DIV, 1069 ADC3XXX_BDIV_MASK, bdiv); 1070 1071 return 0; 1072 } 1073 1074 static const char *adc3xxx_pll_mode_text(int pll_mode) 1075 { 1076 switch (pll_mode) { 1077 case ADC3XXX_PLL_AUTO: 1078 return "PLL auto"; 1079 case ADC3XXX_PLL_ENABLE: 1080 return "PLL enable"; 1081 case ADC3XXX_PLL_BYPASS: 1082 return "PLL bypass"; 1083 default: 1084 break; 1085 } 1086 1087 return "PLL unknown"; 1088 } 1089 1090 static int adc3xxx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1091 int clk_id, unsigned int freq, int dir) 1092 { 1093 struct snd_soc_component *component = codec_dai->component; 1094 struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component); 1095 int ret; 1096 1097 ret = adc3xxx_parse_pll_mode(clk_id, &adc3xxx->pll_mode); 1098 if (ret < 0) 1099 return ret; 1100 1101 adc3xxx->sysclk = freq; 1102 dev_dbg(component->dev, "Set sysclk to %u Hz, %s\n", 1103 freq, adc3xxx_pll_mode_text(adc3xxx->pll_mode)); 1104 return 0; 1105 } 1106 1107 static int adc3xxx_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1108 { 1109 struct snd_soc_component *component = codec_dai->component; 1110 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1111 struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component); 1112 u8 clkdir = 0, format = 0; 1113 int master = 0; 1114 1115 /* set master/slave audio interface */ 1116 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1117 case SND_SOC_DAIFMT_CBP_CFP: 1118 master = 1; 1119 clkdir = ADC3XXX_BCLK_MASTER | ADC3XXX_WCLK_MASTER; 1120 break; 1121 case SND_SOC_DAIFMT_CBC_CFC: 1122 master = 0; 1123 break; 1124 default: 1125 dev_err(component->dev, "Invalid DAI clock setup\n"); 1126 return -EINVAL; 1127 } 1128 1129 /* 1130 * match both interface format and signal polarities since they 1131 * are fixed 1132 */ 1133 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK)) { 1134 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF: 1135 format = ADC3XXX_FORMAT_I2S; 1136 break; 1137 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF: 1138 format = ADC3XXX_FORMAT_DSP; 1139 break; 1140 case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF: 1141 format = ADC3XXX_FORMAT_DSP; 1142 break; 1143 case SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF: 1144 format = ADC3XXX_FORMAT_RJF; 1145 break; 1146 case SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF: 1147 format = ADC3XXX_FORMAT_LJF; 1148 break; 1149 default: 1150 dev_err(component->dev, "Invalid DAI format\n"); 1151 return -EINVAL; 1152 } 1153 1154 /* Add/del route enabling BCLK output as applicable */ 1155 if (master && !adc3xxx->master) 1156 snd_soc_dapm_add_routes(dapm, adc3xxx_bclk_out_intercon, 1157 ARRAY_SIZE(adc3xxx_bclk_out_intercon)); 1158 else if (!master && adc3xxx->master) 1159 snd_soc_dapm_del_routes(dapm, adc3xxx_bclk_out_intercon, 1160 ARRAY_SIZE(adc3xxx_bclk_out_intercon)); 1161 adc3xxx->master = master; 1162 1163 /* set clock direction and format */ 1164 return snd_soc_component_update_bits(component, 1165 ADC3XXX_INTERFACE_CTRL_1, 1166 ADC3XXX_CLKDIR_MASK | ADC3XXX_FORMAT_MASK, 1167 clkdir | format); 1168 } 1169 1170 static const struct snd_soc_dai_ops adc3xxx_dai_ops = { 1171 .hw_params = adc3xxx_hw_params, 1172 .set_sysclk = adc3xxx_set_dai_sysclk, 1173 .set_fmt = adc3xxx_set_dai_fmt, 1174 }; 1175 1176 static struct snd_soc_dai_driver adc3xxx_dai = { 1177 .name = "tlv320adc3xxx-hifi", 1178 .capture = { 1179 .stream_name = "Capture", 1180 .channels_min = 1, 1181 .channels_max = 2, 1182 .rates = ADC3XXX_RATES, 1183 .formats = ADC3XXX_FORMATS, 1184 }, 1185 .ops = &adc3xxx_dai_ops, 1186 }; 1187 1188 static const struct snd_soc_component_driver soc_component_dev_adc3xxx = { 1189 .controls = adc3xxx_snd_controls, 1190 .num_controls = ARRAY_SIZE(adc3xxx_snd_controls), 1191 .dapm_widgets = adc3xxx_dapm_widgets, 1192 .num_dapm_widgets = ARRAY_SIZE(adc3xxx_dapm_widgets), 1193 .dapm_routes = adc3xxx_intercon, 1194 .num_dapm_routes = ARRAY_SIZE(adc3xxx_intercon), 1195 }; 1196 1197 static int adc3xxx_i2c_probe(struct i2c_client *i2c, 1198 const struct i2c_device_id *id) 1199 { 1200 struct device *dev = &i2c->dev; 1201 struct adc3xxx *adc3xxx = NULL; 1202 int ret; 1203 1204 adc3xxx = devm_kzalloc(dev, sizeof(struct adc3xxx), GFP_KERNEL); 1205 if (!adc3xxx) 1206 return -ENOMEM; 1207 adc3xxx->dev = dev; 1208 1209 adc3xxx->rst_pin = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 1210 if (IS_ERR(adc3xxx->rst_pin)) { 1211 return dev_err_probe(dev, PTR_ERR(adc3xxx->rst_pin), 1212 "Failed to request rst_pin\n"); 1213 } 1214 1215 adc3xxx->mclk = devm_clk_get(dev, NULL); 1216 if (IS_ERR(adc3xxx->mclk)) { 1217 /* 1218 * The chip itself supports running off the BCLK either 1219 * directly or via the PLL, but the driver does not (yet), so 1220 * having a specified mclk is required. Otherwise, we could 1221 * use the lack of a clocks property to indicate when BCLK is 1222 * intended as the clock source. 1223 */ 1224 return dev_err_probe(dev, PTR_ERR(adc3xxx->mclk), 1225 "Failed to acquire MCLK\n"); 1226 } else if (adc3xxx->mclk) { 1227 ret = clk_prepare_enable(adc3xxx->mclk); 1228 if (ret < 0) 1229 return ret; 1230 dev_dbg(dev, "Enabled MCLK, freq %lu Hz\n", clk_get_rate(adc3xxx->mclk)); 1231 } 1232 1233 ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmdin-gpio1", &adc3xxx->gpio_cfg[0]); 1234 if (ret < 0) 1235 goto err_unprepare_mclk; 1236 ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmclk-gpio2", &adc3xxx->gpio_cfg[1]); 1237 if (ret < 0) 1238 goto err_unprepare_mclk; 1239 ret = adc3xxx_parse_dt_micbias(adc3xxx, "ti,micbias1-vg", &adc3xxx->micbias_vg[0]); 1240 if (ret < 0) 1241 goto err_unprepare_mclk; 1242 ret = adc3xxx_parse_dt_micbias(adc3xxx, "ti,micbias2-vg", &adc3xxx->micbias_vg[1]); 1243 if (ret < 0) 1244 goto err_unprepare_mclk; 1245 1246 adc3xxx->regmap = devm_regmap_init_i2c(i2c, &adc3xxx_regmap); 1247 if (IS_ERR(adc3xxx->regmap)) { 1248 ret = PTR_ERR(adc3xxx->regmap); 1249 goto err_unprepare_mclk; 1250 } 1251 1252 i2c_set_clientdata(i2c, adc3xxx); 1253 1254 adc3xxx->type = id->driver_data; 1255 1256 /* Reset codec chip */ 1257 gpiod_set_value_cansleep(adc3xxx->rst_pin, 1); 1258 usleep_range(2000, 100000); /* Requirement: > 10 ns (datasheet p13) */ 1259 gpiod_set_value_cansleep(adc3xxx->rst_pin, 0); 1260 1261 /* Potentially set up pins used as GPIOs */ 1262 adc3xxx_init_gpio(adc3xxx); 1263 1264 ret = snd_soc_register_component(dev, 1265 &soc_component_dev_adc3xxx, &adc3xxx_dai, 1); 1266 if (ret < 0) { 1267 dev_err(dev, "Failed to register codec: %d\n", ret); 1268 goto err_unprepare_mclk; 1269 } 1270 1271 return 0; 1272 1273 err_unprepare_mclk: 1274 clk_disable_unprepare(adc3xxx->mclk); 1275 return ret; 1276 } 1277 1278 static int __exit adc3xxx_i2c_remove(struct i2c_client *client) 1279 { 1280 struct adc3xxx *adc3xxx = i2c_get_clientdata(client); 1281 1282 if (adc3xxx->mclk) 1283 clk_disable_unprepare(adc3xxx->mclk); 1284 adc3xxx_free_gpio(adc3xxx); 1285 snd_soc_unregister_component(&client->dev); 1286 return 0; 1287 } 1288 1289 static const struct of_device_id tlv320adc3xxx_of_match[] = { 1290 { .compatible = "ti,tlv320adc3001", }, 1291 { .compatible = "ti,tlv320adc3101", }, 1292 {}, 1293 }; 1294 MODULE_DEVICE_TABLE(of, tlv320adc3xxx_of_match); 1295 1296 static const struct i2c_device_id adc3xxx_i2c_id[] = { 1297 { "tlv320adc3001", ADC3001 }, 1298 { "tlv320adc3101", ADC3101 }, 1299 {} 1300 }; 1301 MODULE_DEVICE_TABLE(i2c, adc3xxx_i2c_id); 1302 1303 static struct i2c_driver adc3xxx_i2c_driver = { 1304 .driver = { 1305 .name = "tlv320adc3xxx-codec", 1306 .of_match_table = tlv320adc3xxx_of_match, 1307 }, 1308 .probe = adc3xxx_i2c_probe, 1309 .remove = adc3xxx_i2c_remove, 1310 .id_table = adc3xxx_i2c_id, 1311 }; 1312 1313 module_i2c_driver(adc3xxx_i2c_driver); 1314 1315 MODULE_DESCRIPTION("ASoC TLV320ADC3xxx codec driver"); 1316 MODULE_AUTHOR("shahina.s@mistralsolutions.com"); 1317 MODULE_LICENSE("GPL v2"); 1318