1*e9a3b57eSRicard Wanderlof // SPDX-License-Identifier: GPL-2.0-only 2*e9a3b57eSRicard Wanderlof // 3*e9a3b57eSRicard Wanderlof // Based on sound/soc/codecs/tlv320aic3x.c by Vladimir Barinov 4*e9a3b57eSRicard Wanderlof // 5*e9a3b57eSRicard Wanderlof // Copyright (C) 2010 Mistral Solutions Pvt Ltd. 6*e9a3b57eSRicard Wanderlof // Author: Shahina Shaik <shahina.s@mistralsolutions.com> 7*e9a3b57eSRicard Wanderlof // 8*e9a3b57eSRicard Wanderlof // Copyright (C) 2014-2018, Ambarella, Inc. 9*e9a3b57eSRicard Wanderlof // Author: Dongge wu <dgwu@ambarella.com> 10*e9a3b57eSRicard Wanderlof // 11*e9a3b57eSRicard Wanderlof // Copyright (C) 2021 Axis Communications AB 12*e9a3b57eSRicard Wanderlof // Author: Ricard Wanderlof <ricardw@axis.com> 13*e9a3b57eSRicard Wanderlof // 14*e9a3b57eSRicard Wanderlof 15*e9a3b57eSRicard Wanderlof #include <dt-bindings/sound/tlv320adc3xxx.h> 16*e9a3b57eSRicard Wanderlof #include <linux/clk.h> 17*e9a3b57eSRicard Wanderlof #include <linux/module.h> 18*e9a3b57eSRicard Wanderlof #include <linux/moduleparam.h> 19*e9a3b57eSRicard Wanderlof #include <linux/io.h> 20*e9a3b57eSRicard Wanderlof #include <linux/init.h> 21*e9a3b57eSRicard Wanderlof #include <linux/delay.h> 22*e9a3b57eSRicard Wanderlof #include <linux/gpio/driver.h> 23*e9a3b57eSRicard Wanderlof #include <linux/pm.h> 24*e9a3b57eSRicard Wanderlof #include <linux/i2c.h> 25*e9a3b57eSRicard Wanderlof #include <linux/platform_device.h> 26*e9a3b57eSRicard Wanderlof #include <linux/cdev.h> 27*e9a3b57eSRicard Wanderlof #include <linux/of_gpio.h> 28*e9a3b57eSRicard Wanderlof #include <linux/slab.h> 29*e9a3b57eSRicard Wanderlof #include <sound/core.h> 30*e9a3b57eSRicard Wanderlof #include <sound/pcm.h> 31*e9a3b57eSRicard Wanderlof #include <sound/pcm_params.h> 32*e9a3b57eSRicard Wanderlof #include <sound/soc.h> 33*e9a3b57eSRicard Wanderlof #include <sound/soc-dapm.h> 34*e9a3b57eSRicard Wanderlof #include <sound/tlv.h> 35*e9a3b57eSRicard Wanderlof #include <sound/initval.h> 36*e9a3b57eSRicard Wanderlof 37*e9a3b57eSRicard Wanderlof /* 38*e9a3b57eSRicard Wanderlof * General definitions defining exported functionality. 39*e9a3b57eSRicard Wanderlof */ 40*e9a3b57eSRicard Wanderlof 41*e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS_PINS 2 42*e9a3b57eSRicard Wanderlof 43*e9a3b57eSRicard Wanderlof /* Number of GPIO pins exposed via the gpiolib interface */ 44*e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIOS_MAX 2 45*e9a3b57eSRicard Wanderlof 46*e9a3b57eSRicard Wanderlof #define ADC3XXX_RATES SNDRV_PCM_RATE_8000_96000 47*e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 48*e9a3b57eSRicard Wanderlof SNDRV_PCM_FMTBIT_S20_3LE | \ 49*e9a3b57eSRicard Wanderlof SNDRV_PCM_FMTBIT_S24_3LE | \ 50*e9a3b57eSRicard Wanderlof SNDRV_PCM_FMTBIT_S32_LE) 51*e9a3b57eSRicard Wanderlof 52*e9a3b57eSRicard Wanderlof /* 53*e9a3b57eSRicard Wanderlof * PLL modes, to be used for clk_id for set_sysclk callback. 54*e9a3b57eSRicard Wanderlof * 55*e9a3b57eSRicard Wanderlof * The default behavior (AUTO) is to take the first matching entry in the clock 56*e9a3b57eSRicard Wanderlof * table, which is intended to be the PLL based one if there is more than one. 57*e9a3b57eSRicard Wanderlof * 58*e9a3b57eSRicard Wanderlof * Setting the clock source using simple-card (clocks or 59*e9a3b57eSRicard Wanderlof * system-clock-frequency property) sets clk_id = 0 = ADC3XXX_PLL_AUTO. 60*e9a3b57eSRicard Wanderlof */ 61*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_AUTO 0 /* Use first available mode */ 62*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_ENABLE 1 /* Use PLL for clock generation */ 63*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_BYPASS 2 /* Don't use PLL for clock generation */ 64*e9a3b57eSRicard Wanderlof 65*e9a3b57eSRicard Wanderlof /* Register definitions. */ 66*e9a3b57eSRicard Wanderlof 67*e9a3b57eSRicard Wanderlof #define ADC3XXX_PAGE_SIZE 128 68*e9a3b57eSRicard Wanderlof #define ADC3XXX_REG(page, reg) ((page * ADC3XXX_PAGE_SIZE) + reg) 69*e9a3b57eSRicard Wanderlof 70*e9a3b57eSRicard Wanderlof /* 71*e9a3b57eSRicard Wanderlof * Page 0 registers. 72*e9a3b57eSRicard Wanderlof */ 73*e9a3b57eSRicard Wanderlof 74*e9a3b57eSRicard Wanderlof #define ADC3XXX_PAGE_SELECT ADC3XXX_REG(0, 0) 75*e9a3b57eSRicard Wanderlof #define ADC3XXX_RESET ADC3XXX_REG(0, 1) 76*e9a3b57eSRicard Wanderlof 77*e9a3b57eSRicard Wanderlof /* 2-3 Reserved */ 78*e9a3b57eSRicard Wanderlof 79*e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKGEN_MUX ADC3XXX_REG(0, 4) 80*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PROG_PR ADC3XXX_REG(0, 5) 81*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PROG_J ADC3XXX_REG(0, 6) 82*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PROG_D_MSB ADC3XXX_REG(0, 7) 83*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PROG_D_LSB ADC3XXX_REG(0, 8) 84*e9a3b57eSRicard Wanderlof 85*e9a3b57eSRicard Wanderlof /* 9-17 Reserved */ 86*e9a3b57eSRicard Wanderlof 87*e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_NADC ADC3XXX_REG(0, 18) 88*e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_MADC ADC3XXX_REG(0, 19) 89*e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_AOSR ADC3XXX_REG(0, 20) 90*e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_IADC ADC3XXX_REG(0, 21) 91*e9a3b57eSRicard Wanderlof 92*e9a3b57eSRicard Wanderlof /* 23-24 Reserved */ 93*e9a3b57eSRicard Wanderlof 94*e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKOUT_MUX ADC3XXX_REG(0, 25) 95*e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKOUT_M_DIV ADC3XXX_REG(0, 26) 96*e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_1 ADC3XXX_REG(0, 27) 97*e9a3b57eSRicard Wanderlof #define ADC3XXX_CH_OFFSET_1 ADC3XXX_REG(0, 28) 98*e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_2 ADC3XXX_REG(0, 29) 99*e9a3b57eSRicard Wanderlof #define ADC3XXX_BCLK_N_DIV ADC3XXX_REG(0, 30) 100*e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_3 ADC3XXX_REG(0, 31) 101*e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_4 ADC3XXX_REG(0, 32) 102*e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_5 ADC3XXX_REG(0, 33) 103*e9a3b57eSRicard Wanderlof #define ADC3XXX_I2S_SYNC ADC3XXX_REG(0, 34) 104*e9a3b57eSRicard Wanderlof /* 35 Reserved */ 105*e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_FLAG ADC3XXX_REG(0, 36) 106*e9a3b57eSRicard Wanderlof #define ADC3XXX_CH_OFFSET_2 ADC3XXX_REG(0, 37) 107*e9a3b57eSRicard Wanderlof #define ADC3XXX_I2S_TDM_CTRL ADC3XXX_REG(0, 38) 108*e9a3b57eSRicard Wanderlof /* 39-41 Reserved */ 109*e9a3b57eSRicard Wanderlof #define ADC3XXX_INTR_FLAG_1 ADC3XXX_REG(0, 42) 110*e9a3b57eSRicard Wanderlof #define ADC3XXX_INTR_FLAG_2 ADC3XXX_REG(0, 43) 111*e9a3b57eSRicard Wanderlof /* 44 Reserved */ 112*e9a3b57eSRicard Wanderlof #define ADC3XXX_INTR_FLAG_ADC1 ADC3XXX_REG(0, 45) 113*e9a3b57eSRicard Wanderlof /* 46 Reserved */ 114*e9a3b57eSRicard Wanderlof #define ADC3XXX_INTR_FLAG_ADC2 ADC3XXX_REG(0, 47) 115*e9a3b57eSRicard Wanderlof #define ADC3XXX_INT1_CTRL ADC3XXX_REG(0, 48) 116*e9a3b57eSRicard Wanderlof #define ADC3XXX_INT2_CTRL ADC3XXX_REG(0, 49) 117*e9a3b57eSRicard Wanderlof /* 50 Reserved */ 118*e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO2_CTRL ADC3XXX_REG(0, 51) 119*e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO1_CTRL ADC3XXX_REG(0, 52) 120*e9a3b57eSRicard Wanderlof #define ADC3XXX_DOUT_CTRL ADC3XXX_REG(0, 53) 121*e9a3b57eSRicard Wanderlof /* 54-56 Reserved */ 122*e9a3b57eSRicard Wanderlof #define ADC3XXX_SYNC_CTRL_1 ADC3XXX_REG(0, 57) 123*e9a3b57eSRicard Wanderlof #define ADC3XXX_SYNC_CTRL_2 ADC3XXX_REG(0, 58) 124*e9a3b57eSRicard Wanderlof #define ADC3XXX_CIC_GAIN_CTRL ADC3XXX_REG(0, 59) 125*e9a3b57eSRicard Wanderlof /* 60 Reserved */ 126*e9a3b57eSRicard Wanderlof #define ADC3XXX_PRB_SELECT ADC3XXX_REG(0, 61) 127*e9a3b57eSRicard Wanderlof #define ADC3XXX_INST_MODE_CTRL ADC3XXX_REG(0, 62) 128*e9a3b57eSRicard Wanderlof /* 63-79 Reserved */ 129*e9a3b57eSRicard Wanderlof #define ADC3XXX_MIC_POLARITY_CTRL ADC3XXX_REG(0, 80) 130*e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_DIGITAL ADC3XXX_REG(0, 81) 131*e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_FGA ADC3XXX_REG(0, 82) 132*e9a3b57eSRicard Wanderlof #define ADC3XXX_LADC_VOL ADC3XXX_REG(0, 83) 133*e9a3b57eSRicard Wanderlof #define ADC3XXX_RADC_VOL ADC3XXX_REG(0, 84) 134*e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_PHASE_COMP ADC3XXX_REG(0, 85) 135*e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_1 ADC3XXX_REG(0, 86) 136*e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_2 ADC3XXX_REG(0, 87) 137*e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_3 ADC3XXX_REG(0, 88) 138*e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_4 ADC3XXX_REG(0, 89) 139*e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_5 ADC3XXX_REG(0, 90) 140*e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_6 ADC3XXX_REG(0, 91) 141*e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_7 ADC3XXX_REG(0, 92) 142*e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_AGC_GAIN ADC3XXX_REG(0, 93) 143*e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_1 ADC3XXX_REG(0, 94) 144*e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_2 ADC3XXX_REG(0, 95) 145*e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_3 ADC3XXX_REG(0, 96) 146*e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_4 ADC3XXX_REG(0, 97) 147*e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_5 ADC3XXX_REG(0, 98) 148*e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_6 ADC3XXX_REG(0, 99) 149*e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_7 ADC3XXX_REG(0, 100) 150*e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_AGC_GAIN ADC3XXX_REG(0, 101) 151*e9a3b57eSRicard Wanderlof /* 102-127 Reserved */ 152*e9a3b57eSRicard Wanderlof 153*e9a3b57eSRicard Wanderlof /* 154*e9a3b57eSRicard Wanderlof * Page 1 registers. 155*e9a3b57eSRicard Wanderlof */ 156*e9a3b57eSRicard Wanderlof 157*e9a3b57eSRicard Wanderlof /* 1-25 Reserved */ 158*e9a3b57eSRicard Wanderlof #define ADC3XXX_DITHER_CTRL ADC3XXX_REG(1, 26) 159*e9a3b57eSRicard Wanderlof /* 27-50 Reserved */ 160*e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS_CTRL ADC3XXX_REG(1, 51) 161*e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_PGA_SEL_1 ADC3XXX_REG(1, 52) 162*e9a3b57eSRicard Wanderlof /* 53 Reserved */ 163*e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_PGA_SEL_2 ADC3XXX_REG(1, 54) 164*e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_PGA_SEL_1 ADC3XXX_REG(1, 55) 165*e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_PGA_SEL_2 ADC3XXX_REG(1, 57) 166*e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_APGA_CTRL ADC3XXX_REG(1, 59) 167*e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_APGA_CTRL ADC3XXX_REG(1, 60) 168*e9a3b57eSRicard Wanderlof #define ADC3XXX_LOW_CURRENT_MODES ADC3XXX_REG(1, 61) 169*e9a3b57eSRicard Wanderlof #define ADC3XXX_ANALOG_PGA_FLAGS ADC3XXX_REG(1, 62) 170*e9a3b57eSRicard Wanderlof /* 63-127 Reserved */ 171*e9a3b57eSRicard Wanderlof 172*e9a3b57eSRicard Wanderlof /* 173*e9a3b57eSRicard Wanderlof * Register bits. 174*e9a3b57eSRicard Wanderlof */ 175*e9a3b57eSRicard Wanderlof 176*e9a3b57eSRicard Wanderlof /* PLL Enable bits */ 177*e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_PLL_SHIFT 7 178*e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_PLL (1 << ADC3XXX_ENABLE_PLL_SHIFT) 179*e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_NADC_SHIFT 7 180*e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_NADC (1 << ADC3XXX_ENABLE_NADC_SHIFT) 181*e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_MADC_SHIFT 7 182*e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_MADC (1 << ADC3XXX_ENABLE_MADC_SHIFT) 183*e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_BCLK_SHIFT 7 184*e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_BCLK (1 << ADC3XXX_ENABLE_BCLK_SHIFT) 185*e9a3b57eSRicard Wanderlof 186*e9a3b57eSRicard Wanderlof /* Power bits */ 187*e9a3b57eSRicard Wanderlof #define ADC3XXX_LADC_PWR_ON 0x80 188*e9a3b57eSRicard Wanderlof #define ADC3XXX_RADC_PWR_ON 0x40 189*e9a3b57eSRicard Wanderlof 190*e9a3b57eSRicard Wanderlof #define ADC3XXX_SOFT_RESET 0x01 191*e9a3b57eSRicard Wanderlof #define ADC3XXX_BCLK_MASTER 0x08 192*e9a3b57eSRicard Wanderlof #define ADC3XXX_WCLK_MASTER 0x04 193*e9a3b57eSRicard Wanderlof 194*e9a3b57eSRicard Wanderlof /* Interface register masks */ 195*e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_MASK 0xc0 196*e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_SHIFT 6 197*e9a3b57eSRicard Wanderlof #define ADC3XXX_WLENGTH_MASK 0x30 198*e9a3b57eSRicard Wanderlof #define ADC3XXX_WLENGTH_SHIFT 4 199*e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKDIR_MASK 0x0c 200*e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKDIR_SHIFT 2 201*e9a3b57eSRicard Wanderlof 202*e9a3b57eSRicard Wanderlof /* Interface register bit patterns */ 203*e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_I2S (0 << ADC3XXX_FORMAT_SHIFT) 204*e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_DSP (1 << ADC3XXX_FORMAT_SHIFT) 205*e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_RJF (2 << ADC3XXX_FORMAT_SHIFT) 206*e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_LJF (3 << ADC3XXX_FORMAT_SHIFT) 207*e9a3b57eSRicard Wanderlof 208*e9a3b57eSRicard Wanderlof #define ADC3XXX_IFACE_16BITS (0 << ADC3XXX_WLENGTH_SHIFT) 209*e9a3b57eSRicard Wanderlof #define ADC3XXX_IFACE_20BITS (1 << ADC3XXX_WLENGTH_SHIFT) 210*e9a3b57eSRicard Wanderlof #define ADC3XXX_IFACE_24BITS (2 << ADC3XXX_WLENGTH_SHIFT) 211*e9a3b57eSRicard Wanderlof #define ADC3XXX_IFACE_32BITS (3 << ADC3XXX_WLENGTH_SHIFT) 212*e9a3b57eSRicard Wanderlof 213*e9a3b57eSRicard Wanderlof /* PLL P/R bit offsets */ 214*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLP_SHIFT 4 215*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLR_SHIFT 0 216*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PR_MASK 0x7f 217*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLJ_MASK 0x3f 218*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLD_MSB_MASK 0x3f 219*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLD_LSB_MASK 0xff 220*e9a3b57eSRicard Wanderlof #define ADC3XXX_NADC_MASK 0x7f 221*e9a3b57eSRicard Wanderlof #define ADC3XXX_MADC_MASK 0x7f 222*e9a3b57eSRicard Wanderlof #define ADC3XXX_AOSR_MASK 0xff 223*e9a3b57eSRicard Wanderlof #define ADC3XXX_IADC_MASK 0xff 224*e9a3b57eSRicard Wanderlof #define ADC3XXX_BDIV_MASK 0x7f 225*e9a3b57eSRicard Wanderlof 226*e9a3b57eSRicard Wanderlof /* PLL_CLKIN bits */ 227*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_CLKIN_SHIFT 2 228*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_CLKIN_MCLK 0x0 229*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_CLKIN_BCLK 0x1 230*e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_CLKIN_ZERO 0x3 231*e9a3b57eSRicard Wanderlof 232*e9a3b57eSRicard Wanderlof /* CODEC_CLKIN bits */ 233*e9a3b57eSRicard Wanderlof #define ADC3XXX_CODEC_CLKIN_SHIFT 0 234*e9a3b57eSRicard Wanderlof #define ADC3XXX_CODEC_CLKIN_MCLK 0x0 235*e9a3b57eSRicard Wanderlof #define ADC3XXX_CODEC_CLKIN_BCLK 0x1 236*e9a3b57eSRicard Wanderlof #define ADC3XXX_CODEC_CLKIN_PLL_CLK 0x3 237*e9a3b57eSRicard Wanderlof 238*e9a3b57eSRicard Wanderlof #define ADC3XXX_USE_PLL ((ADC3XXX_PLL_CLKIN_MCLK << ADC3XXX_PLL_CLKIN_SHIFT) | \ 239*e9a3b57eSRicard Wanderlof (ADC3XXX_CODEC_CLKIN_PLL_CLK << ADC3XXX_CODEC_CLKIN_SHIFT)) 240*e9a3b57eSRicard Wanderlof #define ADC3XXX_NO_PLL ((ADC3XXX_PLL_CLKIN_ZERO << ADC3XXX_PLL_CLKIN_SHIFT) | \ 241*e9a3b57eSRicard Wanderlof (ADC3XXX_CODEC_CLKIN_MCLK << ADC3XXX_CODEC_CLKIN_SHIFT)) 242*e9a3b57eSRicard Wanderlof 243*e9a3b57eSRicard Wanderlof /* Analog PGA control bits */ 244*e9a3b57eSRicard Wanderlof #define ADC3XXX_LPGA_MUTE 0x80 245*e9a3b57eSRicard Wanderlof #define ADC3XXX_RPGA_MUTE 0x80 246*e9a3b57eSRicard Wanderlof 247*e9a3b57eSRicard Wanderlof #define ADC3XXX_LPGA_GAIN_MASK 0x7f 248*e9a3b57eSRicard Wanderlof #define ADC3XXX_RPGA_GAIN_MASK 0x7f 249*e9a3b57eSRicard Wanderlof 250*e9a3b57eSRicard Wanderlof /* ADC current modes */ 251*e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_LOW_CURR_MODE 0x01 252*e9a3b57eSRicard Wanderlof 253*e9a3b57eSRicard Wanderlof /* Left ADC Input selection bits */ 254*e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL1_SHIFT 0 255*e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL2_SHIFT 2 256*e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL3_SHIFT 4 257*e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL4_SHIFT 6 258*e9a3b57eSRicard Wanderlof 259*e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL1X_SHIFT 0 260*e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL2X_SHIFT 2 261*e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL3X_SHIFT 4 262*e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_COMMON_MODE 0x40 263*e9a3b57eSRicard Wanderlof #define ADC3XXX_BYPASS_LPGA 0x80 264*e9a3b57eSRicard Wanderlof 265*e9a3b57eSRicard Wanderlof /* Right ADC Input selection bits */ 266*e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL1_SHIFT 0 267*e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL2_SHIFT 2 268*e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL3_SHIFT 4 269*e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL4_SHIFT 6 270*e9a3b57eSRicard Wanderlof 271*e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL1X_SHIFT 0 272*e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL2X_SHIFT 2 273*e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL3X_SHIFT 4 274*e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_COMMON_MODE 0x40 275*e9a3b57eSRicard Wanderlof #define ADC3XXX_BYPASS_RPGA 0x80 276*e9a3b57eSRicard Wanderlof 277*e9a3b57eSRicard Wanderlof /* MICBIAS control bits */ 278*e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS_MASK 0x2 279*e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS1_SHIFT 5 280*e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS2_SHIFT 3 281*e9a3b57eSRicard Wanderlof 282*e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_MAX_VOLUME 64 283*e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_POS_VOL 24 284*e9a3b57eSRicard Wanderlof 285*e9a3b57eSRicard Wanderlof /* GPIO control bits (GPIO1_CTRL and GPIO2_CTRL) */ 286*e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_CFG_MASK 0x3c 287*e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_CFG_SHIFT 2 288*e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK 0x01 289*e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT 0 290*e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_INPUT_VALUE_MASK 0x02 291*e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_INPUT_VALUE_SHIFT 1 292*e9a3b57eSRicard Wanderlof 293*e9a3b57eSRicard Wanderlof enum adc3xxx_type { 294*e9a3b57eSRicard Wanderlof ADC3001 = 0, 295*e9a3b57eSRicard Wanderlof ADC3101 296*e9a3b57eSRicard Wanderlof }; 297*e9a3b57eSRicard Wanderlof 298*e9a3b57eSRicard Wanderlof struct adc3xxx { 299*e9a3b57eSRicard Wanderlof struct device *dev; 300*e9a3b57eSRicard Wanderlof enum adc3xxx_type type; 301*e9a3b57eSRicard Wanderlof struct clk *mclk; 302*e9a3b57eSRicard Wanderlof struct regmap *regmap; 303*e9a3b57eSRicard Wanderlof struct gpio_desc *rst_pin; 304*e9a3b57eSRicard Wanderlof unsigned int pll_mode; 305*e9a3b57eSRicard Wanderlof unsigned int sysclk; 306*e9a3b57eSRicard Wanderlof unsigned int gpio_cfg[ADC3XXX_GPIOS_MAX]; /* value+1 (0 => not set) */ 307*e9a3b57eSRicard Wanderlof unsigned int micbias_vg[ADC3XXX_MICBIAS_PINS]; 308*e9a3b57eSRicard Wanderlof int master; 309*e9a3b57eSRicard Wanderlof u8 page_no; 310*e9a3b57eSRicard Wanderlof int use_pll; 311*e9a3b57eSRicard Wanderlof struct gpio_chip gpio_chip; 312*e9a3b57eSRicard Wanderlof }; 313*e9a3b57eSRicard Wanderlof 314*e9a3b57eSRicard Wanderlof static const unsigned int adc3xxx_gpio_ctrl_reg[ADC3XXX_GPIOS_MAX] = { 315*e9a3b57eSRicard Wanderlof ADC3XXX_GPIO1_CTRL, 316*e9a3b57eSRicard Wanderlof ADC3XXX_GPIO2_CTRL 317*e9a3b57eSRicard Wanderlof }; 318*e9a3b57eSRicard Wanderlof 319*e9a3b57eSRicard Wanderlof static const unsigned int adc3xxx_micbias_shift[ADC3XXX_MICBIAS_PINS] = { 320*e9a3b57eSRicard Wanderlof ADC3XXX_MICBIAS1_SHIFT, 321*e9a3b57eSRicard Wanderlof ADC3XXX_MICBIAS2_SHIFT 322*e9a3b57eSRicard Wanderlof }; 323*e9a3b57eSRicard Wanderlof 324*e9a3b57eSRicard Wanderlof static const struct reg_default adc3xxx_defaults[] = { 325*e9a3b57eSRicard Wanderlof /* Page 0 */ 326*e9a3b57eSRicard Wanderlof { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x00 }, 327*e9a3b57eSRicard Wanderlof { 4, 0x00 }, { 5, 0x11 }, { 6, 0x04 }, { 7, 0x00 }, 328*e9a3b57eSRicard Wanderlof { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x00 }, 329*e9a3b57eSRicard Wanderlof { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x00 }, 330*e9a3b57eSRicard Wanderlof { 16, 0x00 }, { 17, 0x00 }, { 18, 0x01 }, { 19, 0x01 }, 331*e9a3b57eSRicard Wanderlof { 20, 0x80 }, { 21, 0x80 }, { 22, 0x04 }, { 23, 0x00 }, 332*e9a3b57eSRicard Wanderlof { 24, 0x00 }, { 25, 0x00 }, { 26, 0x01 }, { 27, 0x00 }, 333*e9a3b57eSRicard Wanderlof { 28, 0x00 }, { 29, 0x02 }, { 30, 0x01 }, { 31, 0x00 }, 334*e9a3b57eSRicard Wanderlof { 32, 0x00 }, { 33, 0x10 }, { 34, 0x00 }, { 35, 0x00 }, 335*e9a3b57eSRicard Wanderlof { 36, 0x00 }, { 37, 0x00 }, { 38, 0x02 }, { 39, 0x00 }, 336*e9a3b57eSRicard Wanderlof { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x00 }, 337*e9a3b57eSRicard Wanderlof { 44, 0x00 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 }, 338*e9a3b57eSRicard Wanderlof { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x00 }, 339*e9a3b57eSRicard Wanderlof { 52, 0x00 }, { 53, 0x12 }, { 54, 0x00 }, { 55, 0x00 }, 340*e9a3b57eSRicard Wanderlof { 56, 0x00 }, { 57, 0x00 }, { 58, 0x00 }, { 59, 0x44 }, 341*e9a3b57eSRicard Wanderlof { 60, 0x00 }, { 61, 0x01 }, { 62, 0x00 }, { 63, 0x00 }, 342*e9a3b57eSRicard Wanderlof { 64, 0x00 }, { 65, 0x00 }, { 66, 0x00 }, { 67, 0x00 }, 343*e9a3b57eSRicard Wanderlof { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 }, 344*e9a3b57eSRicard Wanderlof { 72, 0x00 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 }, 345*e9a3b57eSRicard Wanderlof { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 }, 346*e9a3b57eSRicard Wanderlof { 80, 0x00 }, { 81, 0x00 }, { 82, 0x88 }, { 83, 0x00 }, 347*e9a3b57eSRicard Wanderlof { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 }, 348*e9a3b57eSRicard Wanderlof { 88, 0x7f }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 }, 349*e9a3b57eSRicard Wanderlof { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 }, 350*e9a3b57eSRicard Wanderlof { 96, 0x7f }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 }, 351*e9a3b57eSRicard Wanderlof { 100, 0x00 }, { 101, 0x00 }, { 102, 0x00 }, { 103, 0x00 }, 352*e9a3b57eSRicard Wanderlof { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 }, 353*e9a3b57eSRicard Wanderlof { 108, 0x00 }, { 109, 0x00 }, { 110, 0x00 }, { 111, 0x00 }, 354*e9a3b57eSRicard Wanderlof { 112, 0x00 }, { 113, 0x00 }, { 114, 0x00 }, { 115, 0x00 }, 355*e9a3b57eSRicard Wanderlof { 116, 0x00 }, { 117, 0x00 }, { 118, 0x00 }, { 119, 0x00 }, 356*e9a3b57eSRicard Wanderlof { 120, 0x00 }, { 121, 0x00 }, { 122, 0x00 }, { 123, 0x00 }, 357*e9a3b57eSRicard Wanderlof { 124, 0x00 }, { 125, 0x00 }, { 126, 0x00 }, { 127, 0x00 }, 358*e9a3b57eSRicard Wanderlof 359*e9a3b57eSRicard Wanderlof /* Page 1 */ 360*e9a3b57eSRicard Wanderlof { 128, 0x00 }, { 129, 0x00 }, { 130, 0x00 }, { 131, 0x00 }, 361*e9a3b57eSRicard Wanderlof { 132, 0x00 }, { 133, 0x00 }, { 134, 0x00 }, { 135, 0x00 }, 362*e9a3b57eSRicard Wanderlof { 136, 0x00 }, { 137, 0x00 }, { 138, 0x00 }, { 139, 0x00 }, 363*e9a3b57eSRicard Wanderlof { 140, 0x00 }, { 141, 0x00 }, { 142, 0x00 }, { 143, 0x00 }, 364*e9a3b57eSRicard Wanderlof { 144, 0x00 }, { 145, 0x00 }, { 146, 0x00 }, { 147, 0x00 }, 365*e9a3b57eSRicard Wanderlof { 148, 0x00 }, { 149, 0x00 }, { 150, 0x00 }, { 151, 0x00 }, 366*e9a3b57eSRicard Wanderlof { 152, 0x00 }, { 153, 0x00 }, { 154, 0x00 }, { 155, 0x00 }, 367*e9a3b57eSRicard Wanderlof { 156, 0x00 }, { 157, 0x00 }, { 158, 0x00 }, { 159, 0x00 }, 368*e9a3b57eSRicard Wanderlof { 160, 0x00 }, { 161, 0x00 }, { 162, 0x00 }, { 163, 0x00 }, 369*e9a3b57eSRicard Wanderlof { 164, 0x00 }, { 165, 0x00 }, { 166, 0x00 }, { 167, 0x00 }, 370*e9a3b57eSRicard Wanderlof { 168, 0x00 }, { 169, 0x00 }, { 170, 0x00 }, { 171, 0x00 }, 371*e9a3b57eSRicard Wanderlof { 172, 0x00 }, { 173, 0x00 }, { 174, 0x00 }, { 175, 0x00 }, 372*e9a3b57eSRicard Wanderlof { 176, 0x00 }, { 177, 0x00 }, { 178, 0x00 }, { 179, 0x00 }, 373*e9a3b57eSRicard Wanderlof { 180, 0xff }, { 181, 0x00 }, { 182, 0x3f }, { 183, 0xff }, 374*e9a3b57eSRicard Wanderlof { 184, 0x00 }, { 185, 0x3f }, { 186, 0x00 }, { 187, 0x80 }, 375*e9a3b57eSRicard Wanderlof { 188, 0x80 }, { 189, 0x00 }, { 190, 0x00 }, { 191, 0x00 }, 376*e9a3b57eSRicard Wanderlof }; 377*e9a3b57eSRicard Wanderlof 378*e9a3b57eSRicard Wanderlof static bool adc3xxx_volatile_reg(struct device *dev, unsigned int reg) 379*e9a3b57eSRicard Wanderlof { 380*e9a3b57eSRicard Wanderlof switch (reg) { 381*e9a3b57eSRicard Wanderlof case ADC3XXX_RESET: 382*e9a3b57eSRicard Wanderlof return true; 383*e9a3b57eSRicard Wanderlof default: 384*e9a3b57eSRicard Wanderlof return false; 385*e9a3b57eSRicard Wanderlof } 386*e9a3b57eSRicard Wanderlof } 387*e9a3b57eSRicard Wanderlof 388*e9a3b57eSRicard Wanderlof static const struct regmap_range_cfg adc3xxx_ranges[] = { 389*e9a3b57eSRicard Wanderlof { 390*e9a3b57eSRicard Wanderlof .range_min = 0, 391*e9a3b57eSRicard Wanderlof .range_max = 2 * ADC3XXX_PAGE_SIZE, 392*e9a3b57eSRicard Wanderlof .selector_reg = ADC3XXX_PAGE_SELECT, 393*e9a3b57eSRicard Wanderlof .selector_mask = 0xff, 394*e9a3b57eSRicard Wanderlof .selector_shift = 0, 395*e9a3b57eSRicard Wanderlof .window_start = 0, 396*e9a3b57eSRicard Wanderlof .window_len = ADC3XXX_PAGE_SIZE, 397*e9a3b57eSRicard Wanderlof } 398*e9a3b57eSRicard Wanderlof }; 399*e9a3b57eSRicard Wanderlof 400*e9a3b57eSRicard Wanderlof static const struct regmap_config adc3xxx_regmap = { 401*e9a3b57eSRicard Wanderlof .reg_bits = 8, 402*e9a3b57eSRicard Wanderlof .val_bits = 8, 403*e9a3b57eSRicard Wanderlof 404*e9a3b57eSRicard Wanderlof .reg_defaults = adc3xxx_defaults, 405*e9a3b57eSRicard Wanderlof .num_reg_defaults = ARRAY_SIZE(adc3xxx_defaults), 406*e9a3b57eSRicard Wanderlof 407*e9a3b57eSRicard Wanderlof .volatile_reg = adc3xxx_volatile_reg, 408*e9a3b57eSRicard Wanderlof 409*e9a3b57eSRicard Wanderlof .cache_type = REGCACHE_RBTREE, 410*e9a3b57eSRicard Wanderlof 411*e9a3b57eSRicard Wanderlof .ranges = adc3xxx_ranges, 412*e9a3b57eSRicard Wanderlof .num_ranges = ARRAY_SIZE(adc3xxx_ranges), 413*e9a3b57eSRicard Wanderlof .max_register = 2 * ADC3XXX_PAGE_SIZE, 414*e9a3b57eSRicard Wanderlof }; 415*e9a3b57eSRicard Wanderlof 416*e9a3b57eSRicard Wanderlof struct adc3xxx_rate_divs { 417*e9a3b57eSRicard Wanderlof u32 mclk; 418*e9a3b57eSRicard Wanderlof u32 rate; 419*e9a3b57eSRicard Wanderlof u8 pll_p; 420*e9a3b57eSRicard Wanderlof u8 pll_r; 421*e9a3b57eSRicard Wanderlof u8 pll_j; 422*e9a3b57eSRicard Wanderlof u16 pll_d; 423*e9a3b57eSRicard Wanderlof u8 nadc; 424*e9a3b57eSRicard Wanderlof u8 madc; 425*e9a3b57eSRicard Wanderlof u8 aosr; 426*e9a3b57eSRicard Wanderlof }; 427*e9a3b57eSRicard Wanderlof 428*e9a3b57eSRicard Wanderlof /* 429*e9a3b57eSRicard Wanderlof * PLL and Clock settings. 430*e9a3b57eSRicard Wanderlof * If p member is 0, PLL is not used. 431*e9a3b57eSRicard Wanderlof * The order of the entries in this table have the PLL entries before 432*e9a3b57eSRicard Wanderlof * the non-PLL entries, so that the PLL modes are preferred unless 433*e9a3b57eSRicard Wanderlof * the PLL mode setting says otherwise. 434*e9a3b57eSRicard Wanderlof */ 435*e9a3b57eSRicard Wanderlof static const struct adc3xxx_rate_divs adc3xxx_divs[] = { 436*e9a3b57eSRicard Wanderlof /* mclk, rate, p, r, j, d, nadc, madc, aosr */ 437*e9a3b57eSRicard Wanderlof /* 8k rate */ 438*e9a3b57eSRicard Wanderlof { 12000000, 8000, 1, 1, 7, 1680, 42, 2, 128 }, 439*e9a3b57eSRicard Wanderlof { 12288000, 8000, 1, 1, 7, 0000, 42, 2, 128 }, 440*e9a3b57eSRicard Wanderlof /* 11.025k rate */ 441*e9a3b57eSRicard Wanderlof { 12000000, 11025, 1, 1, 6, 8208, 29, 2, 128 }, 442*e9a3b57eSRicard Wanderlof /* 16k rate */ 443*e9a3b57eSRicard Wanderlof { 12000000, 16000, 1, 1, 7, 1680, 21, 2, 128 }, 444*e9a3b57eSRicard Wanderlof { 12288000, 16000, 1, 1, 7, 0000, 21, 2, 128 }, 445*e9a3b57eSRicard Wanderlof /* 22.05k rate */ 446*e9a3b57eSRicard Wanderlof { 12000000, 22050, 1, 1, 7, 560, 15, 2, 128 }, 447*e9a3b57eSRicard Wanderlof /* 32k rate */ 448*e9a3b57eSRicard Wanderlof { 12000000, 32000, 1, 1, 8, 1920, 12, 2, 128 }, 449*e9a3b57eSRicard Wanderlof { 12288000, 32000, 1, 1, 8, 0000, 12, 2, 128 }, 450*e9a3b57eSRicard Wanderlof /* 44.1k rate */ 451*e9a3b57eSRicard Wanderlof { 12000000, 44100, 1, 1, 7, 5264, 8, 2, 128 }, 452*e9a3b57eSRicard Wanderlof /* 48k rate */ 453*e9a3b57eSRicard Wanderlof { 12000000, 48000, 1, 1, 7, 1680, 7, 2, 128 }, 454*e9a3b57eSRicard Wanderlof { 12288000, 48000, 1, 1, 7, 0000, 7, 2, 128 }, 455*e9a3b57eSRicard Wanderlof { 24576000, 48000, 1, 1, 3, 5000, 7, 2, 128 }, /* With PLL */ 456*e9a3b57eSRicard Wanderlof { 24576000, 48000, 0, 0, 0, 0000, 2, 2, 128 }, /* Without PLL */ 457*e9a3b57eSRicard Wanderlof /* 88.2k rate */ 458*e9a3b57eSRicard Wanderlof { 12000000, 88200, 1, 1, 7, 5264, 4, 4, 64 }, 459*e9a3b57eSRicard Wanderlof /* 96k rate */ 460*e9a3b57eSRicard Wanderlof { 12000000, 96000, 1, 1, 8, 1920, 4, 4, 64 }, 461*e9a3b57eSRicard Wanderlof }; 462*e9a3b57eSRicard Wanderlof 463*e9a3b57eSRicard Wanderlof static int adc3xxx_get_divs(struct device *dev, int mclk, int rate, int pll_mode) 464*e9a3b57eSRicard Wanderlof { 465*e9a3b57eSRicard Wanderlof int i; 466*e9a3b57eSRicard Wanderlof 467*e9a3b57eSRicard Wanderlof dev_dbg(dev, "mclk = %d, rate = %d, clock mode %u\n", 468*e9a3b57eSRicard Wanderlof mclk, rate, pll_mode); 469*e9a3b57eSRicard Wanderlof for (i = 0; i < ARRAY_SIZE(adc3xxx_divs); i++) { 470*e9a3b57eSRicard Wanderlof const struct adc3xxx_rate_divs *mode = &adc3xxx_divs[i]; 471*e9a3b57eSRicard Wanderlof 472*e9a3b57eSRicard Wanderlof /* Skip this entry if it doesn't fulfill the intended clock 473*e9a3b57eSRicard Wanderlof * mode requirement. We consider anything besides the two 474*e9a3b57eSRicard Wanderlof * modes below to be the same as ADC3XXX_PLL_AUTO. 475*e9a3b57eSRicard Wanderlof */ 476*e9a3b57eSRicard Wanderlof if ((pll_mode == ADC3XXX_PLL_BYPASS && mode->pll_p) || 477*e9a3b57eSRicard Wanderlof (pll_mode == ADC3XXX_PLL_ENABLE && !mode->pll_p)) 478*e9a3b57eSRicard Wanderlof continue; 479*e9a3b57eSRicard Wanderlof 480*e9a3b57eSRicard Wanderlof if (mode->rate == rate && mode->mclk == mclk) 481*e9a3b57eSRicard Wanderlof return i; 482*e9a3b57eSRicard Wanderlof } 483*e9a3b57eSRicard Wanderlof 484*e9a3b57eSRicard Wanderlof dev_info(dev, "Master clock rate %d and sample rate %d is not supported\n", 485*e9a3b57eSRicard Wanderlof mclk, rate); 486*e9a3b57eSRicard Wanderlof return -EINVAL; 487*e9a3b57eSRicard Wanderlof } 488*e9a3b57eSRicard Wanderlof 489*e9a3b57eSRicard Wanderlof static int adc3xxx_pll_delay(struct snd_soc_dapm_widget *w, 490*e9a3b57eSRicard Wanderlof struct snd_kcontrol *kcontrol, int event) 491*e9a3b57eSRicard Wanderlof { 492*e9a3b57eSRicard Wanderlof /* 10msec delay needed after PLL power-up to allow 493*e9a3b57eSRicard Wanderlof * PLL and dividers to stabilize (datasheet p13). 494*e9a3b57eSRicard Wanderlof */ 495*e9a3b57eSRicard Wanderlof usleep_range(10000, 20000); 496*e9a3b57eSRicard Wanderlof 497*e9a3b57eSRicard Wanderlof return 0; 498*e9a3b57eSRicard Wanderlof } 499*e9a3b57eSRicard Wanderlof 500*e9a3b57eSRicard Wanderlof static const char * const adc_softstepping_text[] = { "1 step", "2 step", "off" }; 501*e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(adc_softstepping_enum, ADC3XXX_ADC_DIGITAL, 0, 502*e9a3b57eSRicard Wanderlof adc_softstepping_text); 503*e9a3b57eSRicard Wanderlof 504*e9a3b57eSRicard Wanderlof static const char * const multiplier_text[] = { "1", "2", "4", "8", "16", "32", "64", "128" }; 505*e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(left_agc_attack_mult_enum, 506*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_CHN_AGC_4, 0, multiplier_text); 507*e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(right_agc_attack_mult_enum, 508*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_4, 0, multiplier_text); 509*e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(left_agc_decay_mult_enum, 510*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_CHN_AGC_5, 0, multiplier_text); 511*e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(right_agc_decay_mult_enum, 512*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_5, 0, multiplier_text); 513*e9a3b57eSRicard Wanderlof 514*e9a3b57eSRicard Wanderlof static const char * const dither_dc_offset_text[] = { 515*e9a3b57eSRicard Wanderlof "0mV", "15mV", "30mV", "45mV", "60mV", "75mV", "90mV", "105mV", 516*e9a3b57eSRicard Wanderlof "-15mV", "-30mV", "-45mV", "-60mV", "-75mV", "-90mV", "-105mV" 517*e9a3b57eSRicard Wanderlof }; 518*e9a3b57eSRicard Wanderlof static const unsigned int dither_dc_offset_values[] = { 519*e9a3b57eSRicard Wanderlof 0, 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15 520*e9a3b57eSRicard Wanderlof }; 521*e9a3b57eSRicard Wanderlof static SOC_VALUE_ENUM_DOUBLE_DECL(dither_dc_offset_enum, 522*e9a3b57eSRicard Wanderlof ADC3XXX_DITHER_CTRL, 523*e9a3b57eSRicard Wanderlof 4, 0, 0xf, dither_dc_offset_text, 524*e9a3b57eSRicard Wanderlof dither_dc_offset_values); 525*e9a3b57eSRicard Wanderlof 526*e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 50, 0); 527*e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0); 528*e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0); 529*e9a3b57eSRicard Wanderlof /* AGC target: 8 values: -5.5, -8, -10, -12, -14, -17, -20, -24 dB */ 530*e9a3b57eSRicard Wanderlof /* It would be nice to declare these in the order above, but empirically 531*e9a3b57eSRicard Wanderlof * TLV_DB_SCALE_ITEM doesn't take lightly to the increment (second) parameter 532*e9a3b57eSRicard Wanderlof * being negative, despite there being examples to the contrary in other 533*e9a3b57eSRicard Wanderlof * drivers. So declare these in the order from lowest to highest, and 534*e9a3b57eSRicard Wanderlof * set the invert flag in the SOC_DOUBLE_R_TLV declaration instead. 535*e9a3b57eSRicard Wanderlof */ 536*e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_RANGE(agc_target_tlv, 537*e9a3b57eSRicard Wanderlof 0, 0, TLV_DB_SCALE_ITEM(-2400, 0, 0), 538*e9a3b57eSRicard Wanderlof 1, 3, TLV_DB_SCALE_ITEM(-2000, 300, 0), 539*e9a3b57eSRicard Wanderlof 4, 6, TLV_DB_SCALE_ITEM(-1200, 200, 0), 540*e9a3b57eSRicard Wanderlof 7, 7, TLV_DB_SCALE_ITEM(-550, 0, 0)); 541*e9a3b57eSRicard Wanderlof /* Since the 'disabled' value (mute) is at the highest value in the dB 542*e9a3b57eSRicard Wanderlof * range (i.e. just before -32 dB) rather than the lowest, we need to resort 543*e9a3b57eSRicard Wanderlof * to using a TLV_DB_RANGE in order to get the mute value in the right place. 544*e9a3b57eSRicard Wanderlof */ 545*e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_RANGE(agc_thresh_tlv, 546*e9a3b57eSRicard Wanderlof 0, 30, TLV_DB_SCALE_ITEM(-9000, 200, 0), 547*e9a3b57eSRicard Wanderlof 31, 31, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */ 548*e9a3b57eSRicard Wanderlof /* AGC hysteresis: 4 values: 1, 2, 4 dB, disabled (= mute) */ 549*e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_RANGE(agc_hysteresis_tlv, 550*e9a3b57eSRicard Wanderlof 0, 1, TLV_DB_SCALE_ITEM(100, 100, 0), 551*e9a3b57eSRicard Wanderlof 2, 2, TLV_DB_SCALE_ITEM(400, 0, 0), 552*e9a3b57eSRicard Wanderlof 3, 3, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */ 553*e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(agc_max_tlv, 0, 50, 0); 554*e9a3b57eSRicard Wanderlof /* Input attenuation: -6 dB or 0 dB */ 555*e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(input_attenuation_tlv, -600, 600, 0); 556*e9a3b57eSRicard Wanderlof 557*e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new adc3xxx_snd_controls[] = { 558*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("PGA Capture Volume", ADC3XXX_LEFT_APGA_CTRL, 559*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_APGA_CTRL, 0, 80, 0, pga_tlv), 560*e9a3b57eSRicard Wanderlof SOC_DOUBLE("PGA Capture Switch", ADC3XXX_ADC_FGA, 7, 3, 1, 1), 561*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Capture Switch", ADC3XXX_LEFT_CHN_AGC_1, 562*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_1, 7, 1, 0), 563*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("AGC Target Level Capture Volume", ADC3XXX_LEFT_CHN_AGC_1, 564*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_2, 4, 0x07, 1, agc_target_tlv), 565*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("AGC Noise Threshold Capture Volume", ADC3XXX_LEFT_CHN_AGC_2, 566*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_2, 1, 0x1f, 1, agc_thresh_tlv), 567*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("AGC Hysteresis Capture Volume", ADC3XXX_LEFT_CHN_AGC_2, 568*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_2, 6, 3, 0, agc_hysteresis_tlv), 569*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Clip Stepping Capture Switch", ADC3XXX_LEFT_CHN_AGC_2, 570*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_2, 0, 1, 0), 571*e9a3b57eSRicard Wanderlof /* 572*e9a3b57eSRicard Wanderlof * Oddly enough, the data sheet says the default value 573*e9a3b57eSRicard Wanderlof * for the left/right AGC maximum gain register field 574*e9a3b57eSRicard Wanderlof * (ADC3XXX_LEFT/RIGHT_CHN_AGC_3 bits 0..6) is 0x7f = 127 575*e9a3b57eSRicard Wanderlof * (verified empirically) even though this value (indeed, above 576*e9a3b57eSRicard Wanderlof * 0x50) is specified as 'Reserved. Do not use.' in the accompanying 577*e9a3b57eSRicard Wanderlof * table in the data sheet. 578*e9a3b57eSRicard Wanderlof */ 579*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("AGC Maximum Capture Volume", ADC3XXX_LEFT_CHN_AGC_3, 580*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_3, 0, 0x50, 0, agc_max_tlv), 581*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Attack Time", ADC3XXX_LEFT_CHN_AGC_4, 582*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_4, 3, 0x1f, 0), 583*e9a3b57eSRicard Wanderlof /* Would like to have the multipliers as LR pairs, but there is 584*e9a3b57eSRicard Wanderlof * no SOC_ENUM_foo which accepts two values in separate registers. 585*e9a3b57eSRicard Wanderlof */ 586*e9a3b57eSRicard Wanderlof SOC_ENUM("AGC Left Attack Time Multiplier", left_agc_attack_mult_enum), 587*e9a3b57eSRicard Wanderlof SOC_ENUM("AGC Right Attack Time Multiplier", right_agc_attack_mult_enum), 588*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Decay Time", ADC3XXX_LEFT_CHN_AGC_5, 589*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_5, 3, 0x1f, 0), 590*e9a3b57eSRicard Wanderlof SOC_ENUM("AGC Left Decay Time Multiplier", left_agc_decay_mult_enum), 591*e9a3b57eSRicard Wanderlof SOC_ENUM("AGC Right Decay Time Multiplier", right_agc_decay_mult_enum), 592*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Noise Debounce", ADC3XXX_LEFT_CHN_AGC_6, 593*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_6, 0, 0x1f, 0), 594*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Signal Debounce", ADC3XXX_LEFT_CHN_AGC_7, 595*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_7, 0, 0x0f, 0), 596*e9a3b57eSRicard Wanderlof /* Read only register */ 597*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_S_TLV("AGC Applied Capture Volume", ADC3XXX_LEFT_AGC_GAIN, 598*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_AGC_GAIN, 0, -24, 40, 6, 0, adc_tlv), 599*e9a3b57eSRicard Wanderlof /* ADC soft stepping */ 600*e9a3b57eSRicard Wanderlof SOC_ENUM("ADC Soft Stepping", adc_softstepping_enum), 601*e9a3b57eSRicard Wanderlof /* Left/Right Input attenuation */ 602*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input IN_1L Capture Volume", 603*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv), 604*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input IN_2L Capture Volume", 605*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv), 606*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input IN_3L Capture Volume", 607*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv), 608*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input IN_1R Capture Volume", 609*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv), 610*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input DIF_2L_3L Capture Volume", 611*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv), 612*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input DIF_1L_1R Capture Volume", 613*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv), 614*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input DIF_2R_3R Capture Volume", 615*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv), 616*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input IN_1R Capture Volume", 617*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv), 618*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input IN_2R Capture Volume", 619*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv), 620*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input IN_3R Capture Volume", 621*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv), 622*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input IN_1L Capture Volume", 623*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv), 624*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input DIF_2R_3R Capture Volume", 625*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv), 626*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input DIF_1L_1R Capture Volume", 627*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv), 628*e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input DIF_2L_3L Capture Volume", 629*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv), 630*e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_S_TLV("ADC Volume Control Capture Volume", ADC3XXX_LADC_VOL, 631*e9a3b57eSRicard Wanderlof ADC3XXX_RADC_VOL, 0, -24, 40, 6, 0, adc_tlv), 632*e9a3b57eSRicard Wanderlof /* Empirically, the following doesn't work the way it's supposed 633*e9a3b57eSRicard Wanderlof * to. Values 0, -0.1, -0.2 and -0.3 dB result in the same level, and 634*e9a3b57eSRicard Wanderlof * -0.4 dB drops about 0.12 dB on a specific chip. 635*e9a3b57eSRicard Wanderlof */ 636*e9a3b57eSRicard Wanderlof SOC_DOUBLE_TLV("ADC Fine Volume Control Capture Volume", ADC3XXX_ADC_FGA, 637*e9a3b57eSRicard Wanderlof 4, 0, 4, 1, adc_fine_tlv), 638*e9a3b57eSRicard Wanderlof SOC_SINGLE("Left ADC Unselected CM Bias Capture Switch", 639*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 6, 1, 0), 640*e9a3b57eSRicard Wanderlof SOC_SINGLE("Right ADC Unselected CM Bias Capture Switch", 641*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 6, 1, 0), 642*e9a3b57eSRicard Wanderlof SOC_ENUM("Dither Control DC Offset", dither_dc_offset_enum), 643*e9a3b57eSRicard Wanderlof }; 644*e9a3b57eSRicard Wanderlof 645*e9a3b57eSRicard Wanderlof /* Left input selection, Single Ended inputs and Differential inputs */ 646*e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new left_input_mixer_controls[] = { 647*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_1L Capture Switch", 648*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 1, 0x1, 1), 649*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_2L Capture Switch", 650*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 3, 0x1, 1), 651*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_3L Capture Switch", 652*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 5, 0x1, 1), 653*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch", 654*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 7, 0x1, 1), 655*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch", 656*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 5, 0x1, 1), 657*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch", 658*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 3, 0x1, 1), 659*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_1R Capture Switch", 660*e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 1, 0x1, 1), 661*e9a3b57eSRicard Wanderlof }; 662*e9a3b57eSRicard Wanderlof 663*e9a3b57eSRicard Wanderlof /* Right input selection, Single Ended inputs and Differential inputs */ 664*e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new right_input_mixer_controls[] = { 665*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_1R Capture Switch", 666*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 1, 0x1, 1), 667*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_2R Capture Switch", 668*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 3, 0x1, 1), 669*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_3R Capture Switch", 670*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 5, 0x1, 1), 671*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch", 672*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 7, 0x1, 1), 673*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch", 674*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 5, 0x1, 1), 675*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch", 676*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 3, 0x1, 1), 677*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_1L Capture Switch", 678*e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 1, 0x1, 1), 679*e9a3b57eSRicard Wanderlof }; 680*e9a3b57eSRicard Wanderlof 681*e9a3b57eSRicard Wanderlof /* Left Digital Mic input for left ADC */ 682*e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new left_input_dmic_controls[] = { 683*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("Left ADC Capture Switch", 684*e9a3b57eSRicard Wanderlof ADC3XXX_ADC_DIGITAL, 3, 0x1, 0), 685*e9a3b57eSRicard Wanderlof }; 686*e9a3b57eSRicard Wanderlof 687*e9a3b57eSRicard Wanderlof /* Right Digital Mic input for Right ADC */ 688*e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new right_input_dmic_controls[] = { 689*e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("Right ADC Capture Switch", 690*e9a3b57eSRicard Wanderlof ADC3XXX_ADC_DIGITAL, 2, 0x1, 0), 691*e9a3b57eSRicard Wanderlof }; 692*e9a3b57eSRicard Wanderlof 693*e9a3b57eSRicard Wanderlof /* DAPM widgets */ 694*e9a3b57eSRicard Wanderlof static const struct snd_soc_dapm_widget adc3xxx_dapm_widgets[] = { 695*e9a3b57eSRicard Wanderlof 696*e9a3b57eSRicard Wanderlof /* Left Input Selection */ 697*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_MIXER("Left Input", SND_SOC_NOPM, 0, 0, 698*e9a3b57eSRicard Wanderlof &left_input_mixer_controls[0], 699*e9a3b57eSRicard Wanderlof ARRAY_SIZE(left_input_mixer_controls)), 700*e9a3b57eSRicard Wanderlof /* Right Input Selection */ 701*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_MIXER("Right Input", SND_SOC_NOPM, 0, 0, 702*e9a3b57eSRicard Wanderlof &right_input_mixer_controls[0], 703*e9a3b57eSRicard Wanderlof ARRAY_SIZE(right_input_mixer_controls)), 704*e9a3b57eSRicard Wanderlof /* PGA selection */ 705*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_PGA("Left PGA", ADC3XXX_LEFT_APGA_CTRL, 7, 1, NULL, 0), 706*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_PGA("Right PGA", ADC3XXX_RIGHT_APGA_CTRL, 7, 1, NULL, 0), 707*e9a3b57eSRicard Wanderlof 708*e9a3b57eSRicard Wanderlof /* Digital Microphone Input Control for Left/Right ADC */ 709*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_MIXER("Left DMic Input", SND_SOC_NOPM, 0, 0, 710*e9a3b57eSRicard Wanderlof &left_input_dmic_controls[0], 711*e9a3b57eSRicard Wanderlof ARRAY_SIZE(left_input_dmic_controls)), 712*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_MIXER("Right DMic Input", SND_SOC_NOPM, 0, 0, 713*e9a3b57eSRicard Wanderlof &right_input_dmic_controls[0], 714*e9a3b57eSRicard Wanderlof ARRAY_SIZE(right_input_dmic_controls)), 715*e9a3b57eSRicard Wanderlof 716*e9a3b57eSRicard Wanderlof /* Left/Right ADC */ 717*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ADC3XXX_ADC_DIGITAL, 7, 0), 718*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ADC3XXX_ADC_DIGITAL, 6, 0), 719*e9a3b57eSRicard Wanderlof 720*e9a3b57eSRicard Wanderlof /* Inputs */ 721*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_1L"), 722*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_1R"), 723*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_2L"), 724*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_2R"), 725*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_3L"), 726*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_3R"), 727*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFL_1L_1R"), 728*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFL_2L_3L"), 729*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFL_2R_3R"), 730*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFR_1L_1R"), 731*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFR_2L_3L"), 732*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFR_2R_3R"), 733*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DMic_L"), 734*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DMic_R"), 735*e9a3b57eSRicard Wanderlof 736*e9a3b57eSRicard Wanderlof /* Digital audio interface output */ 737*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_AIF_OUT("AIF_OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 738*e9a3b57eSRicard Wanderlof 739*e9a3b57eSRicard Wanderlof /* Clocks */ 740*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_SUPPLY("PLL_CLK", ADC3XXX_PLL_PROG_PR, ADC3XXX_ENABLE_PLL_SHIFT, 741*e9a3b57eSRicard Wanderlof 0, adc3xxx_pll_delay, SND_SOC_DAPM_POST_PMU), 742*e9a3b57eSRicard Wanderlof 743*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_SUPPLY("ADC_CLK", ADC3XXX_ADC_NADC, ADC3XXX_ENABLE_NADC_SHIFT, 744*e9a3b57eSRicard Wanderlof 0, NULL, 0), 745*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK", ADC3XXX_ADC_MADC, ADC3XXX_ENABLE_MADC_SHIFT, 746*e9a3b57eSRicard Wanderlof 0, NULL, 0), 747*e9a3b57eSRicard Wanderlof 748*e9a3b57eSRicard Wanderlof /* This refers to the generated BCLK in master mode. */ 749*e9a3b57eSRicard Wanderlof SND_SOC_DAPM_SUPPLY("BCLK", ADC3XXX_BCLK_N_DIV, ADC3XXX_ENABLE_BCLK_SHIFT, 750*e9a3b57eSRicard Wanderlof 0, NULL, 0), 751*e9a3b57eSRicard Wanderlof }; 752*e9a3b57eSRicard Wanderlof 753*e9a3b57eSRicard Wanderlof static const struct snd_soc_dapm_route adc3xxx_intercon[] = { 754*e9a3b57eSRicard Wanderlof /* Left input selection from switches */ 755*e9a3b57eSRicard Wanderlof { "Left Input", "IN_1L Capture Switch", "IN_1L" }, 756*e9a3b57eSRicard Wanderlof { "Left Input", "IN_2L Capture Switch", "IN_2L" }, 757*e9a3b57eSRicard Wanderlof { "Left Input", "IN_3L Capture Switch", "IN_3L" }, 758*e9a3b57eSRicard Wanderlof { "Left Input", "DIF_2L_3L Capture Switch", "DIFL_2L_3L" }, 759*e9a3b57eSRicard Wanderlof { "Left Input", "DIF_1L_1R Capture Switch", "DIFL_1L_1R" }, 760*e9a3b57eSRicard Wanderlof { "Left Input", "DIF_2R_3R Capture Switch", "DIFL_2R_3R" }, 761*e9a3b57eSRicard Wanderlof { "Left Input", "IN_1R Capture Switch", "IN_1R" }, 762*e9a3b57eSRicard Wanderlof 763*e9a3b57eSRicard Wanderlof /* Left input selection to left PGA */ 764*e9a3b57eSRicard Wanderlof { "Left PGA", NULL, "Left Input" }, 765*e9a3b57eSRicard Wanderlof 766*e9a3b57eSRicard Wanderlof /* Left PGA to left ADC */ 767*e9a3b57eSRicard Wanderlof { "Left ADC", NULL, "Left PGA" }, 768*e9a3b57eSRicard Wanderlof 769*e9a3b57eSRicard Wanderlof /* Right input selection from switches */ 770*e9a3b57eSRicard Wanderlof { "Right Input", "IN_1R Capture Switch", "IN_1R" }, 771*e9a3b57eSRicard Wanderlof { "Right Input", "IN_2R Capture Switch", "IN_2R" }, 772*e9a3b57eSRicard Wanderlof { "Right Input", "IN_3R Capture Switch", "IN_3R" }, 773*e9a3b57eSRicard Wanderlof { "Right Input", "DIF_2R_3R Capture Switch", "DIFR_2R_3R" }, 774*e9a3b57eSRicard Wanderlof { "Right Input", "DIF_1L_1R Capture Switch", "DIFR_1L_1R" }, 775*e9a3b57eSRicard Wanderlof { "Right Input", "DIF_2L_3L Capture Switch", "DIFR_2L_3L" }, 776*e9a3b57eSRicard Wanderlof { "Right Input", "IN_1L Capture Switch", "IN_1L" }, 777*e9a3b57eSRicard Wanderlof 778*e9a3b57eSRicard Wanderlof /* Right input selection to right PGA */ 779*e9a3b57eSRicard Wanderlof { "Right PGA", NULL, "Right Input" }, 780*e9a3b57eSRicard Wanderlof 781*e9a3b57eSRicard Wanderlof /* Right PGA to right ADC */ 782*e9a3b57eSRicard Wanderlof { "Right ADC", NULL, "Right PGA" }, 783*e9a3b57eSRicard Wanderlof 784*e9a3b57eSRicard Wanderlof /* Left DMic Input selection from switch */ 785*e9a3b57eSRicard Wanderlof { "Left DMic Input", "Left ADC Capture Switch", "DMic_L" }, 786*e9a3b57eSRicard Wanderlof 787*e9a3b57eSRicard Wanderlof /* Left DMic to left ADC */ 788*e9a3b57eSRicard Wanderlof { "Left ADC", NULL, "Left DMic Input" }, 789*e9a3b57eSRicard Wanderlof 790*e9a3b57eSRicard Wanderlof /* Right DMic Input selection from switch */ 791*e9a3b57eSRicard Wanderlof { "Right DMic Input", "Right ADC Capture Switch", "DMic_R" }, 792*e9a3b57eSRicard Wanderlof 793*e9a3b57eSRicard Wanderlof /* Right DMic to right ADC */ 794*e9a3b57eSRicard Wanderlof { "Right ADC", NULL, "Right DMic Input" }, 795*e9a3b57eSRicard Wanderlof 796*e9a3b57eSRicard Wanderlof /* ADC to AIF output */ 797*e9a3b57eSRicard Wanderlof { "AIF_OUT", NULL, "Left ADC" }, 798*e9a3b57eSRicard Wanderlof { "AIF_OUT", NULL, "Right ADC" }, 799*e9a3b57eSRicard Wanderlof 800*e9a3b57eSRicard Wanderlof /* Clocking */ 801*e9a3b57eSRicard Wanderlof { "ADC_MOD_CLK", NULL, "ADC_CLK" }, 802*e9a3b57eSRicard Wanderlof { "Left ADC", NULL, "ADC_MOD_CLK" }, 803*e9a3b57eSRicard Wanderlof { "Right ADC", NULL, "ADC_MOD_CLK" }, 804*e9a3b57eSRicard Wanderlof 805*e9a3b57eSRicard Wanderlof { "BCLK", NULL, "ADC_CLK" }, 806*e9a3b57eSRicard Wanderlof }; 807*e9a3b57eSRicard Wanderlof 808*e9a3b57eSRicard Wanderlof static const struct snd_soc_dapm_route adc3xxx_pll_intercon[] = { 809*e9a3b57eSRicard Wanderlof { "ADC_CLK", NULL, "PLL_CLK" }, 810*e9a3b57eSRicard Wanderlof }; 811*e9a3b57eSRicard Wanderlof 812*e9a3b57eSRicard Wanderlof static const struct snd_soc_dapm_route adc3xxx_bclk_out_intercon[] = { 813*e9a3b57eSRicard Wanderlof { "AIF_OUT", NULL, "BCLK" } 814*e9a3b57eSRicard Wanderlof }; 815*e9a3b57eSRicard Wanderlof 816*e9a3b57eSRicard Wanderlof static int adc3xxx_gpio_request(struct gpio_chip *chip, unsigned int offset) 817*e9a3b57eSRicard Wanderlof { 818*e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = gpiochip_get_data(chip); 819*e9a3b57eSRicard Wanderlof 820*e9a3b57eSRicard Wanderlof if (offset >= ADC3XXX_GPIOS_MAX) 821*e9a3b57eSRicard Wanderlof return -EINVAL; 822*e9a3b57eSRicard Wanderlof 823*e9a3b57eSRicard Wanderlof /* GPIO1 is offset 0, GPIO2 is offset 1 */ 824*e9a3b57eSRicard Wanderlof /* We check here that the GPIO pins are either not configured in the 825*e9a3b57eSRicard Wanderlof * DT, or that they purposely are set as outputs. 826*e9a3b57eSRicard Wanderlof * (Input mode not yet implemented). 827*e9a3b57eSRicard Wanderlof */ 828*e9a3b57eSRicard Wanderlof if (adc3xxx->gpio_cfg[offset] != 0 && 829*e9a3b57eSRicard Wanderlof adc3xxx->gpio_cfg[offset] != ADC3XXX_GPIO_GPO + 1) 830*e9a3b57eSRicard Wanderlof return -EINVAL; 831*e9a3b57eSRicard Wanderlof 832*e9a3b57eSRicard Wanderlof return 0; 833*e9a3b57eSRicard Wanderlof } 834*e9a3b57eSRicard Wanderlof 835*e9a3b57eSRicard Wanderlof static int adc3xxx_gpio_direction_out(struct gpio_chip *chip, 836*e9a3b57eSRicard Wanderlof unsigned int offset, int value) 837*e9a3b57eSRicard Wanderlof { 838*e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = gpiochip_get_data(chip); 839*e9a3b57eSRicard Wanderlof 840*e9a3b57eSRicard Wanderlof /* Set GPIO output function. */ 841*e9a3b57eSRicard Wanderlof return regmap_update_bits(adc3xxx->regmap, 842*e9a3b57eSRicard Wanderlof adc3xxx_gpio_ctrl_reg[offset], 843*e9a3b57eSRicard Wanderlof ADC3XXX_GPIO_CTRL_CFG_MASK | 844*e9a3b57eSRicard Wanderlof ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK, 845*e9a3b57eSRicard Wanderlof ADC3XXX_GPIO_GPO << ADC3XXX_GPIO_CTRL_CFG_SHIFT | 846*e9a3b57eSRicard Wanderlof !!value << ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT); 847*e9a3b57eSRicard Wanderlof } 848*e9a3b57eSRicard Wanderlof 849*e9a3b57eSRicard Wanderlof /* With only GPIO outputs configured, we never get the .direction_out call, 850*e9a3b57eSRicard Wanderlof * so we set the output mode and output value in the same call. Hence 851*e9a3b57eSRicard Wanderlof * .set in practice does the same thing as .direction_out . 852*e9a3b57eSRicard Wanderlof */ 853*e9a3b57eSRicard Wanderlof static void adc3xxx_gpio_set(struct gpio_chip *chip, unsigned int offset, 854*e9a3b57eSRicard Wanderlof int value) 855*e9a3b57eSRicard Wanderlof { 856*e9a3b57eSRicard Wanderlof (void) adc3xxx_gpio_direction_out(chip, offset, value); 857*e9a3b57eSRicard Wanderlof } 858*e9a3b57eSRicard Wanderlof 859*e9a3b57eSRicard Wanderlof /* Even though we only support GPIO output for now, some GPIO clients 860*e9a3b57eSRicard Wanderlof * want to read the current pin state using the .get callback. 861*e9a3b57eSRicard Wanderlof */ 862*e9a3b57eSRicard Wanderlof static int adc3xxx_gpio_get(struct gpio_chip *chip, unsigned int offset) 863*e9a3b57eSRicard Wanderlof { 864*e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = gpiochip_get_data(chip); 865*e9a3b57eSRicard Wanderlof unsigned int regval; 866*e9a3b57eSRicard Wanderlof int ret; 867*e9a3b57eSRicard Wanderlof 868*e9a3b57eSRicard Wanderlof /* We only allow output pins, so just read the value set in the output 869*e9a3b57eSRicard Wanderlof * pin register field. 870*e9a3b57eSRicard Wanderlof */ 871*e9a3b57eSRicard Wanderlof ret = regmap_read(adc3xxx->regmap, adc3xxx_gpio_ctrl_reg[offset], ®val); 872*e9a3b57eSRicard Wanderlof if (ret) 873*e9a3b57eSRicard Wanderlof return ret; 874*e9a3b57eSRicard Wanderlof return !!(regval & ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK); 875*e9a3b57eSRicard Wanderlof } 876*e9a3b57eSRicard Wanderlof 877*e9a3b57eSRicard Wanderlof static const struct gpio_chip adc3xxx_gpio_chip = { 878*e9a3b57eSRicard Wanderlof .label = "adc3xxx", 879*e9a3b57eSRicard Wanderlof .owner = THIS_MODULE, 880*e9a3b57eSRicard Wanderlof .request = adc3xxx_gpio_request, 881*e9a3b57eSRicard Wanderlof .direction_output = adc3xxx_gpio_direction_out, 882*e9a3b57eSRicard Wanderlof .set = adc3xxx_gpio_set, 883*e9a3b57eSRicard Wanderlof .get = adc3xxx_gpio_get, 884*e9a3b57eSRicard Wanderlof .can_sleep = 1, 885*e9a3b57eSRicard Wanderlof }; 886*e9a3b57eSRicard Wanderlof 887*e9a3b57eSRicard Wanderlof static void adc3xxx_free_gpio(struct adc3xxx *adc3xxx) 888*e9a3b57eSRicard Wanderlof { 889*e9a3b57eSRicard Wanderlof gpiochip_remove(&adc3xxx->gpio_chip); 890*e9a3b57eSRicard Wanderlof } 891*e9a3b57eSRicard Wanderlof 892*e9a3b57eSRicard Wanderlof static void adc3xxx_init_gpio(struct adc3xxx *adc3xxx) 893*e9a3b57eSRicard Wanderlof { 894*e9a3b57eSRicard Wanderlof int gpio, micbias; 895*e9a3b57eSRicard Wanderlof int ret; 896*e9a3b57eSRicard Wanderlof 897*e9a3b57eSRicard Wanderlof adc3xxx->gpio_chip = adc3xxx_gpio_chip; 898*e9a3b57eSRicard Wanderlof adc3xxx->gpio_chip.ngpio = ADC3XXX_GPIOS_MAX; 899*e9a3b57eSRicard Wanderlof adc3xxx->gpio_chip.parent = adc3xxx->dev; 900*e9a3b57eSRicard Wanderlof adc3xxx->gpio_chip.base = -1; 901*e9a3b57eSRicard Wanderlof 902*e9a3b57eSRicard Wanderlof ret = gpiochip_add_data(&adc3xxx->gpio_chip, adc3xxx); 903*e9a3b57eSRicard Wanderlof if (ret) 904*e9a3b57eSRicard Wanderlof dev_err(adc3xxx->dev, "Failed to add gpios: %d\n", ret); 905*e9a3b57eSRicard Wanderlof 906*e9a3b57eSRicard Wanderlof /* Set up potential GPIO configuration from the devicetree. 907*e9a3b57eSRicard Wanderlof * This allows us to set up things which are not software 908*e9a3b57eSRicard Wanderlof * controllable GPIOs, such as PDM microphone I/O, 909*e9a3b57eSRicard Wanderlof */ 910*e9a3b57eSRicard Wanderlof for (gpio = 0; gpio < ADC3XXX_GPIOS_MAX; gpio++) { 911*e9a3b57eSRicard Wanderlof unsigned int cfg = adc3xxx->gpio_cfg[gpio]; 912*e9a3b57eSRicard Wanderlof 913*e9a3b57eSRicard Wanderlof if (cfg) { 914*e9a3b57eSRicard Wanderlof cfg--; /* actual value to use is stored +1 */ 915*e9a3b57eSRicard Wanderlof regmap_update_bits(adc3xxx->regmap, 916*e9a3b57eSRicard Wanderlof adc3xxx_gpio_ctrl_reg[gpio], 917*e9a3b57eSRicard Wanderlof ADC3XXX_GPIO_CTRL_CFG_MASK, 918*e9a3b57eSRicard Wanderlof cfg << ADC3XXX_GPIO_CTRL_CFG_SHIFT); 919*e9a3b57eSRicard Wanderlof } 920*e9a3b57eSRicard Wanderlof } 921*e9a3b57eSRicard Wanderlof 922*e9a3b57eSRicard Wanderlof /* Set up micbias voltage */ 923*e9a3b57eSRicard Wanderlof for (micbias = 0; micbias < ADC3XXX_MICBIAS_PINS; micbias++) { 924*e9a3b57eSRicard Wanderlof unsigned int vg = adc3xxx->micbias_vg[micbias]; 925*e9a3b57eSRicard Wanderlof 926*e9a3b57eSRicard Wanderlof regmap_update_bits(adc3xxx->regmap, 927*e9a3b57eSRicard Wanderlof ADC3XXX_MICBIAS_CTRL, 928*e9a3b57eSRicard Wanderlof ADC3XXX_MICBIAS_MASK << adc3xxx_micbias_shift[micbias], 929*e9a3b57eSRicard Wanderlof vg << adc3xxx_micbias_shift[micbias]); 930*e9a3b57eSRicard Wanderlof } 931*e9a3b57eSRicard Wanderlof } 932*e9a3b57eSRicard Wanderlof 933*e9a3b57eSRicard Wanderlof static int adc3xxx_parse_dt_gpio(struct adc3xxx *adc3xxx, 934*e9a3b57eSRicard Wanderlof const char *propname, unsigned int *cfg) 935*e9a3b57eSRicard Wanderlof { 936*e9a3b57eSRicard Wanderlof struct device *dev = adc3xxx->dev; 937*e9a3b57eSRicard Wanderlof struct device_node *np = dev->of_node; 938*e9a3b57eSRicard Wanderlof unsigned int val; 939*e9a3b57eSRicard Wanderlof 940*e9a3b57eSRicard Wanderlof if (!of_property_read_u32(np, propname, &val)) { 941*e9a3b57eSRicard Wanderlof if (val & ~15 || val == 7 || val >= 11) { 942*e9a3b57eSRicard Wanderlof dev_err(dev, "Invalid property value for '%s'\n", propname); 943*e9a3b57eSRicard Wanderlof return -EINVAL; 944*e9a3b57eSRicard Wanderlof } 945*e9a3b57eSRicard Wanderlof if (val == ADC3XXX_GPIO_GPI) 946*e9a3b57eSRicard Wanderlof dev_warn(dev, "GPIO Input read not yet implemented\n"); 947*e9a3b57eSRicard Wanderlof *cfg = val + 1; /* 0 => not set up, all others shifted +1 */ 948*e9a3b57eSRicard Wanderlof } 949*e9a3b57eSRicard Wanderlof return 0; 950*e9a3b57eSRicard Wanderlof } 951*e9a3b57eSRicard Wanderlof 952*e9a3b57eSRicard Wanderlof static int adc3xxx_parse_dt_micbias(struct adc3xxx *adc3xxx, 953*e9a3b57eSRicard Wanderlof const char *propname, unsigned int *vg) 954*e9a3b57eSRicard Wanderlof { 955*e9a3b57eSRicard Wanderlof struct device *dev = adc3xxx->dev; 956*e9a3b57eSRicard Wanderlof struct device_node *np = dev->of_node; 957*e9a3b57eSRicard Wanderlof unsigned int val; 958*e9a3b57eSRicard Wanderlof 959*e9a3b57eSRicard Wanderlof if (!of_property_read_u32(np, propname, &val)) { 960*e9a3b57eSRicard Wanderlof if (val >= ADC3XXX_MICBIAS_AVDD) { 961*e9a3b57eSRicard Wanderlof dev_err(dev, "Invalid property value for '%s'\n", propname); 962*e9a3b57eSRicard Wanderlof return -EINVAL; 963*e9a3b57eSRicard Wanderlof } 964*e9a3b57eSRicard Wanderlof *vg = val; 965*e9a3b57eSRicard Wanderlof } 966*e9a3b57eSRicard Wanderlof return 0; 967*e9a3b57eSRicard Wanderlof } 968*e9a3b57eSRicard Wanderlof 969*e9a3b57eSRicard Wanderlof static int adc3xxx_parse_pll_mode(uint32_t val, unsigned int *pll_mode) 970*e9a3b57eSRicard Wanderlof { 971*e9a3b57eSRicard Wanderlof if (val != ADC3XXX_PLL_ENABLE && val != ADC3XXX_PLL_BYPASS && 972*e9a3b57eSRicard Wanderlof val != ADC3XXX_PLL_AUTO) 973*e9a3b57eSRicard Wanderlof return -EINVAL; 974*e9a3b57eSRicard Wanderlof 975*e9a3b57eSRicard Wanderlof *pll_mode = val; 976*e9a3b57eSRicard Wanderlof 977*e9a3b57eSRicard Wanderlof return 0; 978*e9a3b57eSRicard Wanderlof } 979*e9a3b57eSRicard Wanderlof 980*e9a3b57eSRicard Wanderlof static void adc3xxx_setup_pll(struct snd_soc_component *component, 981*e9a3b57eSRicard Wanderlof int div_entry) 982*e9a3b57eSRicard Wanderlof { 983*e9a3b57eSRicard Wanderlof int i = div_entry; 984*e9a3b57eSRicard Wanderlof 985*e9a3b57eSRicard Wanderlof /* P & R values */ 986*e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_PLL_PROG_PR, 987*e9a3b57eSRicard Wanderlof (adc3xxx_divs[i].pll_p << ADC3XXX_PLLP_SHIFT) | 988*e9a3b57eSRicard Wanderlof (adc3xxx_divs[i].pll_r << ADC3XXX_PLLR_SHIFT)); 989*e9a3b57eSRicard Wanderlof /* J value */ 990*e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_PLL_PROG_J, 991*e9a3b57eSRicard Wanderlof adc3xxx_divs[i].pll_j & ADC3XXX_PLLJ_MASK); 992*e9a3b57eSRicard Wanderlof /* D value */ 993*e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_LSB, 994*e9a3b57eSRicard Wanderlof adc3xxx_divs[i].pll_d & ADC3XXX_PLLD_LSB_MASK); 995*e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_MSB, 996*e9a3b57eSRicard Wanderlof (adc3xxx_divs[i].pll_d >> 8) & ADC3XXX_PLLD_MSB_MASK); 997*e9a3b57eSRicard Wanderlof } 998*e9a3b57eSRicard Wanderlof 999*e9a3b57eSRicard Wanderlof static int adc3xxx_hw_params(struct snd_pcm_substream *substream, 1000*e9a3b57eSRicard Wanderlof struct snd_pcm_hw_params *params, 1001*e9a3b57eSRicard Wanderlof struct snd_soc_dai *dai) 1002*e9a3b57eSRicard Wanderlof { 1003*e9a3b57eSRicard Wanderlof struct snd_soc_component *component = dai->component; 1004*e9a3b57eSRicard Wanderlof struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component); 1005*e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component); 1006*e9a3b57eSRicard Wanderlof int i, width = 16; 1007*e9a3b57eSRicard Wanderlof u8 iface_len, bdiv; 1008*e9a3b57eSRicard Wanderlof 1009*e9a3b57eSRicard Wanderlof i = adc3xxx_get_divs(component->dev, adc3xxx->sysclk, 1010*e9a3b57eSRicard Wanderlof params_rate(params), adc3xxx->pll_mode); 1011*e9a3b57eSRicard Wanderlof 1012*e9a3b57eSRicard Wanderlof if (i < 0) 1013*e9a3b57eSRicard Wanderlof return i; 1014*e9a3b57eSRicard Wanderlof 1015*e9a3b57eSRicard Wanderlof /* select data word length */ 1016*e9a3b57eSRicard Wanderlof switch (params_format(params)) { 1017*e9a3b57eSRicard Wanderlof case SNDRV_PCM_FORMAT_S16_LE: 1018*e9a3b57eSRicard Wanderlof iface_len = ADC3XXX_IFACE_16BITS; 1019*e9a3b57eSRicard Wanderlof width = 16; 1020*e9a3b57eSRicard Wanderlof break; 1021*e9a3b57eSRicard Wanderlof case SNDRV_PCM_FORMAT_S20_3LE: 1022*e9a3b57eSRicard Wanderlof iface_len = ADC3XXX_IFACE_20BITS; 1023*e9a3b57eSRicard Wanderlof width = 20; 1024*e9a3b57eSRicard Wanderlof break; 1025*e9a3b57eSRicard Wanderlof case SNDRV_PCM_FORMAT_S24_LE: 1026*e9a3b57eSRicard Wanderlof iface_len = ADC3XXX_IFACE_24BITS; 1027*e9a3b57eSRicard Wanderlof width = 24; 1028*e9a3b57eSRicard Wanderlof break; 1029*e9a3b57eSRicard Wanderlof case SNDRV_PCM_FORMAT_S32_LE: 1030*e9a3b57eSRicard Wanderlof iface_len = ADC3XXX_IFACE_32BITS; 1031*e9a3b57eSRicard Wanderlof width = 32; 1032*e9a3b57eSRicard Wanderlof break; 1033*e9a3b57eSRicard Wanderlof default: 1034*e9a3b57eSRicard Wanderlof dev_err(component->dev, "Unsupported serial data format\n"); 1035*e9a3b57eSRicard Wanderlof return -EINVAL; 1036*e9a3b57eSRicard Wanderlof } 1037*e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_INTERFACE_CTRL_1, 1038*e9a3b57eSRicard Wanderlof ADC3XXX_WLENGTH_MASK, iface_len); 1039*e9a3b57eSRicard Wanderlof if (adc3xxx_divs[i].pll_p) { /* If PLL used for this mode */ 1040*e9a3b57eSRicard Wanderlof adc3xxx_setup_pll(component, i); 1041*e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_USE_PLL); 1042*e9a3b57eSRicard Wanderlof if (!adc3xxx->use_pll) { 1043*e9a3b57eSRicard Wanderlof snd_soc_dapm_add_routes(dapm, adc3xxx_pll_intercon, 1044*e9a3b57eSRicard Wanderlof ARRAY_SIZE(adc3xxx_pll_intercon)); 1045*e9a3b57eSRicard Wanderlof adc3xxx->use_pll = 1; 1046*e9a3b57eSRicard Wanderlof } 1047*e9a3b57eSRicard Wanderlof } else { 1048*e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_NO_PLL); 1049*e9a3b57eSRicard Wanderlof if (adc3xxx->use_pll) { 1050*e9a3b57eSRicard Wanderlof snd_soc_dapm_del_routes(dapm, adc3xxx_pll_intercon, 1051*e9a3b57eSRicard Wanderlof ARRAY_SIZE(adc3xxx_pll_intercon)); 1052*e9a3b57eSRicard Wanderlof adc3xxx->use_pll = 0; 1053*e9a3b57eSRicard Wanderlof } 1054*e9a3b57eSRicard Wanderlof } 1055*e9a3b57eSRicard Wanderlof 1056*e9a3b57eSRicard Wanderlof /* NADC */ 1057*e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_ADC_NADC, 1058*e9a3b57eSRicard Wanderlof ADC3XXX_NADC_MASK, adc3xxx_divs[i].nadc); 1059*e9a3b57eSRicard Wanderlof /* MADC */ 1060*e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_ADC_MADC, 1061*e9a3b57eSRicard Wanderlof ADC3XXX_MADC_MASK, adc3xxx_divs[i].madc); 1062*e9a3b57eSRicard Wanderlof /* AOSR */ 1063*e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_ADC_AOSR, 1064*e9a3b57eSRicard Wanderlof ADC3XXX_AOSR_MASK, adc3xxx_divs[i].aosr); 1065*e9a3b57eSRicard Wanderlof /* BDIV N Value */ 1066*e9a3b57eSRicard Wanderlof /* BCLK is (by default) set up to be derived from ADC_CLK */ 1067*e9a3b57eSRicard Wanderlof bdiv = (adc3xxx_divs[i].aosr * adc3xxx_divs[i].madc) / (2 * width); 1068*e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_BCLK_N_DIV, 1069*e9a3b57eSRicard Wanderlof ADC3XXX_BDIV_MASK, bdiv); 1070*e9a3b57eSRicard Wanderlof 1071*e9a3b57eSRicard Wanderlof return 0; 1072*e9a3b57eSRicard Wanderlof } 1073*e9a3b57eSRicard Wanderlof 1074*e9a3b57eSRicard Wanderlof static const char *adc3xxx_pll_mode_text(int pll_mode) 1075*e9a3b57eSRicard Wanderlof { 1076*e9a3b57eSRicard Wanderlof switch (pll_mode) { 1077*e9a3b57eSRicard Wanderlof case ADC3XXX_PLL_AUTO: 1078*e9a3b57eSRicard Wanderlof return "PLL auto"; 1079*e9a3b57eSRicard Wanderlof case ADC3XXX_PLL_ENABLE: 1080*e9a3b57eSRicard Wanderlof return "PLL enable"; 1081*e9a3b57eSRicard Wanderlof case ADC3XXX_PLL_BYPASS: 1082*e9a3b57eSRicard Wanderlof return "PLL bypass"; 1083*e9a3b57eSRicard Wanderlof default: 1084*e9a3b57eSRicard Wanderlof break; 1085*e9a3b57eSRicard Wanderlof } 1086*e9a3b57eSRicard Wanderlof 1087*e9a3b57eSRicard Wanderlof return "PLL unknown"; 1088*e9a3b57eSRicard Wanderlof } 1089*e9a3b57eSRicard Wanderlof 1090*e9a3b57eSRicard Wanderlof static int adc3xxx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1091*e9a3b57eSRicard Wanderlof int clk_id, unsigned int freq, int dir) 1092*e9a3b57eSRicard Wanderlof { 1093*e9a3b57eSRicard Wanderlof struct snd_soc_component *component = codec_dai->component; 1094*e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component); 1095*e9a3b57eSRicard Wanderlof int ret; 1096*e9a3b57eSRicard Wanderlof 1097*e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_pll_mode(clk_id, &adc3xxx->pll_mode); 1098*e9a3b57eSRicard Wanderlof if (ret < 0) 1099*e9a3b57eSRicard Wanderlof return ret; 1100*e9a3b57eSRicard Wanderlof 1101*e9a3b57eSRicard Wanderlof adc3xxx->sysclk = freq; 1102*e9a3b57eSRicard Wanderlof dev_dbg(component->dev, "Set sysclk to %u Hz, %s\n", 1103*e9a3b57eSRicard Wanderlof freq, adc3xxx_pll_mode_text(adc3xxx->pll_mode)); 1104*e9a3b57eSRicard Wanderlof return 0; 1105*e9a3b57eSRicard Wanderlof } 1106*e9a3b57eSRicard Wanderlof 1107*e9a3b57eSRicard Wanderlof static int adc3xxx_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1108*e9a3b57eSRicard Wanderlof { 1109*e9a3b57eSRicard Wanderlof struct snd_soc_component *component = codec_dai->component; 1110*e9a3b57eSRicard Wanderlof struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1111*e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component); 1112*e9a3b57eSRicard Wanderlof u8 clkdir = 0, format = 0; 1113*e9a3b57eSRicard Wanderlof int master = 0; 1114*e9a3b57eSRicard Wanderlof 1115*e9a3b57eSRicard Wanderlof /* set master/slave audio interface */ 1116*e9a3b57eSRicard Wanderlof switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1117*e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_CBP_CFP: 1118*e9a3b57eSRicard Wanderlof master = 1; 1119*e9a3b57eSRicard Wanderlof clkdir = ADC3XXX_BCLK_MASTER | ADC3XXX_WCLK_MASTER; 1120*e9a3b57eSRicard Wanderlof break; 1121*e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_CBC_CFC: 1122*e9a3b57eSRicard Wanderlof master = 0; 1123*e9a3b57eSRicard Wanderlof break; 1124*e9a3b57eSRicard Wanderlof default: 1125*e9a3b57eSRicard Wanderlof dev_err(component->dev, "Invalid DAI clock setup\n"); 1126*e9a3b57eSRicard Wanderlof return -EINVAL; 1127*e9a3b57eSRicard Wanderlof } 1128*e9a3b57eSRicard Wanderlof 1129*e9a3b57eSRicard Wanderlof /* 1130*e9a3b57eSRicard Wanderlof * match both interface format and signal polarities since they 1131*e9a3b57eSRicard Wanderlof * are fixed 1132*e9a3b57eSRicard Wanderlof */ 1133*e9a3b57eSRicard Wanderlof switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK)) { 1134*e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF: 1135*e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_I2S; 1136*e9a3b57eSRicard Wanderlof break; 1137*e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF: 1138*e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_DSP; 1139*e9a3b57eSRicard Wanderlof break; 1140*e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF: 1141*e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_DSP; 1142*e9a3b57eSRicard Wanderlof break; 1143*e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF: 1144*e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_RJF; 1145*e9a3b57eSRicard Wanderlof break; 1146*e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF: 1147*e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_LJF; 1148*e9a3b57eSRicard Wanderlof break; 1149*e9a3b57eSRicard Wanderlof default: 1150*e9a3b57eSRicard Wanderlof dev_err(component->dev, "Invalid DAI format\n"); 1151*e9a3b57eSRicard Wanderlof return -EINVAL; 1152*e9a3b57eSRicard Wanderlof } 1153*e9a3b57eSRicard Wanderlof 1154*e9a3b57eSRicard Wanderlof /* Add/del route enabling BCLK output as applicable */ 1155*e9a3b57eSRicard Wanderlof if (master && !adc3xxx->master) 1156*e9a3b57eSRicard Wanderlof snd_soc_dapm_add_routes(dapm, adc3xxx_bclk_out_intercon, 1157*e9a3b57eSRicard Wanderlof ARRAY_SIZE(adc3xxx_bclk_out_intercon)); 1158*e9a3b57eSRicard Wanderlof else if (!master && adc3xxx->master) 1159*e9a3b57eSRicard Wanderlof snd_soc_dapm_del_routes(dapm, adc3xxx_bclk_out_intercon, 1160*e9a3b57eSRicard Wanderlof ARRAY_SIZE(adc3xxx_bclk_out_intercon)); 1161*e9a3b57eSRicard Wanderlof adc3xxx->master = master; 1162*e9a3b57eSRicard Wanderlof 1163*e9a3b57eSRicard Wanderlof /* set clock direction and format */ 1164*e9a3b57eSRicard Wanderlof return snd_soc_component_update_bits(component, 1165*e9a3b57eSRicard Wanderlof ADC3XXX_INTERFACE_CTRL_1, 1166*e9a3b57eSRicard Wanderlof ADC3XXX_CLKDIR_MASK | ADC3XXX_FORMAT_MASK, 1167*e9a3b57eSRicard Wanderlof clkdir | format); 1168*e9a3b57eSRicard Wanderlof } 1169*e9a3b57eSRicard Wanderlof 1170*e9a3b57eSRicard Wanderlof static const struct snd_soc_dai_ops adc3xxx_dai_ops = { 1171*e9a3b57eSRicard Wanderlof .hw_params = adc3xxx_hw_params, 1172*e9a3b57eSRicard Wanderlof .set_sysclk = adc3xxx_set_dai_sysclk, 1173*e9a3b57eSRicard Wanderlof .set_fmt = adc3xxx_set_dai_fmt, 1174*e9a3b57eSRicard Wanderlof }; 1175*e9a3b57eSRicard Wanderlof 1176*e9a3b57eSRicard Wanderlof static struct snd_soc_dai_driver adc3xxx_dai = { 1177*e9a3b57eSRicard Wanderlof .name = "tlv320adc3xxx-hifi", 1178*e9a3b57eSRicard Wanderlof .capture = { 1179*e9a3b57eSRicard Wanderlof .stream_name = "Capture", 1180*e9a3b57eSRicard Wanderlof .channels_min = 1, 1181*e9a3b57eSRicard Wanderlof .channels_max = 2, 1182*e9a3b57eSRicard Wanderlof .rates = ADC3XXX_RATES, 1183*e9a3b57eSRicard Wanderlof .formats = ADC3XXX_FORMATS, 1184*e9a3b57eSRicard Wanderlof }, 1185*e9a3b57eSRicard Wanderlof .ops = &adc3xxx_dai_ops, 1186*e9a3b57eSRicard Wanderlof }; 1187*e9a3b57eSRicard Wanderlof 1188*e9a3b57eSRicard Wanderlof static const struct snd_soc_component_driver soc_component_dev_adc3xxx = { 1189*e9a3b57eSRicard Wanderlof .controls = adc3xxx_snd_controls, 1190*e9a3b57eSRicard Wanderlof .num_controls = ARRAY_SIZE(adc3xxx_snd_controls), 1191*e9a3b57eSRicard Wanderlof .dapm_widgets = adc3xxx_dapm_widgets, 1192*e9a3b57eSRicard Wanderlof .num_dapm_widgets = ARRAY_SIZE(adc3xxx_dapm_widgets), 1193*e9a3b57eSRicard Wanderlof .dapm_routes = adc3xxx_intercon, 1194*e9a3b57eSRicard Wanderlof .num_dapm_routes = ARRAY_SIZE(adc3xxx_intercon), 1195*e9a3b57eSRicard Wanderlof }; 1196*e9a3b57eSRicard Wanderlof 1197*e9a3b57eSRicard Wanderlof static int adc3xxx_i2c_probe(struct i2c_client *i2c, 1198*e9a3b57eSRicard Wanderlof const struct i2c_device_id *id) 1199*e9a3b57eSRicard Wanderlof { 1200*e9a3b57eSRicard Wanderlof struct device *dev = &i2c->dev; 1201*e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = NULL; 1202*e9a3b57eSRicard Wanderlof int ret; 1203*e9a3b57eSRicard Wanderlof 1204*e9a3b57eSRicard Wanderlof adc3xxx = devm_kzalloc(dev, sizeof(struct adc3xxx), GFP_KERNEL); 1205*e9a3b57eSRicard Wanderlof if (!adc3xxx) 1206*e9a3b57eSRicard Wanderlof return -ENOMEM; 1207*e9a3b57eSRicard Wanderlof adc3xxx->dev = dev; 1208*e9a3b57eSRicard Wanderlof 1209*e9a3b57eSRicard Wanderlof adc3xxx->rst_pin = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 1210*e9a3b57eSRicard Wanderlof if (IS_ERR(adc3xxx->rst_pin)) { 1211*e9a3b57eSRicard Wanderlof return dev_err_probe(dev, PTR_ERR(adc3xxx->rst_pin), 1212*e9a3b57eSRicard Wanderlof "Failed to request rst_pin\n"); 1213*e9a3b57eSRicard Wanderlof } 1214*e9a3b57eSRicard Wanderlof 1215*e9a3b57eSRicard Wanderlof adc3xxx->mclk = devm_clk_get(dev, NULL); 1216*e9a3b57eSRicard Wanderlof if (IS_ERR(adc3xxx->mclk)) { 1217*e9a3b57eSRicard Wanderlof /* 1218*e9a3b57eSRicard Wanderlof * The chip itself supports running off the BCLK either 1219*e9a3b57eSRicard Wanderlof * directly or via the PLL, but the driver does not (yet), so 1220*e9a3b57eSRicard Wanderlof * having a specified mclk is required. Otherwise, we could 1221*e9a3b57eSRicard Wanderlof * use the lack of a clocks property to indicate when BCLK is 1222*e9a3b57eSRicard Wanderlof * intended as the clock source. 1223*e9a3b57eSRicard Wanderlof */ 1224*e9a3b57eSRicard Wanderlof return dev_err_probe(dev, PTR_ERR(adc3xxx->mclk), 1225*e9a3b57eSRicard Wanderlof "Failed to acquire MCLK\n"); 1226*e9a3b57eSRicard Wanderlof } else if (adc3xxx->mclk) { 1227*e9a3b57eSRicard Wanderlof ret = clk_prepare_enable(adc3xxx->mclk); 1228*e9a3b57eSRicard Wanderlof if (ret < 0) 1229*e9a3b57eSRicard Wanderlof return ret; 1230*e9a3b57eSRicard Wanderlof dev_dbg(dev, "Enabled MCLK, freq %lu Hz\n", clk_get_rate(adc3xxx->mclk)); 1231*e9a3b57eSRicard Wanderlof } 1232*e9a3b57eSRicard Wanderlof 1233*e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmdin-gpio1", &adc3xxx->gpio_cfg[0]); 1234*e9a3b57eSRicard Wanderlof if (ret < 0) 1235*e9a3b57eSRicard Wanderlof return ret; 1236*e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmclk-gpio2", &adc3xxx->gpio_cfg[1]); 1237*e9a3b57eSRicard Wanderlof if (ret < 0) 1238*e9a3b57eSRicard Wanderlof return ret; 1239*e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_dt_micbias(adc3xxx, "ti,micbias1-vg", &adc3xxx->micbias_vg[0]); 1240*e9a3b57eSRicard Wanderlof if (ret < 0) 1241*e9a3b57eSRicard Wanderlof return ret; 1242*e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_dt_micbias(adc3xxx, "ti,micbias2-vg", &adc3xxx->micbias_vg[1]); 1243*e9a3b57eSRicard Wanderlof if (ret < 0) 1244*e9a3b57eSRicard Wanderlof return ret; 1245*e9a3b57eSRicard Wanderlof 1246*e9a3b57eSRicard Wanderlof adc3xxx->regmap = devm_regmap_init_i2c(i2c, &adc3xxx_regmap); 1247*e9a3b57eSRicard Wanderlof if (IS_ERR(adc3xxx->regmap)) { 1248*e9a3b57eSRicard Wanderlof ret = PTR_ERR(adc3xxx->regmap); 1249*e9a3b57eSRicard Wanderlof return ret; 1250*e9a3b57eSRicard Wanderlof } 1251*e9a3b57eSRicard Wanderlof 1252*e9a3b57eSRicard Wanderlof i2c_set_clientdata(i2c, adc3xxx); 1253*e9a3b57eSRicard Wanderlof 1254*e9a3b57eSRicard Wanderlof adc3xxx->type = id->driver_data; 1255*e9a3b57eSRicard Wanderlof 1256*e9a3b57eSRicard Wanderlof /* Reset codec chip */ 1257*e9a3b57eSRicard Wanderlof gpiod_set_value_cansleep(adc3xxx->rst_pin, 1); 1258*e9a3b57eSRicard Wanderlof usleep_range(2000, 100000); /* Requirement: > 10 ns (datasheet p13) */ 1259*e9a3b57eSRicard Wanderlof gpiod_set_value_cansleep(adc3xxx->rst_pin, 0); 1260*e9a3b57eSRicard Wanderlof 1261*e9a3b57eSRicard Wanderlof /* Potentially set up pins used as GPIOs */ 1262*e9a3b57eSRicard Wanderlof adc3xxx_init_gpio(adc3xxx); 1263*e9a3b57eSRicard Wanderlof 1264*e9a3b57eSRicard Wanderlof ret = snd_soc_register_component(dev, 1265*e9a3b57eSRicard Wanderlof &soc_component_dev_adc3xxx, &adc3xxx_dai, 1); 1266*e9a3b57eSRicard Wanderlof if (ret < 0) 1267*e9a3b57eSRicard Wanderlof dev_err(dev, "Failed to register codec: %d\n", ret); 1268*e9a3b57eSRicard Wanderlof 1269*e9a3b57eSRicard Wanderlof return ret; 1270*e9a3b57eSRicard Wanderlof } 1271*e9a3b57eSRicard Wanderlof 1272*e9a3b57eSRicard Wanderlof static int __exit adc3xxx_i2c_remove(struct i2c_client *client) 1273*e9a3b57eSRicard Wanderlof { 1274*e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = i2c_get_clientdata(client); 1275*e9a3b57eSRicard Wanderlof 1276*e9a3b57eSRicard Wanderlof if (adc3xxx->mclk) 1277*e9a3b57eSRicard Wanderlof clk_disable_unprepare(adc3xxx->mclk); 1278*e9a3b57eSRicard Wanderlof adc3xxx_free_gpio(adc3xxx); 1279*e9a3b57eSRicard Wanderlof snd_soc_unregister_component(&client->dev); 1280*e9a3b57eSRicard Wanderlof return 0; 1281*e9a3b57eSRicard Wanderlof } 1282*e9a3b57eSRicard Wanderlof 1283*e9a3b57eSRicard Wanderlof static const struct of_device_id tlv320adc3xxx_of_match[] = { 1284*e9a3b57eSRicard Wanderlof { .compatible = "ti,tlv320adc3001", }, 1285*e9a3b57eSRicard Wanderlof { .compatible = "ti,tlv320adc3101", }, 1286*e9a3b57eSRicard Wanderlof {}, 1287*e9a3b57eSRicard Wanderlof }; 1288*e9a3b57eSRicard Wanderlof MODULE_DEVICE_TABLE(of, tlv320adc3xxx_of_match); 1289*e9a3b57eSRicard Wanderlof 1290*e9a3b57eSRicard Wanderlof static const struct i2c_device_id adc3xxx_i2c_id[] = { 1291*e9a3b57eSRicard Wanderlof { "tlv320adc3001", ADC3001 }, 1292*e9a3b57eSRicard Wanderlof { "tlv320adc3101", ADC3101 }, 1293*e9a3b57eSRicard Wanderlof {} 1294*e9a3b57eSRicard Wanderlof }; 1295*e9a3b57eSRicard Wanderlof MODULE_DEVICE_TABLE(i2c, adc3xxx_i2c_id); 1296*e9a3b57eSRicard Wanderlof 1297*e9a3b57eSRicard Wanderlof static struct i2c_driver adc3xxx_i2c_driver = { 1298*e9a3b57eSRicard Wanderlof .driver = { 1299*e9a3b57eSRicard Wanderlof .name = "tlv320adc3xxx-codec", 1300*e9a3b57eSRicard Wanderlof .of_match_table = tlv320adc3xxx_of_match, 1301*e9a3b57eSRicard Wanderlof }, 1302*e9a3b57eSRicard Wanderlof .probe = adc3xxx_i2c_probe, 1303*e9a3b57eSRicard Wanderlof .remove = adc3xxx_i2c_remove, 1304*e9a3b57eSRicard Wanderlof .id_table = adc3xxx_i2c_id, 1305*e9a3b57eSRicard Wanderlof }; 1306*e9a3b57eSRicard Wanderlof 1307*e9a3b57eSRicard Wanderlof module_i2c_driver(adc3xxx_i2c_driver); 1308*e9a3b57eSRicard Wanderlof 1309*e9a3b57eSRicard Wanderlof MODULE_DESCRIPTION("ASoC TLV320ADC3xxx codec driver"); 1310*e9a3b57eSRicard Wanderlof MODULE_AUTHOR("shahina.s@mistralsolutions.com"); 1311*e9a3b57eSRicard Wanderlof MODULE_LICENSE("GPL v2"); 1312