1e9a3b57eSRicard Wanderlof // SPDX-License-Identifier: GPL-2.0-only 2e9a3b57eSRicard Wanderlof // 3e9a3b57eSRicard Wanderlof // Based on sound/soc/codecs/tlv320aic3x.c by Vladimir Barinov 4e9a3b57eSRicard Wanderlof // 5e9a3b57eSRicard Wanderlof // Copyright (C) 2010 Mistral Solutions Pvt Ltd. 6e9a3b57eSRicard Wanderlof // Author: Shahina Shaik <shahina.s@mistralsolutions.com> 7e9a3b57eSRicard Wanderlof // 8e9a3b57eSRicard Wanderlof // Copyright (C) 2014-2018, Ambarella, Inc. 9e9a3b57eSRicard Wanderlof // Author: Dongge wu <dgwu@ambarella.com> 10e9a3b57eSRicard Wanderlof // 11e9a3b57eSRicard Wanderlof // Copyright (C) 2021 Axis Communications AB 12e9a3b57eSRicard Wanderlof // Author: Ricard Wanderlof <ricardw@axis.com> 13e9a3b57eSRicard Wanderlof // 14e9a3b57eSRicard Wanderlof 15e9a3b57eSRicard Wanderlof #include <dt-bindings/sound/tlv320adc3xxx.h> 16e9a3b57eSRicard Wanderlof #include <linux/clk.h> 1719c5bda7SHui Tang #include <linux/gpio/consumer.h> 18e9a3b57eSRicard Wanderlof #include <linux/module.h> 19e9a3b57eSRicard Wanderlof #include <linux/moduleparam.h> 20e9a3b57eSRicard Wanderlof #include <linux/io.h> 21e9a3b57eSRicard Wanderlof #include <linux/init.h> 22e9a3b57eSRicard Wanderlof #include <linux/delay.h> 23e9a3b57eSRicard Wanderlof #include <linux/gpio/driver.h> 24e9a3b57eSRicard Wanderlof #include <linux/pm.h> 25e9a3b57eSRicard Wanderlof #include <linux/i2c.h> 26e9a3b57eSRicard Wanderlof #include <linux/platform_device.h> 27e9a3b57eSRicard Wanderlof #include <linux/cdev.h> 28e9a3b57eSRicard Wanderlof #include <linux/of_gpio.h> 29e9a3b57eSRicard Wanderlof #include <linux/slab.h> 30e9a3b57eSRicard Wanderlof #include <sound/core.h> 31e9a3b57eSRicard Wanderlof #include <sound/pcm.h> 32e9a3b57eSRicard Wanderlof #include <sound/pcm_params.h> 33e9a3b57eSRicard Wanderlof #include <sound/soc.h> 34e9a3b57eSRicard Wanderlof #include <sound/soc-dapm.h> 35e9a3b57eSRicard Wanderlof #include <sound/tlv.h> 36e9a3b57eSRicard Wanderlof #include <sound/initval.h> 37e9a3b57eSRicard Wanderlof 38e9a3b57eSRicard Wanderlof /* 39e9a3b57eSRicard Wanderlof * General definitions defining exported functionality. 40e9a3b57eSRicard Wanderlof */ 41e9a3b57eSRicard Wanderlof 42e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS_PINS 2 43e9a3b57eSRicard Wanderlof 44e9a3b57eSRicard Wanderlof /* Number of GPIO pins exposed via the gpiolib interface */ 45e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIOS_MAX 2 46e9a3b57eSRicard Wanderlof 47e9a3b57eSRicard Wanderlof #define ADC3XXX_RATES SNDRV_PCM_RATE_8000_96000 48e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 49e9a3b57eSRicard Wanderlof SNDRV_PCM_FMTBIT_S20_3LE | \ 50e9a3b57eSRicard Wanderlof SNDRV_PCM_FMTBIT_S24_3LE | \ 51e9a3b57eSRicard Wanderlof SNDRV_PCM_FMTBIT_S32_LE) 52e9a3b57eSRicard Wanderlof 53e9a3b57eSRicard Wanderlof /* 54e9a3b57eSRicard Wanderlof * PLL modes, to be used for clk_id for set_sysclk callback. 55e9a3b57eSRicard Wanderlof * 56e9a3b57eSRicard Wanderlof * The default behavior (AUTO) is to take the first matching entry in the clock 57e9a3b57eSRicard Wanderlof * table, which is intended to be the PLL based one if there is more than one. 58e9a3b57eSRicard Wanderlof * 59e9a3b57eSRicard Wanderlof * Setting the clock source using simple-card (clocks or 60e9a3b57eSRicard Wanderlof * system-clock-frequency property) sets clk_id = 0 = ADC3XXX_PLL_AUTO. 61e9a3b57eSRicard Wanderlof */ 62e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_AUTO 0 /* Use first available mode */ 63e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_ENABLE 1 /* Use PLL for clock generation */ 64e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_BYPASS 2 /* Don't use PLL for clock generation */ 65e9a3b57eSRicard Wanderlof 66e9a3b57eSRicard Wanderlof /* Register definitions. */ 67e9a3b57eSRicard Wanderlof 68e9a3b57eSRicard Wanderlof #define ADC3XXX_PAGE_SIZE 128 69e9a3b57eSRicard Wanderlof #define ADC3XXX_REG(page, reg) ((page * ADC3XXX_PAGE_SIZE) + reg) 70e9a3b57eSRicard Wanderlof 71e9a3b57eSRicard Wanderlof /* 72e9a3b57eSRicard Wanderlof * Page 0 registers. 73e9a3b57eSRicard Wanderlof */ 74e9a3b57eSRicard Wanderlof 75e9a3b57eSRicard Wanderlof #define ADC3XXX_PAGE_SELECT ADC3XXX_REG(0, 0) 76e9a3b57eSRicard Wanderlof #define ADC3XXX_RESET ADC3XXX_REG(0, 1) 77e9a3b57eSRicard Wanderlof 78e9a3b57eSRicard Wanderlof /* 2-3 Reserved */ 79e9a3b57eSRicard Wanderlof 80e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKGEN_MUX ADC3XXX_REG(0, 4) 81e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PROG_PR ADC3XXX_REG(0, 5) 82e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PROG_J ADC3XXX_REG(0, 6) 83e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PROG_D_MSB ADC3XXX_REG(0, 7) 84e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PROG_D_LSB ADC3XXX_REG(0, 8) 85e9a3b57eSRicard Wanderlof 86e9a3b57eSRicard Wanderlof /* 9-17 Reserved */ 87e9a3b57eSRicard Wanderlof 88e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_NADC ADC3XXX_REG(0, 18) 89e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_MADC ADC3XXX_REG(0, 19) 90e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_AOSR ADC3XXX_REG(0, 20) 91e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_IADC ADC3XXX_REG(0, 21) 92e9a3b57eSRicard Wanderlof 93e9a3b57eSRicard Wanderlof /* 23-24 Reserved */ 94e9a3b57eSRicard Wanderlof 95e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKOUT_MUX ADC3XXX_REG(0, 25) 96e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKOUT_M_DIV ADC3XXX_REG(0, 26) 97e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_1 ADC3XXX_REG(0, 27) 98e9a3b57eSRicard Wanderlof #define ADC3XXX_CH_OFFSET_1 ADC3XXX_REG(0, 28) 99e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_2 ADC3XXX_REG(0, 29) 100e9a3b57eSRicard Wanderlof #define ADC3XXX_BCLK_N_DIV ADC3XXX_REG(0, 30) 101e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_3 ADC3XXX_REG(0, 31) 102e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_4 ADC3XXX_REG(0, 32) 103e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_5 ADC3XXX_REG(0, 33) 104e9a3b57eSRicard Wanderlof #define ADC3XXX_I2S_SYNC ADC3XXX_REG(0, 34) 105e9a3b57eSRicard Wanderlof /* 35 Reserved */ 106e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_FLAG ADC3XXX_REG(0, 36) 107e9a3b57eSRicard Wanderlof #define ADC3XXX_CH_OFFSET_2 ADC3XXX_REG(0, 37) 108e9a3b57eSRicard Wanderlof #define ADC3XXX_I2S_TDM_CTRL ADC3XXX_REG(0, 38) 109e9a3b57eSRicard Wanderlof /* 39-41 Reserved */ 110e9a3b57eSRicard Wanderlof #define ADC3XXX_INTR_FLAG_1 ADC3XXX_REG(0, 42) 111e9a3b57eSRicard Wanderlof #define ADC3XXX_INTR_FLAG_2 ADC3XXX_REG(0, 43) 112e9a3b57eSRicard Wanderlof /* 44 Reserved */ 113e9a3b57eSRicard Wanderlof #define ADC3XXX_INTR_FLAG_ADC1 ADC3XXX_REG(0, 45) 114e9a3b57eSRicard Wanderlof /* 46 Reserved */ 115e9a3b57eSRicard Wanderlof #define ADC3XXX_INTR_FLAG_ADC2 ADC3XXX_REG(0, 47) 116e9a3b57eSRicard Wanderlof #define ADC3XXX_INT1_CTRL ADC3XXX_REG(0, 48) 117e9a3b57eSRicard Wanderlof #define ADC3XXX_INT2_CTRL ADC3XXX_REG(0, 49) 118e9a3b57eSRicard Wanderlof /* 50 Reserved */ 119e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO2_CTRL ADC3XXX_REG(0, 51) 120e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO1_CTRL ADC3XXX_REG(0, 52) 121e9a3b57eSRicard Wanderlof #define ADC3XXX_DOUT_CTRL ADC3XXX_REG(0, 53) 122e9a3b57eSRicard Wanderlof /* 54-56 Reserved */ 123e9a3b57eSRicard Wanderlof #define ADC3XXX_SYNC_CTRL_1 ADC3XXX_REG(0, 57) 124e9a3b57eSRicard Wanderlof #define ADC3XXX_SYNC_CTRL_2 ADC3XXX_REG(0, 58) 125e9a3b57eSRicard Wanderlof #define ADC3XXX_CIC_GAIN_CTRL ADC3XXX_REG(0, 59) 126e9a3b57eSRicard Wanderlof /* 60 Reserved */ 127e9a3b57eSRicard Wanderlof #define ADC3XXX_PRB_SELECT ADC3XXX_REG(0, 61) 128e9a3b57eSRicard Wanderlof #define ADC3XXX_INST_MODE_CTRL ADC3XXX_REG(0, 62) 129e9a3b57eSRicard Wanderlof /* 63-79 Reserved */ 130e9a3b57eSRicard Wanderlof #define ADC3XXX_MIC_POLARITY_CTRL ADC3XXX_REG(0, 80) 131e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_DIGITAL ADC3XXX_REG(0, 81) 132e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_FGA ADC3XXX_REG(0, 82) 133e9a3b57eSRicard Wanderlof #define ADC3XXX_LADC_VOL ADC3XXX_REG(0, 83) 134e9a3b57eSRicard Wanderlof #define ADC3XXX_RADC_VOL ADC3XXX_REG(0, 84) 135e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_PHASE_COMP ADC3XXX_REG(0, 85) 136e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_1 ADC3XXX_REG(0, 86) 137e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_2 ADC3XXX_REG(0, 87) 138e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_3 ADC3XXX_REG(0, 88) 139e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_4 ADC3XXX_REG(0, 89) 140e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_5 ADC3XXX_REG(0, 90) 141e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_6 ADC3XXX_REG(0, 91) 142e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_7 ADC3XXX_REG(0, 92) 143e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_AGC_GAIN ADC3XXX_REG(0, 93) 144e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_1 ADC3XXX_REG(0, 94) 145e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_2 ADC3XXX_REG(0, 95) 146e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_3 ADC3XXX_REG(0, 96) 147e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_4 ADC3XXX_REG(0, 97) 148e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_5 ADC3XXX_REG(0, 98) 149e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_6 ADC3XXX_REG(0, 99) 150e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_7 ADC3XXX_REG(0, 100) 151e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_AGC_GAIN ADC3XXX_REG(0, 101) 152e9a3b57eSRicard Wanderlof /* 102-127 Reserved */ 153e9a3b57eSRicard Wanderlof 154e9a3b57eSRicard Wanderlof /* 155e9a3b57eSRicard Wanderlof * Page 1 registers. 156e9a3b57eSRicard Wanderlof */ 157e9a3b57eSRicard Wanderlof 158e9a3b57eSRicard Wanderlof /* 1-25 Reserved */ 159e9a3b57eSRicard Wanderlof #define ADC3XXX_DITHER_CTRL ADC3XXX_REG(1, 26) 160e9a3b57eSRicard Wanderlof /* 27-50 Reserved */ 161e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS_CTRL ADC3XXX_REG(1, 51) 162e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_PGA_SEL_1 ADC3XXX_REG(1, 52) 163e9a3b57eSRicard Wanderlof /* 53 Reserved */ 164e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_PGA_SEL_2 ADC3XXX_REG(1, 54) 165e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_PGA_SEL_1 ADC3XXX_REG(1, 55) 166e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_PGA_SEL_2 ADC3XXX_REG(1, 57) 167e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_APGA_CTRL ADC3XXX_REG(1, 59) 168e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_APGA_CTRL ADC3XXX_REG(1, 60) 169e9a3b57eSRicard Wanderlof #define ADC3XXX_LOW_CURRENT_MODES ADC3XXX_REG(1, 61) 170e9a3b57eSRicard Wanderlof #define ADC3XXX_ANALOG_PGA_FLAGS ADC3XXX_REG(1, 62) 171e9a3b57eSRicard Wanderlof /* 63-127 Reserved */ 172e9a3b57eSRicard Wanderlof 173e9a3b57eSRicard Wanderlof /* 1749193bc05SRicard Wanderlof * Page 4 registers. First page of coefficient memory for the miniDSP. 1759193bc05SRicard Wanderlof */ 1769193bc05SRicard Wanderlof #define ADC3XXX_LEFT_ADC_IIR_COEFF_N0_MSB ADC3XXX_REG(4, 8) 1779193bc05SRicard Wanderlof #define ADC3XXX_LEFT_ADC_IIR_COEFF_N0_LSB ADC3XXX_REG(4, 9) 1789193bc05SRicard Wanderlof #define ADC3XXX_LEFT_ADC_IIR_COEFF_N1_MSB ADC3XXX_REG(4, 10) 1799193bc05SRicard Wanderlof #define ADC3XXX_LEFT_ADC_IIR_COEFF_N1_LSB ADC3XXX_REG(4, 11) 1809193bc05SRicard Wanderlof #define ADC3XXX_LEFT_ADC_IIR_COEFF_D1_MSB ADC3XXX_REG(4, 12) 1819193bc05SRicard Wanderlof #define ADC3XXX_LEFT_ADC_IIR_COEFF_D1_LSB ADC3XXX_REG(4, 13) 1829193bc05SRicard Wanderlof 1839193bc05SRicard Wanderlof #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_MSB ADC3XXX_REG(4, 72) 1849193bc05SRicard Wanderlof #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_LSB ADC3XXX_REG(4, 73) 1859193bc05SRicard Wanderlof #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N1_MSB ADC3XXX_REG(4, 74) 1869193bc05SRicard Wanderlof #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N1_LSB ADC3XXX_REG(4, 75) 1879193bc05SRicard Wanderlof #define ADC3XXX_RIGHT_ADC_IIR_COEFF_D1_MSB ADC3XXX_REG(4, 76) 1889193bc05SRicard Wanderlof #define ADC3XXX_RIGHT_ADC_IIR_COEFF_D1_LSB ADC3XXX_REG(4, 77) 1899193bc05SRicard Wanderlof 1909193bc05SRicard Wanderlof /* 191e9a3b57eSRicard Wanderlof * Register bits. 192e9a3b57eSRicard Wanderlof */ 193e9a3b57eSRicard Wanderlof 194e9a3b57eSRicard Wanderlof /* PLL Enable bits */ 195e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_PLL_SHIFT 7 196e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_PLL (1 << ADC3XXX_ENABLE_PLL_SHIFT) 197e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_NADC_SHIFT 7 198e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_NADC (1 << ADC3XXX_ENABLE_NADC_SHIFT) 199e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_MADC_SHIFT 7 200e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_MADC (1 << ADC3XXX_ENABLE_MADC_SHIFT) 201e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_BCLK_SHIFT 7 202e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_BCLK (1 << ADC3XXX_ENABLE_BCLK_SHIFT) 203e9a3b57eSRicard Wanderlof 204e9a3b57eSRicard Wanderlof /* Power bits */ 205e9a3b57eSRicard Wanderlof #define ADC3XXX_LADC_PWR_ON 0x80 206e9a3b57eSRicard Wanderlof #define ADC3XXX_RADC_PWR_ON 0x40 207e9a3b57eSRicard Wanderlof 208e9a3b57eSRicard Wanderlof #define ADC3XXX_SOFT_RESET 0x01 209e9a3b57eSRicard Wanderlof #define ADC3XXX_BCLK_MASTER 0x08 210e9a3b57eSRicard Wanderlof #define ADC3XXX_WCLK_MASTER 0x04 211e9a3b57eSRicard Wanderlof 212e9a3b57eSRicard Wanderlof /* Interface register masks */ 213e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_MASK 0xc0 214e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_SHIFT 6 215e9a3b57eSRicard Wanderlof #define ADC3XXX_WLENGTH_MASK 0x30 216e9a3b57eSRicard Wanderlof #define ADC3XXX_WLENGTH_SHIFT 4 217e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKDIR_MASK 0x0c 218e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKDIR_SHIFT 2 219e9a3b57eSRicard Wanderlof 220e9a3b57eSRicard Wanderlof /* Interface register bit patterns */ 221e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_I2S (0 << ADC3XXX_FORMAT_SHIFT) 222e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_DSP (1 << ADC3XXX_FORMAT_SHIFT) 223e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_RJF (2 << ADC3XXX_FORMAT_SHIFT) 224e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_LJF (3 << ADC3XXX_FORMAT_SHIFT) 225e9a3b57eSRicard Wanderlof 226e9a3b57eSRicard Wanderlof #define ADC3XXX_IFACE_16BITS (0 << ADC3XXX_WLENGTH_SHIFT) 227e9a3b57eSRicard Wanderlof #define ADC3XXX_IFACE_20BITS (1 << ADC3XXX_WLENGTH_SHIFT) 228e9a3b57eSRicard Wanderlof #define ADC3XXX_IFACE_24BITS (2 << ADC3XXX_WLENGTH_SHIFT) 229e9a3b57eSRicard Wanderlof #define ADC3XXX_IFACE_32BITS (3 << ADC3XXX_WLENGTH_SHIFT) 230e9a3b57eSRicard Wanderlof 231e9a3b57eSRicard Wanderlof /* PLL P/R bit offsets */ 232e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLP_SHIFT 4 233e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLR_SHIFT 0 234e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PR_MASK 0x7f 235e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLJ_MASK 0x3f 236e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLD_MSB_MASK 0x3f 237e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLD_LSB_MASK 0xff 238e9a3b57eSRicard Wanderlof #define ADC3XXX_NADC_MASK 0x7f 239e9a3b57eSRicard Wanderlof #define ADC3XXX_MADC_MASK 0x7f 240e9a3b57eSRicard Wanderlof #define ADC3XXX_AOSR_MASK 0xff 241e9a3b57eSRicard Wanderlof #define ADC3XXX_IADC_MASK 0xff 242e9a3b57eSRicard Wanderlof #define ADC3XXX_BDIV_MASK 0x7f 243e9a3b57eSRicard Wanderlof 244e9a3b57eSRicard Wanderlof /* PLL_CLKIN bits */ 245e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_CLKIN_SHIFT 2 246e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_CLKIN_MCLK 0x0 247e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_CLKIN_BCLK 0x1 248e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_CLKIN_ZERO 0x3 249e9a3b57eSRicard Wanderlof 250e9a3b57eSRicard Wanderlof /* CODEC_CLKIN bits */ 251e9a3b57eSRicard Wanderlof #define ADC3XXX_CODEC_CLKIN_SHIFT 0 252e9a3b57eSRicard Wanderlof #define ADC3XXX_CODEC_CLKIN_MCLK 0x0 253e9a3b57eSRicard Wanderlof #define ADC3XXX_CODEC_CLKIN_BCLK 0x1 254e9a3b57eSRicard Wanderlof #define ADC3XXX_CODEC_CLKIN_PLL_CLK 0x3 255e9a3b57eSRicard Wanderlof 256e9a3b57eSRicard Wanderlof #define ADC3XXX_USE_PLL ((ADC3XXX_PLL_CLKIN_MCLK << ADC3XXX_PLL_CLKIN_SHIFT) | \ 257e9a3b57eSRicard Wanderlof (ADC3XXX_CODEC_CLKIN_PLL_CLK << ADC3XXX_CODEC_CLKIN_SHIFT)) 258e9a3b57eSRicard Wanderlof #define ADC3XXX_NO_PLL ((ADC3XXX_PLL_CLKIN_ZERO << ADC3XXX_PLL_CLKIN_SHIFT) | \ 259e9a3b57eSRicard Wanderlof (ADC3XXX_CODEC_CLKIN_MCLK << ADC3XXX_CODEC_CLKIN_SHIFT)) 260e9a3b57eSRicard Wanderlof 261e9a3b57eSRicard Wanderlof /* Analog PGA control bits */ 262e9a3b57eSRicard Wanderlof #define ADC3XXX_LPGA_MUTE 0x80 263e9a3b57eSRicard Wanderlof #define ADC3XXX_RPGA_MUTE 0x80 264e9a3b57eSRicard Wanderlof 265e9a3b57eSRicard Wanderlof #define ADC3XXX_LPGA_GAIN_MASK 0x7f 266e9a3b57eSRicard Wanderlof #define ADC3XXX_RPGA_GAIN_MASK 0x7f 267e9a3b57eSRicard Wanderlof 268e9a3b57eSRicard Wanderlof /* ADC current modes */ 269e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_LOW_CURR_MODE 0x01 270e9a3b57eSRicard Wanderlof 271e9a3b57eSRicard Wanderlof /* Left ADC Input selection bits */ 272e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL1_SHIFT 0 273e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL2_SHIFT 2 274e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL3_SHIFT 4 275e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL4_SHIFT 6 276e9a3b57eSRicard Wanderlof 277e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL1X_SHIFT 0 278e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL2X_SHIFT 2 279e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL3X_SHIFT 4 280e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_COMMON_MODE 0x40 281e9a3b57eSRicard Wanderlof #define ADC3XXX_BYPASS_LPGA 0x80 282e9a3b57eSRicard Wanderlof 283e9a3b57eSRicard Wanderlof /* Right ADC Input selection bits */ 284e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL1_SHIFT 0 285e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL2_SHIFT 2 286e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL3_SHIFT 4 287e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL4_SHIFT 6 288e9a3b57eSRicard Wanderlof 289e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL1X_SHIFT 0 290e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL2X_SHIFT 2 291e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL3X_SHIFT 4 292e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_COMMON_MODE 0x40 293e9a3b57eSRicard Wanderlof #define ADC3XXX_BYPASS_RPGA 0x80 294e9a3b57eSRicard Wanderlof 295e9a3b57eSRicard Wanderlof /* MICBIAS control bits */ 296e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS_MASK 0x2 297e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS1_SHIFT 5 298e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS2_SHIFT 3 299e9a3b57eSRicard Wanderlof 300e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_MAX_VOLUME 64 301e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_POS_VOL 24 302e9a3b57eSRicard Wanderlof 303e9a3b57eSRicard Wanderlof /* GPIO control bits (GPIO1_CTRL and GPIO2_CTRL) */ 304e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_CFG_MASK 0x3c 305e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_CFG_SHIFT 2 306e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK 0x01 307e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT 0 308e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_INPUT_VALUE_MASK 0x02 309e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_INPUT_VALUE_SHIFT 1 310e9a3b57eSRicard Wanderlof 311e9a3b57eSRicard Wanderlof enum adc3xxx_type { 312e9a3b57eSRicard Wanderlof ADC3001 = 0, 313e9a3b57eSRicard Wanderlof ADC3101 314e9a3b57eSRicard Wanderlof }; 315e9a3b57eSRicard Wanderlof 316e9a3b57eSRicard Wanderlof struct adc3xxx { 317e9a3b57eSRicard Wanderlof struct device *dev; 318e9a3b57eSRicard Wanderlof enum adc3xxx_type type; 319e9a3b57eSRicard Wanderlof struct clk *mclk; 320e9a3b57eSRicard Wanderlof struct regmap *regmap; 321e9a3b57eSRicard Wanderlof struct gpio_desc *rst_pin; 322e9a3b57eSRicard Wanderlof unsigned int pll_mode; 323e9a3b57eSRicard Wanderlof unsigned int sysclk; 324e9a3b57eSRicard Wanderlof unsigned int gpio_cfg[ADC3XXX_GPIOS_MAX]; /* value+1 (0 => not set) */ 325e9a3b57eSRicard Wanderlof unsigned int micbias_vg[ADC3XXX_MICBIAS_PINS]; 326e9a3b57eSRicard Wanderlof int master; 327e9a3b57eSRicard Wanderlof u8 page_no; 328e9a3b57eSRicard Wanderlof int use_pll; 329e9a3b57eSRicard Wanderlof struct gpio_chip gpio_chip; 330e9a3b57eSRicard Wanderlof }; 331e9a3b57eSRicard Wanderlof 332e9a3b57eSRicard Wanderlof static const unsigned int adc3xxx_gpio_ctrl_reg[ADC3XXX_GPIOS_MAX] = { 333e9a3b57eSRicard Wanderlof ADC3XXX_GPIO1_CTRL, 334e9a3b57eSRicard Wanderlof ADC3XXX_GPIO2_CTRL 335e9a3b57eSRicard Wanderlof }; 336e9a3b57eSRicard Wanderlof 337e9a3b57eSRicard Wanderlof static const unsigned int adc3xxx_micbias_shift[ADC3XXX_MICBIAS_PINS] = { 338e9a3b57eSRicard Wanderlof ADC3XXX_MICBIAS1_SHIFT, 339e9a3b57eSRicard Wanderlof ADC3XXX_MICBIAS2_SHIFT 340e9a3b57eSRicard Wanderlof }; 341e9a3b57eSRicard Wanderlof 342e9a3b57eSRicard Wanderlof static const struct reg_default adc3xxx_defaults[] = { 343e9a3b57eSRicard Wanderlof /* Page 0 */ 344e9a3b57eSRicard Wanderlof { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x00 }, 345e9a3b57eSRicard Wanderlof { 4, 0x00 }, { 5, 0x11 }, { 6, 0x04 }, { 7, 0x00 }, 346e9a3b57eSRicard Wanderlof { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x00 }, 347e9a3b57eSRicard Wanderlof { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x00 }, 348e9a3b57eSRicard Wanderlof { 16, 0x00 }, { 17, 0x00 }, { 18, 0x01 }, { 19, 0x01 }, 349e9a3b57eSRicard Wanderlof { 20, 0x80 }, { 21, 0x80 }, { 22, 0x04 }, { 23, 0x00 }, 350e9a3b57eSRicard Wanderlof { 24, 0x00 }, { 25, 0x00 }, { 26, 0x01 }, { 27, 0x00 }, 351e9a3b57eSRicard Wanderlof { 28, 0x00 }, { 29, 0x02 }, { 30, 0x01 }, { 31, 0x00 }, 352e9a3b57eSRicard Wanderlof { 32, 0x00 }, { 33, 0x10 }, { 34, 0x00 }, { 35, 0x00 }, 353e9a3b57eSRicard Wanderlof { 36, 0x00 }, { 37, 0x00 }, { 38, 0x02 }, { 39, 0x00 }, 354e9a3b57eSRicard Wanderlof { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x00 }, 355e9a3b57eSRicard Wanderlof { 44, 0x00 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 }, 356e9a3b57eSRicard Wanderlof { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x00 }, 357e9a3b57eSRicard Wanderlof { 52, 0x00 }, { 53, 0x12 }, { 54, 0x00 }, { 55, 0x00 }, 358e9a3b57eSRicard Wanderlof { 56, 0x00 }, { 57, 0x00 }, { 58, 0x00 }, { 59, 0x44 }, 359e9a3b57eSRicard Wanderlof { 60, 0x00 }, { 61, 0x01 }, { 62, 0x00 }, { 63, 0x00 }, 360e9a3b57eSRicard Wanderlof { 64, 0x00 }, { 65, 0x00 }, { 66, 0x00 }, { 67, 0x00 }, 361e9a3b57eSRicard Wanderlof { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 }, 362e9a3b57eSRicard Wanderlof { 72, 0x00 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 }, 363e9a3b57eSRicard Wanderlof { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 }, 364e9a3b57eSRicard Wanderlof { 80, 0x00 }, { 81, 0x00 }, { 82, 0x88 }, { 83, 0x00 }, 365e9a3b57eSRicard Wanderlof { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 }, 366e9a3b57eSRicard Wanderlof { 88, 0x7f }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 }, 367e9a3b57eSRicard Wanderlof { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 }, 368e9a3b57eSRicard Wanderlof { 96, 0x7f }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 }, 369e9a3b57eSRicard Wanderlof { 100, 0x00 }, { 101, 0x00 }, { 102, 0x00 }, { 103, 0x00 }, 370e9a3b57eSRicard Wanderlof { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 }, 371e9a3b57eSRicard Wanderlof { 108, 0x00 }, { 109, 0x00 }, { 110, 0x00 }, { 111, 0x00 }, 372e9a3b57eSRicard Wanderlof { 112, 0x00 }, { 113, 0x00 }, { 114, 0x00 }, { 115, 0x00 }, 373e9a3b57eSRicard Wanderlof { 116, 0x00 }, { 117, 0x00 }, { 118, 0x00 }, { 119, 0x00 }, 374e9a3b57eSRicard Wanderlof { 120, 0x00 }, { 121, 0x00 }, { 122, 0x00 }, { 123, 0x00 }, 375e9a3b57eSRicard Wanderlof { 124, 0x00 }, { 125, 0x00 }, { 126, 0x00 }, { 127, 0x00 }, 376e9a3b57eSRicard Wanderlof 377e9a3b57eSRicard Wanderlof /* Page 1 */ 378e9a3b57eSRicard Wanderlof { 128, 0x00 }, { 129, 0x00 }, { 130, 0x00 }, { 131, 0x00 }, 379e9a3b57eSRicard Wanderlof { 132, 0x00 }, { 133, 0x00 }, { 134, 0x00 }, { 135, 0x00 }, 380e9a3b57eSRicard Wanderlof { 136, 0x00 }, { 137, 0x00 }, { 138, 0x00 }, { 139, 0x00 }, 381e9a3b57eSRicard Wanderlof { 140, 0x00 }, { 141, 0x00 }, { 142, 0x00 }, { 143, 0x00 }, 382e9a3b57eSRicard Wanderlof { 144, 0x00 }, { 145, 0x00 }, { 146, 0x00 }, { 147, 0x00 }, 383e9a3b57eSRicard Wanderlof { 148, 0x00 }, { 149, 0x00 }, { 150, 0x00 }, { 151, 0x00 }, 384e9a3b57eSRicard Wanderlof { 152, 0x00 }, { 153, 0x00 }, { 154, 0x00 }, { 155, 0x00 }, 385e9a3b57eSRicard Wanderlof { 156, 0x00 }, { 157, 0x00 }, { 158, 0x00 }, { 159, 0x00 }, 386e9a3b57eSRicard Wanderlof { 160, 0x00 }, { 161, 0x00 }, { 162, 0x00 }, { 163, 0x00 }, 387e9a3b57eSRicard Wanderlof { 164, 0x00 }, { 165, 0x00 }, { 166, 0x00 }, { 167, 0x00 }, 388e9a3b57eSRicard Wanderlof { 168, 0x00 }, { 169, 0x00 }, { 170, 0x00 }, { 171, 0x00 }, 389e9a3b57eSRicard Wanderlof { 172, 0x00 }, { 173, 0x00 }, { 174, 0x00 }, { 175, 0x00 }, 390e9a3b57eSRicard Wanderlof { 176, 0x00 }, { 177, 0x00 }, { 178, 0x00 }, { 179, 0x00 }, 391e9a3b57eSRicard Wanderlof { 180, 0xff }, { 181, 0x00 }, { 182, 0x3f }, { 183, 0xff }, 392e9a3b57eSRicard Wanderlof { 184, 0x00 }, { 185, 0x3f }, { 186, 0x00 }, { 187, 0x80 }, 393e9a3b57eSRicard Wanderlof { 188, 0x80 }, { 189, 0x00 }, { 190, 0x00 }, { 191, 0x00 }, 3949193bc05SRicard Wanderlof 3959193bc05SRicard Wanderlof /* Page 4 */ 3969193bc05SRicard Wanderlof { 1024, 0x00 }, { 1026, 0x01 }, { 1027, 0x17 }, 3979193bc05SRicard Wanderlof { 1028, 0x01 }, { 1029, 0x17 }, { 1030, 0x7d }, { 1031, 0xd3 }, 3989193bc05SRicard Wanderlof { 1032, 0x7f }, { 1033, 0xff }, { 1034, 0x00 }, { 1035, 0x00 }, 3999193bc05SRicard Wanderlof { 1036, 0x00 }, { 1037, 0x00 }, { 1038, 0x7f }, { 1039, 0xff }, 4009193bc05SRicard Wanderlof { 1040, 0x00 }, { 1041, 0x00 }, { 1042, 0x00 }, { 1043, 0x00 }, 4019193bc05SRicard Wanderlof { 1044, 0x00 }, { 1045, 0x00 }, { 1046, 0x00 }, { 1047, 0x00 }, 4029193bc05SRicard Wanderlof { 1048, 0x7f }, { 1049, 0xff }, { 1050, 0x00 }, { 1051, 0x00 }, 4039193bc05SRicard Wanderlof { 1052, 0x00 }, { 1053, 0x00 }, { 1054, 0x00 }, { 1055, 0x00 }, 4049193bc05SRicard Wanderlof { 1056, 0x00 }, { 1057, 0x00 }, { 1058, 0x7f }, { 1059, 0xff }, 4059193bc05SRicard Wanderlof { 1060, 0x00 }, { 1061, 0x00 }, { 1062, 0x00 }, { 1063, 0x00 }, 4069193bc05SRicard Wanderlof { 1064, 0x00 }, { 1065, 0x00 }, { 1066, 0x00 }, { 1067, 0x00 }, 4079193bc05SRicard Wanderlof { 1068, 0x7f }, { 1069, 0xff }, { 1070, 0x00 }, { 1071, 0x00 }, 4089193bc05SRicard Wanderlof { 1072, 0x00 }, { 1073, 0x00 }, { 1074, 0x00 }, { 1075, 0x00 }, 4099193bc05SRicard Wanderlof { 1076, 0x00 }, { 1077, 0x00 }, { 1078, 0x7f }, { 1079, 0xff }, 4109193bc05SRicard Wanderlof { 1080, 0x00 }, { 1081, 0x00 }, { 1082, 0x00 }, { 1083, 0x00 }, 4119193bc05SRicard Wanderlof { 1084, 0x00 }, { 1085, 0x00 }, { 1086, 0x00 }, { 1087, 0x00 }, 4129193bc05SRicard Wanderlof { 1088, 0x00 }, { 1089, 0x00 }, { 1090, 0x00 }, { 1091, 0x00 }, 4139193bc05SRicard Wanderlof { 1092, 0x00 }, { 1093, 0x00 }, { 1094, 0x00 }, { 1095, 0x00 }, 4149193bc05SRicard Wanderlof { 1096, 0x00 }, { 1097, 0x00 }, { 1098, 0x00 }, { 1099, 0x00 }, 4159193bc05SRicard Wanderlof { 1100, 0x00 }, { 1101, 0x00 }, { 1102, 0x00 }, { 1103, 0x00 }, 4169193bc05SRicard Wanderlof { 1104, 0x00 }, { 1105, 0x00 }, { 1106, 0x00 }, { 1107, 0x00 }, 4179193bc05SRicard Wanderlof { 1108, 0x00 }, { 1109, 0x00 }, { 1110, 0x00 }, { 1111, 0x00 }, 4189193bc05SRicard Wanderlof { 1112, 0x00 }, { 1113, 0x00 }, { 1114, 0x00 }, { 1115, 0x00 }, 4199193bc05SRicard Wanderlof { 1116, 0x00 }, { 1117, 0x00 }, { 1118, 0x00 }, { 1119, 0x00 }, 4209193bc05SRicard Wanderlof { 1120, 0x00 }, { 1121, 0x00 }, { 1122, 0x00 }, { 1123, 0x00 }, 4219193bc05SRicard Wanderlof { 1124, 0x00 }, { 1125, 0x00 }, { 1126, 0x00 }, { 1127, 0x00 }, 4229193bc05SRicard Wanderlof { 1128, 0x00 }, { 1129, 0x00 }, { 1130, 0x00 }, { 1131, 0x00 }, 4239193bc05SRicard Wanderlof { 1132, 0x00 }, { 1133, 0x00 }, { 1134, 0x00 }, { 1135, 0x00 }, 4249193bc05SRicard Wanderlof { 1136, 0x00 }, { 1137, 0x00 }, { 1138, 0x00 }, { 1139, 0x00 }, 4259193bc05SRicard Wanderlof { 1140, 0x00 }, { 1141, 0x00 }, { 1142, 0x00 }, { 1143, 0x00 }, 4269193bc05SRicard Wanderlof { 1144, 0x00 }, { 1145, 0x00 }, { 1146, 0x00 }, { 1147, 0x00 }, 4279193bc05SRicard Wanderlof { 1148, 0x00 }, { 1149, 0x00 }, { 1150, 0x00 }, { 1151, 0x00 }, 428e9a3b57eSRicard Wanderlof }; 429e9a3b57eSRicard Wanderlof 430e9a3b57eSRicard Wanderlof static bool adc3xxx_volatile_reg(struct device *dev, unsigned int reg) 431e9a3b57eSRicard Wanderlof { 432e9a3b57eSRicard Wanderlof switch (reg) { 433e9a3b57eSRicard Wanderlof case ADC3XXX_RESET: 434e9a3b57eSRicard Wanderlof return true; 435e9a3b57eSRicard Wanderlof default: 436e9a3b57eSRicard Wanderlof return false; 437e9a3b57eSRicard Wanderlof } 438e9a3b57eSRicard Wanderlof } 439e9a3b57eSRicard Wanderlof 440e9a3b57eSRicard Wanderlof static const struct regmap_range_cfg adc3xxx_ranges[] = { 441e9a3b57eSRicard Wanderlof { 442e9a3b57eSRicard Wanderlof .range_min = 0, 4439193bc05SRicard Wanderlof .range_max = 5 * ADC3XXX_PAGE_SIZE, 444e9a3b57eSRicard Wanderlof .selector_reg = ADC3XXX_PAGE_SELECT, 445e9a3b57eSRicard Wanderlof .selector_mask = 0xff, 446e9a3b57eSRicard Wanderlof .selector_shift = 0, 447e9a3b57eSRicard Wanderlof .window_start = 0, 448e9a3b57eSRicard Wanderlof .window_len = ADC3XXX_PAGE_SIZE, 449e9a3b57eSRicard Wanderlof } 450e9a3b57eSRicard Wanderlof }; 451e9a3b57eSRicard Wanderlof 452e9a3b57eSRicard Wanderlof static const struct regmap_config adc3xxx_regmap = { 453e9a3b57eSRicard Wanderlof .reg_bits = 8, 454e9a3b57eSRicard Wanderlof .val_bits = 8, 455e9a3b57eSRicard Wanderlof 456e9a3b57eSRicard Wanderlof .reg_defaults = adc3xxx_defaults, 457e9a3b57eSRicard Wanderlof .num_reg_defaults = ARRAY_SIZE(adc3xxx_defaults), 458e9a3b57eSRicard Wanderlof 459e9a3b57eSRicard Wanderlof .volatile_reg = adc3xxx_volatile_reg, 460e9a3b57eSRicard Wanderlof 461e9a3b57eSRicard Wanderlof .cache_type = REGCACHE_RBTREE, 462e9a3b57eSRicard Wanderlof 463e9a3b57eSRicard Wanderlof .ranges = adc3xxx_ranges, 464e9a3b57eSRicard Wanderlof .num_ranges = ARRAY_SIZE(adc3xxx_ranges), 4659193bc05SRicard Wanderlof .max_register = 5 * ADC3XXX_PAGE_SIZE, 466e9a3b57eSRicard Wanderlof }; 467e9a3b57eSRicard Wanderlof 468e9a3b57eSRicard Wanderlof struct adc3xxx_rate_divs { 469e9a3b57eSRicard Wanderlof u32 mclk; 470e9a3b57eSRicard Wanderlof u32 rate; 471e9a3b57eSRicard Wanderlof u8 pll_p; 472e9a3b57eSRicard Wanderlof u8 pll_r; 473e9a3b57eSRicard Wanderlof u8 pll_j; 474e9a3b57eSRicard Wanderlof u16 pll_d; 475e9a3b57eSRicard Wanderlof u8 nadc; 476e9a3b57eSRicard Wanderlof u8 madc; 477e9a3b57eSRicard Wanderlof u8 aosr; 478e9a3b57eSRicard Wanderlof }; 479e9a3b57eSRicard Wanderlof 480e9a3b57eSRicard Wanderlof /* 481e9a3b57eSRicard Wanderlof * PLL and Clock settings. 482e9a3b57eSRicard Wanderlof * If p member is 0, PLL is not used. 483e9a3b57eSRicard Wanderlof * The order of the entries in this table have the PLL entries before 484e9a3b57eSRicard Wanderlof * the non-PLL entries, so that the PLL modes are preferred unless 485e9a3b57eSRicard Wanderlof * the PLL mode setting says otherwise. 486e9a3b57eSRicard Wanderlof */ 487e9a3b57eSRicard Wanderlof static const struct adc3xxx_rate_divs adc3xxx_divs[] = { 488e9a3b57eSRicard Wanderlof /* mclk, rate, p, r, j, d, nadc, madc, aosr */ 489e9a3b57eSRicard Wanderlof /* 8k rate */ 490e9a3b57eSRicard Wanderlof { 12000000, 8000, 1, 1, 7, 1680, 42, 2, 128 }, 491e9a3b57eSRicard Wanderlof { 12288000, 8000, 1, 1, 7, 0000, 42, 2, 128 }, 492e9a3b57eSRicard Wanderlof /* 11.025k rate */ 493e9a3b57eSRicard Wanderlof { 12000000, 11025, 1, 1, 6, 8208, 29, 2, 128 }, 494e9a3b57eSRicard Wanderlof /* 16k rate */ 495e9a3b57eSRicard Wanderlof { 12000000, 16000, 1, 1, 7, 1680, 21, 2, 128 }, 496e9a3b57eSRicard Wanderlof { 12288000, 16000, 1, 1, 7, 0000, 21, 2, 128 }, 497e9a3b57eSRicard Wanderlof /* 22.05k rate */ 498e9a3b57eSRicard Wanderlof { 12000000, 22050, 1, 1, 7, 560, 15, 2, 128 }, 499e9a3b57eSRicard Wanderlof /* 32k rate */ 500e9a3b57eSRicard Wanderlof { 12000000, 32000, 1, 1, 8, 1920, 12, 2, 128 }, 501e9a3b57eSRicard Wanderlof { 12288000, 32000, 1, 1, 8, 0000, 12, 2, 128 }, 502e9a3b57eSRicard Wanderlof /* 44.1k rate */ 503e9a3b57eSRicard Wanderlof { 12000000, 44100, 1, 1, 7, 5264, 8, 2, 128 }, 504e9a3b57eSRicard Wanderlof /* 48k rate */ 505e9a3b57eSRicard Wanderlof { 12000000, 48000, 1, 1, 7, 1680, 7, 2, 128 }, 506e9a3b57eSRicard Wanderlof { 12288000, 48000, 1, 1, 7, 0000, 7, 2, 128 }, 507e9a3b57eSRicard Wanderlof { 24576000, 48000, 1, 1, 3, 5000, 7, 2, 128 }, /* With PLL */ 508e9a3b57eSRicard Wanderlof { 24576000, 48000, 0, 0, 0, 0000, 2, 2, 128 }, /* Without PLL */ 509e9a3b57eSRicard Wanderlof /* 88.2k rate */ 510e9a3b57eSRicard Wanderlof { 12000000, 88200, 1, 1, 7, 5264, 4, 4, 64 }, 511e9a3b57eSRicard Wanderlof /* 96k rate */ 512e9a3b57eSRicard Wanderlof { 12000000, 96000, 1, 1, 8, 1920, 4, 4, 64 }, 513e9a3b57eSRicard Wanderlof }; 514e9a3b57eSRicard Wanderlof 515e9a3b57eSRicard Wanderlof static int adc3xxx_get_divs(struct device *dev, int mclk, int rate, int pll_mode) 516e9a3b57eSRicard Wanderlof { 517e9a3b57eSRicard Wanderlof int i; 518e9a3b57eSRicard Wanderlof 519e9a3b57eSRicard Wanderlof dev_dbg(dev, "mclk = %d, rate = %d, clock mode %u\n", 520e9a3b57eSRicard Wanderlof mclk, rate, pll_mode); 521e9a3b57eSRicard Wanderlof for (i = 0; i < ARRAY_SIZE(adc3xxx_divs); i++) { 522e9a3b57eSRicard Wanderlof const struct adc3xxx_rate_divs *mode = &adc3xxx_divs[i]; 523e9a3b57eSRicard Wanderlof 524e9a3b57eSRicard Wanderlof /* Skip this entry if it doesn't fulfill the intended clock 525e9a3b57eSRicard Wanderlof * mode requirement. We consider anything besides the two 526e9a3b57eSRicard Wanderlof * modes below to be the same as ADC3XXX_PLL_AUTO. 527e9a3b57eSRicard Wanderlof */ 528e9a3b57eSRicard Wanderlof if ((pll_mode == ADC3XXX_PLL_BYPASS && mode->pll_p) || 529e9a3b57eSRicard Wanderlof (pll_mode == ADC3XXX_PLL_ENABLE && !mode->pll_p)) 530e9a3b57eSRicard Wanderlof continue; 531e9a3b57eSRicard Wanderlof 532e9a3b57eSRicard Wanderlof if (mode->rate == rate && mode->mclk == mclk) 533e9a3b57eSRicard Wanderlof return i; 534e9a3b57eSRicard Wanderlof } 535e9a3b57eSRicard Wanderlof 536e9a3b57eSRicard Wanderlof dev_info(dev, "Master clock rate %d and sample rate %d is not supported\n", 537e9a3b57eSRicard Wanderlof mclk, rate); 538e9a3b57eSRicard Wanderlof return -EINVAL; 539e9a3b57eSRicard Wanderlof } 540e9a3b57eSRicard Wanderlof 541e9a3b57eSRicard Wanderlof static int adc3xxx_pll_delay(struct snd_soc_dapm_widget *w, 542e9a3b57eSRicard Wanderlof struct snd_kcontrol *kcontrol, int event) 543e9a3b57eSRicard Wanderlof { 544e9a3b57eSRicard Wanderlof /* 10msec delay needed after PLL power-up to allow 545e9a3b57eSRicard Wanderlof * PLL and dividers to stabilize (datasheet p13). 546e9a3b57eSRicard Wanderlof */ 547e9a3b57eSRicard Wanderlof usleep_range(10000, 20000); 548e9a3b57eSRicard Wanderlof 549e9a3b57eSRicard Wanderlof return 0; 550e9a3b57eSRicard Wanderlof } 551e9a3b57eSRicard Wanderlof 5529193bc05SRicard Wanderlof static int adc3xxx_coefficient_info(struct snd_kcontrol *kcontrol, 5539193bc05SRicard Wanderlof struct snd_ctl_elem_info *uinfo) 5549193bc05SRicard Wanderlof { 5559193bc05SRicard Wanderlof int numcoeff = kcontrol->private_value >> 16; 5569193bc05SRicard Wanderlof 5579193bc05SRicard Wanderlof uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5589193bc05SRicard Wanderlof uinfo->count = numcoeff; 5599193bc05SRicard Wanderlof uinfo->value.integer.min = 0; 5609193bc05SRicard Wanderlof uinfo->value.integer.max = 0xffff; /* all coefficients are 16 bit */ 5619193bc05SRicard Wanderlof return 0; 5629193bc05SRicard Wanderlof } 5639193bc05SRicard Wanderlof 5649193bc05SRicard Wanderlof static int adc3xxx_coefficient_get(struct snd_kcontrol *kcontrol, 5659193bc05SRicard Wanderlof struct snd_ctl_elem_value *ucontrol) 5669193bc05SRicard Wanderlof { 5679193bc05SRicard Wanderlof struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 5689193bc05SRicard Wanderlof int numcoeff = kcontrol->private_value >> 16; 5699193bc05SRicard Wanderlof int reg = kcontrol->private_value & 0xffff; 5709193bc05SRicard Wanderlof int index = 0; 5719193bc05SRicard Wanderlof 5729193bc05SRicard Wanderlof for (index = 0; index < numcoeff; index++) { 5739193bc05SRicard Wanderlof unsigned int value_msb, value_lsb, value; 5749193bc05SRicard Wanderlof 5759193bc05SRicard Wanderlof value_msb = snd_soc_component_read(component, reg++); 5769193bc05SRicard Wanderlof if ((int)value_msb < 0) 5779193bc05SRicard Wanderlof return (int)value_msb; 5789193bc05SRicard Wanderlof 5799193bc05SRicard Wanderlof value_lsb = snd_soc_component_read(component, reg++); 5809193bc05SRicard Wanderlof if ((int)value_lsb < 0) 5819193bc05SRicard Wanderlof return (int)value_lsb; 5829193bc05SRicard Wanderlof 5839193bc05SRicard Wanderlof value = (value_msb << 8) | value_lsb; 5849193bc05SRicard Wanderlof ucontrol->value.integer.value[index] = value; 5859193bc05SRicard Wanderlof } 5869193bc05SRicard Wanderlof 5879193bc05SRicard Wanderlof return 0; 5889193bc05SRicard Wanderlof } 5899193bc05SRicard Wanderlof 5909193bc05SRicard Wanderlof static int adc3xxx_coefficient_put(struct snd_kcontrol *kcontrol, 5919193bc05SRicard Wanderlof struct snd_ctl_elem_value *ucontrol) 5929193bc05SRicard Wanderlof { 5939193bc05SRicard Wanderlof struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 5949193bc05SRicard Wanderlof int numcoeff = kcontrol->private_value >> 16; 5959193bc05SRicard Wanderlof int reg = kcontrol->private_value & 0xffff; 5969193bc05SRicard Wanderlof int index = 0; 5979193bc05SRicard Wanderlof int ret; 5989193bc05SRicard Wanderlof 5999193bc05SRicard Wanderlof for (index = 0; index < numcoeff; index++) { 6009193bc05SRicard Wanderlof unsigned int value = ucontrol->value.integer.value[index]; 6019193bc05SRicard Wanderlof unsigned int value_msb = (value >> 8) & 0xff; 6029193bc05SRicard Wanderlof unsigned int value_lsb = value & 0xff; 6039193bc05SRicard Wanderlof 6049193bc05SRicard Wanderlof ret = snd_soc_component_write(component, reg++, value_msb); 6059193bc05SRicard Wanderlof if (ret) 6069193bc05SRicard Wanderlof return ret; 6079193bc05SRicard Wanderlof 6089193bc05SRicard Wanderlof ret = snd_soc_component_write(component, reg++, value_lsb); 6099193bc05SRicard Wanderlof if (ret) 6109193bc05SRicard Wanderlof return ret; 6119193bc05SRicard Wanderlof } 6129193bc05SRicard Wanderlof 6139193bc05SRicard Wanderlof return 0; 6149193bc05SRicard Wanderlof } 6159193bc05SRicard Wanderlof 6169193bc05SRicard Wanderlof /* All on-chip filters have coefficients which are expressed in terms of 6179193bc05SRicard Wanderlof * 16 bit values, so represent them as strings of 16-bit integers. 6189193bc05SRicard Wanderlof */ 6199193bc05SRicard Wanderlof #define TI_COEFFICIENTS(xname, reg, numcoeffs) { \ 6209193bc05SRicard Wanderlof .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 6219193bc05SRicard Wanderlof .name = xname, \ 6229193bc05SRicard Wanderlof .info = adc3xxx_coefficient_info, \ 6239193bc05SRicard Wanderlof .get = adc3xxx_coefficient_get,\ 6249193bc05SRicard Wanderlof .put = adc3xxx_coefficient_put, \ 6259193bc05SRicard Wanderlof .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 6269193bc05SRicard Wanderlof .private_value = reg | (numcoeffs << 16) \ 6279193bc05SRicard Wanderlof } 6289193bc05SRicard Wanderlof 629e9a3b57eSRicard Wanderlof static const char * const adc_softstepping_text[] = { "1 step", "2 step", "off" }; 630e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(adc_softstepping_enum, ADC3XXX_ADC_DIGITAL, 0, 631e9a3b57eSRicard Wanderlof adc_softstepping_text); 632e9a3b57eSRicard Wanderlof 633e9a3b57eSRicard Wanderlof static const char * const multiplier_text[] = { "1", "2", "4", "8", "16", "32", "64", "128" }; 634e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(left_agc_attack_mult_enum, 635e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_CHN_AGC_4, 0, multiplier_text); 636e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(right_agc_attack_mult_enum, 637e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_4, 0, multiplier_text); 638e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(left_agc_decay_mult_enum, 639e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_CHN_AGC_5, 0, multiplier_text); 640e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(right_agc_decay_mult_enum, 641e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_5, 0, multiplier_text); 642e9a3b57eSRicard Wanderlof 643e9a3b57eSRicard Wanderlof static const char * const dither_dc_offset_text[] = { 644e9a3b57eSRicard Wanderlof "0mV", "15mV", "30mV", "45mV", "60mV", "75mV", "90mV", "105mV", 645e9a3b57eSRicard Wanderlof "-15mV", "-30mV", "-45mV", "-60mV", "-75mV", "-90mV", "-105mV" 646e9a3b57eSRicard Wanderlof }; 647e9a3b57eSRicard Wanderlof static const unsigned int dither_dc_offset_values[] = { 648e9a3b57eSRicard Wanderlof 0, 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15 649e9a3b57eSRicard Wanderlof }; 650e9a3b57eSRicard Wanderlof static SOC_VALUE_ENUM_DOUBLE_DECL(dither_dc_offset_enum, 651e9a3b57eSRicard Wanderlof ADC3XXX_DITHER_CTRL, 652e9a3b57eSRicard Wanderlof 4, 0, 0xf, dither_dc_offset_text, 653e9a3b57eSRicard Wanderlof dither_dc_offset_values); 654e9a3b57eSRicard Wanderlof 655e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 50, 0); 656e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0); 657e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0); 658e9a3b57eSRicard Wanderlof /* AGC target: 8 values: -5.5, -8, -10, -12, -14, -17, -20, -24 dB */ 659e9a3b57eSRicard Wanderlof /* It would be nice to declare these in the order above, but empirically 660e9a3b57eSRicard Wanderlof * TLV_DB_SCALE_ITEM doesn't take lightly to the increment (second) parameter 661e9a3b57eSRicard Wanderlof * being negative, despite there being examples to the contrary in other 662e9a3b57eSRicard Wanderlof * drivers. So declare these in the order from lowest to highest, and 663e9a3b57eSRicard Wanderlof * set the invert flag in the SOC_DOUBLE_R_TLV declaration instead. 664e9a3b57eSRicard Wanderlof */ 665e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_RANGE(agc_target_tlv, 666e9a3b57eSRicard Wanderlof 0, 0, TLV_DB_SCALE_ITEM(-2400, 0, 0), 667e9a3b57eSRicard Wanderlof 1, 3, TLV_DB_SCALE_ITEM(-2000, 300, 0), 668e9a3b57eSRicard Wanderlof 4, 6, TLV_DB_SCALE_ITEM(-1200, 200, 0), 669e9a3b57eSRicard Wanderlof 7, 7, TLV_DB_SCALE_ITEM(-550, 0, 0)); 670e9a3b57eSRicard Wanderlof /* Since the 'disabled' value (mute) is at the highest value in the dB 671e9a3b57eSRicard Wanderlof * range (i.e. just before -32 dB) rather than the lowest, we need to resort 672e9a3b57eSRicard Wanderlof * to using a TLV_DB_RANGE in order to get the mute value in the right place. 673e9a3b57eSRicard Wanderlof */ 674e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_RANGE(agc_thresh_tlv, 675e9a3b57eSRicard Wanderlof 0, 30, TLV_DB_SCALE_ITEM(-9000, 200, 0), 676e9a3b57eSRicard Wanderlof 31, 31, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */ 677e9a3b57eSRicard Wanderlof /* AGC hysteresis: 4 values: 1, 2, 4 dB, disabled (= mute) */ 678e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_RANGE(agc_hysteresis_tlv, 679e9a3b57eSRicard Wanderlof 0, 1, TLV_DB_SCALE_ITEM(100, 100, 0), 680e9a3b57eSRicard Wanderlof 2, 2, TLV_DB_SCALE_ITEM(400, 0, 0), 681e9a3b57eSRicard Wanderlof 3, 3, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */ 682e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(agc_max_tlv, 0, 50, 0); 683e9a3b57eSRicard Wanderlof /* Input attenuation: -6 dB or 0 dB */ 684e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(input_attenuation_tlv, -600, 600, 0); 685e9a3b57eSRicard Wanderlof 686e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new adc3xxx_snd_controls[] = { 687e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("PGA Capture Volume", ADC3XXX_LEFT_APGA_CTRL, 688e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_APGA_CTRL, 0, 80, 0, pga_tlv), 689e9a3b57eSRicard Wanderlof SOC_DOUBLE("PGA Capture Switch", ADC3XXX_ADC_FGA, 7, 3, 1, 1), 690e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Capture Switch", ADC3XXX_LEFT_CHN_AGC_1, 691e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_1, 7, 1, 0), 692e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("AGC Target Level Capture Volume", ADC3XXX_LEFT_CHN_AGC_1, 693e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_2, 4, 0x07, 1, agc_target_tlv), 694e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("AGC Noise Threshold Capture Volume", ADC3XXX_LEFT_CHN_AGC_2, 695e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_2, 1, 0x1f, 1, agc_thresh_tlv), 696e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("AGC Hysteresis Capture Volume", ADC3XXX_LEFT_CHN_AGC_2, 697e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_2, 6, 3, 0, agc_hysteresis_tlv), 698e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Clip Stepping Capture Switch", ADC3XXX_LEFT_CHN_AGC_2, 699e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_2, 0, 1, 0), 700e9a3b57eSRicard Wanderlof /* 701e9a3b57eSRicard Wanderlof * Oddly enough, the data sheet says the default value 702e9a3b57eSRicard Wanderlof * for the left/right AGC maximum gain register field 703e9a3b57eSRicard Wanderlof * (ADC3XXX_LEFT/RIGHT_CHN_AGC_3 bits 0..6) is 0x7f = 127 704e9a3b57eSRicard Wanderlof * (verified empirically) even though this value (indeed, above 705e9a3b57eSRicard Wanderlof * 0x50) is specified as 'Reserved. Do not use.' in the accompanying 706e9a3b57eSRicard Wanderlof * table in the data sheet. 707e9a3b57eSRicard Wanderlof */ 708e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("AGC Maximum Capture Volume", ADC3XXX_LEFT_CHN_AGC_3, 709e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_3, 0, 0x50, 0, agc_max_tlv), 710e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Attack Time", ADC3XXX_LEFT_CHN_AGC_4, 711e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_4, 3, 0x1f, 0), 712e9a3b57eSRicard Wanderlof /* Would like to have the multipliers as LR pairs, but there is 713e9a3b57eSRicard Wanderlof * no SOC_ENUM_foo which accepts two values in separate registers. 714e9a3b57eSRicard Wanderlof */ 715e9a3b57eSRicard Wanderlof SOC_ENUM("AGC Left Attack Time Multiplier", left_agc_attack_mult_enum), 716e9a3b57eSRicard Wanderlof SOC_ENUM("AGC Right Attack Time Multiplier", right_agc_attack_mult_enum), 717e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Decay Time", ADC3XXX_LEFT_CHN_AGC_5, 718e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_5, 3, 0x1f, 0), 719e9a3b57eSRicard Wanderlof SOC_ENUM("AGC Left Decay Time Multiplier", left_agc_decay_mult_enum), 720e9a3b57eSRicard Wanderlof SOC_ENUM("AGC Right Decay Time Multiplier", right_agc_decay_mult_enum), 721e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Noise Debounce", ADC3XXX_LEFT_CHN_AGC_6, 722e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_6, 0, 0x1f, 0), 723e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Signal Debounce", ADC3XXX_LEFT_CHN_AGC_7, 724e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_7, 0, 0x0f, 0), 725e9a3b57eSRicard Wanderlof /* Read only register */ 726e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_S_TLV("AGC Applied Capture Volume", ADC3XXX_LEFT_AGC_GAIN, 727e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_AGC_GAIN, 0, -24, 40, 6, 0, adc_tlv), 728e9a3b57eSRicard Wanderlof /* ADC soft stepping */ 729e9a3b57eSRicard Wanderlof SOC_ENUM("ADC Soft Stepping", adc_softstepping_enum), 730e9a3b57eSRicard Wanderlof /* Left/Right Input attenuation */ 731e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input IN_1L Capture Volume", 732e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv), 733e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input IN_2L Capture Volume", 734e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv), 735e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input IN_3L Capture Volume", 736e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv), 737e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input IN_1R Capture Volume", 738e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv), 739e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input DIF_2L_3L Capture Volume", 740e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv), 741e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input DIF_1L_1R Capture Volume", 742e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv), 743e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input DIF_2R_3R Capture Volume", 744e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv), 745e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input IN_1R Capture Volume", 746e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv), 747e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input IN_2R Capture Volume", 748e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv), 749e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input IN_3R Capture Volume", 750e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv), 751e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input IN_1L Capture Volume", 752e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv), 753e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input DIF_2R_3R Capture Volume", 754e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv), 755e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input DIF_1L_1R Capture Volume", 756e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv), 757e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input DIF_2L_3L Capture Volume", 758e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv), 759e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_S_TLV("ADC Volume Control Capture Volume", ADC3XXX_LADC_VOL, 760e9a3b57eSRicard Wanderlof ADC3XXX_RADC_VOL, 0, -24, 40, 6, 0, adc_tlv), 761e9a3b57eSRicard Wanderlof /* Empirically, the following doesn't work the way it's supposed 762e9a3b57eSRicard Wanderlof * to. Values 0, -0.1, -0.2 and -0.3 dB result in the same level, and 763e9a3b57eSRicard Wanderlof * -0.4 dB drops about 0.12 dB on a specific chip. 764e9a3b57eSRicard Wanderlof */ 765e9a3b57eSRicard Wanderlof SOC_DOUBLE_TLV("ADC Fine Volume Control Capture Volume", ADC3XXX_ADC_FGA, 766e9a3b57eSRicard Wanderlof 4, 0, 4, 1, adc_fine_tlv), 767e9a3b57eSRicard Wanderlof SOC_SINGLE("Left ADC Unselected CM Bias Capture Switch", 768e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 6, 1, 0), 769e9a3b57eSRicard Wanderlof SOC_SINGLE("Right ADC Unselected CM Bias Capture Switch", 770e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 6, 1, 0), 771e9a3b57eSRicard Wanderlof SOC_ENUM("Dither Control DC Offset", dither_dc_offset_enum), 7729193bc05SRicard Wanderlof 7739193bc05SRicard Wanderlof /* Coefficient memory for miniDSP. */ 7749193bc05SRicard Wanderlof /* For the default PRB_R1 processing block, the only available 7759193bc05SRicard Wanderlof * filter is the first order IIR. 7769193bc05SRicard Wanderlof */ 7779193bc05SRicard Wanderlof 7789193bc05SRicard Wanderlof TI_COEFFICIENTS("Left ADC IIR Coefficients N0 N1 D1", 7799193bc05SRicard Wanderlof ADC3XXX_LEFT_ADC_IIR_COEFF_N0_MSB, 3), 7809193bc05SRicard Wanderlof 7819193bc05SRicard Wanderlof TI_COEFFICIENTS("Right ADC IIR Coefficients N0 N1 D1", 7829193bc05SRicard Wanderlof ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_MSB, 3), 783e9a3b57eSRicard Wanderlof }; 784e9a3b57eSRicard Wanderlof 785e9a3b57eSRicard Wanderlof /* Left input selection, Single Ended inputs and Differential inputs */ 786e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new left_input_mixer_controls[] = { 787e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_1L Capture Switch", 788e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 1, 0x1, 1), 789e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_2L Capture Switch", 790e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 3, 0x1, 1), 791e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_3L Capture Switch", 792e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 5, 0x1, 1), 793e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch", 794e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 7, 0x1, 1), 795e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch", 796e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 5, 0x1, 1), 797e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch", 798e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 3, 0x1, 1), 799e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_1R Capture Switch", 800e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 1, 0x1, 1), 801e9a3b57eSRicard Wanderlof }; 802e9a3b57eSRicard Wanderlof 803e9a3b57eSRicard Wanderlof /* Right input selection, Single Ended inputs and Differential inputs */ 804e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new right_input_mixer_controls[] = { 805e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_1R Capture Switch", 806e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 1, 0x1, 1), 807e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_2R Capture Switch", 808e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 3, 0x1, 1), 809e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_3R Capture Switch", 810e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 5, 0x1, 1), 811e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch", 812e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 7, 0x1, 1), 813e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch", 814e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 5, 0x1, 1), 815e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch", 816e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 3, 0x1, 1), 817e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_1L Capture Switch", 818e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 1, 0x1, 1), 819e9a3b57eSRicard Wanderlof }; 820e9a3b57eSRicard Wanderlof 821e9a3b57eSRicard Wanderlof /* Left Digital Mic input for left ADC */ 822e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new left_input_dmic_controls[] = { 823e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("Left ADC Capture Switch", 824e9a3b57eSRicard Wanderlof ADC3XXX_ADC_DIGITAL, 3, 0x1, 0), 825e9a3b57eSRicard Wanderlof }; 826e9a3b57eSRicard Wanderlof 827e9a3b57eSRicard Wanderlof /* Right Digital Mic input for Right ADC */ 828e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new right_input_dmic_controls[] = { 829e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("Right ADC Capture Switch", 830e9a3b57eSRicard Wanderlof ADC3XXX_ADC_DIGITAL, 2, 0x1, 0), 831e9a3b57eSRicard Wanderlof }; 832e9a3b57eSRicard Wanderlof 833e9a3b57eSRicard Wanderlof /* DAPM widgets */ 834e9a3b57eSRicard Wanderlof static const struct snd_soc_dapm_widget adc3xxx_dapm_widgets[] = { 835e9a3b57eSRicard Wanderlof 836e9a3b57eSRicard Wanderlof /* Left Input Selection */ 837e9a3b57eSRicard Wanderlof SND_SOC_DAPM_MIXER("Left Input", SND_SOC_NOPM, 0, 0, 838e9a3b57eSRicard Wanderlof &left_input_mixer_controls[0], 839e9a3b57eSRicard Wanderlof ARRAY_SIZE(left_input_mixer_controls)), 840e9a3b57eSRicard Wanderlof /* Right Input Selection */ 841e9a3b57eSRicard Wanderlof SND_SOC_DAPM_MIXER("Right Input", SND_SOC_NOPM, 0, 0, 842e9a3b57eSRicard Wanderlof &right_input_mixer_controls[0], 843e9a3b57eSRicard Wanderlof ARRAY_SIZE(right_input_mixer_controls)), 844e9a3b57eSRicard Wanderlof /* PGA selection */ 845e9a3b57eSRicard Wanderlof SND_SOC_DAPM_PGA("Left PGA", ADC3XXX_LEFT_APGA_CTRL, 7, 1, NULL, 0), 846e9a3b57eSRicard Wanderlof SND_SOC_DAPM_PGA("Right PGA", ADC3XXX_RIGHT_APGA_CTRL, 7, 1, NULL, 0), 847e9a3b57eSRicard Wanderlof 848e9a3b57eSRicard Wanderlof /* Digital Microphone Input Control for Left/Right ADC */ 849e9a3b57eSRicard Wanderlof SND_SOC_DAPM_MIXER("Left DMic Input", SND_SOC_NOPM, 0, 0, 850e9a3b57eSRicard Wanderlof &left_input_dmic_controls[0], 851e9a3b57eSRicard Wanderlof ARRAY_SIZE(left_input_dmic_controls)), 852e9a3b57eSRicard Wanderlof SND_SOC_DAPM_MIXER("Right DMic Input", SND_SOC_NOPM, 0, 0, 853e9a3b57eSRicard Wanderlof &right_input_dmic_controls[0], 854e9a3b57eSRicard Wanderlof ARRAY_SIZE(right_input_dmic_controls)), 855e9a3b57eSRicard Wanderlof 856e9a3b57eSRicard Wanderlof /* Left/Right ADC */ 857e9a3b57eSRicard Wanderlof SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ADC3XXX_ADC_DIGITAL, 7, 0), 858e9a3b57eSRicard Wanderlof SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ADC3XXX_ADC_DIGITAL, 6, 0), 859e9a3b57eSRicard Wanderlof 860e9a3b57eSRicard Wanderlof /* Inputs */ 861e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_1L"), 862e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_1R"), 863e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_2L"), 864e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_2R"), 865e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_3L"), 866e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_3R"), 867e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFL_1L_1R"), 868e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFL_2L_3L"), 869e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFL_2R_3R"), 870e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFR_1L_1R"), 871e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFR_2L_3L"), 872e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFR_2R_3R"), 873e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DMic_L"), 874e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DMic_R"), 875e9a3b57eSRicard Wanderlof 876e9a3b57eSRicard Wanderlof /* Digital audio interface output */ 877e9a3b57eSRicard Wanderlof SND_SOC_DAPM_AIF_OUT("AIF_OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 878e9a3b57eSRicard Wanderlof 879e9a3b57eSRicard Wanderlof /* Clocks */ 880e9a3b57eSRicard Wanderlof SND_SOC_DAPM_SUPPLY("PLL_CLK", ADC3XXX_PLL_PROG_PR, ADC3XXX_ENABLE_PLL_SHIFT, 881e9a3b57eSRicard Wanderlof 0, adc3xxx_pll_delay, SND_SOC_DAPM_POST_PMU), 882e9a3b57eSRicard Wanderlof 883e9a3b57eSRicard Wanderlof SND_SOC_DAPM_SUPPLY("ADC_CLK", ADC3XXX_ADC_NADC, ADC3XXX_ENABLE_NADC_SHIFT, 884e9a3b57eSRicard Wanderlof 0, NULL, 0), 885e9a3b57eSRicard Wanderlof SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK", ADC3XXX_ADC_MADC, ADC3XXX_ENABLE_MADC_SHIFT, 886e9a3b57eSRicard Wanderlof 0, NULL, 0), 887e9a3b57eSRicard Wanderlof 888e9a3b57eSRicard Wanderlof /* This refers to the generated BCLK in master mode. */ 889e9a3b57eSRicard Wanderlof SND_SOC_DAPM_SUPPLY("BCLK", ADC3XXX_BCLK_N_DIV, ADC3XXX_ENABLE_BCLK_SHIFT, 890e9a3b57eSRicard Wanderlof 0, NULL, 0), 891e9a3b57eSRicard Wanderlof }; 892e9a3b57eSRicard Wanderlof 893e9a3b57eSRicard Wanderlof static const struct snd_soc_dapm_route adc3xxx_intercon[] = { 894e9a3b57eSRicard Wanderlof /* Left input selection from switches */ 895e9a3b57eSRicard Wanderlof { "Left Input", "IN_1L Capture Switch", "IN_1L" }, 896e9a3b57eSRicard Wanderlof { "Left Input", "IN_2L Capture Switch", "IN_2L" }, 897e9a3b57eSRicard Wanderlof { "Left Input", "IN_3L Capture Switch", "IN_3L" }, 898e9a3b57eSRicard Wanderlof { "Left Input", "DIF_2L_3L Capture Switch", "DIFL_2L_3L" }, 899e9a3b57eSRicard Wanderlof { "Left Input", "DIF_1L_1R Capture Switch", "DIFL_1L_1R" }, 900e9a3b57eSRicard Wanderlof { "Left Input", "DIF_2R_3R Capture Switch", "DIFL_2R_3R" }, 901e9a3b57eSRicard Wanderlof { "Left Input", "IN_1R Capture Switch", "IN_1R" }, 902e9a3b57eSRicard Wanderlof 903e9a3b57eSRicard Wanderlof /* Left input selection to left PGA */ 904e9a3b57eSRicard Wanderlof { "Left PGA", NULL, "Left Input" }, 905e9a3b57eSRicard Wanderlof 906e9a3b57eSRicard Wanderlof /* Left PGA to left ADC */ 907e9a3b57eSRicard Wanderlof { "Left ADC", NULL, "Left PGA" }, 908e9a3b57eSRicard Wanderlof 909e9a3b57eSRicard Wanderlof /* Right input selection from switches */ 910e9a3b57eSRicard Wanderlof { "Right Input", "IN_1R Capture Switch", "IN_1R" }, 911e9a3b57eSRicard Wanderlof { "Right Input", "IN_2R Capture Switch", "IN_2R" }, 912e9a3b57eSRicard Wanderlof { "Right Input", "IN_3R Capture Switch", "IN_3R" }, 913e9a3b57eSRicard Wanderlof { "Right Input", "DIF_2R_3R Capture Switch", "DIFR_2R_3R" }, 914e9a3b57eSRicard Wanderlof { "Right Input", "DIF_1L_1R Capture Switch", "DIFR_1L_1R" }, 915e9a3b57eSRicard Wanderlof { "Right Input", "DIF_2L_3L Capture Switch", "DIFR_2L_3L" }, 916e9a3b57eSRicard Wanderlof { "Right Input", "IN_1L Capture Switch", "IN_1L" }, 917e9a3b57eSRicard Wanderlof 918e9a3b57eSRicard Wanderlof /* Right input selection to right PGA */ 919e9a3b57eSRicard Wanderlof { "Right PGA", NULL, "Right Input" }, 920e9a3b57eSRicard Wanderlof 921e9a3b57eSRicard Wanderlof /* Right PGA to right ADC */ 922e9a3b57eSRicard Wanderlof { "Right ADC", NULL, "Right PGA" }, 923e9a3b57eSRicard Wanderlof 924e9a3b57eSRicard Wanderlof /* Left DMic Input selection from switch */ 925e9a3b57eSRicard Wanderlof { "Left DMic Input", "Left ADC Capture Switch", "DMic_L" }, 926e9a3b57eSRicard Wanderlof 927e9a3b57eSRicard Wanderlof /* Left DMic to left ADC */ 928e9a3b57eSRicard Wanderlof { "Left ADC", NULL, "Left DMic Input" }, 929e9a3b57eSRicard Wanderlof 930e9a3b57eSRicard Wanderlof /* Right DMic Input selection from switch */ 931e9a3b57eSRicard Wanderlof { "Right DMic Input", "Right ADC Capture Switch", "DMic_R" }, 932e9a3b57eSRicard Wanderlof 933e9a3b57eSRicard Wanderlof /* Right DMic to right ADC */ 934e9a3b57eSRicard Wanderlof { "Right ADC", NULL, "Right DMic Input" }, 935e9a3b57eSRicard Wanderlof 936e9a3b57eSRicard Wanderlof /* ADC to AIF output */ 937e9a3b57eSRicard Wanderlof { "AIF_OUT", NULL, "Left ADC" }, 938e9a3b57eSRicard Wanderlof { "AIF_OUT", NULL, "Right ADC" }, 939e9a3b57eSRicard Wanderlof 940e9a3b57eSRicard Wanderlof /* Clocking */ 941e9a3b57eSRicard Wanderlof { "ADC_MOD_CLK", NULL, "ADC_CLK" }, 942e9a3b57eSRicard Wanderlof { "Left ADC", NULL, "ADC_MOD_CLK" }, 943e9a3b57eSRicard Wanderlof { "Right ADC", NULL, "ADC_MOD_CLK" }, 944e9a3b57eSRicard Wanderlof 945e9a3b57eSRicard Wanderlof { "BCLK", NULL, "ADC_CLK" }, 946e9a3b57eSRicard Wanderlof }; 947e9a3b57eSRicard Wanderlof 948e9a3b57eSRicard Wanderlof static const struct snd_soc_dapm_route adc3xxx_pll_intercon[] = { 949e9a3b57eSRicard Wanderlof { "ADC_CLK", NULL, "PLL_CLK" }, 950e9a3b57eSRicard Wanderlof }; 951e9a3b57eSRicard Wanderlof 952e9a3b57eSRicard Wanderlof static const struct snd_soc_dapm_route adc3xxx_bclk_out_intercon[] = { 953e9a3b57eSRicard Wanderlof { "AIF_OUT", NULL, "BCLK" } 954e9a3b57eSRicard Wanderlof }; 955e9a3b57eSRicard Wanderlof 956e9a3b57eSRicard Wanderlof static int adc3xxx_gpio_request(struct gpio_chip *chip, unsigned int offset) 957e9a3b57eSRicard Wanderlof { 958e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = gpiochip_get_data(chip); 959e9a3b57eSRicard Wanderlof 960e9a3b57eSRicard Wanderlof if (offset >= ADC3XXX_GPIOS_MAX) 961e9a3b57eSRicard Wanderlof return -EINVAL; 962e9a3b57eSRicard Wanderlof 963e9a3b57eSRicard Wanderlof /* GPIO1 is offset 0, GPIO2 is offset 1 */ 964e9a3b57eSRicard Wanderlof /* We check here that the GPIO pins are either not configured in the 965e9a3b57eSRicard Wanderlof * DT, or that they purposely are set as outputs. 966e9a3b57eSRicard Wanderlof * (Input mode not yet implemented). 967e9a3b57eSRicard Wanderlof */ 968e9a3b57eSRicard Wanderlof if (adc3xxx->gpio_cfg[offset] != 0 && 969e9a3b57eSRicard Wanderlof adc3xxx->gpio_cfg[offset] != ADC3XXX_GPIO_GPO + 1) 970e9a3b57eSRicard Wanderlof return -EINVAL; 971e9a3b57eSRicard Wanderlof 972e9a3b57eSRicard Wanderlof return 0; 973e9a3b57eSRicard Wanderlof } 974e9a3b57eSRicard Wanderlof 975e9a3b57eSRicard Wanderlof static int adc3xxx_gpio_direction_out(struct gpio_chip *chip, 976e9a3b57eSRicard Wanderlof unsigned int offset, int value) 977e9a3b57eSRicard Wanderlof { 978e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = gpiochip_get_data(chip); 979e9a3b57eSRicard Wanderlof 980e9a3b57eSRicard Wanderlof /* Set GPIO output function. */ 981e9a3b57eSRicard Wanderlof return regmap_update_bits(adc3xxx->regmap, 982e9a3b57eSRicard Wanderlof adc3xxx_gpio_ctrl_reg[offset], 983e9a3b57eSRicard Wanderlof ADC3XXX_GPIO_CTRL_CFG_MASK | 984e9a3b57eSRicard Wanderlof ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK, 985e9a3b57eSRicard Wanderlof ADC3XXX_GPIO_GPO << ADC3XXX_GPIO_CTRL_CFG_SHIFT | 986e9a3b57eSRicard Wanderlof !!value << ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT); 987e9a3b57eSRicard Wanderlof } 988e9a3b57eSRicard Wanderlof 989e9a3b57eSRicard Wanderlof /* With only GPIO outputs configured, we never get the .direction_out call, 990e9a3b57eSRicard Wanderlof * so we set the output mode and output value in the same call. Hence 991e9a3b57eSRicard Wanderlof * .set in practice does the same thing as .direction_out . 992e9a3b57eSRicard Wanderlof */ 993e9a3b57eSRicard Wanderlof static void adc3xxx_gpio_set(struct gpio_chip *chip, unsigned int offset, 994e9a3b57eSRicard Wanderlof int value) 995e9a3b57eSRicard Wanderlof { 996e9a3b57eSRicard Wanderlof (void) adc3xxx_gpio_direction_out(chip, offset, value); 997e9a3b57eSRicard Wanderlof } 998e9a3b57eSRicard Wanderlof 999e9a3b57eSRicard Wanderlof /* Even though we only support GPIO output for now, some GPIO clients 1000e9a3b57eSRicard Wanderlof * want to read the current pin state using the .get callback. 1001e9a3b57eSRicard Wanderlof */ 1002e9a3b57eSRicard Wanderlof static int adc3xxx_gpio_get(struct gpio_chip *chip, unsigned int offset) 1003e9a3b57eSRicard Wanderlof { 1004e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = gpiochip_get_data(chip); 1005e9a3b57eSRicard Wanderlof unsigned int regval; 1006e9a3b57eSRicard Wanderlof int ret; 1007e9a3b57eSRicard Wanderlof 1008e9a3b57eSRicard Wanderlof /* We only allow output pins, so just read the value set in the output 1009e9a3b57eSRicard Wanderlof * pin register field. 1010e9a3b57eSRicard Wanderlof */ 1011e9a3b57eSRicard Wanderlof ret = regmap_read(adc3xxx->regmap, adc3xxx_gpio_ctrl_reg[offset], ®val); 1012e9a3b57eSRicard Wanderlof if (ret) 1013e9a3b57eSRicard Wanderlof return ret; 1014e9a3b57eSRicard Wanderlof return !!(regval & ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK); 1015e9a3b57eSRicard Wanderlof } 1016e9a3b57eSRicard Wanderlof 1017e9a3b57eSRicard Wanderlof static const struct gpio_chip adc3xxx_gpio_chip = { 1018e9a3b57eSRicard Wanderlof .label = "adc3xxx", 1019e9a3b57eSRicard Wanderlof .owner = THIS_MODULE, 1020e9a3b57eSRicard Wanderlof .request = adc3xxx_gpio_request, 1021e9a3b57eSRicard Wanderlof .direction_output = adc3xxx_gpio_direction_out, 1022e9a3b57eSRicard Wanderlof .set = adc3xxx_gpio_set, 1023e9a3b57eSRicard Wanderlof .get = adc3xxx_gpio_get, 1024e9a3b57eSRicard Wanderlof .can_sleep = 1, 1025e9a3b57eSRicard Wanderlof }; 1026e9a3b57eSRicard Wanderlof 1027e9a3b57eSRicard Wanderlof static void adc3xxx_free_gpio(struct adc3xxx *adc3xxx) 1028e9a3b57eSRicard Wanderlof { 102919c5bda7SHui Tang #ifdef CONFIG_GPIOLIB 1030e9a3b57eSRicard Wanderlof gpiochip_remove(&adc3xxx->gpio_chip); 103119c5bda7SHui Tang #endif 1032e9a3b57eSRicard Wanderlof } 1033e9a3b57eSRicard Wanderlof 1034e9a3b57eSRicard Wanderlof static void adc3xxx_init_gpio(struct adc3xxx *adc3xxx) 1035e9a3b57eSRicard Wanderlof { 1036e9a3b57eSRicard Wanderlof int gpio, micbias; 1037e9a3b57eSRicard Wanderlof int ret; 1038e9a3b57eSRicard Wanderlof 1039e9a3b57eSRicard Wanderlof adc3xxx->gpio_chip = adc3xxx_gpio_chip; 1040e9a3b57eSRicard Wanderlof adc3xxx->gpio_chip.ngpio = ADC3XXX_GPIOS_MAX; 1041e9a3b57eSRicard Wanderlof adc3xxx->gpio_chip.parent = adc3xxx->dev; 1042e9a3b57eSRicard Wanderlof adc3xxx->gpio_chip.base = -1; 1043e9a3b57eSRicard Wanderlof 1044e9a3b57eSRicard Wanderlof ret = gpiochip_add_data(&adc3xxx->gpio_chip, adc3xxx); 1045e9a3b57eSRicard Wanderlof if (ret) 1046e9a3b57eSRicard Wanderlof dev_err(adc3xxx->dev, "Failed to add gpios: %d\n", ret); 1047e9a3b57eSRicard Wanderlof 1048e9a3b57eSRicard Wanderlof /* Set up potential GPIO configuration from the devicetree. 1049e9a3b57eSRicard Wanderlof * This allows us to set up things which are not software 1050e9a3b57eSRicard Wanderlof * controllable GPIOs, such as PDM microphone I/O, 1051e9a3b57eSRicard Wanderlof */ 1052e9a3b57eSRicard Wanderlof for (gpio = 0; gpio < ADC3XXX_GPIOS_MAX; gpio++) { 1053e9a3b57eSRicard Wanderlof unsigned int cfg = adc3xxx->gpio_cfg[gpio]; 1054e9a3b57eSRicard Wanderlof 1055e9a3b57eSRicard Wanderlof if (cfg) { 1056e9a3b57eSRicard Wanderlof cfg--; /* actual value to use is stored +1 */ 1057e9a3b57eSRicard Wanderlof regmap_update_bits(adc3xxx->regmap, 1058e9a3b57eSRicard Wanderlof adc3xxx_gpio_ctrl_reg[gpio], 1059e9a3b57eSRicard Wanderlof ADC3XXX_GPIO_CTRL_CFG_MASK, 1060e9a3b57eSRicard Wanderlof cfg << ADC3XXX_GPIO_CTRL_CFG_SHIFT); 1061e9a3b57eSRicard Wanderlof } 1062e9a3b57eSRicard Wanderlof } 1063e9a3b57eSRicard Wanderlof 1064e9a3b57eSRicard Wanderlof /* Set up micbias voltage */ 1065e9a3b57eSRicard Wanderlof for (micbias = 0; micbias < ADC3XXX_MICBIAS_PINS; micbias++) { 1066e9a3b57eSRicard Wanderlof unsigned int vg = adc3xxx->micbias_vg[micbias]; 1067e9a3b57eSRicard Wanderlof 1068e9a3b57eSRicard Wanderlof regmap_update_bits(adc3xxx->regmap, 1069e9a3b57eSRicard Wanderlof ADC3XXX_MICBIAS_CTRL, 1070e9a3b57eSRicard Wanderlof ADC3XXX_MICBIAS_MASK << adc3xxx_micbias_shift[micbias], 1071e9a3b57eSRicard Wanderlof vg << adc3xxx_micbias_shift[micbias]); 1072e9a3b57eSRicard Wanderlof } 1073e9a3b57eSRicard Wanderlof } 1074e9a3b57eSRicard Wanderlof 1075e9a3b57eSRicard Wanderlof static int adc3xxx_parse_dt_gpio(struct adc3xxx *adc3xxx, 1076e9a3b57eSRicard Wanderlof const char *propname, unsigned int *cfg) 1077e9a3b57eSRicard Wanderlof { 1078e9a3b57eSRicard Wanderlof struct device *dev = adc3xxx->dev; 1079e9a3b57eSRicard Wanderlof struct device_node *np = dev->of_node; 1080e9a3b57eSRicard Wanderlof unsigned int val; 1081e9a3b57eSRicard Wanderlof 1082e9a3b57eSRicard Wanderlof if (!of_property_read_u32(np, propname, &val)) { 1083e9a3b57eSRicard Wanderlof if (val & ~15 || val == 7 || val >= 11) { 1084e9a3b57eSRicard Wanderlof dev_err(dev, "Invalid property value for '%s'\n", propname); 1085e9a3b57eSRicard Wanderlof return -EINVAL; 1086e9a3b57eSRicard Wanderlof } 1087e9a3b57eSRicard Wanderlof if (val == ADC3XXX_GPIO_GPI) 1088e9a3b57eSRicard Wanderlof dev_warn(dev, "GPIO Input read not yet implemented\n"); 1089e9a3b57eSRicard Wanderlof *cfg = val + 1; /* 0 => not set up, all others shifted +1 */ 1090e9a3b57eSRicard Wanderlof } 1091e9a3b57eSRicard Wanderlof return 0; 1092e9a3b57eSRicard Wanderlof } 1093e9a3b57eSRicard Wanderlof 1094e9a3b57eSRicard Wanderlof static int adc3xxx_parse_dt_micbias(struct adc3xxx *adc3xxx, 1095e9a3b57eSRicard Wanderlof const char *propname, unsigned int *vg) 1096e9a3b57eSRicard Wanderlof { 1097e9a3b57eSRicard Wanderlof struct device *dev = adc3xxx->dev; 1098e9a3b57eSRicard Wanderlof struct device_node *np = dev->of_node; 1099e9a3b57eSRicard Wanderlof unsigned int val; 1100e9a3b57eSRicard Wanderlof 1101e9a3b57eSRicard Wanderlof if (!of_property_read_u32(np, propname, &val)) { 1102e9a3b57eSRicard Wanderlof if (val >= ADC3XXX_MICBIAS_AVDD) { 1103e9a3b57eSRicard Wanderlof dev_err(dev, "Invalid property value for '%s'\n", propname); 1104e9a3b57eSRicard Wanderlof return -EINVAL; 1105e9a3b57eSRicard Wanderlof } 1106e9a3b57eSRicard Wanderlof *vg = val; 1107e9a3b57eSRicard Wanderlof } 1108e9a3b57eSRicard Wanderlof return 0; 1109e9a3b57eSRicard Wanderlof } 1110e9a3b57eSRicard Wanderlof 1111e9a3b57eSRicard Wanderlof static int adc3xxx_parse_pll_mode(uint32_t val, unsigned int *pll_mode) 1112e9a3b57eSRicard Wanderlof { 1113e9a3b57eSRicard Wanderlof if (val != ADC3XXX_PLL_ENABLE && val != ADC3XXX_PLL_BYPASS && 1114e9a3b57eSRicard Wanderlof val != ADC3XXX_PLL_AUTO) 1115e9a3b57eSRicard Wanderlof return -EINVAL; 1116e9a3b57eSRicard Wanderlof 1117e9a3b57eSRicard Wanderlof *pll_mode = val; 1118e9a3b57eSRicard Wanderlof 1119e9a3b57eSRicard Wanderlof return 0; 1120e9a3b57eSRicard Wanderlof } 1121e9a3b57eSRicard Wanderlof 1122e9a3b57eSRicard Wanderlof static void adc3xxx_setup_pll(struct snd_soc_component *component, 1123e9a3b57eSRicard Wanderlof int div_entry) 1124e9a3b57eSRicard Wanderlof { 1125e9a3b57eSRicard Wanderlof int i = div_entry; 1126e9a3b57eSRicard Wanderlof 1127e9a3b57eSRicard Wanderlof /* P & R values */ 1128e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_PLL_PROG_PR, 1129e9a3b57eSRicard Wanderlof (adc3xxx_divs[i].pll_p << ADC3XXX_PLLP_SHIFT) | 1130e9a3b57eSRicard Wanderlof (adc3xxx_divs[i].pll_r << ADC3XXX_PLLR_SHIFT)); 1131e9a3b57eSRicard Wanderlof /* J value */ 1132e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_PLL_PROG_J, 1133e9a3b57eSRicard Wanderlof adc3xxx_divs[i].pll_j & ADC3XXX_PLLJ_MASK); 1134e9a3b57eSRicard Wanderlof /* D value */ 1135e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_LSB, 1136e9a3b57eSRicard Wanderlof adc3xxx_divs[i].pll_d & ADC3XXX_PLLD_LSB_MASK); 1137e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_MSB, 1138e9a3b57eSRicard Wanderlof (adc3xxx_divs[i].pll_d >> 8) & ADC3XXX_PLLD_MSB_MASK); 1139e9a3b57eSRicard Wanderlof } 1140e9a3b57eSRicard Wanderlof 1141e9a3b57eSRicard Wanderlof static int adc3xxx_hw_params(struct snd_pcm_substream *substream, 1142e9a3b57eSRicard Wanderlof struct snd_pcm_hw_params *params, 1143e9a3b57eSRicard Wanderlof struct snd_soc_dai *dai) 1144e9a3b57eSRicard Wanderlof { 1145e9a3b57eSRicard Wanderlof struct snd_soc_component *component = dai->component; 1146e9a3b57eSRicard Wanderlof struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component); 1147e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component); 1148e9a3b57eSRicard Wanderlof int i, width = 16; 1149e9a3b57eSRicard Wanderlof u8 iface_len, bdiv; 1150e9a3b57eSRicard Wanderlof 1151e9a3b57eSRicard Wanderlof i = adc3xxx_get_divs(component->dev, adc3xxx->sysclk, 1152e9a3b57eSRicard Wanderlof params_rate(params), adc3xxx->pll_mode); 1153e9a3b57eSRicard Wanderlof 1154e9a3b57eSRicard Wanderlof if (i < 0) 1155e9a3b57eSRicard Wanderlof return i; 1156e9a3b57eSRicard Wanderlof 1157e9a3b57eSRicard Wanderlof /* select data word length */ 1158f5e0084bSCharles Keepax switch (params_width(params)) { 1159f5e0084bSCharles Keepax case 16: 1160e9a3b57eSRicard Wanderlof iface_len = ADC3XXX_IFACE_16BITS; 1161e9a3b57eSRicard Wanderlof width = 16; 1162e9a3b57eSRicard Wanderlof break; 1163f5e0084bSCharles Keepax case 20: 1164e9a3b57eSRicard Wanderlof iface_len = ADC3XXX_IFACE_20BITS; 1165e9a3b57eSRicard Wanderlof width = 20; 1166e9a3b57eSRicard Wanderlof break; 1167f5e0084bSCharles Keepax case 24: 1168e9a3b57eSRicard Wanderlof iface_len = ADC3XXX_IFACE_24BITS; 1169e9a3b57eSRicard Wanderlof width = 24; 1170e9a3b57eSRicard Wanderlof break; 1171f5e0084bSCharles Keepax case 32: 1172e9a3b57eSRicard Wanderlof iface_len = ADC3XXX_IFACE_32BITS; 1173e9a3b57eSRicard Wanderlof width = 32; 1174e9a3b57eSRicard Wanderlof break; 1175e9a3b57eSRicard Wanderlof default: 1176e9a3b57eSRicard Wanderlof dev_err(component->dev, "Unsupported serial data format\n"); 1177e9a3b57eSRicard Wanderlof return -EINVAL; 1178e9a3b57eSRicard Wanderlof } 1179e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_INTERFACE_CTRL_1, 1180e9a3b57eSRicard Wanderlof ADC3XXX_WLENGTH_MASK, iface_len); 1181e9a3b57eSRicard Wanderlof if (adc3xxx_divs[i].pll_p) { /* If PLL used for this mode */ 1182e9a3b57eSRicard Wanderlof adc3xxx_setup_pll(component, i); 1183e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_USE_PLL); 1184e9a3b57eSRicard Wanderlof if (!adc3xxx->use_pll) { 1185e9a3b57eSRicard Wanderlof snd_soc_dapm_add_routes(dapm, adc3xxx_pll_intercon, 1186e9a3b57eSRicard Wanderlof ARRAY_SIZE(adc3xxx_pll_intercon)); 1187e9a3b57eSRicard Wanderlof adc3xxx->use_pll = 1; 1188e9a3b57eSRicard Wanderlof } 1189e9a3b57eSRicard Wanderlof } else { 1190e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_NO_PLL); 1191e9a3b57eSRicard Wanderlof if (adc3xxx->use_pll) { 1192e9a3b57eSRicard Wanderlof snd_soc_dapm_del_routes(dapm, adc3xxx_pll_intercon, 1193e9a3b57eSRicard Wanderlof ARRAY_SIZE(adc3xxx_pll_intercon)); 1194e9a3b57eSRicard Wanderlof adc3xxx->use_pll = 0; 1195e9a3b57eSRicard Wanderlof } 1196e9a3b57eSRicard Wanderlof } 1197e9a3b57eSRicard Wanderlof 1198e9a3b57eSRicard Wanderlof /* NADC */ 1199e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_ADC_NADC, 1200e9a3b57eSRicard Wanderlof ADC3XXX_NADC_MASK, adc3xxx_divs[i].nadc); 1201e9a3b57eSRicard Wanderlof /* MADC */ 1202e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_ADC_MADC, 1203e9a3b57eSRicard Wanderlof ADC3XXX_MADC_MASK, adc3xxx_divs[i].madc); 1204e9a3b57eSRicard Wanderlof /* AOSR */ 1205e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_ADC_AOSR, 1206e9a3b57eSRicard Wanderlof ADC3XXX_AOSR_MASK, adc3xxx_divs[i].aosr); 1207e9a3b57eSRicard Wanderlof /* BDIV N Value */ 1208e9a3b57eSRicard Wanderlof /* BCLK is (by default) set up to be derived from ADC_CLK */ 1209e9a3b57eSRicard Wanderlof bdiv = (adc3xxx_divs[i].aosr * adc3xxx_divs[i].madc) / (2 * width); 1210e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_BCLK_N_DIV, 1211e9a3b57eSRicard Wanderlof ADC3XXX_BDIV_MASK, bdiv); 1212e9a3b57eSRicard Wanderlof 1213e9a3b57eSRicard Wanderlof return 0; 1214e9a3b57eSRicard Wanderlof } 1215e9a3b57eSRicard Wanderlof 1216e9a3b57eSRicard Wanderlof static const char *adc3xxx_pll_mode_text(int pll_mode) 1217e9a3b57eSRicard Wanderlof { 1218e9a3b57eSRicard Wanderlof switch (pll_mode) { 1219e9a3b57eSRicard Wanderlof case ADC3XXX_PLL_AUTO: 1220e9a3b57eSRicard Wanderlof return "PLL auto"; 1221e9a3b57eSRicard Wanderlof case ADC3XXX_PLL_ENABLE: 1222e9a3b57eSRicard Wanderlof return "PLL enable"; 1223e9a3b57eSRicard Wanderlof case ADC3XXX_PLL_BYPASS: 1224e9a3b57eSRicard Wanderlof return "PLL bypass"; 1225e9a3b57eSRicard Wanderlof default: 1226e9a3b57eSRicard Wanderlof break; 1227e9a3b57eSRicard Wanderlof } 1228e9a3b57eSRicard Wanderlof 1229e9a3b57eSRicard Wanderlof return "PLL unknown"; 1230e9a3b57eSRicard Wanderlof } 1231e9a3b57eSRicard Wanderlof 1232e9a3b57eSRicard Wanderlof static int adc3xxx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1233e9a3b57eSRicard Wanderlof int clk_id, unsigned int freq, int dir) 1234e9a3b57eSRicard Wanderlof { 1235e9a3b57eSRicard Wanderlof struct snd_soc_component *component = codec_dai->component; 1236e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component); 1237e9a3b57eSRicard Wanderlof int ret; 1238e9a3b57eSRicard Wanderlof 1239e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_pll_mode(clk_id, &adc3xxx->pll_mode); 1240e9a3b57eSRicard Wanderlof if (ret < 0) 1241e9a3b57eSRicard Wanderlof return ret; 1242e9a3b57eSRicard Wanderlof 1243e9a3b57eSRicard Wanderlof adc3xxx->sysclk = freq; 1244e9a3b57eSRicard Wanderlof dev_dbg(component->dev, "Set sysclk to %u Hz, %s\n", 1245e9a3b57eSRicard Wanderlof freq, adc3xxx_pll_mode_text(adc3xxx->pll_mode)); 1246e9a3b57eSRicard Wanderlof return 0; 1247e9a3b57eSRicard Wanderlof } 1248e9a3b57eSRicard Wanderlof 1249e9a3b57eSRicard Wanderlof static int adc3xxx_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1250e9a3b57eSRicard Wanderlof { 1251e9a3b57eSRicard Wanderlof struct snd_soc_component *component = codec_dai->component; 1252e9a3b57eSRicard Wanderlof struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1253e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component); 1254e9a3b57eSRicard Wanderlof u8 clkdir = 0, format = 0; 1255e9a3b57eSRicard Wanderlof int master = 0; 1256eb8b5af7SRicard Wanderlof int ret; 1257e9a3b57eSRicard Wanderlof 1258ad60ff09SMark Brown switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1259e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_CBP_CFP: 1260e9a3b57eSRicard Wanderlof master = 1; 1261e9a3b57eSRicard Wanderlof clkdir = ADC3XXX_BCLK_MASTER | ADC3XXX_WCLK_MASTER; 1262e9a3b57eSRicard Wanderlof break; 1263e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_CBC_CFC: 1264e9a3b57eSRicard Wanderlof master = 0; 1265e9a3b57eSRicard Wanderlof break; 1266e9a3b57eSRicard Wanderlof default: 1267e9a3b57eSRicard Wanderlof dev_err(component->dev, "Invalid DAI clock setup\n"); 1268e9a3b57eSRicard Wanderlof return -EINVAL; 1269e9a3b57eSRicard Wanderlof } 1270e9a3b57eSRicard Wanderlof 1271e9a3b57eSRicard Wanderlof /* 1272e9a3b57eSRicard Wanderlof * match both interface format and signal polarities since they 1273e9a3b57eSRicard Wanderlof * are fixed 1274e9a3b57eSRicard Wanderlof */ 1275e9a3b57eSRicard Wanderlof switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK)) { 1276e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF: 1277e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_I2S; 1278e9a3b57eSRicard Wanderlof break; 1279e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF: 1280e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_DSP; 1281e9a3b57eSRicard Wanderlof break; 1282e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF: 1283e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_DSP; 1284e9a3b57eSRicard Wanderlof break; 1285e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF: 1286e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_RJF; 1287e9a3b57eSRicard Wanderlof break; 1288e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF: 1289e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_LJF; 1290e9a3b57eSRicard Wanderlof break; 1291e9a3b57eSRicard Wanderlof default: 1292e9a3b57eSRicard Wanderlof dev_err(component->dev, "Invalid DAI format\n"); 1293e9a3b57eSRicard Wanderlof return -EINVAL; 1294e9a3b57eSRicard Wanderlof } 1295e9a3b57eSRicard Wanderlof 1296e9a3b57eSRicard Wanderlof /* Add/del route enabling BCLK output as applicable */ 1297e9a3b57eSRicard Wanderlof if (master && !adc3xxx->master) 1298e9a3b57eSRicard Wanderlof snd_soc_dapm_add_routes(dapm, adc3xxx_bclk_out_intercon, 1299e9a3b57eSRicard Wanderlof ARRAY_SIZE(adc3xxx_bclk_out_intercon)); 1300e9a3b57eSRicard Wanderlof else if (!master && adc3xxx->master) 1301e9a3b57eSRicard Wanderlof snd_soc_dapm_del_routes(dapm, adc3xxx_bclk_out_intercon, 1302e9a3b57eSRicard Wanderlof ARRAY_SIZE(adc3xxx_bclk_out_intercon)); 1303e9a3b57eSRicard Wanderlof adc3xxx->master = master; 1304e9a3b57eSRicard Wanderlof 1305e9a3b57eSRicard Wanderlof /* set clock direction and format */ 1306eb8b5af7SRicard Wanderlof ret = snd_soc_component_update_bits(component, 1307e9a3b57eSRicard Wanderlof ADC3XXX_INTERFACE_CTRL_1, 1308e9a3b57eSRicard Wanderlof ADC3XXX_CLKDIR_MASK | ADC3XXX_FORMAT_MASK, 1309e9a3b57eSRicard Wanderlof clkdir | format); 1310eb8b5af7SRicard Wanderlof if (ret < 0) 1311eb8b5af7SRicard Wanderlof return ret; 1312eb8b5af7SRicard Wanderlof return 0; 1313e9a3b57eSRicard Wanderlof } 1314e9a3b57eSRicard Wanderlof 1315e9a3b57eSRicard Wanderlof static const struct snd_soc_dai_ops adc3xxx_dai_ops = { 1316e9a3b57eSRicard Wanderlof .hw_params = adc3xxx_hw_params, 1317e9a3b57eSRicard Wanderlof .set_sysclk = adc3xxx_set_dai_sysclk, 1318e9a3b57eSRicard Wanderlof .set_fmt = adc3xxx_set_dai_fmt, 1319e9a3b57eSRicard Wanderlof }; 1320e9a3b57eSRicard Wanderlof 1321e9a3b57eSRicard Wanderlof static struct snd_soc_dai_driver adc3xxx_dai = { 1322e9a3b57eSRicard Wanderlof .name = "tlv320adc3xxx-hifi", 1323e9a3b57eSRicard Wanderlof .capture = { 1324e9a3b57eSRicard Wanderlof .stream_name = "Capture", 1325e9a3b57eSRicard Wanderlof .channels_min = 1, 1326e9a3b57eSRicard Wanderlof .channels_max = 2, 1327e9a3b57eSRicard Wanderlof .rates = ADC3XXX_RATES, 1328e9a3b57eSRicard Wanderlof .formats = ADC3XXX_FORMATS, 1329e9a3b57eSRicard Wanderlof }, 1330e9a3b57eSRicard Wanderlof .ops = &adc3xxx_dai_ops, 1331e9a3b57eSRicard Wanderlof }; 1332e9a3b57eSRicard Wanderlof 1333e9a3b57eSRicard Wanderlof static const struct snd_soc_component_driver soc_component_dev_adc3xxx = { 1334e9a3b57eSRicard Wanderlof .controls = adc3xxx_snd_controls, 1335e9a3b57eSRicard Wanderlof .num_controls = ARRAY_SIZE(adc3xxx_snd_controls), 1336e9a3b57eSRicard Wanderlof .dapm_widgets = adc3xxx_dapm_widgets, 1337e9a3b57eSRicard Wanderlof .num_dapm_widgets = ARRAY_SIZE(adc3xxx_dapm_widgets), 1338e9a3b57eSRicard Wanderlof .dapm_routes = adc3xxx_intercon, 1339e9a3b57eSRicard Wanderlof .num_dapm_routes = ARRAY_SIZE(adc3xxx_intercon), 1340f5e0084bSCharles Keepax .endianness = 1, 1341e9a3b57eSRicard Wanderlof }; 1342e9a3b57eSRicard Wanderlof 1343988e6870SStephen Kitt static const struct i2c_device_id adc3xxx_i2c_id[] = { 1344988e6870SStephen Kitt { "tlv320adc3001", ADC3001 }, 1345988e6870SStephen Kitt { "tlv320adc3101", ADC3101 }, 1346988e6870SStephen Kitt {} 1347988e6870SStephen Kitt }; 1348988e6870SStephen Kitt MODULE_DEVICE_TABLE(i2c, adc3xxx_i2c_id); 1349988e6870SStephen Kitt 1350988e6870SStephen Kitt static int adc3xxx_i2c_probe(struct i2c_client *i2c) 1351e9a3b57eSRicard Wanderlof { 1352e9a3b57eSRicard Wanderlof struct device *dev = &i2c->dev; 1353e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = NULL; 1354988e6870SStephen Kitt const struct i2c_device_id *id; 1355e9a3b57eSRicard Wanderlof int ret; 1356e9a3b57eSRicard Wanderlof 1357e9a3b57eSRicard Wanderlof adc3xxx = devm_kzalloc(dev, sizeof(struct adc3xxx), GFP_KERNEL); 1358e9a3b57eSRicard Wanderlof if (!adc3xxx) 1359e9a3b57eSRicard Wanderlof return -ENOMEM; 1360e9a3b57eSRicard Wanderlof adc3xxx->dev = dev; 1361e9a3b57eSRicard Wanderlof 1362e9a3b57eSRicard Wanderlof adc3xxx->rst_pin = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 1363e9a3b57eSRicard Wanderlof if (IS_ERR(adc3xxx->rst_pin)) { 1364e9a3b57eSRicard Wanderlof return dev_err_probe(dev, PTR_ERR(adc3xxx->rst_pin), 1365e9a3b57eSRicard Wanderlof "Failed to request rst_pin\n"); 1366e9a3b57eSRicard Wanderlof } 1367e9a3b57eSRicard Wanderlof 1368e9a3b57eSRicard Wanderlof adc3xxx->mclk = devm_clk_get(dev, NULL); 1369e9a3b57eSRicard Wanderlof if (IS_ERR(adc3xxx->mclk)) { 1370e9a3b57eSRicard Wanderlof /* 1371e9a3b57eSRicard Wanderlof * The chip itself supports running off the BCLK either 1372e9a3b57eSRicard Wanderlof * directly or via the PLL, but the driver does not (yet), so 1373e9a3b57eSRicard Wanderlof * having a specified mclk is required. Otherwise, we could 1374e9a3b57eSRicard Wanderlof * use the lack of a clocks property to indicate when BCLK is 1375e9a3b57eSRicard Wanderlof * intended as the clock source. 1376e9a3b57eSRicard Wanderlof */ 1377e9a3b57eSRicard Wanderlof return dev_err_probe(dev, PTR_ERR(adc3xxx->mclk), 1378e9a3b57eSRicard Wanderlof "Failed to acquire MCLK\n"); 1379e9a3b57eSRicard Wanderlof } else if (adc3xxx->mclk) { 1380e9a3b57eSRicard Wanderlof ret = clk_prepare_enable(adc3xxx->mclk); 1381e9a3b57eSRicard Wanderlof if (ret < 0) 1382e9a3b57eSRicard Wanderlof return ret; 1383e9a3b57eSRicard Wanderlof dev_dbg(dev, "Enabled MCLK, freq %lu Hz\n", clk_get_rate(adc3xxx->mclk)); 1384e9a3b57eSRicard Wanderlof } 1385e9a3b57eSRicard Wanderlof 1386e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmdin-gpio1", &adc3xxx->gpio_cfg[0]); 1387e9a3b57eSRicard Wanderlof if (ret < 0) 13888a2d8e4fSYang Yingliang goto err_unprepare_mclk; 1389e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmclk-gpio2", &adc3xxx->gpio_cfg[1]); 1390e9a3b57eSRicard Wanderlof if (ret < 0) 13918a2d8e4fSYang Yingliang goto err_unprepare_mclk; 1392e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_dt_micbias(adc3xxx, "ti,micbias1-vg", &adc3xxx->micbias_vg[0]); 1393e9a3b57eSRicard Wanderlof if (ret < 0) 13948a2d8e4fSYang Yingliang goto err_unprepare_mclk; 1395e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_dt_micbias(adc3xxx, "ti,micbias2-vg", &adc3xxx->micbias_vg[1]); 1396e9a3b57eSRicard Wanderlof if (ret < 0) 13978a2d8e4fSYang Yingliang goto err_unprepare_mclk; 1398e9a3b57eSRicard Wanderlof 1399e9a3b57eSRicard Wanderlof adc3xxx->regmap = devm_regmap_init_i2c(i2c, &adc3xxx_regmap); 1400e9a3b57eSRicard Wanderlof if (IS_ERR(adc3xxx->regmap)) { 1401e9a3b57eSRicard Wanderlof ret = PTR_ERR(adc3xxx->regmap); 14028a2d8e4fSYang Yingliang goto err_unprepare_mclk; 1403e9a3b57eSRicard Wanderlof } 1404e9a3b57eSRicard Wanderlof 1405e9a3b57eSRicard Wanderlof i2c_set_clientdata(i2c, adc3xxx); 1406e9a3b57eSRicard Wanderlof 1407988e6870SStephen Kitt id = i2c_match_id(adc3xxx_i2c_id, i2c); 1408e9a3b57eSRicard Wanderlof adc3xxx->type = id->driver_data; 1409e9a3b57eSRicard Wanderlof 1410e9a3b57eSRicard Wanderlof /* Reset codec chip */ 1411e9a3b57eSRicard Wanderlof gpiod_set_value_cansleep(adc3xxx->rst_pin, 1); 1412e9a3b57eSRicard Wanderlof usleep_range(2000, 100000); /* Requirement: > 10 ns (datasheet p13) */ 1413e9a3b57eSRicard Wanderlof gpiod_set_value_cansleep(adc3xxx->rst_pin, 0); 1414e9a3b57eSRicard Wanderlof 1415e9a3b57eSRicard Wanderlof /* Potentially set up pins used as GPIOs */ 1416e9a3b57eSRicard Wanderlof adc3xxx_init_gpio(adc3xxx); 1417e9a3b57eSRicard Wanderlof 1418e9a3b57eSRicard Wanderlof ret = snd_soc_register_component(dev, 1419e9a3b57eSRicard Wanderlof &soc_component_dev_adc3xxx, &adc3xxx_dai, 1); 14208a2d8e4fSYang Yingliang if (ret < 0) { 1421e9a3b57eSRicard Wanderlof dev_err(dev, "Failed to register codec: %d\n", ret); 14228a2d8e4fSYang Yingliang goto err_unprepare_mclk; 14238a2d8e4fSYang Yingliang } 1424e9a3b57eSRicard Wanderlof 14258a2d8e4fSYang Yingliang return 0; 14268a2d8e4fSYang Yingliang 14278a2d8e4fSYang Yingliang err_unprepare_mclk: 14288a2d8e4fSYang Yingliang clk_disable_unprepare(adc3xxx->mclk); 1429e9a3b57eSRicard Wanderlof return ret; 1430e9a3b57eSRicard Wanderlof } 1431e9a3b57eSRicard Wanderlof 1432ed5c2f5fSUwe Kleine-König static void __exit adc3xxx_i2c_remove(struct i2c_client *client) 1433e9a3b57eSRicard Wanderlof { 1434e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = i2c_get_clientdata(client); 1435e9a3b57eSRicard Wanderlof 1436e9a3b57eSRicard Wanderlof if (adc3xxx->mclk) 1437e9a3b57eSRicard Wanderlof clk_disable_unprepare(adc3xxx->mclk); 1438e9a3b57eSRicard Wanderlof adc3xxx_free_gpio(adc3xxx); 1439e9a3b57eSRicard Wanderlof snd_soc_unregister_component(&client->dev); 1440e9a3b57eSRicard Wanderlof } 1441e9a3b57eSRicard Wanderlof 1442e9a3b57eSRicard Wanderlof static const struct of_device_id tlv320adc3xxx_of_match[] = { 1443e9a3b57eSRicard Wanderlof { .compatible = "ti,tlv320adc3001", }, 1444e9a3b57eSRicard Wanderlof { .compatible = "ti,tlv320adc3101", }, 1445e9a3b57eSRicard Wanderlof {}, 1446e9a3b57eSRicard Wanderlof }; 1447e9a3b57eSRicard Wanderlof MODULE_DEVICE_TABLE(of, tlv320adc3xxx_of_match); 1448e9a3b57eSRicard Wanderlof 1449e9a3b57eSRicard Wanderlof static struct i2c_driver adc3xxx_i2c_driver = { 1450e9a3b57eSRicard Wanderlof .driver = { 1451e9a3b57eSRicard Wanderlof .name = "tlv320adc3xxx-codec", 1452e9a3b57eSRicard Wanderlof .of_match_table = tlv320adc3xxx_of_match, 1453e9a3b57eSRicard Wanderlof }, 1454*9abcd240SUwe Kleine-König .probe = adc3xxx_i2c_probe, 14554e8ff358SGeert Uytterhoeven .remove = __exit_p(adc3xxx_i2c_remove), 1456e9a3b57eSRicard Wanderlof .id_table = adc3xxx_i2c_id, 1457e9a3b57eSRicard Wanderlof }; 1458e9a3b57eSRicard Wanderlof 1459e9a3b57eSRicard Wanderlof module_i2c_driver(adc3xxx_i2c_driver); 1460e9a3b57eSRicard Wanderlof 1461e9a3b57eSRicard Wanderlof MODULE_DESCRIPTION("ASoC TLV320ADC3xxx codec driver"); 1462e9a3b57eSRicard Wanderlof MODULE_AUTHOR("shahina.s@mistralsolutions.com"); 1463e9a3b57eSRicard Wanderlof MODULE_LICENSE("GPL v2"); 1464