1e9a3b57eSRicard Wanderlof // SPDX-License-Identifier: GPL-2.0-only 2e9a3b57eSRicard Wanderlof // 3e9a3b57eSRicard Wanderlof // Based on sound/soc/codecs/tlv320aic3x.c by Vladimir Barinov 4e9a3b57eSRicard Wanderlof // 5e9a3b57eSRicard Wanderlof // Copyright (C) 2010 Mistral Solutions Pvt Ltd. 6e9a3b57eSRicard Wanderlof // Author: Shahina Shaik <shahina.s@mistralsolutions.com> 7e9a3b57eSRicard Wanderlof // 8e9a3b57eSRicard Wanderlof // Copyright (C) 2014-2018, Ambarella, Inc. 9e9a3b57eSRicard Wanderlof // Author: Dongge wu <dgwu@ambarella.com> 10e9a3b57eSRicard Wanderlof // 11e9a3b57eSRicard Wanderlof // Copyright (C) 2021 Axis Communications AB 12e9a3b57eSRicard Wanderlof // Author: Ricard Wanderlof <ricardw@axis.com> 13e9a3b57eSRicard Wanderlof // 14e9a3b57eSRicard Wanderlof 15e9a3b57eSRicard Wanderlof #include <dt-bindings/sound/tlv320adc3xxx.h> 16e9a3b57eSRicard Wanderlof #include <linux/clk.h> 17e9a3b57eSRicard Wanderlof #include <linux/module.h> 18e9a3b57eSRicard Wanderlof #include <linux/moduleparam.h> 19e9a3b57eSRicard Wanderlof #include <linux/io.h> 20e9a3b57eSRicard Wanderlof #include <linux/init.h> 21e9a3b57eSRicard Wanderlof #include <linux/delay.h> 22e9a3b57eSRicard Wanderlof #include <linux/gpio/driver.h> 23e9a3b57eSRicard Wanderlof #include <linux/pm.h> 24e9a3b57eSRicard Wanderlof #include <linux/i2c.h> 25e9a3b57eSRicard Wanderlof #include <linux/platform_device.h> 26e9a3b57eSRicard Wanderlof #include <linux/cdev.h> 27e9a3b57eSRicard Wanderlof #include <linux/of_gpio.h> 28e9a3b57eSRicard Wanderlof #include <linux/slab.h> 29e9a3b57eSRicard Wanderlof #include <sound/core.h> 30e9a3b57eSRicard Wanderlof #include <sound/pcm.h> 31e9a3b57eSRicard Wanderlof #include <sound/pcm_params.h> 32e9a3b57eSRicard Wanderlof #include <sound/soc.h> 33e9a3b57eSRicard Wanderlof #include <sound/soc-dapm.h> 34e9a3b57eSRicard Wanderlof #include <sound/tlv.h> 35e9a3b57eSRicard Wanderlof #include <sound/initval.h> 36e9a3b57eSRicard Wanderlof 37e9a3b57eSRicard Wanderlof /* 38e9a3b57eSRicard Wanderlof * General definitions defining exported functionality. 39e9a3b57eSRicard Wanderlof */ 40e9a3b57eSRicard Wanderlof 41e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS_PINS 2 42e9a3b57eSRicard Wanderlof 43e9a3b57eSRicard Wanderlof /* Number of GPIO pins exposed via the gpiolib interface */ 44e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIOS_MAX 2 45e9a3b57eSRicard Wanderlof 46e9a3b57eSRicard Wanderlof #define ADC3XXX_RATES SNDRV_PCM_RATE_8000_96000 47e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 48e9a3b57eSRicard Wanderlof SNDRV_PCM_FMTBIT_S20_3LE | \ 49e9a3b57eSRicard Wanderlof SNDRV_PCM_FMTBIT_S24_3LE | \ 50e9a3b57eSRicard Wanderlof SNDRV_PCM_FMTBIT_S32_LE) 51e9a3b57eSRicard Wanderlof 52e9a3b57eSRicard Wanderlof /* 53e9a3b57eSRicard Wanderlof * PLL modes, to be used for clk_id for set_sysclk callback. 54e9a3b57eSRicard Wanderlof * 55e9a3b57eSRicard Wanderlof * The default behavior (AUTO) is to take the first matching entry in the clock 56e9a3b57eSRicard Wanderlof * table, which is intended to be the PLL based one if there is more than one. 57e9a3b57eSRicard Wanderlof * 58e9a3b57eSRicard Wanderlof * Setting the clock source using simple-card (clocks or 59e9a3b57eSRicard Wanderlof * system-clock-frequency property) sets clk_id = 0 = ADC3XXX_PLL_AUTO. 60e9a3b57eSRicard Wanderlof */ 61e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_AUTO 0 /* Use first available mode */ 62e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_ENABLE 1 /* Use PLL for clock generation */ 63e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_BYPASS 2 /* Don't use PLL for clock generation */ 64e9a3b57eSRicard Wanderlof 65e9a3b57eSRicard Wanderlof /* Register definitions. */ 66e9a3b57eSRicard Wanderlof 67e9a3b57eSRicard Wanderlof #define ADC3XXX_PAGE_SIZE 128 68e9a3b57eSRicard Wanderlof #define ADC3XXX_REG(page, reg) ((page * ADC3XXX_PAGE_SIZE) + reg) 69e9a3b57eSRicard Wanderlof 70e9a3b57eSRicard Wanderlof /* 71e9a3b57eSRicard Wanderlof * Page 0 registers. 72e9a3b57eSRicard Wanderlof */ 73e9a3b57eSRicard Wanderlof 74e9a3b57eSRicard Wanderlof #define ADC3XXX_PAGE_SELECT ADC3XXX_REG(0, 0) 75e9a3b57eSRicard Wanderlof #define ADC3XXX_RESET ADC3XXX_REG(0, 1) 76e9a3b57eSRicard Wanderlof 77e9a3b57eSRicard Wanderlof /* 2-3 Reserved */ 78e9a3b57eSRicard Wanderlof 79e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKGEN_MUX ADC3XXX_REG(0, 4) 80e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PROG_PR ADC3XXX_REG(0, 5) 81e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PROG_J ADC3XXX_REG(0, 6) 82e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PROG_D_MSB ADC3XXX_REG(0, 7) 83e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PROG_D_LSB ADC3XXX_REG(0, 8) 84e9a3b57eSRicard Wanderlof 85e9a3b57eSRicard Wanderlof /* 9-17 Reserved */ 86e9a3b57eSRicard Wanderlof 87e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_NADC ADC3XXX_REG(0, 18) 88e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_MADC ADC3XXX_REG(0, 19) 89e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_AOSR ADC3XXX_REG(0, 20) 90e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_IADC ADC3XXX_REG(0, 21) 91e9a3b57eSRicard Wanderlof 92e9a3b57eSRicard Wanderlof /* 23-24 Reserved */ 93e9a3b57eSRicard Wanderlof 94e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKOUT_MUX ADC3XXX_REG(0, 25) 95e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKOUT_M_DIV ADC3XXX_REG(0, 26) 96e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_1 ADC3XXX_REG(0, 27) 97e9a3b57eSRicard Wanderlof #define ADC3XXX_CH_OFFSET_1 ADC3XXX_REG(0, 28) 98e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_2 ADC3XXX_REG(0, 29) 99e9a3b57eSRicard Wanderlof #define ADC3XXX_BCLK_N_DIV ADC3XXX_REG(0, 30) 100e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_3 ADC3XXX_REG(0, 31) 101e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_4 ADC3XXX_REG(0, 32) 102e9a3b57eSRicard Wanderlof #define ADC3XXX_INTERFACE_CTRL_5 ADC3XXX_REG(0, 33) 103e9a3b57eSRicard Wanderlof #define ADC3XXX_I2S_SYNC ADC3XXX_REG(0, 34) 104e9a3b57eSRicard Wanderlof /* 35 Reserved */ 105e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_FLAG ADC3XXX_REG(0, 36) 106e9a3b57eSRicard Wanderlof #define ADC3XXX_CH_OFFSET_2 ADC3XXX_REG(0, 37) 107e9a3b57eSRicard Wanderlof #define ADC3XXX_I2S_TDM_CTRL ADC3XXX_REG(0, 38) 108e9a3b57eSRicard Wanderlof /* 39-41 Reserved */ 109e9a3b57eSRicard Wanderlof #define ADC3XXX_INTR_FLAG_1 ADC3XXX_REG(0, 42) 110e9a3b57eSRicard Wanderlof #define ADC3XXX_INTR_FLAG_2 ADC3XXX_REG(0, 43) 111e9a3b57eSRicard Wanderlof /* 44 Reserved */ 112e9a3b57eSRicard Wanderlof #define ADC3XXX_INTR_FLAG_ADC1 ADC3XXX_REG(0, 45) 113e9a3b57eSRicard Wanderlof /* 46 Reserved */ 114e9a3b57eSRicard Wanderlof #define ADC3XXX_INTR_FLAG_ADC2 ADC3XXX_REG(0, 47) 115e9a3b57eSRicard Wanderlof #define ADC3XXX_INT1_CTRL ADC3XXX_REG(0, 48) 116e9a3b57eSRicard Wanderlof #define ADC3XXX_INT2_CTRL ADC3XXX_REG(0, 49) 117e9a3b57eSRicard Wanderlof /* 50 Reserved */ 118e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO2_CTRL ADC3XXX_REG(0, 51) 119e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO1_CTRL ADC3XXX_REG(0, 52) 120e9a3b57eSRicard Wanderlof #define ADC3XXX_DOUT_CTRL ADC3XXX_REG(0, 53) 121e9a3b57eSRicard Wanderlof /* 54-56 Reserved */ 122e9a3b57eSRicard Wanderlof #define ADC3XXX_SYNC_CTRL_1 ADC3XXX_REG(0, 57) 123e9a3b57eSRicard Wanderlof #define ADC3XXX_SYNC_CTRL_2 ADC3XXX_REG(0, 58) 124e9a3b57eSRicard Wanderlof #define ADC3XXX_CIC_GAIN_CTRL ADC3XXX_REG(0, 59) 125e9a3b57eSRicard Wanderlof /* 60 Reserved */ 126e9a3b57eSRicard Wanderlof #define ADC3XXX_PRB_SELECT ADC3XXX_REG(0, 61) 127e9a3b57eSRicard Wanderlof #define ADC3XXX_INST_MODE_CTRL ADC3XXX_REG(0, 62) 128e9a3b57eSRicard Wanderlof /* 63-79 Reserved */ 129e9a3b57eSRicard Wanderlof #define ADC3XXX_MIC_POLARITY_CTRL ADC3XXX_REG(0, 80) 130e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_DIGITAL ADC3XXX_REG(0, 81) 131e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_FGA ADC3XXX_REG(0, 82) 132e9a3b57eSRicard Wanderlof #define ADC3XXX_LADC_VOL ADC3XXX_REG(0, 83) 133e9a3b57eSRicard Wanderlof #define ADC3XXX_RADC_VOL ADC3XXX_REG(0, 84) 134e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_PHASE_COMP ADC3XXX_REG(0, 85) 135e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_1 ADC3XXX_REG(0, 86) 136e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_2 ADC3XXX_REG(0, 87) 137e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_3 ADC3XXX_REG(0, 88) 138e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_4 ADC3XXX_REG(0, 89) 139e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_5 ADC3XXX_REG(0, 90) 140e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_6 ADC3XXX_REG(0, 91) 141e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_CHN_AGC_7 ADC3XXX_REG(0, 92) 142e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_AGC_GAIN ADC3XXX_REG(0, 93) 143e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_1 ADC3XXX_REG(0, 94) 144e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_2 ADC3XXX_REG(0, 95) 145e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_3 ADC3XXX_REG(0, 96) 146e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_4 ADC3XXX_REG(0, 97) 147e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_5 ADC3XXX_REG(0, 98) 148e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_6 ADC3XXX_REG(0, 99) 149e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_CHN_AGC_7 ADC3XXX_REG(0, 100) 150e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_AGC_GAIN ADC3XXX_REG(0, 101) 151e9a3b57eSRicard Wanderlof /* 102-127 Reserved */ 152e9a3b57eSRicard Wanderlof 153e9a3b57eSRicard Wanderlof /* 154e9a3b57eSRicard Wanderlof * Page 1 registers. 155e9a3b57eSRicard Wanderlof */ 156e9a3b57eSRicard Wanderlof 157e9a3b57eSRicard Wanderlof /* 1-25 Reserved */ 158e9a3b57eSRicard Wanderlof #define ADC3XXX_DITHER_CTRL ADC3XXX_REG(1, 26) 159e9a3b57eSRicard Wanderlof /* 27-50 Reserved */ 160e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS_CTRL ADC3XXX_REG(1, 51) 161e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_PGA_SEL_1 ADC3XXX_REG(1, 52) 162e9a3b57eSRicard Wanderlof /* 53 Reserved */ 163e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_PGA_SEL_2 ADC3XXX_REG(1, 54) 164e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_PGA_SEL_1 ADC3XXX_REG(1, 55) 165e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_PGA_SEL_2 ADC3XXX_REG(1, 57) 166e9a3b57eSRicard Wanderlof #define ADC3XXX_LEFT_APGA_CTRL ADC3XXX_REG(1, 59) 167e9a3b57eSRicard Wanderlof #define ADC3XXX_RIGHT_APGA_CTRL ADC3XXX_REG(1, 60) 168e9a3b57eSRicard Wanderlof #define ADC3XXX_LOW_CURRENT_MODES ADC3XXX_REG(1, 61) 169e9a3b57eSRicard Wanderlof #define ADC3XXX_ANALOG_PGA_FLAGS ADC3XXX_REG(1, 62) 170e9a3b57eSRicard Wanderlof /* 63-127 Reserved */ 171e9a3b57eSRicard Wanderlof 172e9a3b57eSRicard Wanderlof /* 173e9a3b57eSRicard Wanderlof * Register bits. 174e9a3b57eSRicard Wanderlof */ 175e9a3b57eSRicard Wanderlof 176e9a3b57eSRicard Wanderlof /* PLL Enable bits */ 177e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_PLL_SHIFT 7 178e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_PLL (1 << ADC3XXX_ENABLE_PLL_SHIFT) 179e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_NADC_SHIFT 7 180e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_NADC (1 << ADC3XXX_ENABLE_NADC_SHIFT) 181e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_MADC_SHIFT 7 182e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_MADC (1 << ADC3XXX_ENABLE_MADC_SHIFT) 183e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_BCLK_SHIFT 7 184e9a3b57eSRicard Wanderlof #define ADC3XXX_ENABLE_BCLK (1 << ADC3XXX_ENABLE_BCLK_SHIFT) 185e9a3b57eSRicard Wanderlof 186e9a3b57eSRicard Wanderlof /* Power bits */ 187e9a3b57eSRicard Wanderlof #define ADC3XXX_LADC_PWR_ON 0x80 188e9a3b57eSRicard Wanderlof #define ADC3XXX_RADC_PWR_ON 0x40 189e9a3b57eSRicard Wanderlof 190e9a3b57eSRicard Wanderlof #define ADC3XXX_SOFT_RESET 0x01 191e9a3b57eSRicard Wanderlof #define ADC3XXX_BCLK_MASTER 0x08 192e9a3b57eSRicard Wanderlof #define ADC3XXX_WCLK_MASTER 0x04 193e9a3b57eSRicard Wanderlof 194e9a3b57eSRicard Wanderlof /* Interface register masks */ 195e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_MASK 0xc0 196e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_SHIFT 6 197e9a3b57eSRicard Wanderlof #define ADC3XXX_WLENGTH_MASK 0x30 198e9a3b57eSRicard Wanderlof #define ADC3XXX_WLENGTH_SHIFT 4 199e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKDIR_MASK 0x0c 200e9a3b57eSRicard Wanderlof #define ADC3XXX_CLKDIR_SHIFT 2 201e9a3b57eSRicard Wanderlof 202e9a3b57eSRicard Wanderlof /* Interface register bit patterns */ 203e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_I2S (0 << ADC3XXX_FORMAT_SHIFT) 204e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_DSP (1 << ADC3XXX_FORMAT_SHIFT) 205e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_RJF (2 << ADC3XXX_FORMAT_SHIFT) 206e9a3b57eSRicard Wanderlof #define ADC3XXX_FORMAT_LJF (3 << ADC3XXX_FORMAT_SHIFT) 207e9a3b57eSRicard Wanderlof 208e9a3b57eSRicard Wanderlof #define ADC3XXX_IFACE_16BITS (0 << ADC3XXX_WLENGTH_SHIFT) 209e9a3b57eSRicard Wanderlof #define ADC3XXX_IFACE_20BITS (1 << ADC3XXX_WLENGTH_SHIFT) 210e9a3b57eSRicard Wanderlof #define ADC3XXX_IFACE_24BITS (2 << ADC3XXX_WLENGTH_SHIFT) 211e9a3b57eSRicard Wanderlof #define ADC3XXX_IFACE_32BITS (3 << ADC3XXX_WLENGTH_SHIFT) 212e9a3b57eSRicard Wanderlof 213e9a3b57eSRicard Wanderlof /* PLL P/R bit offsets */ 214e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLP_SHIFT 4 215e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLR_SHIFT 0 216e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_PR_MASK 0x7f 217e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLJ_MASK 0x3f 218e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLD_MSB_MASK 0x3f 219e9a3b57eSRicard Wanderlof #define ADC3XXX_PLLD_LSB_MASK 0xff 220e9a3b57eSRicard Wanderlof #define ADC3XXX_NADC_MASK 0x7f 221e9a3b57eSRicard Wanderlof #define ADC3XXX_MADC_MASK 0x7f 222e9a3b57eSRicard Wanderlof #define ADC3XXX_AOSR_MASK 0xff 223e9a3b57eSRicard Wanderlof #define ADC3XXX_IADC_MASK 0xff 224e9a3b57eSRicard Wanderlof #define ADC3XXX_BDIV_MASK 0x7f 225e9a3b57eSRicard Wanderlof 226e9a3b57eSRicard Wanderlof /* PLL_CLKIN bits */ 227e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_CLKIN_SHIFT 2 228e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_CLKIN_MCLK 0x0 229e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_CLKIN_BCLK 0x1 230e9a3b57eSRicard Wanderlof #define ADC3XXX_PLL_CLKIN_ZERO 0x3 231e9a3b57eSRicard Wanderlof 232e9a3b57eSRicard Wanderlof /* CODEC_CLKIN bits */ 233e9a3b57eSRicard Wanderlof #define ADC3XXX_CODEC_CLKIN_SHIFT 0 234e9a3b57eSRicard Wanderlof #define ADC3XXX_CODEC_CLKIN_MCLK 0x0 235e9a3b57eSRicard Wanderlof #define ADC3XXX_CODEC_CLKIN_BCLK 0x1 236e9a3b57eSRicard Wanderlof #define ADC3XXX_CODEC_CLKIN_PLL_CLK 0x3 237e9a3b57eSRicard Wanderlof 238e9a3b57eSRicard Wanderlof #define ADC3XXX_USE_PLL ((ADC3XXX_PLL_CLKIN_MCLK << ADC3XXX_PLL_CLKIN_SHIFT) | \ 239e9a3b57eSRicard Wanderlof (ADC3XXX_CODEC_CLKIN_PLL_CLK << ADC3XXX_CODEC_CLKIN_SHIFT)) 240e9a3b57eSRicard Wanderlof #define ADC3XXX_NO_PLL ((ADC3XXX_PLL_CLKIN_ZERO << ADC3XXX_PLL_CLKIN_SHIFT) | \ 241e9a3b57eSRicard Wanderlof (ADC3XXX_CODEC_CLKIN_MCLK << ADC3XXX_CODEC_CLKIN_SHIFT)) 242e9a3b57eSRicard Wanderlof 243e9a3b57eSRicard Wanderlof /* Analog PGA control bits */ 244e9a3b57eSRicard Wanderlof #define ADC3XXX_LPGA_MUTE 0x80 245e9a3b57eSRicard Wanderlof #define ADC3XXX_RPGA_MUTE 0x80 246e9a3b57eSRicard Wanderlof 247e9a3b57eSRicard Wanderlof #define ADC3XXX_LPGA_GAIN_MASK 0x7f 248e9a3b57eSRicard Wanderlof #define ADC3XXX_RPGA_GAIN_MASK 0x7f 249e9a3b57eSRicard Wanderlof 250e9a3b57eSRicard Wanderlof /* ADC current modes */ 251e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_LOW_CURR_MODE 0x01 252e9a3b57eSRicard Wanderlof 253e9a3b57eSRicard Wanderlof /* Left ADC Input selection bits */ 254e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL1_SHIFT 0 255e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL2_SHIFT 2 256e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL3_SHIFT 4 257e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL4_SHIFT 6 258e9a3b57eSRicard Wanderlof 259e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL1X_SHIFT 0 260e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL2X_SHIFT 2 261e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_SEL3X_SHIFT 4 262e9a3b57eSRicard Wanderlof #define ADC3XXX_LCH_COMMON_MODE 0x40 263e9a3b57eSRicard Wanderlof #define ADC3XXX_BYPASS_LPGA 0x80 264e9a3b57eSRicard Wanderlof 265e9a3b57eSRicard Wanderlof /* Right ADC Input selection bits */ 266e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL1_SHIFT 0 267e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL2_SHIFT 2 268e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL3_SHIFT 4 269e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL4_SHIFT 6 270e9a3b57eSRicard Wanderlof 271e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL1X_SHIFT 0 272e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL2X_SHIFT 2 273e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_SEL3X_SHIFT 4 274e9a3b57eSRicard Wanderlof #define ADC3XXX_RCH_COMMON_MODE 0x40 275e9a3b57eSRicard Wanderlof #define ADC3XXX_BYPASS_RPGA 0x80 276e9a3b57eSRicard Wanderlof 277e9a3b57eSRicard Wanderlof /* MICBIAS control bits */ 278e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS_MASK 0x2 279e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS1_SHIFT 5 280e9a3b57eSRicard Wanderlof #define ADC3XXX_MICBIAS2_SHIFT 3 281e9a3b57eSRicard Wanderlof 282e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_MAX_VOLUME 64 283e9a3b57eSRicard Wanderlof #define ADC3XXX_ADC_POS_VOL 24 284e9a3b57eSRicard Wanderlof 285e9a3b57eSRicard Wanderlof /* GPIO control bits (GPIO1_CTRL and GPIO2_CTRL) */ 286e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_CFG_MASK 0x3c 287e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_CFG_SHIFT 2 288e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK 0x01 289e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT 0 290e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_INPUT_VALUE_MASK 0x02 291e9a3b57eSRicard Wanderlof #define ADC3XXX_GPIO_CTRL_INPUT_VALUE_SHIFT 1 292e9a3b57eSRicard Wanderlof 293e9a3b57eSRicard Wanderlof enum adc3xxx_type { 294e9a3b57eSRicard Wanderlof ADC3001 = 0, 295e9a3b57eSRicard Wanderlof ADC3101 296e9a3b57eSRicard Wanderlof }; 297e9a3b57eSRicard Wanderlof 298e9a3b57eSRicard Wanderlof struct adc3xxx { 299e9a3b57eSRicard Wanderlof struct device *dev; 300e9a3b57eSRicard Wanderlof enum adc3xxx_type type; 301e9a3b57eSRicard Wanderlof struct clk *mclk; 302e9a3b57eSRicard Wanderlof struct regmap *regmap; 303e9a3b57eSRicard Wanderlof struct gpio_desc *rst_pin; 304e9a3b57eSRicard Wanderlof unsigned int pll_mode; 305e9a3b57eSRicard Wanderlof unsigned int sysclk; 306e9a3b57eSRicard Wanderlof unsigned int gpio_cfg[ADC3XXX_GPIOS_MAX]; /* value+1 (0 => not set) */ 307e9a3b57eSRicard Wanderlof unsigned int micbias_vg[ADC3XXX_MICBIAS_PINS]; 308e9a3b57eSRicard Wanderlof int master; 309e9a3b57eSRicard Wanderlof u8 page_no; 310e9a3b57eSRicard Wanderlof int use_pll; 311e9a3b57eSRicard Wanderlof struct gpio_chip gpio_chip; 312e9a3b57eSRicard Wanderlof }; 313e9a3b57eSRicard Wanderlof 314e9a3b57eSRicard Wanderlof static const unsigned int adc3xxx_gpio_ctrl_reg[ADC3XXX_GPIOS_MAX] = { 315e9a3b57eSRicard Wanderlof ADC3XXX_GPIO1_CTRL, 316e9a3b57eSRicard Wanderlof ADC3XXX_GPIO2_CTRL 317e9a3b57eSRicard Wanderlof }; 318e9a3b57eSRicard Wanderlof 319e9a3b57eSRicard Wanderlof static const unsigned int adc3xxx_micbias_shift[ADC3XXX_MICBIAS_PINS] = { 320e9a3b57eSRicard Wanderlof ADC3XXX_MICBIAS1_SHIFT, 321e9a3b57eSRicard Wanderlof ADC3XXX_MICBIAS2_SHIFT 322e9a3b57eSRicard Wanderlof }; 323e9a3b57eSRicard Wanderlof 324e9a3b57eSRicard Wanderlof static const struct reg_default adc3xxx_defaults[] = { 325e9a3b57eSRicard Wanderlof /* Page 0 */ 326e9a3b57eSRicard Wanderlof { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x00 }, 327e9a3b57eSRicard Wanderlof { 4, 0x00 }, { 5, 0x11 }, { 6, 0x04 }, { 7, 0x00 }, 328e9a3b57eSRicard Wanderlof { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x00 }, 329e9a3b57eSRicard Wanderlof { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x00 }, 330e9a3b57eSRicard Wanderlof { 16, 0x00 }, { 17, 0x00 }, { 18, 0x01 }, { 19, 0x01 }, 331e9a3b57eSRicard Wanderlof { 20, 0x80 }, { 21, 0x80 }, { 22, 0x04 }, { 23, 0x00 }, 332e9a3b57eSRicard Wanderlof { 24, 0x00 }, { 25, 0x00 }, { 26, 0x01 }, { 27, 0x00 }, 333e9a3b57eSRicard Wanderlof { 28, 0x00 }, { 29, 0x02 }, { 30, 0x01 }, { 31, 0x00 }, 334e9a3b57eSRicard Wanderlof { 32, 0x00 }, { 33, 0x10 }, { 34, 0x00 }, { 35, 0x00 }, 335e9a3b57eSRicard Wanderlof { 36, 0x00 }, { 37, 0x00 }, { 38, 0x02 }, { 39, 0x00 }, 336e9a3b57eSRicard Wanderlof { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x00 }, 337e9a3b57eSRicard Wanderlof { 44, 0x00 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 }, 338e9a3b57eSRicard Wanderlof { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x00 }, 339e9a3b57eSRicard Wanderlof { 52, 0x00 }, { 53, 0x12 }, { 54, 0x00 }, { 55, 0x00 }, 340e9a3b57eSRicard Wanderlof { 56, 0x00 }, { 57, 0x00 }, { 58, 0x00 }, { 59, 0x44 }, 341e9a3b57eSRicard Wanderlof { 60, 0x00 }, { 61, 0x01 }, { 62, 0x00 }, { 63, 0x00 }, 342e9a3b57eSRicard Wanderlof { 64, 0x00 }, { 65, 0x00 }, { 66, 0x00 }, { 67, 0x00 }, 343e9a3b57eSRicard Wanderlof { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 }, 344e9a3b57eSRicard Wanderlof { 72, 0x00 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 }, 345e9a3b57eSRicard Wanderlof { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 }, 346e9a3b57eSRicard Wanderlof { 80, 0x00 }, { 81, 0x00 }, { 82, 0x88 }, { 83, 0x00 }, 347e9a3b57eSRicard Wanderlof { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 }, 348e9a3b57eSRicard Wanderlof { 88, 0x7f }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 }, 349e9a3b57eSRicard Wanderlof { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 }, 350e9a3b57eSRicard Wanderlof { 96, 0x7f }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 }, 351e9a3b57eSRicard Wanderlof { 100, 0x00 }, { 101, 0x00 }, { 102, 0x00 }, { 103, 0x00 }, 352e9a3b57eSRicard Wanderlof { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 }, 353e9a3b57eSRicard Wanderlof { 108, 0x00 }, { 109, 0x00 }, { 110, 0x00 }, { 111, 0x00 }, 354e9a3b57eSRicard Wanderlof { 112, 0x00 }, { 113, 0x00 }, { 114, 0x00 }, { 115, 0x00 }, 355e9a3b57eSRicard Wanderlof { 116, 0x00 }, { 117, 0x00 }, { 118, 0x00 }, { 119, 0x00 }, 356e9a3b57eSRicard Wanderlof { 120, 0x00 }, { 121, 0x00 }, { 122, 0x00 }, { 123, 0x00 }, 357e9a3b57eSRicard Wanderlof { 124, 0x00 }, { 125, 0x00 }, { 126, 0x00 }, { 127, 0x00 }, 358e9a3b57eSRicard Wanderlof 359e9a3b57eSRicard Wanderlof /* Page 1 */ 360e9a3b57eSRicard Wanderlof { 128, 0x00 }, { 129, 0x00 }, { 130, 0x00 }, { 131, 0x00 }, 361e9a3b57eSRicard Wanderlof { 132, 0x00 }, { 133, 0x00 }, { 134, 0x00 }, { 135, 0x00 }, 362e9a3b57eSRicard Wanderlof { 136, 0x00 }, { 137, 0x00 }, { 138, 0x00 }, { 139, 0x00 }, 363e9a3b57eSRicard Wanderlof { 140, 0x00 }, { 141, 0x00 }, { 142, 0x00 }, { 143, 0x00 }, 364e9a3b57eSRicard Wanderlof { 144, 0x00 }, { 145, 0x00 }, { 146, 0x00 }, { 147, 0x00 }, 365e9a3b57eSRicard Wanderlof { 148, 0x00 }, { 149, 0x00 }, { 150, 0x00 }, { 151, 0x00 }, 366e9a3b57eSRicard Wanderlof { 152, 0x00 }, { 153, 0x00 }, { 154, 0x00 }, { 155, 0x00 }, 367e9a3b57eSRicard Wanderlof { 156, 0x00 }, { 157, 0x00 }, { 158, 0x00 }, { 159, 0x00 }, 368e9a3b57eSRicard Wanderlof { 160, 0x00 }, { 161, 0x00 }, { 162, 0x00 }, { 163, 0x00 }, 369e9a3b57eSRicard Wanderlof { 164, 0x00 }, { 165, 0x00 }, { 166, 0x00 }, { 167, 0x00 }, 370e9a3b57eSRicard Wanderlof { 168, 0x00 }, { 169, 0x00 }, { 170, 0x00 }, { 171, 0x00 }, 371e9a3b57eSRicard Wanderlof { 172, 0x00 }, { 173, 0x00 }, { 174, 0x00 }, { 175, 0x00 }, 372e9a3b57eSRicard Wanderlof { 176, 0x00 }, { 177, 0x00 }, { 178, 0x00 }, { 179, 0x00 }, 373e9a3b57eSRicard Wanderlof { 180, 0xff }, { 181, 0x00 }, { 182, 0x3f }, { 183, 0xff }, 374e9a3b57eSRicard Wanderlof { 184, 0x00 }, { 185, 0x3f }, { 186, 0x00 }, { 187, 0x80 }, 375e9a3b57eSRicard Wanderlof { 188, 0x80 }, { 189, 0x00 }, { 190, 0x00 }, { 191, 0x00 }, 376e9a3b57eSRicard Wanderlof }; 377e9a3b57eSRicard Wanderlof 378e9a3b57eSRicard Wanderlof static bool adc3xxx_volatile_reg(struct device *dev, unsigned int reg) 379e9a3b57eSRicard Wanderlof { 380e9a3b57eSRicard Wanderlof switch (reg) { 381e9a3b57eSRicard Wanderlof case ADC3XXX_RESET: 382e9a3b57eSRicard Wanderlof return true; 383e9a3b57eSRicard Wanderlof default: 384e9a3b57eSRicard Wanderlof return false; 385e9a3b57eSRicard Wanderlof } 386e9a3b57eSRicard Wanderlof } 387e9a3b57eSRicard Wanderlof 388e9a3b57eSRicard Wanderlof static const struct regmap_range_cfg adc3xxx_ranges[] = { 389e9a3b57eSRicard Wanderlof { 390e9a3b57eSRicard Wanderlof .range_min = 0, 391e9a3b57eSRicard Wanderlof .range_max = 2 * ADC3XXX_PAGE_SIZE, 392e9a3b57eSRicard Wanderlof .selector_reg = ADC3XXX_PAGE_SELECT, 393e9a3b57eSRicard Wanderlof .selector_mask = 0xff, 394e9a3b57eSRicard Wanderlof .selector_shift = 0, 395e9a3b57eSRicard Wanderlof .window_start = 0, 396e9a3b57eSRicard Wanderlof .window_len = ADC3XXX_PAGE_SIZE, 397e9a3b57eSRicard Wanderlof } 398e9a3b57eSRicard Wanderlof }; 399e9a3b57eSRicard Wanderlof 400e9a3b57eSRicard Wanderlof static const struct regmap_config adc3xxx_regmap = { 401e9a3b57eSRicard Wanderlof .reg_bits = 8, 402e9a3b57eSRicard Wanderlof .val_bits = 8, 403e9a3b57eSRicard Wanderlof 404e9a3b57eSRicard Wanderlof .reg_defaults = adc3xxx_defaults, 405e9a3b57eSRicard Wanderlof .num_reg_defaults = ARRAY_SIZE(adc3xxx_defaults), 406e9a3b57eSRicard Wanderlof 407e9a3b57eSRicard Wanderlof .volatile_reg = adc3xxx_volatile_reg, 408e9a3b57eSRicard Wanderlof 409e9a3b57eSRicard Wanderlof .cache_type = REGCACHE_RBTREE, 410e9a3b57eSRicard Wanderlof 411e9a3b57eSRicard Wanderlof .ranges = adc3xxx_ranges, 412e9a3b57eSRicard Wanderlof .num_ranges = ARRAY_SIZE(adc3xxx_ranges), 413e9a3b57eSRicard Wanderlof .max_register = 2 * ADC3XXX_PAGE_SIZE, 414e9a3b57eSRicard Wanderlof }; 415e9a3b57eSRicard Wanderlof 416e9a3b57eSRicard Wanderlof struct adc3xxx_rate_divs { 417e9a3b57eSRicard Wanderlof u32 mclk; 418e9a3b57eSRicard Wanderlof u32 rate; 419e9a3b57eSRicard Wanderlof u8 pll_p; 420e9a3b57eSRicard Wanderlof u8 pll_r; 421e9a3b57eSRicard Wanderlof u8 pll_j; 422e9a3b57eSRicard Wanderlof u16 pll_d; 423e9a3b57eSRicard Wanderlof u8 nadc; 424e9a3b57eSRicard Wanderlof u8 madc; 425e9a3b57eSRicard Wanderlof u8 aosr; 426e9a3b57eSRicard Wanderlof }; 427e9a3b57eSRicard Wanderlof 428e9a3b57eSRicard Wanderlof /* 429e9a3b57eSRicard Wanderlof * PLL and Clock settings. 430e9a3b57eSRicard Wanderlof * If p member is 0, PLL is not used. 431e9a3b57eSRicard Wanderlof * The order of the entries in this table have the PLL entries before 432e9a3b57eSRicard Wanderlof * the non-PLL entries, so that the PLL modes are preferred unless 433e9a3b57eSRicard Wanderlof * the PLL mode setting says otherwise. 434e9a3b57eSRicard Wanderlof */ 435e9a3b57eSRicard Wanderlof static const struct adc3xxx_rate_divs adc3xxx_divs[] = { 436e9a3b57eSRicard Wanderlof /* mclk, rate, p, r, j, d, nadc, madc, aosr */ 437e9a3b57eSRicard Wanderlof /* 8k rate */ 438e9a3b57eSRicard Wanderlof { 12000000, 8000, 1, 1, 7, 1680, 42, 2, 128 }, 439e9a3b57eSRicard Wanderlof { 12288000, 8000, 1, 1, 7, 0000, 42, 2, 128 }, 440e9a3b57eSRicard Wanderlof /* 11.025k rate */ 441e9a3b57eSRicard Wanderlof { 12000000, 11025, 1, 1, 6, 8208, 29, 2, 128 }, 442e9a3b57eSRicard Wanderlof /* 16k rate */ 443e9a3b57eSRicard Wanderlof { 12000000, 16000, 1, 1, 7, 1680, 21, 2, 128 }, 444e9a3b57eSRicard Wanderlof { 12288000, 16000, 1, 1, 7, 0000, 21, 2, 128 }, 445e9a3b57eSRicard Wanderlof /* 22.05k rate */ 446e9a3b57eSRicard Wanderlof { 12000000, 22050, 1, 1, 7, 560, 15, 2, 128 }, 447e9a3b57eSRicard Wanderlof /* 32k rate */ 448e9a3b57eSRicard Wanderlof { 12000000, 32000, 1, 1, 8, 1920, 12, 2, 128 }, 449e9a3b57eSRicard Wanderlof { 12288000, 32000, 1, 1, 8, 0000, 12, 2, 128 }, 450e9a3b57eSRicard Wanderlof /* 44.1k rate */ 451e9a3b57eSRicard Wanderlof { 12000000, 44100, 1, 1, 7, 5264, 8, 2, 128 }, 452e9a3b57eSRicard Wanderlof /* 48k rate */ 453e9a3b57eSRicard Wanderlof { 12000000, 48000, 1, 1, 7, 1680, 7, 2, 128 }, 454e9a3b57eSRicard Wanderlof { 12288000, 48000, 1, 1, 7, 0000, 7, 2, 128 }, 455e9a3b57eSRicard Wanderlof { 24576000, 48000, 1, 1, 3, 5000, 7, 2, 128 }, /* With PLL */ 456e9a3b57eSRicard Wanderlof { 24576000, 48000, 0, 0, 0, 0000, 2, 2, 128 }, /* Without PLL */ 457e9a3b57eSRicard Wanderlof /* 88.2k rate */ 458e9a3b57eSRicard Wanderlof { 12000000, 88200, 1, 1, 7, 5264, 4, 4, 64 }, 459e9a3b57eSRicard Wanderlof /* 96k rate */ 460e9a3b57eSRicard Wanderlof { 12000000, 96000, 1, 1, 8, 1920, 4, 4, 64 }, 461e9a3b57eSRicard Wanderlof }; 462e9a3b57eSRicard Wanderlof 463e9a3b57eSRicard Wanderlof static int adc3xxx_get_divs(struct device *dev, int mclk, int rate, int pll_mode) 464e9a3b57eSRicard Wanderlof { 465e9a3b57eSRicard Wanderlof int i; 466e9a3b57eSRicard Wanderlof 467e9a3b57eSRicard Wanderlof dev_dbg(dev, "mclk = %d, rate = %d, clock mode %u\n", 468e9a3b57eSRicard Wanderlof mclk, rate, pll_mode); 469e9a3b57eSRicard Wanderlof for (i = 0; i < ARRAY_SIZE(adc3xxx_divs); i++) { 470e9a3b57eSRicard Wanderlof const struct adc3xxx_rate_divs *mode = &adc3xxx_divs[i]; 471e9a3b57eSRicard Wanderlof 472e9a3b57eSRicard Wanderlof /* Skip this entry if it doesn't fulfill the intended clock 473e9a3b57eSRicard Wanderlof * mode requirement. We consider anything besides the two 474e9a3b57eSRicard Wanderlof * modes below to be the same as ADC3XXX_PLL_AUTO. 475e9a3b57eSRicard Wanderlof */ 476e9a3b57eSRicard Wanderlof if ((pll_mode == ADC3XXX_PLL_BYPASS && mode->pll_p) || 477e9a3b57eSRicard Wanderlof (pll_mode == ADC3XXX_PLL_ENABLE && !mode->pll_p)) 478e9a3b57eSRicard Wanderlof continue; 479e9a3b57eSRicard Wanderlof 480e9a3b57eSRicard Wanderlof if (mode->rate == rate && mode->mclk == mclk) 481e9a3b57eSRicard Wanderlof return i; 482e9a3b57eSRicard Wanderlof } 483e9a3b57eSRicard Wanderlof 484e9a3b57eSRicard Wanderlof dev_info(dev, "Master clock rate %d and sample rate %d is not supported\n", 485e9a3b57eSRicard Wanderlof mclk, rate); 486e9a3b57eSRicard Wanderlof return -EINVAL; 487e9a3b57eSRicard Wanderlof } 488e9a3b57eSRicard Wanderlof 489e9a3b57eSRicard Wanderlof static int adc3xxx_pll_delay(struct snd_soc_dapm_widget *w, 490e9a3b57eSRicard Wanderlof struct snd_kcontrol *kcontrol, int event) 491e9a3b57eSRicard Wanderlof { 492e9a3b57eSRicard Wanderlof /* 10msec delay needed after PLL power-up to allow 493e9a3b57eSRicard Wanderlof * PLL and dividers to stabilize (datasheet p13). 494e9a3b57eSRicard Wanderlof */ 495e9a3b57eSRicard Wanderlof usleep_range(10000, 20000); 496e9a3b57eSRicard Wanderlof 497e9a3b57eSRicard Wanderlof return 0; 498e9a3b57eSRicard Wanderlof } 499e9a3b57eSRicard Wanderlof 500e9a3b57eSRicard Wanderlof static const char * const adc_softstepping_text[] = { "1 step", "2 step", "off" }; 501e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(adc_softstepping_enum, ADC3XXX_ADC_DIGITAL, 0, 502e9a3b57eSRicard Wanderlof adc_softstepping_text); 503e9a3b57eSRicard Wanderlof 504e9a3b57eSRicard Wanderlof static const char * const multiplier_text[] = { "1", "2", "4", "8", "16", "32", "64", "128" }; 505e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(left_agc_attack_mult_enum, 506e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_CHN_AGC_4, 0, multiplier_text); 507e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(right_agc_attack_mult_enum, 508e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_4, 0, multiplier_text); 509e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(left_agc_decay_mult_enum, 510e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_CHN_AGC_5, 0, multiplier_text); 511e9a3b57eSRicard Wanderlof static SOC_ENUM_SINGLE_DECL(right_agc_decay_mult_enum, 512e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_5, 0, multiplier_text); 513e9a3b57eSRicard Wanderlof 514e9a3b57eSRicard Wanderlof static const char * const dither_dc_offset_text[] = { 515e9a3b57eSRicard Wanderlof "0mV", "15mV", "30mV", "45mV", "60mV", "75mV", "90mV", "105mV", 516e9a3b57eSRicard Wanderlof "-15mV", "-30mV", "-45mV", "-60mV", "-75mV", "-90mV", "-105mV" 517e9a3b57eSRicard Wanderlof }; 518e9a3b57eSRicard Wanderlof static const unsigned int dither_dc_offset_values[] = { 519e9a3b57eSRicard Wanderlof 0, 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15 520e9a3b57eSRicard Wanderlof }; 521e9a3b57eSRicard Wanderlof static SOC_VALUE_ENUM_DOUBLE_DECL(dither_dc_offset_enum, 522e9a3b57eSRicard Wanderlof ADC3XXX_DITHER_CTRL, 523e9a3b57eSRicard Wanderlof 4, 0, 0xf, dither_dc_offset_text, 524e9a3b57eSRicard Wanderlof dither_dc_offset_values); 525e9a3b57eSRicard Wanderlof 526e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 50, 0); 527e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0); 528e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0); 529e9a3b57eSRicard Wanderlof /* AGC target: 8 values: -5.5, -8, -10, -12, -14, -17, -20, -24 dB */ 530e9a3b57eSRicard Wanderlof /* It would be nice to declare these in the order above, but empirically 531e9a3b57eSRicard Wanderlof * TLV_DB_SCALE_ITEM doesn't take lightly to the increment (second) parameter 532e9a3b57eSRicard Wanderlof * being negative, despite there being examples to the contrary in other 533e9a3b57eSRicard Wanderlof * drivers. So declare these in the order from lowest to highest, and 534e9a3b57eSRicard Wanderlof * set the invert flag in the SOC_DOUBLE_R_TLV declaration instead. 535e9a3b57eSRicard Wanderlof */ 536e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_RANGE(agc_target_tlv, 537e9a3b57eSRicard Wanderlof 0, 0, TLV_DB_SCALE_ITEM(-2400, 0, 0), 538e9a3b57eSRicard Wanderlof 1, 3, TLV_DB_SCALE_ITEM(-2000, 300, 0), 539e9a3b57eSRicard Wanderlof 4, 6, TLV_DB_SCALE_ITEM(-1200, 200, 0), 540e9a3b57eSRicard Wanderlof 7, 7, TLV_DB_SCALE_ITEM(-550, 0, 0)); 541e9a3b57eSRicard Wanderlof /* Since the 'disabled' value (mute) is at the highest value in the dB 542e9a3b57eSRicard Wanderlof * range (i.e. just before -32 dB) rather than the lowest, we need to resort 543e9a3b57eSRicard Wanderlof * to using a TLV_DB_RANGE in order to get the mute value in the right place. 544e9a3b57eSRicard Wanderlof */ 545e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_RANGE(agc_thresh_tlv, 546e9a3b57eSRicard Wanderlof 0, 30, TLV_DB_SCALE_ITEM(-9000, 200, 0), 547e9a3b57eSRicard Wanderlof 31, 31, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */ 548e9a3b57eSRicard Wanderlof /* AGC hysteresis: 4 values: 1, 2, 4 dB, disabled (= mute) */ 549e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_RANGE(agc_hysteresis_tlv, 550e9a3b57eSRicard Wanderlof 0, 1, TLV_DB_SCALE_ITEM(100, 100, 0), 551e9a3b57eSRicard Wanderlof 2, 2, TLV_DB_SCALE_ITEM(400, 0, 0), 552e9a3b57eSRicard Wanderlof 3, 3, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */ 553e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(agc_max_tlv, 0, 50, 0); 554e9a3b57eSRicard Wanderlof /* Input attenuation: -6 dB or 0 dB */ 555e9a3b57eSRicard Wanderlof static const DECLARE_TLV_DB_SCALE(input_attenuation_tlv, -600, 600, 0); 556e9a3b57eSRicard Wanderlof 557e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new adc3xxx_snd_controls[] = { 558e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("PGA Capture Volume", ADC3XXX_LEFT_APGA_CTRL, 559e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_APGA_CTRL, 0, 80, 0, pga_tlv), 560e9a3b57eSRicard Wanderlof SOC_DOUBLE("PGA Capture Switch", ADC3XXX_ADC_FGA, 7, 3, 1, 1), 561e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Capture Switch", ADC3XXX_LEFT_CHN_AGC_1, 562e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_1, 7, 1, 0), 563e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("AGC Target Level Capture Volume", ADC3XXX_LEFT_CHN_AGC_1, 564e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_2, 4, 0x07, 1, agc_target_tlv), 565e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("AGC Noise Threshold Capture Volume", ADC3XXX_LEFT_CHN_AGC_2, 566e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_2, 1, 0x1f, 1, agc_thresh_tlv), 567e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("AGC Hysteresis Capture Volume", ADC3XXX_LEFT_CHN_AGC_2, 568e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_2, 6, 3, 0, agc_hysteresis_tlv), 569e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Clip Stepping Capture Switch", ADC3XXX_LEFT_CHN_AGC_2, 570e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_2, 0, 1, 0), 571e9a3b57eSRicard Wanderlof /* 572e9a3b57eSRicard Wanderlof * Oddly enough, the data sheet says the default value 573e9a3b57eSRicard Wanderlof * for the left/right AGC maximum gain register field 574e9a3b57eSRicard Wanderlof * (ADC3XXX_LEFT/RIGHT_CHN_AGC_3 bits 0..6) is 0x7f = 127 575e9a3b57eSRicard Wanderlof * (verified empirically) even though this value (indeed, above 576e9a3b57eSRicard Wanderlof * 0x50) is specified as 'Reserved. Do not use.' in the accompanying 577e9a3b57eSRicard Wanderlof * table in the data sheet. 578e9a3b57eSRicard Wanderlof */ 579e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_TLV("AGC Maximum Capture Volume", ADC3XXX_LEFT_CHN_AGC_3, 580e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_3, 0, 0x50, 0, agc_max_tlv), 581e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Attack Time", ADC3XXX_LEFT_CHN_AGC_4, 582e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_4, 3, 0x1f, 0), 583e9a3b57eSRicard Wanderlof /* Would like to have the multipliers as LR pairs, but there is 584e9a3b57eSRicard Wanderlof * no SOC_ENUM_foo which accepts two values in separate registers. 585e9a3b57eSRicard Wanderlof */ 586e9a3b57eSRicard Wanderlof SOC_ENUM("AGC Left Attack Time Multiplier", left_agc_attack_mult_enum), 587e9a3b57eSRicard Wanderlof SOC_ENUM("AGC Right Attack Time Multiplier", right_agc_attack_mult_enum), 588e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Decay Time", ADC3XXX_LEFT_CHN_AGC_5, 589e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_5, 3, 0x1f, 0), 590e9a3b57eSRicard Wanderlof SOC_ENUM("AGC Left Decay Time Multiplier", left_agc_decay_mult_enum), 591e9a3b57eSRicard Wanderlof SOC_ENUM("AGC Right Decay Time Multiplier", right_agc_decay_mult_enum), 592e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Noise Debounce", ADC3XXX_LEFT_CHN_AGC_6, 593e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_6, 0, 0x1f, 0), 594e9a3b57eSRicard Wanderlof SOC_DOUBLE_R("AGC Signal Debounce", ADC3XXX_LEFT_CHN_AGC_7, 595e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_CHN_AGC_7, 0, 0x0f, 0), 596e9a3b57eSRicard Wanderlof /* Read only register */ 597e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_S_TLV("AGC Applied Capture Volume", ADC3XXX_LEFT_AGC_GAIN, 598e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_AGC_GAIN, 0, -24, 40, 6, 0, adc_tlv), 599e9a3b57eSRicard Wanderlof /* ADC soft stepping */ 600e9a3b57eSRicard Wanderlof SOC_ENUM("ADC Soft Stepping", adc_softstepping_enum), 601e9a3b57eSRicard Wanderlof /* Left/Right Input attenuation */ 602e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input IN_1L Capture Volume", 603e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv), 604e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input IN_2L Capture Volume", 605e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv), 606e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input IN_3L Capture Volume", 607e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv), 608e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input IN_1R Capture Volume", 609e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv), 610e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input DIF_2L_3L Capture Volume", 611e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv), 612e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input DIF_1L_1R Capture Volume", 613e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv), 614e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Left Input DIF_2R_3R Capture Volume", 615e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv), 616e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input IN_1R Capture Volume", 617e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv), 618e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input IN_2R Capture Volume", 619e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv), 620e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input IN_3R Capture Volume", 621e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv), 622e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input IN_1L Capture Volume", 623e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv), 624e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input DIF_2R_3R Capture Volume", 625e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv), 626e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input DIF_1L_1R Capture Volume", 627e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv), 628e9a3b57eSRicard Wanderlof SOC_SINGLE_TLV("Right Input DIF_2L_3L Capture Volume", 629e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv), 630e9a3b57eSRicard Wanderlof SOC_DOUBLE_R_S_TLV("ADC Volume Control Capture Volume", ADC3XXX_LADC_VOL, 631e9a3b57eSRicard Wanderlof ADC3XXX_RADC_VOL, 0, -24, 40, 6, 0, adc_tlv), 632e9a3b57eSRicard Wanderlof /* Empirically, the following doesn't work the way it's supposed 633e9a3b57eSRicard Wanderlof * to. Values 0, -0.1, -0.2 and -0.3 dB result in the same level, and 634e9a3b57eSRicard Wanderlof * -0.4 dB drops about 0.12 dB on a specific chip. 635e9a3b57eSRicard Wanderlof */ 636e9a3b57eSRicard Wanderlof SOC_DOUBLE_TLV("ADC Fine Volume Control Capture Volume", ADC3XXX_ADC_FGA, 637e9a3b57eSRicard Wanderlof 4, 0, 4, 1, adc_fine_tlv), 638e9a3b57eSRicard Wanderlof SOC_SINGLE("Left ADC Unselected CM Bias Capture Switch", 639e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 6, 1, 0), 640e9a3b57eSRicard Wanderlof SOC_SINGLE("Right ADC Unselected CM Bias Capture Switch", 641e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 6, 1, 0), 642e9a3b57eSRicard Wanderlof SOC_ENUM("Dither Control DC Offset", dither_dc_offset_enum), 643e9a3b57eSRicard Wanderlof }; 644e9a3b57eSRicard Wanderlof 645e9a3b57eSRicard Wanderlof /* Left input selection, Single Ended inputs and Differential inputs */ 646e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new left_input_mixer_controls[] = { 647e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_1L Capture Switch", 648e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 1, 0x1, 1), 649e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_2L Capture Switch", 650e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 3, 0x1, 1), 651e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_3L Capture Switch", 652e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 5, 0x1, 1), 653e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch", 654e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_1, 7, 0x1, 1), 655e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch", 656e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 5, 0x1, 1), 657e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch", 658e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 3, 0x1, 1), 659e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_1R Capture Switch", 660e9a3b57eSRicard Wanderlof ADC3XXX_LEFT_PGA_SEL_2, 1, 0x1, 1), 661e9a3b57eSRicard Wanderlof }; 662e9a3b57eSRicard Wanderlof 663e9a3b57eSRicard Wanderlof /* Right input selection, Single Ended inputs and Differential inputs */ 664e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new right_input_mixer_controls[] = { 665e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_1R Capture Switch", 666e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 1, 0x1, 1), 667e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_2R Capture Switch", 668e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 3, 0x1, 1), 669e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_3R Capture Switch", 670e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 5, 0x1, 1), 671e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch", 672e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_1, 7, 0x1, 1), 673e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch", 674e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 5, 0x1, 1), 675e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch", 676e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 3, 0x1, 1), 677e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("IN_1L Capture Switch", 678e9a3b57eSRicard Wanderlof ADC3XXX_RIGHT_PGA_SEL_2, 1, 0x1, 1), 679e9a3b57eSRicard Wanderlof }; 680e9a3b57eSRicard Wanderlof 681e9a3b57eSRicard Wanderlof /* Left Digital Mic input for left ADC */ 682e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new left_input_dmic_controls[] = { 683e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("Left ADC Capture Switch", 684e9a3b57eSRicard Wanderlof ADC3XXX_ADC_DIGITAL, 3, 0x1, 0), 685e9a3b57eSRicard Wanderlof }; 686e9a3b57eSRicard Wanderlof 687e9a3b57eSRicard Wanderlof /* Right Digital Mic input for Right ADC */ 688e9a3b57eSRicard Wanderlof static const struct snd_kcontrol_new right_input_dmic_controls[] = { 689e9a3b57eSRicard Wanderlof SOC_DAPM_SINGLE("Right ADC Capture Switch", 690e9a3b57eSRicard Wanderlof ADC3XXX_ADC_DIGITAL, 2, 0x1, 0), 691e9a3b57eSRicard Wanderlof }; 692e9a3b57eSRicard Wanderlof 693e9a3b57eSRicard Wanderlof /* DAPM widgets */ 694e9a3b57eSRicard Wanderlof static const struct snd_soc_dapm_widget adc3xxx_dapm_widgets[] = { 695e9a3b57eSRicard Wanderlof 696e9a3b57eSRicard Wanderlof /* Left Input Selection */ 697e9a3b57eSRicard Wanderlof SND_SOC_DAPM_MIXER("Left Input", SND_SOC_NOPM, 0, 0, 698e9a3b57eSRicard Wanderlof &left_input_mixer_controls[0], 699e9a3b57eSRicard Wanderlof ARRAY_SIZE(left_input_mixer_controls)), 700e9a3b57eSRicard Wanderlof /* Right Input Selection */ 701e9a3b57eSRicard Wanderlof SND_SOC_DAPM_MIXER("Right Input", SND_SOC_NOPM, 0, 0, 702e9a3b57eSRicard Wanderlof &right_input_mixer_controls[0], 703e9a3b57eSRicard Wanderlof ARRAY_SIZE(right_input_mixer_controls)), 704e9a3b57eSRicard Wanderlof /* PGA selection */ 705e9a3b57eSRicard Wanderlof SND_SOC_DAPM_PGA("Left PGA", ADC3XXX_LEFT_APGA_CTRL, 7, 1, NULL, 0), 706e9a3b57eSRicard Wanderlof SND_SOC_DAPM_PGA("Right PGA", ADC3XXX_RIGHT_APGA_CTRL, 7, 1, NULL, 0), 707e9a3b57eSRicard Wanderlof 708e9a3b57eSRicard Wanderlof /* Digital Microphone Input Control for Left/Right ADC */ 709e9a3b57eSRicard Wanderlof SND_SOC_DAPM_MIXER("Left DMic Input", SND_SOC_NOPM, 0, 0, 710e9a3b57eSRicard Wanderlof &left_input_dmic_controls[0], 711e9a3b57eSRicard Wanderlof ARRAY_SIZE(left_input_dmic_controls)), 712e9a3b57eSRicard Wanderlof SND_SOC_DAPM_MIXER("Right DMic Input", SND_SOC_NOPM, 0, 0, 713e9a3b57eSRicard Wanderlof &right_input_dmic_controls[0], 714e9a3b57eSRicard Wanderlof ARRAY_SIZE(right_input_dmic_controls)), 715e9a3b57eSRicard Wanderlof 716e9a3b57eSRicard Wanderlof /* Left/Right ADC */ 717e9a3b57eSRicard Wanderlof SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ADC3XXX_ADC_DIGITAL, 7, 0), 718e9a3b57eSRicard Wanderlof SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ADC3XXX_ADC_DIGITAL, 6, 0), 719e9a3b57eSRicard Wanderlof 720e9a3b57eSRicard Wanderlof /* Inputs */ 721e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_1L"), 722e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_1R"), 723e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_2L"), 724e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_2R"), 725e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_3L"), 726e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("IN_3R"), 727e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFL_1L_1R"), 728e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFL_2L_3L"), 729e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFL_2R_3R"), 730e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFR_1L_1R"), 731e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFR_2L_3L"), 732e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DIFR_2R_3R"), 733e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DMic_L"), 734e9a3b57eSRicard Wanderlof SND_SOC_DAPM_INPUT("DMic_R"), 735e9a3b57eSRicard Wanderlof 736e9a3b57eSRicard Wanderlof /* Digital audio interface output */ 737e9a3b57eSRicard Wanderlof SND_SOC_DAPM_AIF_OUT("AIF_OUT", "Capture", 0, SND_SOC_NOPM, 0, 0), 738e9a3b57eSRicard Wanderlof 739e9a3b57eSRicard Wanderlof /* Clocks */ 740e9a3b57eSRicard Wanderlof SND_SOC_DAPM_SUPPLY("PLL_CLK", ADC3XXX_PLL_PROG_PR, ADC3XXX_ENABLE_PLL_SHIFT, 741e9a3b57eSRicard Wanderlof 0, adc3xxx_pll_delay, SND_SOC_DAPM_POST_PMU), 742e9a3b57eSRicard Wanderlof 743e9a3b57eSRicard Wanderlof SND_SOC_DAPM_SUPPLY("ADC_CLK", ADC3XXX_ADC_NADC, ADC3XXX_ENABLE_NADC_SHIFT, 744e9a3b57eSRicard Wanderlof 0, NULL, 0), 745e9a3b57eSRicard Wanderlof SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK", ADC3XXX_ADC_MADC, ADC3XXX_ENABLE_MADC_SHIFT, 746e9a3b57eSRicard Wanderlof 0, NULL, 0), 747e9a3b57eSRicard Wanderlof 748e9a3b57eSRicard Wanderlof /* This refers to the generated BCLK in master mode. */ 749e9a3b57eSRicard Wanderlof SND_SOC_DAPM_SUPPLY("BCLK", ADC3XXX_BCLK_N_DIV, ADC3XXX_ENABLE_BCLK_SHIFT, 750e9a3b57eSRicard Wanderlof 0, NULL, 0), 751e9a3b57eSRicard Wanderlof }; 752e9a3b57eSRicard Wanderlof 753e9a3b57eSRicard Wanderlof static const struct snd_soc_dapm_route adc3xxx_intercon[] = { 754e9a3b57eSRicard Wanderlof /* Left input selection from switches */ 755e9a3b57eSRicard Wanderlof { "Left Input", "IN_1L Capture Switch", "IN_1L" }, 756e9a3b57eSRicard Wanderlof { "Left Input", "IN_2L Capture Switch", "IN_2L" }, 757e9a3b57eSRicard Wanderlof { "Left Input", "IN_3L Capture Switch", "IN_3L" }, 758e9a3b57eSRicard Wanderlof { "Left Input", "DIF_2L_3L Capture Switch", "DIFL_2L_3L" }, 759e9a3b57eSRicard Wanderlof { "Left Input", "DIF_1L_1R Capture Switch", "DIFL_1L_1R" }, 760e9a3b57eSRicard Wanderlof { "Left Input", "DIF_2R_3R Capture Switch", "DIFL_2R_3R" }, 761e9a3b57eSRicard Wanderlof { "Left Input", "IN_1R Capture Switch", "IN_1R" }, 762e9a3b57eSRicard Wanderlof 763e9a3b57eSRicard Wanderlof /* Left input selection to left PGA */ 764e9a3b57eSRicard Wanderlof { "Left PGA", NULL, "Left Input" }, 765e9a3b57eSRicard Wanderlof 766e9a3b57eSRicard Wanderlof /* Left PGA to left ADC */ 767e9a3b57eSRicard Wanderlof { "Left ADC", NULL, "Left PGA" }, 768e9a3b57eSRicard Wanderlof 769e9a3b57eSRicard Wanderlof /* Right input selection from switches */ 770e9a3b57eSRicard Wanderlof { "Right Input", "IN_1R Capture Switch", "IN_1R" }, 771e9a3b57eSRicard Wanderlof { "Right Input", "IN_2R Capture Switch", "IN_2R" }, 772e9a3b57eSRicard Wanderlof { "Right Input", "IN_3R Capture Switch", "IN_3R" }, 773e9a3b57eSRicard Wanderlof { "Right Input", "DIF_2R_3R Capture Switch", "DIFR_2R_3R" }, 774e9a3b57eSRicard Wanderlof { "Right Input", "DIF_1L_1R Capture Switch", "DIFR_1L_1R" }, 775e9a3b57eSRicard Wanderlof { "Right Input", "DIF_2L_3L Capture Switch", "DIFR_2L_3L" }, 776e9a3b57eSRicard Wanderlof { "Right Input", "IN_1L Capture Switch", "IN_1L" }, 777e9a3b57eSRicard Wanderlof 778e9a3b57eSRicard Wanderlof /* Right input selection to right PGA */ 779e9a3b57eSRicard Wanderlof { "Right PGA", NULL, "Right Input" }, 780e9a3b57eSRicard Wanderlof 781e9a3b57eSRicard Wanderlof /* Right PGA to right ADC */ 782e9a3b57eSRicard Wanderlof { "Right ADC", NULL, "Right PGA" }, 783e9a3b57eSRicard Wanderlof 784e9a3b57eSRicard Wanderlof /* Left DMic Input selection from switch */ 785e9a3b57eSRicard Wanderlof { "Left DMic Input", "Left ADC Capture Switch", "DMic_L" }, 786e9a3b57eSRicard Wanderlof 787e9a3b57eSRicard Wanderlof /* Left DMic to left ADC */ 788e9a3b57eSRicard Wanderlof { "Left ADC", NULL, "Left DMic Input" }, 789e9a3b57eSRicard Wanderlof 790e9a3b57eSRicard Wanderlof /* Right DMic Input selection from switch */ 791e9a3b57eSRicard Wanderlof { "Right DMic Input", "Right ADC Capture Switch", "DMic_R" }, 792e9a3b57eSRicard Wanderlof 793e9a3b57eSRicard Wanderlof /* Right DMic to right ADC */ 794e9a3b57eSRicard Wanderlof { "Right ADC", NULL, "Right DMic Input" }, 795e9a3b57eSRicard Wanderlof 796e9a3b57eSRicard Wanderlof /* ADC to AIF output */ 797e9a3b57eSRicard Wanderlof { "AIF_OUT", NULL, "Left ADC" }, 798e9a3b57eSRicard Wanderlof { "AIF_OUT", NULL, "Right ADC" }, 799e9a3b57eSRicard Wanderlof 800e9a3b57eSRicard Wanderlof /* Clocking */ 801e9a3b57eSRicard Wanderlof { "ADC_MOD_CLK", NULL, "ADC_CLK" }, 802e9a3b57eSRicard Wanderlof { "Left ADC", NULL, "ADC_MOD_CLK" }, 803e9a3b57eSRicard Wanderlof { "Right ADC", NULL, "ADC_MOD_CLK" }, 804e9a3b57eSRicard Wanderlof 805e9a3b57eSRicard Wanderlof { "BCLK", NULL, "ADC_CLK" }, 806e9a3b57eSRicard Wanderlof }; 807e9a3b57eSRicard Wanderlof 808e9a3b57eSRicard Wanderlof static const struct snd_soc_dapm_route adc3xxx_pll_intercon[] = { 809e9a3b57eSRicard Wanderlof { "ADC_CLK", NULL, "PLL_CLK" }, 810e9a3b57eSRicard Wanderlof }; 811e9a3b57eSRicard Wanderlof 812e9a3b57eSRicard Wanderlof static const struct snd_soc_dapm_route adc3xxx_bclk_out_intercon[] = { 813e9a3b57eSRicard Wanderlof { "AIF_OUT", NULL, "BCLK" } 814e9a3b57eSRicard Wanderlof }; 815e9a3b57eSRicard Wanderlof 816e9a3b57eSRicard Wanderlof static int adc3xxx_gpio_request(struct gpio_chip *chip, unsigned int offset) 817e9a3b57eSRicard Wanderlof { 818e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = gpiochip_get_data(chip); 819e9a3b57eSRicard Wanderlof 820e9a3b57eSRicard Wanderlof if (offset >= ADC3XXX_GPIOS_MAX) 821e9a3b57eSRicard Wanderlof return -EINVAL; 822e9a3b57eSRicard Wanderlof 823e9a3b57eSRicard Wanderlof /* GPIO1 is offset 0, GPIO2 is offset 1 */ 824e9a3b57eSRicard Wanderlof /* We check here that the GPIO pins are either not configured in the 825e9a3b57eSRicard Wanderlof * DT, or that they purposely are set as outputs. 826e9a3b57eSRicard Wanderlof * (Input mode not yet implemented). 827e9a3b57eSRicard Wanderlof */ 828e9a3b57eSRicard Wanderlof if (adc3xxx->gpio_cfg[offset] != 0 && 829e9a3b57eSRicard Wanderlof adc3xxx->gpio_cfg[offset] != ADC3XXX_GPIO_GPO + 1) 830e9a3b57eSRicard Wanderlof return -EINVAL; 831e9a3b57eSRicard Wanderlof 832e9a3b57eSRicard Wanderlof return 0; 833e9a3b57eSRicard Wanderlof } 834e9a3b57eSRicard Wanderlof 835e9a3b57eSRicard Wanderlof static int adc3xxx_gpio_direction_out(struct gpio_chip *chip, 836e9a3b57eSRicard Wanderlof unsigned int offset, int value) 837e9a3b57eSRicard Wanderlof { 838e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = gpiochip_get_data(chip); 839e9a3b57eSRicard Wanderlof 840e9a3b57eSRicard Wanderlof /* Set GPIO output function. */ 841e9a3b57eSRicard Wanderlof return regmap_update_bits(adc3xxx->regmap, 842e9a3b57eSRicard Wanderlof adc3xxx_gpio_ctrl_reg[offset], 843e9a3b57eSRicard Wanderlof ADC3XXX_GPIO_CTRL_CFG_MASK | 844e9a3b57eSRicard Wanderlof ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK, 845e9a3b57eSRicard Wanderlof ADC3XXX_GPIO_GPO << ADC3XXX_GPIO_CTRL_CFG_SHIFT | 846e9a3b57eSRicard Wanderlof !!value << ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT); 847e9a3b57eSRicard Wanderlof } 848e9a3b57eSRicard Wanderlof 849e9a3b57eSRicard Wanderlof /* With only GPIO outputs configured, we never get the .direction_out call, 850e9a3b57eSRicard Wanderlof * so we set the output mode and output value in the same call. Hence 851e9a3b57eSRicard Wanderlof * .set in practice does the same thing as .direction_out . 852e9a3b57eSRicard Wanderlof */ 853e9a3b57eSRicard Wanderlof static void adc3xxx_gpio_set(struct gpio_chip *chip, unsigned int offset, 854e9a3b57eSRicard Wanderlof int value) 855e9a3b57eSRicard Wanderlof { 856e9a3b57eSRicard Wanderlof (void) adc3xxx_gpio_direction_out(chip, offset, value); 857e9a3b57eSRicard Wanderlof } 858e9a3b57eSRicard Wanderlof 859e9a3b57eSRicard Wanderlof /* Even though we only support GPIO output for now, some GPIO clients 860e9a3b57eSRicard Wanderlof * want to read the current pin state using the .get callback. 861e9a3b57eSRicard Wanderlof */ 862e9a3b57eSRicard Wanderlof static int adc3xxx_gpio_get(struct gpio_chip *chip, unsigned int offset) 863e9a3b57eSRicard Wanderlof { 864e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = gpiochip_get_data(chip); 865e9a3b57eSRicard Wanderlof unsigned int regval; 866e9a3b57eSRicard Wanderlof int ret; 867e9a3b57eSRicard Wanderlof 868e9a3b57eSRicard Wanderlof /* We only allow output pins, so just read the value set in the output 869e9a3b57eSRicard Wanderlof * pin register field. 870e9a3b57eSRicard Wanderlof */ 871e9a3b57eSRicard Wanderlof ret = regmap_read(adc3xxx->regmap, adc3xxx_gpio_ctrl_reg[offset], ®val); 872e9a3b57eSRicard Wanderlof if (ret) 873e9a3b57eSRicard Wanderlof return ret; 874e9a3b57eSRicard Wanderlof return !!(regval & ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK); 875e9a3b57eSRicard Wanderlof } 876e9a3b57eSRicard Wanderlof 877e9a3b57eSRicard Wanderlof static const struct gpio_chip adc3xxx_gpio_chip = { 878e9a3b57eSRicard Wanderlof .label = "adc3xxx", 879e9a3b57eSRicard Wanderlof .owner = THIS_MODULE, 880e9a3b57eSRicard Wanderlof .request = adc3xxx_gpio_request, 881e9a3b57eSRicard Wanderlof .direction_output = adc3xxx_gpio_direction_out, 882e9a3b57eSRicard Wanderlof .set = adc3xxx_gpio_set, 883e9a3b57eSRicard Wanderlof .get = adc3xxx_gpio_get, 884e9a3b57eSRicard Wanderlof .can_sleep = 1, 885e9a3b57eSRicard Wanderlof }; 886e9a3b57eSRicard Wanderlof 887e9a3b57eSRicard Wanderlof static void adc3xxx_free_gpio(struct adc3xxx *adc3xxx) 888e9a3b57eSRicard Wanderlof { 889e9a3b57eSRicard Wanderlof gpiochip_remove(&adc3xxx->gpio_chip); 890e9a3b57eSRicard Wanderlof } 891e9a3b57eSRicard Wanderlof 892e9a3b57eSRicard Wanderlof static void adc3xxx_init_gpio(struct adc3xxx *adc3xxx) 893e9a3b57eSRicard Wanderlof { 894e9a3b57eSRicard Wanderlof int gpio, micbias; 895e9a3b57eSRicard Wanderlof int ret; 896e9a3b57eSRicard Wanderlof 897e9a3b57eSRicard Wanderlof adc3xxx->gpio_chip = adc3xxx_gpio_chip; 898e9a3b57eSRicard Wanderlof adc3xxx->gpio_chip.ngpio = ADC3XXX_GPIOS_MAX; 899e9a3b57eSRicard Wanderlof adc3xxx->gpio_chip.parent = adc3xxx->dev; 900e9a3b57eSRicard Wanderlof adc3xxx->gpio_chip.base = -1; 901e9a3b57eSRicard Wanderlof 902e9a3b57eSRicard Wanderlof ret = gpiochip_add_data(&adc3xxx->gpio_chip, adc3xxx); 903e9a3b57eSRicard Wanderlof if (ret) 904e9a3b57eSRicard Wanderlof dev_err(adc3xxx->dev, "Failed to add gpios: %d\n", ret); 905e9a3b57eSRicard Wanderlof 906e9a3b57eSRicard Wanderlof /* Set up potential GPIO configuration from the devicetree. 907e9a3b57eSRicard Wanderlof * This allows us to set up things which are not software 908e9a3b57eSRicard Wanderlof * controllable GPIOs, such as PDM microphone I/O, 909e9a3b57eSRicard Wanderlof */ 910e9a3b57eSRicard Wanderlof for (gpio = 0; gpio < ADC3XXX_GPIOS_MAX; gpio++) { 911e9a3b57eSRicard Wanderlof unsigned int cfg = adc3xxx->gpio_cfg[gpio]; 912e9a3b57eSRicard Wanderlof 913e9a3b57eSRicard Wanderlof if (cfg) { 914e9a3b57eSRicard Wanderlof cfg--; /* actual value to use is stored +1 */ 915e9a3b57eSRicard Wanderlof regmap_update_bits(adc3xxx->regmap, 916e9a3b57eSRicard Wanderlof adc3xxx_gpio_ctrl_reg[gpio], 917e9a3b57eSRicard Wanderlof ADC3XXX_GPIO_CTRL_CFG_MASK, 918e9a3b57eSRicard Wanderlof cfg << ADC3XXX_GPIO_CTRL_CFG_SHIFT); 919e9a3b57eSRicard Wanderlof } 920e9a3b57eSRicard Wanderlof } 921e9a3b57eSRicard Wanderlof 922e9a3b57eSRicard Wanderlof /* Set up micbias voltage */ 923e9a3b57eSRicard Wanderlof for (micbias = 0; micbias < ADC3XXX_MICBIAS_PINS; micbias++) { 924e9a3b57eSRicard Wanderlof unsigned int vg = adc3xxx->micbias_vg[micbias]; 925e9a3b57eSRicard Wanderlof 926e9a3b57eSRicard Wanderlof regmap_update_bits(adc3xxx->regmap, 927e9a3b57eSRicard Wanderlof ADC3XXX_MICBIAS_CTRL, 928e9a3b57eSRicard Wanderlof ADC3XXX_MICBIAS_MASK << adc3xxx_micbias_shift[micbias], 929e9a3b57eSRicard Wanderlof vg << adc3xxx_micbias_shift[micbias]); 930e9a3b57eSRicard Wanderlof } 931e9a3b57eSRicard Wanderlof } 932e9a3b57eSRicard Wanderlof 933e9a3b57eSRicard Wanderlof static int adc3xxx_parse_dt_gpio(struct adc3xxx *adc3xxx, 934e9a3b57eSRicard Wanderlof const char *propname, unsigned int *cfg) 935e9a3b57eSRicard Wanderlof { 936e9a3b57eSRicard Wanderlof struct device *dev = adc3xxx->dev; 937e9a3b57eSRicard Wanderlof struct device_node *np = dev->of_node; 938e9a3b57eSRicard Wanderlof unsigned int val; 939e9a3b57eSRicard Wanderlof 940e9a3b57eSRicard Wanderlof if (!of_property_read_u32(np, propname, &val)) { 941e9a3b57eSRicard Wanderlof if (val & ~15 || val == 7 || val >= 11) { 942e9a3b57eSRicard Wanderlof dev_err(dev, "Invalid property value for '%s'\n", propname); 943e9a3b57eSRicard Wanderlof return -EINVAL; 944e9a3b57eSRicard Wanderlof } 945e9a3b57eSRicard Wanderlof if (val == ADC3XXX_GPIO_GPI) 946e9a3b57eSRicard Wanderlof dev_warn(dev, "GPIO Input read not yet implemented\n"); 947e9a3b57eSRicard Wanderlof *cfg = val + 1; /* 0 => not set up, all others shifted +1 */ 948e9a3b57eSRicard Wanderlof } 949e9a3b57eSRicard Wanderlof return 0; 950e9a3b57eSRicard Wanderlof } 951e9a3b57eSRicard Wanderlof 952e9a3b57eSRicard Wanderlof static int adc3xxx_parse_dt_micbias(struct adc3xxx *adc3xxx, 953e9a3b57eSRicard Wanderlof const char *propname, unsigned int *vg) 954e9a3b57eSRicard Wanderlof { 955e9a3b57eSRicard Wanderlof struct device *dev = adc3xxx->dev; 956e9a3b57eSRicard Wanderlof struct device_node *np = dev->of_node; 957e9a3b57eSRicard Wanderlof unsigned int val; 958e9a3b57eSRicard Wanderlof 959e9a3b57eSRicard Wanderlof if (!of_property_read_u32(np, propname, &val)) { 960e9a3b57eSRicard Wanderlof if (val >= ADC3XXX_MICBIAS_AVDD) { 961e9a3b57eSRicard Wanderlof dev_err(dev, "Invalid property value for '%s'\n", propname); 962e9a3b57eSRicard Wanderlof return -EINVAL; 963e9a3b57eSRicard Wanderlof } 964e9a3b57eSRicard Wanderlof *vg = val; 965e9a3b57eSRicard Wanderlof } 966e9a3b57eSRicard Wanderlof return 0; 967e9a3b57eSRicard Wanderlof } 968e9a3b57eSRicard Wanderlof 969e9a3b57eSRicard Wanderlof static int adc3xxx_parse_pll_mode(uint32_t val, unsigned int *pll_mode) 970e9a3b57eSRicard Wanderlof { 971e9a3b57eSRicard Wanderlof if (val != ADC3XXX_PLL_ENABLE && val != ADC3XXX_PLL_BYPASS && 972e9a3b57eSRicard Wanderlof val != ADC3XXX_PLL_AUTO) 973e9a3b57eSRicard Wanderlof return -EINVAL; 974e9a3b57eSRicard Wanderlof 975e9a3b57eSRicard Wanderlof *pll_mode = val; 976e9a3b57eSRicard Wanderlof 977e9a3b57eSRicard Wanderlof return 0; 978e9a3b57eSRicard Wanderlof } 979e9a3b57eSRicard Wanderlof 980e9a3b57eSRicard Wanderlof static void adc3xxx_setup_pll(struct snd_soc_component *component, 981e9a3b57eSRicard Wanderlof int div_entry) 982e9a3b57eSRicard Wanderlof { 983e9a3b57eSRicard Wanderlof int i = div_entry; 984e9a3b57eSRicard Wanderlof 985e9a3b57eSRicard Wanderlof /* P & R values */ 986e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_PLL_PROG_PR, 987e9a3b57eSRicard Wanderlof (adc3xxx_divs[i].pll_p << ADC3XXX_PLLP_SHIFT) | 988e9a3b57eSRicard Wanderlof (adc3xxx_divs[i].pll_r << ADC3XXX_PLLR_SHIFT)); 989e9a3b57eSRicard Wanderlof /* J value */ 990e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_PLL_PROG_J, 991e9a3b57eSRicard Wanderlof adc3xxx_divs[i].pll_j & ADC3XXX_PLLJ_MASK); 992e9a3b57eSRicard Wanderlof /* D value */ 993e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_LSB, 994e9a3b57eSRicard Wanderlof adc3xxx_divs[i].pll_d & ADC3XXX_PLLD_LSB_MASK); 995e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_MSB, 996e9a3b57eSRicard Wanderlof (adc3xxx_divs[i].pll_d >> 8) & ADC3XXX_PLLD_MSB_MASK); 997e9a3b57eSRicard Wanderlof } 998e9a3b57eSRicard Wanderlof 999e9a3b57eSRicard Wanderlof static int adc3xxx_hw_params(struct snd_pcm_substream *substream, 1000e9a3b57eSRicard Wanderlof struct snd_pcm_hw_params *params, 1001e9a3b57eSRicard Wanderlof struct snd_soc_dai *dai) 1002e9a3b57eSRicard Wanderlof { 1003e9a3b57eSRicard Wanderlof struct snd_soc_component *component = dai->component; 1004e9a3b57eSRicard Wanderlof struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component); 1005e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component); 1006e9a3b57eSRicard Wanderlof int i, width = 16; 1007e9a3b57eSRicard Wanderlof u8 iface_len, bdiv; 1008e9a3b57eSRicard Wanderlof 1009e9a3b57eSRicard Wanderlof i = adc3xxx_get_divs(component->dev, adc3xxx->sysclk, 1010e9a3b57eSRicard Wanderlof params_rate(params), adc3xxx->pll_mode); 1011e9a3b57eSRicard Wanderlof 1012e9a3b57eSRicard Wanderlof if (i < 0) 1013e9a3b57eSRicard Wanderlof return i; 1014e9a3b57eSRicard Wanderlof 1015e9a3b57eSRicard Wanderlof /* select data word length */ 1016e9a3b57eSRicard Wanderlof switch (params_format(params)) { 1017e9a3b57eSRicard Wanderlof case SNDRV_PCM_FORMAT_S16_LE: 1018e9a3b57eSRicard Wanderlof iface_len = ADC3XXX_IFACE_16BITS; 1019e9a3b57eSRicard Wanderlof width = 16; 1020e9a3b57eSRicard Wanderlof break; 1021e9a3b57eSRicard Wanderlof case SNDRV_PCM_FORMAT_S20_3LE: 1022e9a3b57eSRicard Wanderlof iface_len = ADC3XXX_IFACE_20BITS; 1023e9a3b57eSRicard Wanderlof width = 20; 1024e9a3b57eSRicard Wanderlof break; 1025e9a3b57eSRicard Wanderlof case SNDRV_PCM_FORMAT_S24_LE: 1026e9a3b57eSRicard Wanderlof iface_len = ADC3XXX_IFACE_24BITS; 1027e9a3b57eSRicard Wanderlof width = 24; 1028e9a3b57eSRicard Wanderlof break; 1029e9a3b57eSRicard Wanderlof case SNDRV_PCM_FORMAT_S32_LE: 1030e9a3b57eSRicard Wanderlof iface_len = ADC3XXX_IFACE_32BITS; 1031e9a3b57eSRicard Wanderlof width = 32; 1032e9a3b57eSRicard Wanderlof break; 1033e9a3b57eSRicard Wanderlof default: 1034e9a3b57eSRicard Wanderlof dev_err(component->dev, "Unsupported serial data format\n"); 1035e9a3b57eSRicard Wanderlof return -EINVAL; 1036e9a3b57eSRicard Wanderlof } 1037e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_INTERFACE_CTRL_1, 1038e9a3b57eSRicard Wanderlof ADC3XXX_WLENGTH_MASK, iface_len); 1039e9a3b57eSRicard Wanderlof if (adc3xxx_divs[i].pll_p) { /* If PLL used for this mode */ 1040e9a3b57eSRicard Wanderlof adc3xxx_setup_pll(component, i); 1041e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_USE_PLL); 1042e9a3b57eSRicard Wanderlof if (!adc3xxx->use_pll) { 1043e9a3b57eSRicard Wanderlof snd_soc_dapm_add_routes(dapm, adc3xxx_pll_intercon, 1044e9a3b57eSRicard Wanderlof ARRAY_SIZE(adc3xxx_pll_intercon)); 1045e9a3b57eSRicard Wanderlof adc3xxx->use_pll = 1; 1046e9a3b57eSRicard Wanderlof } 1047e9a3b57eSRicard Wanderlof } else { 1048e9a3b57eSRicard Wanderlof snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_NO_PLL); 1049e9a3b57eSRicard Wanderlof if (adc3xxx->use_pll) { 1050e9a3b57eSRicard Wanderlof snd_soc_dapm_del_routes(dapm, adc3xxx_pll_intercon, 1051e9a3b57eSRicard Wanderlof ARRAY_SIZE(adc3xxx_pll_intercon)); 1052e9a3b57eSRicard Wanderlof adc3xxx->use_pll = 0; 1053e9a3b57eSRicard Wanderlof } 1054e9a3b57eSRicard Wanderlof } 1055e9a3b57eSRicard Wanderlof 1056e9a3b57eSRicard Wanderlof /* NADC */ 1057e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_ADC_NADC, 1058e9a3b57eSRicard Wanderlof ADC3XXX_NADC_MASK, adc3xxx_divs[i].nadc); 1059e9a3b57eSRicard Wanderlof /* MADC */ 1060e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_ADC_MADC, 1061e9a3b57eSRicard Wanderlof ADC3XXX_MADC_MASK, adc3xxx_divs[i].madc); 1062e9a3b57eSRicard Wanderlof /* AOSR */ 1063e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_ADC_AOSR, 1064e9a3b57eSRicard Wanderlof ADC3XXX_AOSR_MASK, adc3xxx_divs[i].aosr); 1065e9a3b57eSRicard Wanderlof /* BDIV N Value */ 1066e9a3b57eSRicard Wanderlof /* BCLK is (by default) set up to be derived from ADC_CLK */ 1067e9a3b57eSRicard Wanderlof bdiv = (adc3xxx_divs[i].aosr * adc3xxx_divs[i].madc) / (2 * width); 1068e9a3b57eSRicard Wanderlof snd_soc_component_update_bits(component, ADC3XXX_BCLK_N_DIV, 1069e9a3b57eSRicard Wanderlof ADC3XXX_BDIV_MASK, bdiv); 1070e9a3b57eSRicard Wanderlof 1071e9a3b57eSRicard Wanderlof return 0; 1072e9a3b57eSRicard Wanderlof } 1073e9a3b57eSRicard Wanderlof 1074e9a3b57eSRicard Wanderlof static const char *adc3xxx_pll_mode_text(int pll_mode) 1075e9a3b57eSRicard Wanderlof { 1076e9a3b57eSRicard Wanderlof switch (pll_mode) { 1077e9a3b57eSRicard Wanderlof case ADC3XXX_PLL_AUTO: 1078e9a3b57eSRicard Wanderlof return "PLL auto"; 1079e9a3b57eSRicard Wanderlof case ADC3XXX_PLL_ENABLE: 1080e9a3b57eSRicard Wanderlof return "PLL enable"; 1081e9a3b57eSRicard Wanderlof case ADC3XXX_PLL_BYPASS: 1082e9a3b57eSRicard Wanderlof return "PLL bypass"; 1083e9a3b57eSRicard Wanderlof default: 1084e9a3b57eSRicard Wanderlof break; 1085e9a3b57eSRicard Wanderlof } 1086e9a3b57eSRicard Wanderlof 1087e9a3b57eSRicard Wanderlof return "PLL unknown"; 1088e9a3b57eSRicard Wanderlof } 1089e9a3b57eSRicard Wanderlof 1090e9a3b57eSRicard Wanderlof static int adc3xxx_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1091e9a3b57eSRicard Wanderlof int clk_id, unsigned int freq, int dir) 1092e9a3b57eSRicard Wanderlof { 1093e9a3b57eSRicard Wanderlof struct snd_soc_component *component = codec_dai->component; 1094e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component); 1095e9a3b57eSRicard Wanderlof int ret; 1096e9a3b57eSRicard Wanderlof 1097e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_pll_mode(clk_id, &adc3xxx->pll_mode); 1098e9a3b57eSRicard Wanderlof if (ret < 0) 1099e9a3b57eSRicard Wanderlof return ret; 1100e9a3b57eSRicard Wanderlof 1101e9a3b57eSRicard Wanderlof adc3xxx->sysclk = freq; 1102e9a3b57eSRicard Wanderlof dev_dbg(component->dev, "Set sysclk to %u Hz, %s\n", 1103e9a3b57eSRicard Wanderlof freq, adc3xxx_pll_mode_text(adc3xxx->pll_mode)); 1104e9a3b57eSRicard Wanderlof return 0; 1105e9a3b57eSRicard Wanderlof } 1106e9a3b57eSRicard Wanderlof 1107e9a3b57eSRicard Wanderlof static int adc3xxx_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1108e9a3b57eSRicard Wanderlof { 1109e9a3b57eSRicard Wanderlof struct snd_soc_component *component = codec_dai->component; 1110e9a3b57eSRicard Wanderlof struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1111e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component); 1112e9a3b57eSRicard Wanderlof u8 clkdir = 0, format = 0; 1113e9a3b57eSRicard Wanderlof int master = 0; 1114e9a3b57eSRicard Wanderlof 1115e9a3b57eSRicard Wanderlof /* set master/slave audio interface */ 1116e9a3b57eSRicard Wanderlof switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1117e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_CBP_CFP: 1118e9a3b57eSRicard Wanderlof master = 1; 1119e9a3b57eSRicard Wanderlof clkdir = ADC3XXX_BCLK_MASTER | ADC3XXX_WCLK_MASTER; 1120e9a3b57eSRicard Wanderlof break; 1121e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_CBC_CFC: 1122e9a3b57eSRicard Wanderlof master = 0; 1123e9a3b57eSRicard Wanderlof break; 1124e9a3b57eSRicard Wanderlof default: 1125e9a3b57eSRicard Wanderlof dev_err(component->dev, "Invalid DAI clock setup\n"); 1126e9a3b57eSRicard Wanderlof return -EINVAL; 1127e9a3b57eSRicard Wanderlof } 1128e9a3b57eSRicard Wanderlof 1129e9a3b57eSRicard Wanderlof /* 1130e9a3b57eSRicard Wanderlof * match both interface format and signal polarities since they 1131e9a3b57eSRicard Wanderlof * are fixed 1132e9a3b57eSRicard Wanderlof */ 1133e9a3b57eSRicard Wanderlof switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK)) { 1134e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF: 1135e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_I2S; 1136e9a3b57eSRicard Wanderlof break; 1137e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF: 1138e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_DSP; 1139e9a3b57eSRicard Wanderlof break; 1140e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF: 1141e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_DSP; 1142e9a3b57eSRicard Wanderlof break; 1143e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF: 1144e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_RJF; 1145e9a3b57eSRicard Wanderlof break; 1146e9a3b57eSRicard Wanderlof case SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF: 1147e9a3b57eSRicard Wanderlof format = ADC3XXX_FORMAT_LJF; 1148e9a3b57eSRicard Wanderlof break; 1149e9a3b57eSRicard Wanderlof default: 1150e9a3b57eSRicard Wanderlof dev_err(component->dev, "Invalid DAI format\n"); 1151e9a3b57eSRicard Wanderlof return -EINVAL; 1152e9a3b57eSRicard Wanderlof } 1153e9a3b57eSRicard Wanderlof 1154e9a3b57eSRicard Wanderlof /* Add/del route enabling BCLK output as applicable */ 1155e9a3b57eSRicard Wanderlof if (master && !adc3xxx->master) 1156e9a3b57eSRicard Wanderlof snd_soc_dapm_add_routes(dapm, adc3xxx_bclk_out_intercon, 1157e9a3b57eSRicard Wanderlof ARRAY_SIZE(adc3xxx_bclk_out_intercon)); 1158e9a3b57eSRicard Wanderlof else if (!master && adc3xxx->master) 1159e9a3b57eSRicard Wanderlof snd_soc_dapm_del_routes(dapm, adc3xxx_bclk_out_intercon, 1160e9a3b57eSRicard Wanderlof ARRAY_SIZE(adc3xxx_bclk_out_intercon)); 1161e9a3b57eSRicard Wanderlof adc3xxx->master = master; 1162e9a3b57eSRicard Wanderlof 1163e9a3b57eSRicard Wanderlof /* set clock direction and format */ 1164e9a3b57eSRicard Wanderlof return snd_soc_component_update_bits(component, 1165e9a3b57eSRicard Wanderlof ADC3XXX_INTERFACE_CTRL_1, 1166e9a3b57eSRicard Wanderlof ADC3XXX_CLKDIR_MASK | ADC3XXX_FORMAT_MASK, 1167e9a3b57eSRicard Wanderlof clkdir | format); 1168e9a3b57eSRicard Wanderlof } 1169e9a3b57eSRicard Wanderlof 1170e9a3b57eSRicard Wanderlof static const struct snd_soc_dai_ops adc3xxx_dai_ops = { 1171e9a3b57eSRicard Wanderlof .hw_params = adc3xxx_hw_params, 1172e9a3b57eSRicard Wanderlof .set_sysclk = adc3xxx_set_dai_sysclk, 1173e9a3b57eSRicard Wanderlof .set_fmt = adc3xxx_set_dai_fmt, 1174e9a3b57eSRicard Wanderlof }; 1175e9a3b57eSRicard Wanderlof 1176e9a3b57eSRicard Wanderlof static struct snd_soc_dai_driver adc3xxx_dai = { 1177e9a3b57eSRicard Wanderlof .name = "tlv320adc3xxx-hifi", 1178e9a3b57eSRicard Wanderlof .capture = { 1179e9a3b57eSRicard Wanderlof .stream_name = "Capture", 1180e9a3b57eSRicard Wanderlof .channels_min = 1, 1181e9a3b57eSRicard Wanderlof .channels_max = 2, 1182e9a3b57eSRicard Wanderlof .rates = ADC3XXX_RATES, 1183e9a3b57eSRicard Wanderlof .formats = ADC3XXX_FORMATS, 1184e9a3b57eSRicard Wanderlof }, 1185e9a3b57eSRicard Wanderlof .ops = &adc3xxx_dai_ops, 1186e9a3b57eSRicard Wanderlof }; 1187e9a3b57eSRicard Wanderlof 1188e9a3b57eSRicard Wanderlof static const struct snd_soc_component_driver soc_component_dev_adc3xxx = { 1189e9a3b57eSRicard Wanderlof .controls = adc3xxx_snd_controls, 1190e9a3b57eSRicard Wanderlof .num_controls = ARRAY_SIZE(adc3xxx_snd_controls), 1191e9a3b57eSRicard Wanderlof .dapm_widgets = adc3xxx_dapm_widgets, 1192e9a3b57eSRicard Wanderlof .num_dapm_widgets = ARRAY_SIZE(adc3xxx_dapm_widgets), 1193e9a3b57eSRicard Wanderlof .dapm_routes = adc3xxx_intercon, 1194e9a3b57eSRicard Wanderlof .num_dapm_routes = ARRAY_SIZE(adc3xxx_intercon), 1195e9a3b57eSRicard Wanderlof }; 1196e9a3b57eSRicard Wanderlof 1197e9a3b57eSRicard Wanderlof static int adc3xxx_i2c_probe(struct i2c_client *i2c, 1198e9a3b57eSRicard Wanderlof const struct i2c_device_id *id) 1199e9a3b57eSRicard Wanderlof { 1200e9a3b57eSRicard Wanderlof struct device *dev = &i2c->dev; 1201e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = NULL; 1202e9a3b57eSRicard Wanderlof int ret; 1203e9a3b57eSRicard Wanderlof 1204e9a3b57eSRicard Wanderlof adc3xxx = devm_kzalloc(dev, sizeof(struct adc3xxx), GFP_KERNEL); 1205e9a3b57eSRicard Wanderlof if (!adc3xxx) 1206e9a3b57eSRicard Wanderlof return -ENOMEM; 1207e9a3b57eSRicard Wanderlof adc3xxx->dev = dev; 1208e9a3b57eSRicard Wanderlof 1209e9a3b57eSRicard Wanderlof adc3xxx->rst_pin = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); 1210e9a3b57eSRicard Wanderlof if (IS_ERR(adc3xxx->rst_pin)) { 1211e9a3b57eSRicard Wanderlof return dev_err_probe(dev, PTR_ERR(adc3xxx->rst_pin), 1212e9a3b57eSRicard Wanderlof "Failed to request rst_pin\n"); 1213e9a3b57eSRicard Wanderlof } 1214e9a3b57eSRicard Wanderlof 1215e9a3b57eSRicard Wanderlof adc3xxx->mclk = devm_clk_get(dev, NULL); 1216e9a3b57eSRicard Wanderlof if (IS_ERR(adc3xxx->mclk)) { 1217e9a3b57eSRicard Wanderlof /* 1218e9a3b57eSRicard Wanderlof * The chip itself supports running off the BCLK either 1219e9a3b57eSRicard Wanderlof * directly or via the PLL, but the driver does not (yet), so 1220e9a3b57eSRicard Wanderlof * having a specified mclk is required. Otherwise, we could 1221e9a3b57eSRicard Wanderlof * use the lack of a clocks property to indicate when BCLK is 1222e9a3b57eSRicard Wanderlof * intended as the clock source. 1223e9a3b57eSRicard Wanderlof */ 1224e9a3b57eSRicard Wanderlof return dev_err_probe(dev, PTR_ERR(adc3xxx->mclk), 1225e9a3b57eSRicard Wanderlof "Failed to acquire MCLK\n"); 1226e9a3b57eSRicard Wanderlof } else if (adc3xxx->mclk) { 1227e9a3b57eSRicard Wanderlof ret = clk_prepare_enable(adc3xxx->mclk); 1228e9a3b57eSRicard Wanderlof if (ret < 0) 1229e9a3b57eSRicard Wanderlof return ret; 1230e9a3b57eSRicard Wanderlof dev_dbg(dev, "Enabled MCLK, freq %lu Hz\n", clk_get_rate(adc3xxx->mclk)); 1231e9a3b57eSRicard Wanderlof } 1232e9a3b57eSRicard Wanderlof 1233e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmdin-gpio1", &adc3xxx->gpio_cfg[0]); 1234e9a3b57eSRicard Wanderlof if (ret < 0) 1235*8a2d8e4fSYang Yingliang goto err_unprepare_mclk; 1236e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmclk-gpio2", &adc3xxx->gpio_cfg[1]); 1237e9a3b57eSRicard Wanderlof if (ret < 0) 1238*8a2d8e4fSYang Yingliang goto err_unprepare_mclk; 1239e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_dt_micbias(adc3xxx, "ti,micbias1-vg", &adc3xxx->micbias_vg[0]); 1240e9a3b57eSRicard Wanderlof if (ret < 0) 1241*8a2d8e4fSYang Yingliang goto err_unprepare_mclk; 1242e9a3b57eSRicard Wanderlof ret = adc3xxx_parse_dt_micbias(adc3xxx, "ti,micbias2-vg", &adc3xxx->micbias_vg[1]); 1243e9a3b57eSRicard Wanderlof if (ret < 0) 1244*8a2d8e4fSYang Yingliang goto err_unprepare_mclk; 1245e9a3b57eSRicard Wanderlof 1246e9a3b57eSRicard Wanderlof adc3xxx->regmap = devm_regmap_init_i2c(i2c, &adc3xxx_regmap); 1247e9a3b57eSRicard Wanderlof if (IS_ERR(adc3xxx->regmap)) { 1248e9a3b57eSRicard Wanderlof ret = PTR_ERR(adc3xxx->regmap); 1249*8a2d8e4fSYang Yingliang goto err_unprepare_mclk; 1250e9a3b57eSRicard Wanderlof } 1251e9a3b57eSRicard Wanderlof 1252e9a3b57eSRicard Wanderlof i2c_set_clientdata(i2c, adc3xxx); 1253e9a3b57eSRicard Wanderlof 1254e9a3b57eSRicard Wanderlof adc3xxx->type = id->driver_data; 1255e9a3b57eSRicard Wanderlof 1256e9a3b57eSRicard Wanderlof /* Reset codec chip */ 1257e9a3b57eSRicard Wanderlof gpiod_set_value_cansleep(adc3xxx->rst_pin, 1); 1258e9a3b57eSRicard Wanderlof usleep_range(2000, 100000); /* Requirement: > 10 ns (datasheet p13) */ 1259e9a3b57eSRicard Wanderlof gpiod_set_value_cansleep(adc3xxx->rst_pin, 0); 1260e9a3b57eSRicard Wanderlof 1261e9a3b57eSRicard Wanderlof /* Potentially set up pins used as GPIOs */ 1262e9a3b57eSRicard Wanderlof adc3xxx_init_gpio(adc3xxx); 1263e9a3b57eSRicard Wanderlof 1264e9a3b57eSRicard Wanderlof ret = snd_soc_register_component(dev, 1265e9a3b57eSRicard Wanderlof &soc_component_dev_adc3xxx, &adc3xxx_dai, 1); 1266*8a2d8e4fSYang Yingliang if (ret < 0) { 1267e9a3b57eSRicard Wanderlof dev_err(dev, "Failed to register codec: %d\n", ret); 1268*8a2d8e4fSYang Yingliang goto err_unprepare_mclk; 1269*8a2d8e4fSYang Yingliang } 1270e9a3b57eSRicard Wanderlof 1271*8a2d8e4fSYang Yingliang return 0; 1272*8a2d8e4fSYang Yingliang 1273*8a2d8e4fSYang Yingliang err_unprepare_mclk: 1274*8a2d8e4fSYang Yingliang clk_disable_unprepare(adc3xxx->mclk); 1275e9a3b57eSRicard Wanderlof return ret; 1276e9a3b57eSRicard Wanderlof } 1277e9a3b57eSRicard Wanderlof 1278e9a3b57eSRicard Wanderlof static int __exit adc3xxx_i2c_remove(struct i2c_client *client) 1279e9a3b57eSRicard Wanderlof { 1280e9a3b57eSRicard Wanderlof struct adc3xxx *adc3xxx = i2c_get_clientdata(client); 1281e9a3b57eSRicard Wanderlof 1282e9a3b57eSRicard Wanderlof if (adc3xxx->mclk) 1283e9a3b57eSRicard Wanderlof clk_disable_unprepare(adc3xxx->mclk); 1284e9a3b57eSRicard Wanderlof adc3xxx_free_gpio(adc3xxx); 1285e9a3b57eSRicard Wanderlof snd_soc_unregister_component(&client->dev); 1286e9a3b57eSRicard Wanderlof return 0; 1287e9a3b57eSRicard Wanderlof } 1288e9a3b57eSRicard Wanderlof 1289e9a3b57eSRicard Wanderlof static const struct of_device_id tlv320adc3xxx_of_match[] = { 1290e9a3b57eSRicard Wanderlof { .compatible = "ti,tlv320adc3001", }, 1291e9a3b57eSRicard Wanderlof { .compatible = "ti,tlv320adc3101", }, 1292e9a3b57eSRicard Wanderlof {}, 1293e9a3b57eSRicard Wanderlof }; 1294e9a3b57eSRicard Wanderlof MODULE_DEVICE_TABLE(of, tlv320adc3xxx_of_match); 1295e9a3b57eSRicard Wanderlof 1296e9a3b57eSRicard Wanderlof static const struct i2c_device_id adc3xxx_i2c_id[] = { 1297e9a3b57eSRicard Wanderlof { "tlv320adc3001", ADC3001 }, 1298e9a3b57eSRicard Wanderlof { "tlv320adc3101", ADC3101 }, 1299e9a3b57eSRicard Wanderlof {} 1300e9a3b57eSRicard Wanderlof }; 1301e9a3b57eSRicard Wanderlof MODULE_DEVICE_TABLE(i2c, adc3xxx_i2c_id); 1302e9a3b57eSRicard Wanderlof 1303e9a3b57eSRicard Wanderlof static struct i2c_driver adc3xxx_i2c_driver = { 1304e9a3b57eSRicard Wanderlof .driver = { 1305e9a3b57eSRicard Wanderlof .name = "tlv320adc3xxx-codec", 1306e9a3b57eSRicard Wanderlof .of_match_table = tlv320adc3xxx_of_match, 1307e9a3b57eSRicard Wanderlof }, 1308e9a3b57eSRicard Wanderlof .probe = adc3xxx_i2c_probe, 1309e9a3b57eSRicard Wanderlof .remove = adc3xxx_i2c_remove, 1310e9a3b57eSRicard Wanderlof .id_table = adc3xxx_i2c_id, 1311e9a3b57eSRicard Wanderlof }; 1312e9a3b57eSRicard Wanderlof 1313e9a3b57eSRicard Wanderlof module_i2c_driver(adc3xxx_i2c_driver); 1314e9a3b57eSRicard Wanderlof 1315e9a3b57eSRicard Wanderlof MODULE_DESCRIPTION("ASoC TLV320ADC3xxx codec driver"); 1316e9a3b57eSRicard Wanderlof MODULE_AUTHOR("shahina.s@mistralsolutions.com"); 1317e9a3b57eSRicard Wanderlof MODULE_LICENSE("GPL v2"); 1318