1 /* 2 * TAS5086 ASoC codec driver 3 * 4 * Copyright (c) 2013 Daniel Mack <zonque@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * TODO: 17 * - implement DAPM and input muxing 18 * - implement modulation limit 19 * - implement non-default PWM start 20 * 21 * Note that this chip has a very unusual register layout, specifically 22 * because the registers are of unequal size, and multi-byte registers 23 * require bulk writes to take effect. Regmap does not support that kind 24 * of devices. 25 * 26 * Currently, the driver does not touch any of the registers >= 0x20, so 27 * it doesn't matter because the entire map can be accessed as 8-bit 28 * array. In case more features will be added in the future 29 * that require access to higher registers, the entire regmap H/W I/O 30 * routines have to be open-coded. 31 */ 32 33 #include <linux/module.h> 34 #include <linux/slab.h> 35 #include <linux/delay.h> 36 #include <linux/gpio.h> 37 #include <linux/i2c.h> 38 #include <linux/regmap.h> 39 #include <linux/regulator/consumer.h> 40 #include <linux/spi/spi.h> 41 #include <linux/of.h> 42 #include <linux/of_device.h> 43 #include <linux/of_gpio.h> 44 #include <sound/pcm.h> 45 #include <sound/pcm_params.h> 46 #include <sound/soc.h> 47 #include <sound/tlv.h> 48 #include <sound/tas5086.h> 49 50 #define TAS5086_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 51 SNDRV_PCM_FMTBIT_S20_3LE | \ 52 SNDRV_PCM_FMTBIT_S24_3LE) 53 54 #define TAS5086_PCM_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ 55 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | \ 56 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \ 57 SNDRV_PCM_RATE_192000) 58 59 /* 60 * TAS5086 registers 61 */ 62 #define TAS5086_CLOCK_CONTROL 0x00 /* Clock control register */ 63 #define TAS5086_CLOCK_RATE(val) (val << 5) 64 #define TAS5086_CLOCK_RATE_MASK (0x7 << 5) 65 #define TAS5086_CLOCK_RATIO(val) (val << 2) 66 #define TAS5086_CLOCK_RATIO_MASK (0x7 << 2) 67 #define TAS5086_CLOCK_SCLK_RATIO_48 (1 << 1) 68 #define TAS5086_CLOCK_VALID (1 << 0) 69 70 #define TAS5086_DEEMPH_MASK 0x03 71 #define TAS5086_SOFT_MUTE_ALL 0x3f 72 73 #define TAS5086_DEV_ID 0x01 /* Device ID register */ 74 #define TAS5086_ERROR_STATUS 0x02 /* Error status register */ 75 #define TAS5086_SYS_CONTROL_1 0x03 /* System control register 1 */ 76 #define TAS5086_SERIAL_DATA_IF 0x04 /* Serial data interface register */ 77 #define TAS5086_SYS_CONTROL_2 0x05 /* System control register 2 */ 78 #define TAS5086_SOFT_MUTE 0x06 /* Soft mute register */ 79 #define TAS5086_MASTER_VOL 0x07 /* Master volume */ 80 #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */ 81 #define TAS5086_VOLUME_CONTROL 0x09 /* Volume control register */ 82 #define TAS5086_MOD_LIMIT 0x10 /* Modulation limit register */ 83 #define TAS5086_PWM_START 0x18 /* PWM start register */ 84 #define TAS5086_SURROUND 0x19 /* Surround register */ 85 #define TAS5086_SPLIT_CAP_CHARGE 0x1a /* Split cap charge period register */ 86 #define TAS5086_OSC_TRIM 0x1b /* Oscillator trim register */ 87 #define TAS5086_BKNDERR 0x1c 88 #define TAS5086_INPUT_MUX 0x20 89 #define TAS5086_PWM_OUTPUT_MUX 0x25 90 91 #define TAS5086_MAX_REGISTER TAS5086_PWM_OUTPUT_MUX 92 93 #define TAS5086_PWM_START_MIDZ_FOR_START_1 (1 << 7) 94 #define TAS5086_PWM_START_MIDZ_FOR_START_2 (1 << 6) 95 #define TAS5086_PWM_START_CHANNEL_MASK (0x3f) 96 97 /* 98 * Default TAS5086 power-up configuration 99 */ 100 static const struct reg_default tas5086_reg_defaults[] = { 101 { 0x00, 0x6c }, 102 { 0x01, 0x03 }, 103 { 0x02, 0x00 }, 104 { 0x03, 0xa0 }, 105 { 0x04, 0x05 }, 106 { 0x05, 0x60 }, 107 { 0x06, 0x00 }, 108 { 0x07, 0xff }, 109 { 0x08, 0x30 }, 110 { 0x09, 0x30 }, 111 { 0x0a, 0x30 }, 112 { 0x0b, 0x30 }, 113 { 0x0c, 0x30 }, 114 { 0x0d, 0x30 }, 115 { 0x0e, 0xb1 }, 116 { 0x0f, 0x00 }, 117 { 0x10, 0x02 }, 118 { 0x11, 0x00 }, 119 { 0x12, 0x00 }, 120 { 0x13, 0x00 }, 121 { 0x14, 0x00 }, 122 { 0x15, 0x00 }, 123 { 0x16, 0x00 }, 124 { 0x17, 0x00 }, 125 { 0x18, 0x3f }, 126 { 0x19, 0x00 }, 127 { 0x1a, 0x18 }, 128 { 0x1b, 0x82 }, 129 { 0x1c, 0x05 }, 130 }; 131 132 static int tas5086_register_size(struct device *dev, unsigned int reg) 133 { 134 switch (reg) { 135 case TAS5086_CLOCK_CONTROL ... TAS5086_BKNDERR: 136 return 1; 137 case TAS5086_INPUT_MUX: 138 case TAS5086_PWM_OUTPUT_MUX: 139 return 4; 140 } 141 142 dev_err(dev, "Unsupported register address: %d\n", reg); 143 return 0; 144 } 145 146 static bool tas5086_accessible_reg(struct device *dev, unsigned int reg) 147 { 148 switch (reg) { 149 case 0x0f: 150 case 0x11 ... 0x17: 151 case 0x1d ... 0x1f: 152 return false; 153 default: 154 return true; 155 } 156 } 157 158 static bool tas5086_volatile_reg(struct device *dev, unsigned int reg) 159 { 160 switch (reg) { 161 case TAS5086_DEV_ID: 162 case TAS5086_ERROR_STATUS: 163 return true; 164 } 165 166 return false; 167 } 168 169 static bool tas5086_writeable_reg(struct device *dev, unsigned int reg) 170 { 171 return tas5086_accessible_reg(dev, reg) && (reg != TAS5086_DEV_ID); 172 } 173 174 static int tas5086_reg_write(void *context, unsigned int reg, 175 unsigned int value) 176 { 177 struct i2c_client *client = context; 178 unsigned int i, size; 179 uint8_t buf[5]; 180 int ret; 181 182 size = tas5086_register_size(&client->dev, reg); 183 if (size == 0) 184 return -EINVAL; 185 186 buf[0] = reg; 187 188 for (i = size; i >= 1; --i) { 189 buf[i] = value; 190 value >>= 8; 191 } 192 193 ret = i2c_master_send(client, buf, size + 1); 194 if (ret == size + 1) 195 return 0; 196 else if (ret < 0) 197 return ret; 198 else 199 return -EIO; 200 } 201 202 static int tas5086_reg_read(void *context, unsigned int reg, 203 unsigned int *value) 204 { 205 struct i2c_client *client = context; 206 uint8_t send_buf, recv_buf[4]; 207 struct i2c_msg msgs[2]; 208 unsigned int size; 209 unsigned int i; 210 int ret; 211 212 size = tas5086_register_size(&client->dev, reg); 213 if (size == 0) 214 return -EINVAL; 215 216 send_buf = reg; 217 218 msgs[0].addr = client->addr; 219 msgs[0].len = sizeof(send_buf); 220 msgs[0].buf = &send_buf; 221 msgs[0].flags = 0; 222 223 msgs[1].addr = client->addr; 224 msgs[1].len = size; 225 msgs[1].buf = recv_buf; 226 msgs[1].flags = I2C_M_RD; 227 228 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); 229 if (ret < 0) 230 return ret; 231 else if (ret != ARRAY_SIZE(msgs)) 232 return -EIO; 233 234 *value = 0; 235 236 for (i = 0; i < size; i++) { 237 *value <<= 8; 238 *value |= recv_buf[i]; 239 } 240 241 return 0; 242 } 243 244 static const char * const supply_names[] = { 245 "dvdd", "avdd" 246 }; 247 248 struct tas5086_private { 249 struct regmap *regmap; 250 unsigned int mclk, sclk; 251 unsigned int format; 252 bool deemph; 253 unsigned int charge_period; 254 unsigned int pwm_start_mid_z; 255 /* Current sample rate for de-emphasis control */ 256 int rate; 257 /* GPIO driving Reset pin, if any */ 258 int gpio_nreset; 259 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; 260 }; 261 262 static int tas5086_deemph[] = { 0, 32000, 44100, 48000 }; 263 264 static int tas5086_set_deemph(struct snd_soc_codec *codec) 265 { 266 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 267 int i, val = 0; 268 269 if (priv->deemph) { 270 for (i = 0; i < ARRAY_SIZE(tas5086_deemph); i++) { 271 if (tas5086_deemph[i] == priv->rate) { 272 val = i; 273 break; 274 } 275 } 276 } 277 278 return regmap_update_bits(priv->regmap, TAS5086_SYS_CONTROL_1, 279 TAS5086_DEEMPH_MASK, val); 280 } 281 282 static int tas5086_get_deemph(struct snd_kcontrol *kcontrol, 283 struct snd_ctl_elem_value *ucontrol) 284 { 285 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 286 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 287 288 ucontrol->value.integer.value[0] = priv->deemph; 289 290 return 0; 291 } 292 293 static int tas5086_put_deemph(struct snd_kcontrol *kcontrol, 294 struct snd_ctl_elem_value *ucontrol) 295 { 296 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 297 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 298 299 priv->deemph = ucontrol->value.integer.value[0]; 300 301 return tas5086_set_deemph(codec); 302 } 303 304 305 static int tas5086_set_dai_sysclk(struct snd_soc_dai *codec_dai, 306 int clk_id, unsigned int freq, int dir) 307 { 308 struct snd_soc_codec *codec = codec_dai->codec; 309 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 310 311 switch (clk_id) { 312 case TAS5086_CLK_IDX_MCLK: 313 priv->mclk = freq; 314 break; 315 case TAS5086_CLK_IDX_SCLK: 316 priv->sclk = freq; 317 break; 318 } 319 320 return 0; 321 } 322 323 static int tas5086_set_dai_fmt(struct snd_soc_dai *codec_dai, 324 unsigned int format) 325 { 326 struct snd_soc_codec *codec = codec_dai->codec; 327 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 328 329 /* The TAS5086 can only be slave to all clocks */ 330 if ((format & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) { 331 dev_err(codec->dev, "Invalid clocking mode\n"); 332 return -EINVAL; 333 } 334 335 /* we need to refer to the data format from hw_params() */ 336 priv->format = format; 337 338 return 0; 339 } 340 341 static const int tas5086_sample_rates[] = { 342 32000, 38000, 44100, 48000, 88200, 96000, 176400, 192000 343 }; 344 345 static const int tas5086_ratios[] = { 346 64, 128, 192, 256, 384, 512 347 }; 348 349 static int index_in_array(const int *array, int len, int needle) 350 { 351 int i; 352 353 for (i = 0; i < len; i++) 354 if (array[i] == needle) 355 return i; 356 357 return -ENOENT; 358 } 359 360 static int tas5086_hw_params(struct snd_pcm_substream *substream, 361 struct snd_pcm_hw_params *params, 362 struct snd_soc_dai *dai) 363 { 364 struct snd_soc_codec *codec = dai->codec; 365 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 366 int val; 367 int ret; 368 369 priv->rate = params_rate(params); 370 371 /* Look up the sample rate and refer to the offset in the list */ 372 val = index_in_array(tas5086_sample_rates, 373 ARRAY_SIZE(tas5086_sample_rates), priv->rate); 374 375 if (val < 0) { 376 dev_err(codec->dev, "Invalid sample rate\n"); 377 return -EINVAL; 378 } 379 380 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, 381 TAS5086_CLOCK_RATE_MASK, 382 TAS5086_CLOCK_RATE(val)); 383 if (ret < 0) 384 return ret; 385 386 /* MCLK / Fs ratio */ 387 val = index_in_array(tas5086_ratios, ARRAY_SIZE(tas5086_ratios), 388 priv->mclk / priv->rate); 389 if (val < 0) { 390 dev_err(codec->dev, "Invalid MCLK / Fs ratio\n"); 391 return -EINVAL; 392 } 393 394 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, 395 TAS5086_CLOCK_RATIO_MASK, 396 TAS5086_CLOCK_RATIO(val)); 397 if (ret < 0) 398 return ret; 399 400 401 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, 402 TAS5086_CLOCK_SCLK_RATIO_48, 403 (priv->sclk == 48 * priv->rate) ? 404 TAS5086_CLOCK_SCLK_RATIO_48 : 0); 405 if (ret < 0) 406 return ret; 407 408 /* 409 * The chip has a very unituitive register mapping and muxes information 410 * about data format and sample depth into the same register, but not on 411 * a logical bit-boundary. Hence, we have to refer to the format passed 412 * in the set_dai_fmt() callback and set up everything from here. 413 * 414 * First, determine the 'base' value, using the format ... 415 */ 416 switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) { 417 case SND_SOC_DAIFMT_RIGHT_J: 418 val = 0x00; 419 break; 420 case SND_SOC_DAIFMT_I2S: 421 val = 0x03; 422 break; 423 case SND_SOC_DAIFMT_LEFT_J: 424 val = 0x06; 425 break; 426 default: 427 dev_err(codec->dev, "Invalid DAI format\n"); 428 return -EINVAL; 429 } 430 431 /* ... then add the offset for the sample bit depth. */ 432 switch (params_width(params)) { 433 case 16: 434 val += 0; 435 break; 436 case 20: 437 val += 1; 438 break; 439 case 24: 440 val += 2; 441 break; 442 default: 443 dev_err(codec->dev, "Invalid bit width\n"); 444 return -EINVAL; 445 } 446 447 ret = regmap_write(priv->regmap, TAS5086_SERIAL_DATA_IF, val); 448 if (ret < 0) 449 return ret; 450 451 /* clock is considered valid now */ 452 ret = regmap_update_bits(priv->regmap, TAS5086_CLOCK_CONTROL, 453 TAS5086_CLOCK_VALID, TAS5086_CLOCK_VALID); 454 if (ret < 0) 455 return ret; 456 457 return tas5086_set_deemph(codec); 458 } 459 460 static int tas5086_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 461 { 462 struct snd_soc_codec *codec = dai->codec; 463 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 464 unsigned int val = 0; 465 466 if (mute) 467 val = TAS5086_SOFT_MUTE_ALL; 468 469 return regmap_write(priv->regmap, TAS5086_SOFT_MUTE, val); 470 } 471 472 static void tas5086_reset(struct tas5086_private *priv) 473 { 474 if (gpio_is_valid(priv->gpio_nreset)) { 475 /* Reset codec - minimum assertion time is 400ns */ 476 gpio_direction_output(priv->gpio_nreset, 0); 477 udelay(1); 478 gpio_set_value(priv->gpio_nreset, 1); 479 480 /* Codec needs ~15ms to wake up */ 481 msleep(15); 482 } 483 } 484 485 /* charge period values in microseconds */ 486 static const int tas5086_charge_period[] = { 487 13000, 16900, 23400, 31200, 41600, 54600, 72800, 96200, 488 130000, 156000, 234000, 312000, 416000, 546000, 728000, 962000, 489 1300000, 169000, 2340000, 3120000, 4160000, 5460000, 7280000, 9620000, 490 }; 491 492 static int tas5086_init(struct device *dev, struct tas5086_private *priv) 493 { 494 int ret, i; 495 496 /* 497 * If any of the channels is configured to start in Mid-Z mode, 498 * configure 'part 1' of the PWM starts to use Mid-Z, and tell 499 * all configured mid-z channels to start start under 'part 1'. 500 */ 501 if (priv->pwm_start_mid_z) 502 regmap_write(priv->regmap, TAS5086_PWM_START, 503 TAS5086_PWM_START_MIDZ_FOR_START_1 | 504 priv->pwm_start_mid_z); 505 506 /* lookup and set split-capacitor charge period */ 507 if (priv->charge_period == 0) { 508 regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, 0); 509 } else { 510 i = index_in_array(tas5086_charge_period, 511 ARRAY_SIZE(tas5086_charge_period), 512 priv->charge_period); 513 if (i >= 0) 514 regmap_write(priv->regmap, TAS5086_SPLIT_CAP_CHARGE, 515 i + 0x08); 516 else 517 dev_warn(dev, 518 "Invalid split-cap charge period of %d ns.\n", 519 priv->charge_period); 520 } 521 522 /* enable factory trim */ 523 ret = regmap_write(priv->regmap, TAS5086_OSC_TRIM, 0x00); 524 if (ret < 0) 525 return ret; 526 527 /* start all channels */ 528 ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x20); 529 if (ret < 0) 530 return ret; 531 532 /* mute all channels for now */ 533 ret = regmap_write(priv->regmap, TAS5086_SOFT_MUTE, 534 TAS5086_SOFT_MUTE_ALL); 535 if (ret < 0) 536 return ret; 537 538 return 0; 539 } 540 541 /* TAS5086 controls */ 542 static const DECLARE_TLV_DB_SCALE(tas5086_dac_tlv, -10350, 50, 1); 543 544 static const struct snd_kcontrol_new tas5086_controls[] = { 545 SOC_SINGLE_TLV("Master Playback Volume", TAS5086_MASTER_VOL, 546 0, 0xff, 1, tas5086_dac_tlv), 547 SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume", 548 TAS5086_CHANNEL_VOL(0), TAS5086_CHANNEL_VOL(1), 549 0, 0xff, 1, tas5086_dac_tlv), 550 SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume", 551 TAS5086_CHANNEL_VOL(2), TAS5086_CHANNEL_VOL(3), 552 0, 0xff, 1, tas5086_dac_tlv), 553 SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume", 554 TAS5086_CHANNEL_VOL(4), TAS5086_CHANNEL_VOL(5), 555 0, 0xff, 1, tas5086_dac_tlv), 556 SOC_SINGLE_BOOL_EXT("De-emphasis Switch", 0, 557 tas5086_get_deemph, tas5086_put_deemph), 558 }; 559 560 /* Input mux controls */ 561 static const char *tas5086_dapm_sdin_texts[] = 562 { 563 "SDIN1-L", "SDIN1-R", "SDIN2-L", "SDIN2-R", 564 "SDIN3-L", "SDIN3-R", "Ground (0)", "nc" 565 }; 566 567 static const struct soc_enum tas5086_dapm_input_mux_enum[] = { 568 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 20, 8, tas5086_dapm_sdin_texts), 569 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 16, 8, tas5086_dapm_sdin_texts), 570 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 12, 8, tas5086_dapm_sdin_texts), 571 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 8, 8, tas5086_dapm_sdin_texts), 572 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 4, 8, tas5086_dapm_sdin_texts), 573 SOC_ENUM_SINGLE(TAS5086_INPUT_MUX, 0, 8, tas5086_dapm_sdin_texts), 574 }; 575 576 static const struct snd_kcontrol_new tas5086_dapm_input_mux_controls[] = { 577 SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]), 578 SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]), 579 SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]), 580 SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]), 581 SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]), 582 SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]), 583 }; 584 585 /* Output mux controls */ 586 static const char *tas5086_dapm_channel_texts[] = 587 { "Channel 1 Mux", "Channel 2 Mux", "Channel 3 Mux", 588 "Channel 4 Mux", "Channel 5 Mux", "Channel 6 Mux" }; 589 590 static const struct soc_enum tas5086_dapm_output_mux_enum[] = { 591 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 20, 6, tas5086_dapm_channel_texts), 592 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 16, 6, tas5086_dapm_channel_texts), 593 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 12, 6, tas5086_dapm_channel_texts), 594 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 8, 6, tas5086_dapm_channel_texts), 595 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 4, 6, tas5086_dapm_channel_texts), 596 SOC_ENUM_SINGLE(TAS5086_PWM_OUTPUT_MUX, 0, 6, tas5086_dapm_channel_texts), 597 }; 598 599 static const struct snd_kcontrol_new tas5086_dapm_output_mux_controls[] = { 600 SOC_DAPM_ENUM("PWM1 Output", tas5086_dapm_output_mux_enum[0]), 601 SOC_DAPM_ENUM("PWM2 Output", tas5086_dapm_output_mux_enum[1]), 602 SOC_DAPM_ENUM("PWM3 Output", tas5086_dapm_output_mux_enum[2]), 603 SOC_DAPM_ENUM("PWM4 Output", tas5086_dapm_output_mux_enum[3]), 604 SOC_DAPM_ENUM("PWM5 Output", tas5086_dapm_output_mux_enum[4]), 605 SOC_DAPM_ENUM("PWM6 Output", tas5086_dapm_output_mux_enum[5]), 606 }; 607 608 static const struct snd_soc_dapm_widget tas5086_dapm_widgets[] = { 609 SND_SOC_DAPM_INPUT("SDIN1-L"), 610 SND_SOC_DAPM_INPUT("SDIN1-R"), 611 SND_SOC_DAPM_INPUT("SDIN2-L"), 612 SND_SOC_DAPM_INPUT("SDIN2-R"), 613 SND_SOC_DAPM_INPUT("SDIN3-L"), 614 SND_SOC_DAPM_INPUT("SDIN3-R"), 615 SND_SOC_DAPM_INPUT("SDIN4-L"), 616 SND_SOC_DAPM_INPUT("SDIN4-R"), 617 618 SND_SOC_DAPM_OUTPUT("PWM1"), 619 SND_SOC_DAPM_OUTPUT("PWM2"), 620 SND_SOC_DAPM_OUTPUT("PWM3"), 621 SND_SOC_DAPM_OUTPUT("PWM4"), 622 SND_SOC_DAPM_OUTPUT("PWM5"), 623 SND_SOC_DAPM_OUTPUT("PWM6"), 624 625 SND_SOC_DAPM_MUX("Channel 1 Mux", SND_SOC_NOPM, 0, 0, 626 &tas5086_dapm_input_mux_controls[0]), 627 SND_SOC_DAPM_MUX("Channel 2 Mux", SND_SOC_NOPM, 0, 0, 628 &tas5086_dapm_input_mux_controls[1]), 629 SND_SOC_DAPM_MUX("Channel 3 Mux", SND_SOC_NOPM, 0, 0, 630 &tas5086_dapm_input_mux_controls[2]), 631 SND_SOC_DAPM_MUX("Channel 4 Mux", SND_SOC_NOPM, 0, 0, 632 &tas5086_dapm_input_mux_controls[3]), 633 SND_SOC_DAPM_MUX("Channel 5 Mux", SND_SOC_NOPM, 0, 0, 634 &tas5086_dapm_input_mux_controls[4]), 635 SND_SOC_DAPM_MUX("Channel 6 Mux", SND_SOC_NOPM, 0, 0, 636 &tas5086_dapm_input_mux_controls[5]), 637 638 SND_SOC_DAPM_MUX("PWM1 Mux", SND_SOC_NOPM, 0, 0, 639 &tas5086_dapm_output_mux_controls[0]), 640 SND_SOC_DAPM_MUX("PWM2 Mux", SND_SOC_NOPM, 0, 0, 641 &tas5086_dapm_output_mux_controls[1]), 642 SND_SOC_DAPM_MUX("PWM3 Mux", SND_SOC_NOPM, 0, 0, 643 &tas5086_dapm_output_mux_controls[2]), 644 SND_SOC_DAPM_MUX("PWM4 Mux", SND_SOC_NOPM, 0, 0, 645 &tas5086_dapm_output_mux_controls[3]), 646 SND_SOC_DAPM_MUX("PWM5 Mux", SND_SOC_NOPM, 0, 0, 647 &tas5086_dapm_output_mux_controls[4]), 648 SND_SOC_DAPM_MUX("PWM6 Mux", SND_SOC_NOPM, 0, 0, 649 &tas5086_dapm_output_mux_controls[5]), 650 }; 651 652 static const struct snd_soc_dapm_route tas5086_dapm_routes[] = { 653 /* SDIN inputs -> channel muxes */ 654 { "Channel 1 Mux", "SDIN1-L", "SDIN1-L" }, 655 { "Channel 1 Mux", "SDIN1-R", "SDIN1-R" }, 656 { "Channel 1 Mux", "SDIN2-L", "SDIN2-L" }, 657 { "Channel 1 Mux", "SDIN2-R", "SDIN2-R" }, 658 { "Channel 1 Mux", "SDIN3-L", "SDIN3-L" }, 659 { "Channel 1 Mux", "SDIN3-R", "SDIN3-R" }, 660 661 { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" }, 662 { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" }, 663 { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" }, 664 { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" }, 665 { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" }, 666 { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" }, 667 668 { "Channel 2 Mux", "SDIN1-L", "SDIN1-L" }, 669 { "Channel 2 Mux", "SDIN1-R", "SDIN1-R" }, 670 { "Channel 2 Mux", "SDIN2-L", "SDIN2-L" }, 671 { "Channel 2 Mux", "SDIN2-R", "SDIN2-R" }, 672 { "Channel 2 Mux", "SDIN3-L", "SDIN3-L" }, 673 { "Channel 2 Mux", "SDIN3-R", "SDIN3-R" }, 674 675 { "Channel 3 Mux", "SDIN1-L", "SDIN1-L" }, 676 { "Channel 3 Mux", "SDIN1-R", "SDIN1-R" }, 677 { "Channel 3 Mux", "SDIN2-L", "SDIN2-L" }, 678 { "Channel 3 Mux", "SDIN2-R", "SDIN2-R" }, 679 { "Channel 3 Mux", "SDIN3-L", "SDIN3-L" }, 680 { "Channel 3 Mux", "SDIN3-R", "SDIN3-R" }, 681 682 { "Channel 4 Mux", "SDIN1-L", "SDIN1-L" }, 683 { "Channel 4 Mux", "SDIN1-R", "SDIN1-R" }, 684 { "Channel 4 Mux", "SDIN2-L", "SDIN2-L" }, 685 { "Channel 4 Mux", "SDIN2-R", "SDIN2-R" }, 686 { "Channel 4 Mux", "SDIN3-L", "SDIN3-L" }, 687 { "Channel 4 Mux", "SDIN3-R", "SDIN3-R" }, 688 689 { "Channel 5 Mux", "SDIN1-L", "SDIN1-L" }, 690 { "Channel 5 Mux", "SDIN1-R", "SDIN1-R" }, 691 { "Channel 5 Mux", "SDIN2-L", "SDIN2-L" }, 692 { "Channel 5 Mux", "SDIN2-R", "SDIN2-R" }, 693 { "Channel 5 Mux", "SDIN3-L", "SDIN3-L" }, 694 { "Channel 5 Mux", "SDIN3-R", "SDIN3-R" }, 695 696 { "Channel 6 Mux", "SDIN1-L", "SDIN1-L" }, 697 { "Channel 6 Mux", "SDIN1-R", "SDIN1-R" }, 698 { "Channel 6 Mux", "SDIN2-L", "SDIN2-L" }, 699 { "Channel 6 Mux", "SDIN2-R", "SDIN2-R" }, 700 { "Channel 6 Mux", "SDIN3-L", "SDIN3-L" }, 701 { "Channel 6 Mux", "SDIN3-R", "SDIN3-R" }, 702 703 /* Channel muxes -> PWM muxes */ 704 { "PWM1 Mux", "Channel 1 Mux", "Channel 1 Mux" }, 705 { "PWM2 Mux", "Channel 1 Mux", "Channel 1 Mux" }, 706 { "PWM3 Mux", "Channel 1 Mux", "Channel 1 Mux" }, 707 { "PWM4 Mux", "Channel 1 Mux", "Channel 1 Mux" }, 708 { "PWM5 Mux", "Channel 1 Mux", "Channel 1 Mux" }, 709 { "PWM6 Mux", "Channel 1 Mux", "Channel 1 Mux" }, 710 711 { "PWM1 Mux", "Channel 2 Mux", "Channel 2 Mux" }, 712 { "PWM2 Mux", "Channel 2 Mux", "Channel 2 Mux" }, 713 { "PWM3 Mux", "Channel 2 Mux", "Channel 2 Mux" }, 714 { "PWM4 Mux", "Channel 2 Mux", "Channel 2 Mux" }, 715 { "PWM5 Mux", "Channel 2 Mux", "Channel 2 Mux" }, 716 { "PWM6 Mux", "Channel 2 Mux", "Channel 2 Mux" }, 717 718 { "PWM1 Mux", "Channel 3 Mux", "Channel 3 Mux" }, 719 { "PWM2 Mux", "Channel 3 Mux", "Channel 3 Mux" }, 720 { "PWM3 Mux", "Channel 3 Mux", "Channel 3 Mux" }, 721 { "PWM4 Mux", "Channel 3 Mux", "Channel 3 Mux" }, 722 { "PWM5 Mux", "Channel 3 Mux", "Channel 3 Mux" }, 723 { "PWM6 Mux", "Channel 3 Mux", "Channel 3 Mux" }, 724 725 { "PWM1 Mux", "Channel 4 Mux", "Channel 4 Mux" }, 726 { "PWM2 Mux", "Channel 4 Mux", "Channel 4 Mux" }, 727 { "PWM3 Mux", "Channel 4 Mux", "Channel 4 Mux" }, 728 { "PWM4 Mux", "Channel 4 Mux", "Channel 4 Mux" }, 729 { "PWM5 Mux", "Channel 4 Mux", "Channel 4 Mux" }, 730 { "PWM6 Mux", "Channel 4 Mux", "Channel 4 Mux" }, 731 732 { "PWM1 Mux", "Channel 5 Mux", "Channel 5 Mux" }, 733 { "PWM2 Mux", "Channel 5 Mux", "Channel 5 Mux" }, 734 { "PWM3 Mux", "Channel 5 Mux", "Channel 5 Mux" }, 735 { "PWM4 Mux", "Channel 5 Mux", "Channel 5 Mux" }, 736 { "PWM5 Mux", "Channel 5 Mux", "Channel 5 Mux" }, 737 { "PWM6 Mux", "Channel 5 Mux", "Channel 5 Mux" }, 738 739 { "PWM1 Mux", "Channel 6 Mux", "Channel 6 Mux" }, 740 { "PWM2 Mux", "Channel 6 Mux", "Channel 6 Mux" }, 741 { "PWM3 Mux", "Channel 6 Mux", "Channel 6 Mux" }, 742 { "PWM4 Mux", "Channel 6 Mux", "Channel 6 Mux" }, 743 { "PWM5 Mux", "Channel 6 Mux", "Channel 6 Mux" }, 744 { "PWM6 Mux", "Channel 6 Mux", "Channel 6 Mux" }, 745 746 /* The PWM muxes are directly connected to the PWM outputs */ 747 { "PWM1", NULL, "PWM1 Mux" }, 748 { "PWM2", NULL, "PWM2 Mux" }, 749 { "PWM3", NULL, "PWM3 Mux" }, 750 { "PWM4", NULL, "PWM4 Mux" }, 751 { "PWM5", NULL, "PWM5 Mux" }, 752 { "PWM6", NULL, "PWM6 Mux" }, 753 754 }; 755 756 static const struct snd_soc_dai_ops tas5086_dai_ops = { 757 .hw_params = tas5086_hw_params, 758 .set_sysclk = tas5086_set_dai_sysclk, 759 .set_fmt = tas5086_set_dai_fmt, 760 .mute_stream = tas5086_mute_stream, 761 }; 762 763 static struct snd_soc_dai_driver tas5086_dai = { 764 .name = "tas5086-hifi", 765 .playback = { 766 .stream_name = "Playback", 767 .channels_min = 2, 768 .channels_max = 6, 769 .rates = TAS5086_PCM_RATES, 770 .formats = TAS5086_PCM_FORMATS, 771 }, 772 .ops = &tas5086_dai_ops, 773 }; 774 775 #ifdef CONFIG_PM 776 static int tas5086_soc_suspend(struct snd_soc_codec *codec) 777 { 778 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 779 int ret; 780 781 /* Shut down all channels */ 782 ret = regmap_write(priv->regmap, TAS5086_SYS_CONTROL_2, 0x60); 783 if (ret < 0) 784 return ret; 785 786 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); 787 788 return 0; 789 } 790 791 static int tas5086_soc_resume(struct snd_soc_codec *codec) 792 { 793 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 794 int ret; 795 796 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 797 if (ret < 0) 798 return ret; 799 800 tas5086_reset(priv); 801 regcache_mark_dirty(priv->regmap); 802 803 ret = tas5086_init(codec->dev, priv); 804 if (ret < 0) 805 return ret; 806 807 ret = regcache_sync(priv->regmap); 808 if (ret < 0) 809 return ret; 810 811 return 0; 812 } 813 #else 814 #define tas5086_soc_suspend NULL 815 #define tas5086_soc_resume NULL 816 #endif /* CONFIG_PM */ 817 818 #ifdef CONFIG_OF 819 static const struct of_device_id tas5086_dt_ids[] = { 820 { .compatible = "ti,tas5086", }, 821 { } 822 }; 823 MODULE_DEVICE_TABLE(of, tas5086_dt_ids); 824 #endif 825 826 static int tas5086_probe(struct snd_soc_codec *codec) 827 { 828 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 829 int i, ret; 830 831 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 832 if (ret < 0) { 833 dev_err(codec->dev, "Failed to enable regulators: %d\n", ret); 834 return ret; 835 } 836 837 priv->pwm_start_mid_z = 0; 838 priv->charge_period = 1300000; /* hardware default is 1300 ms */ 839 840 if (of_match_device(of_match_ptr(tas5086_dt_ids), codec->dev)) { 841 struct device_node *of_node = codec->dev->of_node; 842 843 of_property_read_u32(of_node, "ti,charge-period", 844 &priv->charge_period); 845 846 for (i = 0; i < 6; i++) { 847 char name[25]; 848 849 snprintf(name, sizeof(name), 850 "ti,mid-z-channel-%d", i + 1); 851 852 if (of_get_property(of_node, name, NULL) != NULL) 853 priv->pwm_start_mid_z |= 1 << i; 854 } 855 } 856 857 tas5086_reset(priv); 858 ret = tas5086_init(codec->dev, priv); 859 if (ret < 0) 860 goto exit_disable_regulators; 861 862 /* set master volume to 0 dB */ 863 ret = regmap_write(priv->regmap, TAS5086_MASTER_VOL, 0x30); 864 if (ret < 0) 865 goto exit_disable_regulators; 866 867 return 0; 868 869 exit_disable_regulators: 870 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); 871 872 return ret; 873 } 874 875 static int tas5086_remove(struct snd_soc_codec *codec) 876 { 877 struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); 878 879 if (gpio_is_valid(priv->gpio_nreset)) 880 /* Set codec to the reset state */ 881 gpio_set_value(priv->gpio_nreset, 0); 882 883 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); 884 885 return 0; 886 }; 887 888 static const struct snd_soc_codec_driver soc_codec_dev_tas5086 = { 889 .probe = tas5086_probe, 890 .remove = tas5086_remove, 891 .suspend = tas5086_soc_suspend, 892 .resume = tas5086_soc_resume, 893 .component_driver = { 894 .controls = tas5086_controls, 895 .num_controls = ARRAY_SIZE(tas5086_controls), 896 .dapm_widgets = tas5086_dapm_widgets, 897 .num_dapm_widgets = ARRAY_SIZE(tas5086_dapm_widgets), 898 .dapm_routes = tas5086_dapm_routes, 899 .num_dapm_routes = ARRAY_SIZE(tas5086_dapm_routes), 900 }, 901 }; 902 903 static const struct i2c_device_id tas5086_i2c_id[] = { 904 { "tas5086", 0 }, 905 { } 906 }; 907 MODULE_DEVICE_TABLE(i2c, tas5086_i2c_id); 908 909 static const struct regmap_config tas5086_regmap = { 910 .reg_bits = 8, 911 .val_bits = 32, 912 .max_register = TAS5086_MAX_REGISTER, 913 .reg_defaults = tas5086_reg_defaults, 914 .num_reg_defaults = ARRAY_SIZE(tas5086_reg_defaults), 915 .cache_type = REGCACHE_RBTREE, 916 .volatile_reg = tas5086_volatile_reg, 917 .writeable_reg = tas5086_writeable_reg, 918 .readable_reg = tas5086_accessible_reg, 919 .reg_read = tas5086_reg_read, 920 .reg_write = tas5086_reg_write, 921 }; 922 923 static int tas5086_i2c_probe(struct i2c_client *i2c, 924 const struct i2c_device_id *id) 925 { 926 struct tas5086_private *priv; 927 struct device *dev = &i2c->dev; 928 int gpio_nreset = -EINVAL; 929 int i, ret; 930 931 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 932 if (!priv) 933 return -ENOMEM; 934 935 for (i = 0; i < ARRAY_SIZE(supply_names); i++) 936 priv->supplies[i].supply = supply_names[i]; 937 938 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies), 939 priv->supplies); 940 if (ret < 0) { 941 dev_err(dev, "Failed to get regulators: %d\n", ret); 942 return ret; 943 } 944 945 priv->regmap = devm_regmap_init(dev, NULL, i2c, &tas5086_regmap); 946 if (IS_ERR(priv->regmap)) { 947 ret = PTR_ERR(priv->regmap); 948 dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret); 949 return ret; 950 } 951 952 i2c_set_clientdata(i2c, priv); 953 954 if (of_match_device(of_match_ptr(tas5086_dt_ids), dev)) { 955 struct device_node *of_node = dev->of_node; 956 gpio_nreset = of_get_named_gpio(of_node, "reset-gpio", 0); 957 } 958 959 if (gpio_is_valid(gpio_nreset)) 960 if (devm_gpio_request(dev, gpio_nreset, "TAS5086 Reset")) 961 gpio_nreset = -EINVAL; 962 963 priv->gpio_nreset = gpio_nreset; 964 965 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 966 if (ret < 0) { 967 dev_err(dev, "Failed to enable regulators: %d\n", ret); 968 return ret; 969 } 970 971 tas5086_reset(priv); 972 973 /* The TAS5086 always returns 0x03 in its TAS5086_DEV_ID register */ 974 ret = regmap_read(priv->regmap, TAS5086_DEV_ID, &i); 975 if (ret == 0 && i != 0x3) { 976 dev_err(dev, 977 "Failed to identify TAS5086 codec (got %02x)\n", i); 978 ret = -ENODEV; 979 } 980 981 /* 982 * The chip has been identified, so we can turn off the power 983 * again until the dai link is set up. 984 */ 985 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies); 986 987 if (ret == 0) 988 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_tas5086, 989 &tas5086_dai, 1); 990 991 return ret; 992 } 993 994 static int tas5086_i2c_remove(struct i2c_client *i2c) 995 { 996 snd_soc_unregister_codec(&i2c->dev); 997 return 0; 998 } 999 1000 static struct i2c_driver tas5086_i2c_driver = { 1001 .driver = { 1002 .name = "tas5086", 1003 .of_match_table = of_match_ptr(tas5086_dt_ids), 1004 }, 1005 .id_table = tas5086_i2c_id, 1006 .probe = tas5086_i2c_probe, 1007 .remove = tas5086_i2c_remove, 1008 }; 1009 1010 module_i2c_driver(tas5086_i2c_driver); 1011 1012 MODULE_AUTHOR("Daniel Mack <zonque@gmail.com>"); 1013 MODULE_DESCRIPTION("Texas Instruments TAS5086 ALSA SoC Codec Driver"); 1014 MODULE_LICENSE("GPL"); 1015